drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Authors:
   5  *      YT Shen <[email protected]>
   6  *      CK Hu <[email protected]>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/of_platform.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/soc/mediatek/mtk-cmdq.h>
  15 #include <drm/drm_print.h>
  16
  17 #include "mtk_disp_drv.h"
  18 #include "mtk_drm_drv.h"
  19 #include "mtk_drm_plane.h"
  20 #include "mtk_drm_ddp_comp.h"
  21 #include "mtk_drm_crtc.h"
  22
  23
  24 #define DISP_REG_DITHER_EN                      0x0000
  25 #define DITHER_EN                               BIT(0)
  26 #define DISP_REG_DITHER_CFG                     0x0020
  27 #define DITHER_RELAY_MODE                       BIT(0)
  28 #define DITHER_ENGINE_EN                        BIT(1)
  29 #define DISP_DITHERING                          BIT(2)
  30 #define DISP_REG_DITHER_SIZE                    0x0030
  31 #define DISP_REG_DITHER_5                       0x0114
  32 #define DISP_REG_DITHER_7                       0x011c
  33 #define DISP_REG_DITHER_15                      0x013c
  34 #define DITHER_LSB_ERR_SHIFT_R(x)               (((x) & 0x7) << 28)
  35 #define DITHER_ADD_LSHIFT_R(x)                  (((x) & 0x7) << 20)
  36 #define DITHER_NEW_BIT_MODE                     BIT(0)
  37 #define DISP_REG_DITHER_16                      0x0140
  38 #define DITHER_LSB_ERR_SHIFT_B(x)               (((x) & 0x7) << 28)
  39 #define DITHER_ADD_LSHIFT_B(x)                  (((x) & 0x7) << 20)
  40 #define DITHER_LSB_ERR_SHIFT_G(x)               (((x) & 0x7) << 12)
  41 #define DITHER_ADD_LSHIFT_G(x)                  (((x) & 0x7) << 4)
  42
  43 #define DISP_REG_DSC_CON                        0x0000
  44 #define DSC_EN                                  BIT(0)
  45 #define DSC_DUAL_INOUT                          BIT(2)
  46 #define DSC_BYPASS                              BIT(4)
  47 #define DSC_UFOE_SEL                            BIT(16)
  48
  49 #define DISP_REG_OD_EN                          0x0000
  50 #define DISP_REG_OD_CFG                         0x0020
  51 #define OD_RELAYMODE                            BIT(0)
  52 #define DISP_REG_OD_SIZE                        0x0030
  53
  54 #define DISP_REG_POSTMASK_EN                    0x0000
  55 #define POSTMASK_EN                                     BIT(0)
  56 #define DISP_REG_POSTMASK_CFG                   0x0020
  57 #define POSTMASK_RELAY_MODE                             BIT(0)
  58 #define DISP_REG_POSTMASK_SIZE                  0x0030
  59
  60 #define DISP_REG_UFO_START                      0x0000
  61 #define UFO_BYPASS                              BIT(2)
  62
  63 struct mtk_ddp_comp_dev {
  64         struct clk *clk;
  65         void __iomem *regs;
  66         struct cmdq_client_reg cmdq_reg;
  67 };
  68
  69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  70                    struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
  71                    unsigned int offset)
  72 {
  73 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  74         if (cmdq_pkt)
  75                 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
  76                                cmdq_reg->offset + offset, value);
  77         else
  78 #endif
  79                 writel(value, regs + offset);
  80 }
  81
  82 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  83                            struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
  84                            unsigned int offset)
  85 {
  86 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
  87         if (cmdq_pkt)
  88                 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys,
  89                                cmdq_reg->offset + offset, value);
  90         else
  91 #endif
  92                 writel_relaxed(value, regs + offset);
  93 }
  94
  95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
  96                         struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
  97                         unsigned int offset, unsigned int mask)
  98 {
  99 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 100         if (cmdq_pkt) {
 101                 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys,
 102                                     cmdq_reg->offset + offset, value, mask);
 103         } else {
 104 #endif
 105                 u32 tmp = readl(regs + offset);
 106
 107                 tmp = (tmp & ~mask) | (value & mask);
 108                 writel(tmp, regs + offset);
 109 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 110         }
 111 #endif
 112 }
 113
 114 static int mtk_ddp_clk_enable(struct device *dev)
 115 {
 116         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 117
 118         return clk_prepare_enable(priv->clk);
 119 }
 120
 121 static void mtk_ddp_clk_disable(struct device *dev)
 122 {
 123         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 124
 125         clk_disable_unprepare(priv->clk);
 126 }
 127
 128 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
 129                            unsigned int bpc, unsigned int cfg,
 130                            unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
 131 {
 132         /* If bpc equal to 0, the dithering function didn't be enabled */
 133         if (bpc == 0)
 134                 return;
 135
 136         if (bpc >= MTK_MIN_BPC) {
 137                 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5);
 138                 mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7);
 139                 mtk_ddp_write(cmdq_pkt,
 140                               DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
 141                               DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
 142                               DITHER_NEW_BIT_MODE,
 143                               cmdq_reg, regs, DISP_REG_DITHER_15);
 144                 mtk_ddp_write(cmdq_pkt,
 145                               DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
 146                               DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
 147                               DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
 148                               DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
 149                               cmdq_reg, regs, DISP_REG_DITHER_16);
 150                 mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
 151         }
 152 }
 153
 154 static void mtk_dither_config(struct device *dev, unsigned int w,
 155                               unsigned int h, unsigned int vrefresh,
 156                               unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 157 {
 158         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 159
 160         mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_DITHER_SIZE);
 161         mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
 162                       DISP_REG_DITHER_CFG);
 163         mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG,
 164                               DITHER_ENGINE_EN, cmdq_pkt);
 165 }
 166
 167 static void mtk_dither_start(struct device *dev)
 168 {
 169         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 170
 171         writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
 172 }
 173
 174 static void mtk_dither_stop(struct device *dev)
 175 {
 176         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 177
 178         writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
 179 }
 180
 181 static void mtk_dither_set(struct device *dev, unsigned int bpc,
 182                            unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
 183 {
 184         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 185
 186         mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
 187                               DISP_DITHERING, cmdq_pkt);
 188 }
 189
 190 static void mtk_dsc_config(struct device *dev, unsigned int w,
 191                            unsigned int h, unsigned int vrefresh,
 192                            unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 193 {
 194         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 195
 196         /* dsc bypass mode */
 197         mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
 198                            DISP_REG_DSC_CON, DSC_BYPASS);
 199         mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
 200                            DISP_REG_DSC_CON, DSC_UFOE_SEL);
 201         mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
 202                            DISP_REG_DSC_CON, DSC_DUAL_INOUT);
 203 }
 204
 205 static void mtk_dsc_start(struct device *dev)
 206 {
 207         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 208
 209         /* write with mask to reserve the value set in mtk_dsc_config */
 210         mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
 211 }
 212
 213 static void mtk_dsc_stop(struct device *dev)
 214 {
 215         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 216
 217         writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
 218 }
 219
 220 static void mtk_od_config(struct device *dev, unsigned int w,
 221                           unsigned int h, unsigned int vrefresh,
 222                           unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 223 {
 224         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 225
 226         mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE);
 227         mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG);
 228         mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
 229 }
 230
 231 static void mtk_od_start(struct device *dev)
 232 {
 233         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 234
 235         writel(1, priv->regs + DISP_REG_OD_EN);
 236 }
 237
 238 static void mtk_postmask_config(struct device *dev, unsigned int w,
 239                                 unsigned int h, unsigned int vrefresh,
 240                                 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 241 {
 242         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 243
 244         mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
 245                       DISP_REG_POSTMASK_SIZE);
 246         mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
 247                       priv->regs, DISP_REG_POSTMASK_CFG);
 248 }
 249
 250 static void mtk_postmask_start(struct device *dev)
 251 {
 252         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 253
 254         writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
 255 }
 256
 257 static void mtk_postmask_stop(struct device *dev)
 258 {
 259         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 260
 261         writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
 262 }
 263
 264 static void mtk_ufoe_start(struct device *dev)
 265 {
 266         struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
 267
 268         writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 269 }
 270
 271 static const struct mtk_ddp_comp_funcs ddp_aal = {
 272         .clk_enable = mtk_aal_clk_enable,
 273         .clk_disable = mtk_aal_clk_disable,
 274         .gamma_get_lut_size = mtk_aal_gamma_get_lut_size,
 275         .gamma_set = mtk_aal_gamma_set,
 276         .config = mtk_aal_config,
 277         .start = mtk_aal_start,
 278         .stop = mtk_aal_stop,
 279 };
 280
 281 static const struct mtk_ddp_comp_funcs ddp_ccorr = {
 282         .clk_enable = mtk_ccorr_clk_enable,
 283         .clk_disable = mtk_ccorr_clk_disable,
 284         .config = mtk_ccorr_config,
 285         .start = mtk_ccorr_start,
 286         .stop = mtk_ccorr_stop,
 287         .ctm_set = mtk_ccorr_ctm_set,
 288 };
 289
 290 static const struct mtk_ddp_comp_funcs ddp_color = {
 291         .clk_enable = mtk_color_clk_enable,
 292         .clk_disable = mtk_color_clk_disable,
 293         .config = mtk_color_config,
 294         .start = mtk_color_start,
 295 };
 296
 297 static const struct mtk_ddp_comp_funcs ddp_dither = {
 298         .clk_enable = mtk_ddp_clk_enable,
 299         .clk_disable = mtk_ddp_clk_disable,
 300         .config = mtk_dither_config,
 301         .start = mtk_dither_start,
 302         .stop = mtk_dither_stop,
 303 };
 304
 305 static const struct mtk_ddp_comp_funcs ddp_dpi = {
 306         .start = mtk_dpi_start,
 307         .stop = mtk_dpi_stop,
 308         .encoder_index = mtk_dpi_encoder_index,
 309 };
 310
 311 static const struct mtk_ddp_comp_funcs ddp_dsc = {
 312         .clk_enable = mtk_ddp_clk_enable,
 313         .clk_disable = mtk_ddp_clk_disable,
 314         .config = mtk_dsc_config,
 315         .start = mtk_dsc_start,
 316         .stop = mtk_dsc_stop,
 317 };
 318
 319 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 320         .start = mtk_dsi_ddp_start,
 321         .stop = mtk_dsi_ddp_stop,
 322         .encoder_index = mtk_dsi_encoder_index,
 323 };
 324
 325 static const struct mtk_ddp_comp_funcs ddp_gamma = {
 326         .clk_enable = mtk_gamma_clk_enable,
 327         .clk_disable = mtk_gamma_clk_disable,
 328         .gamma_get_lut_size = mtk_gamma_get_lut_size,
 329         .gamma_set = mtk_gamma_set,
 330         .config = mtk_gamma_config,
 331         .start = mtk_gamma_start,
 332         .stop = mtk_gamma_stop,
 333 };
 334
 335 static const struct mtk_ddp_comp_funcs ddp_merge = {
 336         .clk_enable = mtk_merge_clk_enable,
 337         .clk_disable = mtk_merge_clk_disable,
 338         .start = mtk_merge_start,
 339         .stop = mtk_merge_stop,
 340         .config = mtk_merge_config,
 341 };
 342
 343 static const struct mtk_ddp_comp_funcs ddp_od = {
 344         .clk_enable = mtk_ddp_clk_enable,
 345         .clk_disable = mtk_ddp_clk_disable,
 346         .config = mtk_od_config,
 347         .start = mtk_od_start,
 348 };
 349
 350 static const struct mtk_ddp_comp_funcs ddp_ovl = {
 351         .clk_enable = mtk_ovl_clk_enable,
 352         .clk_disable = mtk_ovl_clk_disable,
 353         .config = mtk_ovl_config,
 354         .start = mtk_ovl_start,
 355         .stop = mtk_ovl_stop,
 356         .register_vblank_cb = mtk_ovl_register_vblank_cb,
 357         .unregister_vblank_cb = mtk_ovl_unregister_vblank_cb,
 358         .enable_vblank = mtk_ovl_enable_vblank,
 359         .disable_vblank = mtk_ovl_disable_vblank,
 360         .supported_rotations = mtk_ovl_supported_rotations,
 361         .layer_nr = mtk_ovl_layer_nr,
 362         .layer_check = mtk_ovl_layer_check,
 363         .layer_config = mtk_ovl_layer_config,
 364         .bgclr_in_on = mtk_ovl_bgclr_in_on,
 365         .bgclr_in_off = mtk_ovl_bgclr_in_off,
 366         .get_formats = mtk_ovl_get_formats,
 367         .get_num_formats = mtk_ovl_get_num_formats,
 368 };
 369
 370 static const struct mtk_ddp_comp_funcs ddp_postmask = {
 371         .clk_enable = mtk_ddp_clk_enable,
 372         .clk_disable = mtk_ddp_clk_disable,
 373         .config = mtk_postmask_config,
 374         .start = mtk_postmask_start,
 375         .stop = mtk_postmask_stop,
 376 };
 377
 378 static const struct mtk_ddp_comp_funcs ddp_rdma = {
 379         .clk_enable = mtk_rdma_clk_enable,
 380         .clk_disable = mtk_rdma_clk_disable,
 381         .config = mtk_rdma_config,
 382         .start = mtk_rdma_start,
 383         .stop = mtk_rdma_stop,
 384         .register_vblank_cb = mtk_rdma_register_vblank_cb,
 385         .unregister_vblank_cb = mtk_rdma_unregister_vblank_cb,
 386         .enable_vblank = mtk_rdma_enable_vblank,
 387         .disable_vblank = mtk_rdma_disable_vblank,
 388         .layer_nr = mtk_rdma_layer_nr,
 389         .layer_config = mtk_rdma_layer_config,
 390         .get_formats = mtk_rdma_get_formats,
 391         .get_num_formats = mtk_rdma_get_num_formats,
 392 };
 393
 394 static const struct mtk_ddp_comp_funcs ddp_ufoe = {
 395         .clk_enable = mtk_ddp_clk_enable,
 396         .clk_disable = mtk_ddp_clk_disable,
 397         .start = mtk_ufoe_start,
 398 };
 399
 400 static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
 401         .clk_enable = mtk_ovl_adaptor_clk_enable,
 402         .clk_disable = mtk_ovl_adaptor_clk_disable,
 403         .config = mtk_ovl_adaptor_config,
 404         .start = mtk_ovl_adaptor_start,
 405         .stop = mtk_ovl_adaptor_stop,
 406         .layer_nr = mtk_ovl_adaptor_layer_nr,
 407         .layer_config = mtk_ovl_adaptor_layer_config,
 408         .register_vblank_cb = mtk_ovl_adaptor_register_vblank_cb,
 409         .unregister_vblank_cb = mtk_ovl_adaptor_unregister_vblank_cb,
 410         .enable_vblank = mtk_ovl_adaptor_enable_vblank,
 411         .disable_vblank = mtk_ovl_adaptor_disable_vblank,
 412         .dma_dev_get = mtk_ovl_adaptor_dma_dev_get,
 413         .connect = mtk_ovl_adaptor_connect,
 414         .disconnect = mtk_ovl_adaptor_disconnect,
 415         .add = mtk_ovl_adaptor_add_comp,
 416         .remove = mtk_ovl_adaptor_remove_comp,
 417         .get_formats = mtk_ovl_adaptor_get_formats,
 418         .get_num_formats = mtk_ovl_adaptor_get_num_formats,
 419 };
 420
 421 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 422         [MTK_DISP_AAL] = "aal",
 423         [MTK_DISP_BLS] = "bls",
 424         [MTK_DISP_CCORR] = "ccorr",
 425         [MTK_DISP_COLOR] = "color",
 426         [MTK_DISP_DITHER] = "dither",
 427         [MTK_DISP_DSC] = "dsc",
 428         [MTK_DISP_GAMMA] = "gamma",
 429         [MTK_DISP_MERGE] = "merge",
 430         [MTK_DISP_MUTEX] = "mutex",
 431         [MTK_DISP_OD] = "od",
 432         [MTK_DISP_OVL] = "ovl",
 433         [MTK_DISP_OVL_2L] = "ovl-2l",
 434         [MTK_DISP_OVL_ADAPTOR] = "ovl_adaptor",
 435         [MTK_DISP_POSTMASK] = "postmask",
 436         [MTK_DISP_PWM] = "pwm",
 437         [MTK_DISP_RDMA] = "rdma",
 438         [MTK_DISP_UFOE] = "ufoe",
 439         [MTK_DISP_WDMA] = "wdma",
 440         [MTK_DP_INTF] = "dp-intf",
 441         [MTK_DPI] = "dpi",
 442         [MTK_DSI] = "dsi",
 443 };
 444
 445 struct mtk_ddp_comp_match {
 446         enum mtk_ddp_comp_type type;
 447         int alias_id;
 448         const struct mtk_ddp_comp_funcs *funcs;
 449 };
 450
 451 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
 452         [DDP_COMPONENT_AAL0]            = { MTK_DISP_AAL,               0, &ddp_aal },
 453         [DDP_COMPONENT_AAL1]            = { MTK_DISP_AAL,               1, &ddp_aal },
 454         [DDP_COMPONENT_BLS]             = { MTK_DISP_BLS,               0, NULL },
 455         [DDP_COMPONENT_CCORR]           = { MTK_DISP_CCORR,             0, &ddp_ccorr },
 456         [DDP_COMPONENT_COLOR0]          = { MTK_DISP_COLOR,             0, &ddp_color },
 457         [DDP_COMPONENT_COLOR1]          = { MTK_DISP_COLOR,             1, &ddp_color },
 458         [DDP_COMPONENT_DITHER0]         = { MTK_DISP_DITHER,            0, &ddp_dither },
 459         [DDP_COMPONENT_DP_INTF0]        = { MTK_DP_INTF,                0, &ddp_dpi },
 460         [DDP_COMPONENT_DP_INTF1]        = { MTK_DP_INTF,                1, &ddp_dpi },
 461         [DDP_COMPONENT_DPI0]            = { MTK_DPI,                    0, &ddp_dpi },
 462         [DDP_COMPONENT_DPI1]            = { MTK_DPI,                    1, &ddp_dpi },
 463         [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR,       0, &ddp_ovl_adaptor },
 464         [DDP_COMPONENT_DSC0]            = { MTK_DISP_DSC,               0, &ddp_dsc },
 465         [DDP_COMPONENT_DSC1]            = { MTK_DISP_DSC,               1, &ddp_dsc },
 466         [DDP_COMPONENT_DSI0]            = { MTK_DSI,                    0, &ddp_dsi },
 467         [DDP_COMPONENT_DSI1]            = { MTK_DSI,                    1, &ddp_dsi },
 468         [DDP_COMPONENT_DSI2]            = { MTK_DSI,                    2, &ddp_dsi },
 469         [DDP_COMPONENT_DSI3]            = { MTK_DSI,                    3, &ddp_dsi },
 470         [DDP_COMPONENT_GAMMA]           = { MTK_DISP_GAMMA,             0, &ddp_gamma },
 471         [DDP_COMPONENT_MERGE0]          = { MTK_DISP_MERGE,             0, &ddp_merge },
 472         [DDP_COMPONENT_MERGE1]          = { MTK_DISP_MERGE,             1, &ddp_merge },
 473         [DDP_COMPONENT_MERGE2]          = { MTK_DISP_MERGE,             2, &ddp_merge },
 474         [DDP_COMPONENT_MERGE3]          = { MTK_DISP_MERGE,             3, &ddp_merge },
 475         [DDP_COMPONENT_MERGE4]          = { MTK_DISP_MERGE,             4, &ddp_merge },
 476         [DDP_COMPONENT_MERGE5]          = { MTK_DISP_MERGE,             5, &ddp_merge },
 477         [DDP_COMPONENT_OD0]             = { MTK_DISP_OD,                0, &ddp_od },
 478         [DDP_COMPONENT_OD1]             = { MTK_DISP_OD,                1, &ddp_od },
 479         [DDP_COMPONENT_OVL0]            = { MTK_DISP_OVL,               0, &ddp_ovl },
 480         [DDP_COMPONENT_OVL1]            = { MTK_DISP_OVL,               1, &ddp_ovl },
 481         [DDP_COMPONENT_OVL_2L0]         = { MTK_DISP_OVL_2L,            0, &ddp_ovl },
 482         [DDP_COMPONENT_OVL_2L1]         = { MTK_DISP_OVL_2L,            1, &ddp_ovl },
 483         [DDP_COMPONENT_OVL_2L2]         = { MTK_DISP_OVL_2L,            2, &ddp_ovl },
 484         [DDP_COMPONENT_POSTMASK0]       = { MTK_DISP_POSTMASK,          0, &ddp_postmask },
 485         [DDP_COMPONENT_PWM0]            = { MTK_DISP_PWM,               0, NULL },
 486         [DDP_COMPONENT_PWM1]            = { MTK_DISP_PWM,               1, NULL },
 487         [DDP_COMPONENT_PWM2]            = { MTK_DISP_PWM,               2, NULL },
 488         [DDP_COMPONENT_RDMA0]           = { MTK_DISP_RDMA,              0, &ddp_rdma },
 489         [DDP_COMPONENT_RDMA1]           = { MTK_DISP_RDMA,              1, &ddp_rdma },
 490         [DDP_COMPONENT_RDMA2]           = { MTK_DISP_RDMA,              2, &ddp_rdma },
 491         [DDP_COMPONENT_RDMA4]           = { MTK_DISP_RDMA,              4, &ddp_rdma },
 492         [DDP_COMPONENT_UFOE]            = { MTK_DISP_UFOE,              0, &ddp_ufoe },
 493         [DDP_COMPONENT_WDMA0]           = { MTK_DISP_WDMA,              0, NULL },
 494         [DDP_COMPONENT_WDMA1]           = { MTK_DISP_WDMA,              1, NULL },
 495 };
 496
 497 static bool mtk_drm_find_comp_in_ddp(struct device *dev,
 498                                      const unsigned int *path,
 499                                      unsigned int path_len,
 500                                      struct mtk_ddp_comp *ddp_comp)
 501 {
 502         unsigned int i;
 503
 504         if (path == NULL)
 505                 return false;
 506
 507         for (i = 0U; i < path_len; i++)
 508                 if (dev == ddp_comp[path[i]].dev)
 509                         return true;
 510
 511         return false;
 512 }
 513
 514 static unsigned int mtk_drm_find_comp_in_ddp_conn_path(struct device *dev,
 515                                                        const struct mtk_drm_route *routes,
 516                                                        unsigned int num_routes,
 517                                                        struct mtk_ddp_comp *ddp_comp)
 518 {
 519         int ret;
 520         unsigned int i;
 521
 522         if (!routes) {
 523                 ret = -EINVAL;
 524                 goto err;
 525         }
 526
 527         for (i = 0; i < num_routes; i++)
 528                 if (dev == ddp_comp[routes[i].route_ddp].dev)
 529                         return BIT(routes[i].crtc_id);
 530
 531         ret = -ENODEV;
 532 err:
 533
 534         DRM_INFO("Failed to find comp in ddp table, ret = %d\n", ret);
 535
 536         return 0;
 537 }
 538
 539 int mtk_ddp_comp_get_id(struct device_node *node,
 540                         enum mtk_ddp_comp_type comp_type)
 541 {
 542         int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
 543         int i;
 544
 545         for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
 546                 if (comp_type == mtk_ddp_matches[i].type &&
 547                     (id < 0 || id == mtk_ddp_matches[i].alias_id))
 548                         return i;
 549         }
 550
 551         return -EINVAL;
 552 }
 553
 554 unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
 555                                                 struct device *dev)
 556 {
 557         struct mtk_drm_private *private = drm->dev_private;
 558         unsigned int ret = 0;
 559
 560         if (mtk_drm_find_comp_in_ddp(dev, private->data->main_path, private->data->main_len,
 561                                      private->ddp_comp))
 562                 ret = BIT(0);
 563         else if (mtk_drm_find_comp_in_ddp(dev, private->data->ext_path,
 564                                           private->data->ext_len, private->ddp_comp))
 565                 ret = BIT(1);
 566         else if (mtk_drm_find_comp_in_ddp(dev, private->data->third_path,
 567                                           private->data->third_len, private->ddp_comp))
 568                 ret = BIT(2);
 569         else
 570                 ret = mtk_drm_find_comp_in_ddp_conn_path(dev,
 571                                                          private->data->conn_routes,
 572                                                          private->data->num_conn_routes,
 573                                                          private->ddp_comp);
 574
 575         return ret;
 576 }
 577
 578 int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 579                       unsigned int comp_id)
 580 {
 581         struct platform_device *comp_pdev;
 582         enum mtk_ddp_comp_type type;
 583         struct mtk_ddp_comp_dev *priv;
 584 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 585         int ret;
 586 #endif
 587
 588         if (comp_id < 0 || comp_id >= DDP_COMPONENT_DRM_ID_MAX)
 589                 return -EINVAL;
 590
 591         type = mtk_ddp_matches[comp_id].type;
 592
 593         comp->id = comp_id;
 594         comp->funcs = mtk_ddp_matches[comp_id].funcs;
 595         /* Not all drm components have a DTS device node, such as ovl_adaptor,
 596          * which is the drm bring up sub driver
 597          */
 598         if (!node)
 599                 return 0;
 600
 601         comp_pdev = of_find_device_by_node(node);
 602         if (!comp_pdev) {
 603                 DRM_INFO("Waiting for device %s\n", node->full_name);
 604                 return -EPROBE_DEFER;
 605         }
 606         comp->dev = &comp_pdev->dev;
 607
 608         if (type == MTK_DISP_AAL ||
 609             type == MTK_DISP_BLS ||
 610             type == MTK_DISP_CCORR ||
 611             type == MTK_DISP_COLOR ||
 612             type == MTK_DISP_GAMMA ||
 613             type == MTK_DISP_MERGE ||
 614             type == MTK_DISP_OVL ||
 615             type == MTK_DISP_OVL_2L ||
 616             type == MTK_DISP_PWM ||
 617             type == MTK_DISP_RDMA ||
 618             type == MTK_DPI ||
 619             type == MTK_DP_INTF ||
 620             type == MTK_DSI)
 621                 return 0;
 622
 623         priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
 624         if (!priv)
 625                 return -ENOMEM;
 626
 627         priv->regs = of_iomap(node, 0);
 628         priv->clk = of_clk_get(node, 0);
 629         if (IS_ERR(priv->clk))
 630                 return PTR_ERR(priv->clk);
 631
 632 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 633         ret = cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0);
 634         if (ret)
 635                 dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n");
 636 #endif
 637
 638         platform_set_drvdata(comp_pdev, priv);
 639
 640         return 0;
 641 }