1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
7 #include <linux/dma-mapping.h>
8 #include <linux/mailbox_controller.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
15 #include <asm/barrier.h>
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_probe_helper.h>
20 #include <drm/drm_vblank.h>
22 #include "mtk_drm_drv.h"
23 #include "mtk_drm_crtc.h"
24 #include "mtk_drm_ddp_comp.h"
25 #include "mtk_drm_gem.h"
26 #include "mtk_drm_plane.h"
29 * struct mtk_drm_crtc - MediaTek specific crtc structure.
31 * @enabled: records whether crtc_enable succeeded
32 * @planes: array of 4 drm_plane structures, one for each overlay plane
33 * @pending_planes: whether any plane has pending changes to be applied
34 * @mmsys_dev: pointer to the mmsys device for configuration registers
35 * @mutex: handle to one of the ten disp_mutex streams
36 * @ddp_comp_nr: number of components in ddp_comp
37 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
39 * TODO: Needs update: this header is missing a bunch of member descriptions.
45 bool pending_needs_vblank;
46 struct drm_pending_vblank_event *event;
48 struct drm_plane *planes;
49 unsigned int layer_nr;
51 bool pending_async_planes;
53 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
54 struct cmdq_client cmdq_client;
55 struct cmdq_pkt cmdq_handle;
58 wait_queue_head_t cb_blocking_queue;
61 struct device *mmsys_dev;
62 struct device *dma_dev;
63 struct mtk_mutex *mutex;
64 unsigned int ddp_comp_nr;
65 struct mtk_ddp_comp **ddp_comp;
66 unsigned int num_conn_routes;
67 const struct mtk_drm_route *conn_routes;
69 /* lock for display hardware access */
74 struct mtk_crtc_state {
75 struct drm_crtc_state base;
78 unsigned int pending_width;
79 unsigned int pending_height;
80 unsigned int pending_vrefresh;
83 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
85 return container_of(c, struct mtk_drm_crtc, base);
88 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
90 return container_of(s, struct mtk_crtc_state, base);
93 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
95 struct drm_crtc *crtc = &mtk_crtc->base;
98 spin_lock_irqsave(&crtc->dev->event_lock, flags);
99 drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
100 drm_crtc_vblank_put(crtc);
101 mtk_crtc->event = NULL;
102 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
105 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
107 drm_crtc_handle_vblank(&mtk_crtc->base);
108 if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
109 mtk_drm_crtc_finish_page_flip(mtk_crtc);
110 mtk_crtc->pending_needs_vblank = false;
114 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
115 static int mtk_drm_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,
121 pkt->va_base = kzalloc(size, GFP_KERNEL);
125 pkt->buf_size = size;
126 pkt->cl = (void *)client;
128 dev = client->chan->mbox->dev;
129 dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
131 if (dma_mapping_error(dev, dma_addr)) {
132 dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
137 pkt->pa_base = dma_addr;
142 static void mtk_drm_cmdq_pkt_destroy(struct cmdq_pkt *pkt)
144 struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
146 dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
152 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc)
154 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
157 mtk_mutex_put(mtk_crtc->mutex);
158 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
159 mtk_drm_cmdq_pkt_destroy(&mtk_crtc->cmdq_handle);
161 if (mtk_crtc->cmdq_client.chan) {
162 mbox_free_channel(mtk_crtc->cmdq_client.chan);
163 mtk_crtc->cmdq_client.chan = NULL;
167 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
168 struct mtk_ddp_comp *comp;
170 comp = mtk_crtc->ddp_comp[i];
171 mtk_ddp_comp_unregister_vblank_cb(comp);
174 drm_crtc_cleanup(crtc);
177 static void mtk_drm_crtc_reset(struct drm_crtc *crtc)
179 struct mtk_crtc_state *state;
182 __drm_atomic_helper_crtc_destroy_state(crtc->state);
184 kfree(to_mtk_crtc_state(crtc->state));
187 state = kzalloc(sizeof(*state), GFP_KERNEL);
189 __drm_atomic_helper_crtc_reset(crtc, &state->base);
192 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc)
194 struct mtk_crtc_state *state;
196 state = kmalloc(sizeof(*state), GFP_KERNEL);
200 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
202 WARN_ON(state->base.crtc != crtc);
203 state->base.crtc = crtc;
204 state->pending_config = false;
209 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
210 struct drm_crtc_state *state)
212 __drm_atomic_helper_crtc_destroy_state(state);
213 kfree(to_mtk_crtc_state(state));
216 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
217 const struct drm_display_mode *mode,
218 struct drm_display_mode *adjusted_mode)
220 /* Nothing to do here, but this callback is mandatory. */
224 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
226 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
228 state->pending_width = crtc->mode.hdisplay;
229 state->pending_height = crtc->mode.vdisplay;
230 state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
231 wmb(); /* Make sure the above parameters are set before update */
232 state->pending_config = true;
235 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
240 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
241 ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
243 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
251 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
255 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
259 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
260 mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
264 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
265 struct drm_plane *plane,
266 unsigned int *local_layer)
268 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
269 struct mtk_ddp_comp *comp;
271 unsigned int local_index = plane - mtk_crtc->planes;
273 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
274 comp = mtk_crtc->ddp_comp[i];
275 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
276 *local_layer = local_index - count;
279 count += mtk_ddp_comp_layer_nr(comp);
282 WARN(1, "Failed to find component for plane %d\n", plane->index);
286 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
287 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
289 struct cmdq_cb_data *data = mssg;
290 struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
291 struct mtk_drm_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_drm_crtc, cmdq_client);
292 struct mtk_crtc_state *state;
298 state = to_mtk_crtc_state(mtk_crtc->base.state);
300 state->pending_config = false;
302 if (mtk_crtc->pending_planes) {
303 for (i = 0; i < mtk_crtc->layer_nr; i++) {
304 struct drm_plane *plane = &mtk_crtc->planes[i];
305 struct mtk_plane_state *plane_state;
307 plane_state = to_mtk_plane_state(plane->state);
309 plane_state->pending.config = false;
311 mtk_crtc->pending_planes = false;
314 if (mtk_crtc->pending_async_planes) {
315 for (i = 0; i < mtk_crtc->layer_nr; i++) {
316 struct drm_plane *plane = &mtk_crtc->planes[i];
317 struct mtk_plane_state *plane_state;
319 plane_state = to_mtk_plane_state(plane->state);
321 plane_state->pending.async_config = false;
323 mtk_crtc->pending_async_planes = false;
326 mtk_crtc->cmdq_vblank_cnt = 0;
327 wake_up(&mtk_crtc->cb_blocking_queue);
331 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
333 struct drm_crtc *crtc = &mtk_crtc->base;
334 struct drm_connector *connector;
335 struct drm_encoder *encoder;
336 struct drm_connector_list_iter conn_iter;
337 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
341 if (WARN_ON(!crtc->state))
344 width = crtc->state->adjusted_mode.hdisplay;
345 height = crtc->state->adjusted_mode.vdisplay;
346 vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
348 drm_for_each_encoder(encoder, crtc->dev) {
349 if (encoder->crtc != crtc)
352 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
353 drm_for_each_connector_iter(connector, &conn_iter) {
354 if (connector->encoder != encoder)
356 if (connector->display_info.bpc != 0 &&
357 bpc > connector->display_info.bpc)
358 bpc = connector->display_info.bpc;
360 drm_connector_list_iter_end(&conn_iter);
363 ret = pm_runtime_resume_and_get(crtc->dev->dev);
365 DRM_ERROR("Failed to enable power domain: %d\n", ret);
369 ret = mtk_mutex_prepare(mtk_crtc->mutex);
371 DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
372 goto err_pm_runtime_put;
375 ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
377 DRM_ERROR("Failed to enable component clocks: %d\n", ret);
378 goto err_mutex_unprepare;
381 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
382 if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
383 mtk_crtc->ddp_comp[i + 1]->id))
384 mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
385 mtk_crtc->ddp_comp[i]->id,
386 mtk_crtc->ddp_comp[i + 1]->id);
387 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
388 mtk_mutex_add_comp(mtk_crtc->mutex,
389 mtk_crtc->ddp_comp[i]->id);
391 if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
392 mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
393 mtk_mutex_enable(mtk_crtc->mutex);
395 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
396 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
399 mtk_ddp_comp_bgclr_in_on(comp);
401 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
402 mtk_ddp_comp_start(comp);
405 /* Initially configure all planes */
406 for (i = 0; i < mtk_crtc->layer_nr; i++) {
407 struct drm_plane *plane = &mtk_crtc->planes[i];
408 struct mtk_plane_state *plane_state;
409 struct mtk_ddp_comp *comp;
410 unsigned int local_layer;
412 plane_state = to_mtk_plane_state(plane->state);
414 /* should not enable layer before crtc enabled */
415 plane_state->pending.enable = false;
416 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
418 mtk_ddp_comp_layer_config(comp, local_layer,
425 mtk_mutex_unprepare(mtk_crtc->mutex);
427 pm_runtime_put(crtc->dev->dev);
431 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
433 struct drm_device *drm = mtk_crtc->base.dev;
434 struct drm_crtc *crtc = &mtk_crtc->base;
437 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
438 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
440 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
443 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
444 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
445 mtk_mutex_remove_comp(mtk_crtc->mutex,
446 mtk_crtc->ddp_comp[i]->id);
447 mtk_mutex_disable(mtk_crtc->mutex);
448 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
449 if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
450 mtk_crtc->ddp_comp[i + 1]->id))
451 mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
452 mtk_crtc->ddp_comp[i]->id,
453 mtk_crtc->ddp_comp[i + 1]->id);
454 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
455 mtk_mutex_remove_comp(mtk_crtc->mutex,
456 mtk_crtc->ddp_comp[i]->id);
458 if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
459 mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
460 mtk_crtc_ddp_clk_disable(mtk_crtc);
461 mtk_mutex_unprepare(mtk_crtc->mutex);
463 pm_runtime_put(drm->dev);
465 if (crtc->state->event && !crtc->state->active) {
466 spin_lock_irq(&crtc->dev->event_lock);
467 drm_crtc_send_vblank_event(crtc, crtc->state->event);
468 crtc->state->event = NULL;
469 spin_unlock_irq(&crtc->dev->event_lock);
473 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
474 struct cmdq_pkt *cmdq_handle)
476 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
477 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
478 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
480 unsigned int local_layer;
483 * TODO: instead of updating the registers here, we should prepare
484 * working registers in atomic_commit and let the hardware command
485 * queue update module registers on vblank.
487 if (state->pending_config) {
488 mtk_ddp_comp_config(comp, state->pending_width,
489 state->pending_height,
490 state->pending_vrefresh, 0,
494 state->pending_config = false;
497 if (mtk_crtc->pending_planes) {
498 for (i = 0; i < mtk_crtc->layer_nr; i++) {
499 struct drm_plane *plane = &mtk_crtc->planes[i];
500 struct mtk_plane_state *plane_state;
502 plane_state = to_mtk_plane_state(plane->state);
504 if (!plane_state->pending.config)
507 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
511 mtk_ddp_comp_layer_config(comp, local_layer,
515 plane_state->pending.config = false;
519 mtk_crtc->pending_planes = false;
522 if (mtk_crtc->pending_async_planes) {
523 for (i = 0; i < mtk_crtc->layer_nr; i++) {
524 struct drm_plane *plane = &mtk_crtc->planes[i];
525 struct mtk_plane_state *plane_state;
527 plane_state = to_mtk_plane_state(plane->state);
529 if (!plane_state->pending.async_config)
532 comp = mtk_drm_ddp_comp_for_plane(crtc, plane,
536 mtk_ddp_comp_layer_config(comp, local_layer,
540 plane_state->pending.async_config = false;
544 mtk_crtc->pending_async_planes = false;
548 static void mtk_drm_crtc_update_config(struct mtk_drm_crtc *mtk_crtc,
551 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
552 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
554 struct drm_crtc *crtc = &mtk_crtc->base;
555 struct mtk_drm_private *priv = crtc->dev->dev_private;
556 unsigned int pending_planes = 0, pending_async_planes = 0;
559 mutex_lock(&mtk_crtc->hw_lock);
560 mtk_crtc->config_updating = true;
562 mtk_crtc->pending_needs_vblank = true;
564 for (i = 0; i < mtk_crtc->layer_nr; i++) {
565 struct drm_plane *plane = &mtk_crtc->planes[i];
566 struct mtk_plane_state *plane_state;
568 plane_state = to_mtk_plane_state(plane->state);
569 if (plane_state->pending.dirty) {
570 plane_state->pending.config = true;
571 plane_state->pending.dirty = false;
572 pending_planes |= BIT(i);
573 } else if (plane_state->pending.async_dirty) {
574 plane_state->pending.async_config = true;
575 plane_state->pending.async_dirty = false;
576 pending_async_planes |= BIT(i);
580 mtk_crtc->pending_planes = true;
581 if (pending_async_planes)
582 mtk_crtc->pending_async_planes = true;
584 if (priv->data->shadow_register) {
585 mtk_mutex_acquire(mtk_crtc->mutex);
586 mtk_crtc_ddp_config(crtc, NULL);
587 mtk_mutex_release(mtk_crtc->mutex);
589 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
590 if (mtk_crtc->cmdq_client.chan) {
591 mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
592 cmdq_handle->cmd_buf_size = 0;
593 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
594 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
595 mtk_crtc_ddp_config(crtc, cmdq_handle);
596 cmdq_pkt_finalize(cmdq_handle);
597 dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
598 cmdq_handle->pa_base,
599 cmdq_handle->cmd_buf_size,
602 * CMDQ command should execute in next 3 vblank.
603 * One vblank interrupt before send message (occasionally)
604 * and one vblank interrupt after cmdq done,
605 * so it's timeout after 3 vblank interrupt.
606 * If it fail to execute in next 3 vblank, timeout happen.
608 mtk_crtc->cmdq_vblank_cnt = 3;
610 mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
611 mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
614 mtk_crtc->config_updating = false;
615 mutex_unlock(&mtk_crtc->hw_lock);
618 static void mtk_crtc_ddp_irq(void *data)
620 struct drm_crtc *crtc = data;
621 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
622 struct mtk_drm_private *priv = crtc->dev->dev_private;
624 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
625 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
626 mtk_crtc_ddp_config(crtc, NULL);
627 else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
628 DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
629 drm_crtc_index(&mtk_crtc->base));
631 if (!priv->data->shadow_register)
632 mtk_crtc_ddp_config(crtc, NULL);
634 mtk_drm_finish_page_flip(mtk_crtc);
637 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
639 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
640 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
642 mtk_ddp_comp_enable_vblank(comp);
647 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
649 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
650 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
652 mtk_ddp_comp_disable_vblank(comp);
655 static void mtk_drm_crtc_update_output(struct drm_crtc *crtc,
656 struct drm_atomic_state *state)
658 int crtc_index = drm_crtc_index(crtc);
661 struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
662 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
663 struct mtk_drm_private *priv;
664 unsigned int encoder_mask = crtc_state->encoder_mask;
666 if (!crtc_state->connectors_changed)
669 if (!mtk_crtc->num_conn_routes)
672 priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[crtc_index];
675 dev_dbg(dev, "connector change:%d, encoder mask:0x%x for crtc:%d\n",
676 crtc_state->connectors_changed, encoder_mask, crtc_index);
678 for (i = 0; i < mtk_crtc->num_conn_routes; i++) {
679 unsigned int comp_id = mtk_crtc->conn_routes[i].route_ddp;
680 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
682 if (comp->encoder_index >= 0 &&
683 (encoder_mask & BIT(comp->encoder_index))) {
684 mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
685 dev_dbg(dev, "Add comp_id: %d at path index %d\n",
686 comp->id, mtk_crtc->ddp_comp_nr - 1);
692 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
693 struct mtk_plane_state *state)
695 unsigned int local_layer;
696 struct mtk_ddp_comp *comp;
698 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
700 return mtk_ddp_comp_layer_check(comp, local_layer, state);
704 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
705 struct drm_atomic_state *state)
707 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
709 if (!mtk_crtc->enabled)
712 mtk_drm_crtc_update_config(mtk_crtc, false);
715 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
716 struct drm_atomic_state *state)
718 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
719 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
722 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
724 ret = pm_runtime_resume_and_get(comp->dev);
726 DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
730 mtk_drm_crtc_update_output(crtc, state);
732 ret = mtk_crtc_ddp_hw_init(mtk_crtc);
734 pm_runtime_put(comp->dev);
738 drm_crtc_vblank_on(crtc);
739 mtk_crtc->enabled = true;
742 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc,
743 struct drm_atomic_state *state)
745 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
746 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
749 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
750 if (!mtk_crtc->enabled)
753 /* Set all pending plane state to disabled */
754 for (i = 0; i < mtk_crtc->layer_nr; i++) {
755 struct drm_plane *plane = &mtk_crtc->planes[i];
756 struct mtk_plane_state *plane_state;
758 plane_state = to_mtk_plane_state(plane->state);
759 plane_state->pending.enable = false;
760 plane_state->pending.config = true;
762 mtk_crtc->pending_planes = true;
764 mtk_drm_crtc_update_config(mtk_crtc, false);
765 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
766 /* Wait for planes to be disabled by cmdq */
767 if (mtk_crtc->cmdq_client.chan)
768 wait_event_timeout(mtk_crtc->cb_blocking_queue,
769 mtk_crtc->cmdq_vblank_cnt == 0,
770 msecs_to_jiffies(500));
772 /* Wait for planes to be disabled */
773 drm_crtc_wait_one_vblank(crtc);
775 drm_crtc_vblank_off(crtc);
776 mtk_crtc_ddp_hw_fini(mtk_crtc);
777 ret = pm_runtime_put(comp->dev);
779 DRM_DEV_ERROR(comp->dev, "Failed to disable power domain: %d\n", ret);
781 mtk_crtc->enabled = false;
784 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
785 struct drm_atomic_state *state)
787 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
789 struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
790 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
793 if (mtk_crtc->event && mtk_crtc_state->base.event)
794 DRM_ERROR("new event while there is still a pending event\n");
796 if (mtk_crtc_state->base.event) {
797 mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
798 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
800 spin_lock_irqsave(&crtc->dev->event_lock, flags);
801 mtk_crtc->event = mtk_crtc_state->base.event;
802 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
804 mtk_crtc_state->base.event = NULL;
808 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
809 struct drm_atomic_state *state)
811 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
814 if (crtc->state->color_mgmt_changed)
815 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
816 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
817 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
819 mtk_drm_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
822 static const struct drm_crtc_funcs mtk_crtc_funcs = {
823 .set_config = drm_atomic_helper_set_config,
824 .page_flip = drm_atomic_helper_page_flip,
825 .destroy = mtk_drm_crtc_destroy,
826 .reset = mtk_drm_crtc_reset,
827 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state,
828 .atomic_destroy_state = mtk_drm_crtc_destroy_state,
829 .enable_vblank = mtk_drm_crtc_enable_vblank,
830 .disable_vblank = mtk_drm_crtc_disable_vblank,
833 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
834 .mode_fixup = mtk_drm_crtc_mode_fixup,
835 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
836 .atomic_begin = mtk_drm_crtc_atomic_begin,
837 .atomic_flush = mtk_drm_crtc_atomic_flush,
838 .atomic_enable = mtk_drm_crtc_atomic_enable,
839 .atomic_disable = mtk_drm_crtc_atomic_disable,
842 static int mtk_drm_crtc_init(struct drm_device *drm,
843 struct mtk_drm_crtc *mtk_crtc,
846 struct drm_plane *primary = NULL;
847 struct drm_plane *cursor = NULL;
850 for (i = 0; i < mtk_crtc->layer_nr; i++) {
851 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
852 primary = &mtk_crtc->planes[i];
853 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
854 cursor = &mtk_crtc->planes[i];
857 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
858 &mtk_crtc_funcs, NULL);
860 goto err_cleanup_crtc;
862 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
867 drm_crtc_cleanup(&mtk_crtc->base);
871 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
874 struct mtk_ddp_comp *comp;
879 comp = mtk_crtc->ddp_comp[comp_idx];
883 if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
886 return mtk_ddp_comp_layer_nr(comp);
890 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx,
891 unsigned int num_planes)
894 return DRM_PLANE_TYPE_PRIMARY;
895 else if (plane_idx == (num_planes - 1))
896 return DRM_PLANE_TYPE_CURSOR;
898 return DRM_PLANE_TYPE_OVERLAY;
902 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev,
903 struct mtk_drm_crtc *mtk_crtc,
904 int comp_idx, int pipe)
906 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx);
907 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
910 for (i = 0; i < num_planes; i++) {
911 ret = mtk_plane_init(drm_dev,
912 &mtk_crtc->planes[mtk_crtc->layer_nr],
914 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr,
916 mtk_ddp_comp_supported_rotations(comp),
917 mtk_ddp_comp_get_formats(comp),
918 mtk_ddp_comp_get_num_formats(comp));
922 mtk_crtc->layer_nr++;
927 struct device *mtk_drm_crtc_dma_dev_get(struct drm_crtc *crtc)
929 struct mtk_drm_crtc *mtk_crtc = NULL;
934 mtk_crtc = to_mtk_crtc(crtc);
938 return mtk_crtc->dma_dev;
941 int mtk_drm_crtc_create(struct drm_device *drm_dev,
942 const unsigned int *path, unsigned int path_len,
943 int priv_data_index, const struct mtk_drm_route *conn_routes,
944 unsigned int num_conn_routes)
946 struct mtk_drm_private *priv = drm_dev->dev_private;
947 struct device *dev = drm_dev->dev;
948 struct mtk_drm_crtc *mtk_crtc;
949 unsigned int num_comp_planes = 0;
952 bool has_ctm = false;
953 uint gamma_lut_size = 0;
954 struct drm_crtc *tmp;
960 priv = priv->all_drm_private[priv_data_index];
962 drm_for_each_crtc(tmp, drm_dev)
965 for (i = 0; i < path_len; i++) {
966 enum mtk_ddp_comp_id comp_id = path[i];
967 struct device_node *node;
968 struct mtk_ddp_comp *comp;
970 node = priv->comp_node[comp_id];
971 comp = &priv->ddp_comp[comp_id];
973 /* Not all drm components have a DTS device node, such as ovl_adaptor,
974 * which is the drm bring up sub driver
976 if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
978 "Not creating crtc %d because component %d is disabled or missing\n",
984 dev_err(dev, "Component %pOF not initialized\n", node);
989 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
993 mtk_crtc->mmsys_dev = priv->mmsys_dev;
994 mtk_crtc->ddp_comp_nr = path_len;
995 mtk_crtc->ddp_comp = devm_kmalloc_array(dev,
996 mtk_crtc->ddp_comp_nr + (conn_routes ? 1 : 0),
997 sizeof(*mtk_crtc->ddp_comp),
999 if (!mtk_crtc->ddp_comp)
1002 mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
1003 if (IS_ERR(mtk_crtc->mutex)) {
1004 ret = PTR_ERR(mtk_crtc->mutex);
1005 dev_err(dev, "Failed to get mutex: %d\n", ret);
1009 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1010 unsigned int comp_id = path[i];
1011 struct mtk_ddp_comp *comp;
1013 comp = &priv->ddp_comp[comp_id];
1014 mtk_crtc->ddp_comp[i] = comp;
1017 if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
1018 unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp);
1021 gamma_lut_size = lut_sz;
1024 if (comp->funcs->ctm_set)
1028 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq,
1032 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
1033 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i);
1035 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
1036 sizeof(struct drm_plane), GFP_KERNEL);
1037 if (!mtk_crtc->planes)
1040 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1041 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i,
1048 * Default to use the first component as the dma dev.
1049 * In the case of ovl_adaptor sub driver, it needs to use the
1050 * dma_dev_get function to get representative dma dev.
1052 mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]);
1054 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, crtc_i);
1059 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
1060 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
1061 mutex_init(&mtk_crtc->hw_lock);
1063 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
1064 i = priv->mbox_index++;
1065 mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
1066 mtk_crtc->cmdq_client.client.tx_block = false;
1067 mtk_crtc->cmdq_client.client.knows_txdone = true;
1068 mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
1069 mtk_crtc->cmdq_client.chan =
1070 mbox_request_channel(&mtk_crtc->cmdq_client.client, i);
1071 if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
1072 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
1073 drm_crtc_index(&mtk_crtc->base));
1074 mtk_crtc->cmdq_client.chan = NULL;
1077 if (mtk_crtc->cmdq_client.chan) {
1078 ret = of_property_read_u32_index(priv->mutex_node,
1079 "mediatek,gce-events",
1081 &mtk_crtc->cmdq_event);
1083 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
1084 drm_crtc_index(&mtk_crtc->base));
1085 mbox_free_channel(mtk_crtc->cmdq_client.chan);
1086 mtk_crtc->cmdq_client.chan = NULL;
1088 ret = mtk_drm_cmdq_pkt_create(&mtk_crtc->cmdq_client,
1089 &mtk_crtc->cmdq_handle,
1092 dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
1093 drm_crtc_index(&mtk_crtc->base));
1094 mbox_free_channel(mtk_crtc->cmdq_client.chan);
1095 mtk_crtc->cmdq_client.chan = NULL;
1099 /* for sending blocking cmd in crtc disable */
1100 init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
1105 for (i = 0; i < num_conn_routes; i++) {
1106 unsigned int comp_id = conn_routes[i].route_ddp;
1107 struct device_node *node = priv->comp_node[comp_id];
1108 struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
1111 dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
1113 /* mark encoder_index to -1, if route comp device is not enabled */
1114 comp->encoder_index = -1;
1118 mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]);
1121 mtk_crtc->num_conn_routes = num_conn_routes;
1122 mtk_crtc->conn_routes = conn_routes;
1124 /* increase ddp_comp_nr at the end of mtk_drm_crtc_create */
1125 mtk_crtc->ddp_comp_nr++;