drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/list_sort.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_ras.h"
  35 #include "amdgpu_atomfirmware.h"
  36 #include "amdgpu_xgmi.h"
  37 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  38 #include "nbio_v4_3.h"
  39 #include "nbio_v7_9.h"
  40 #include "atom.h"
  41 #include "amdgpu_reset.h"
  42
  43 #ifdef CONFIG_X86_MCE_AMD
  44 #include <asm/mce.h>
  45
  46 static bool notifier_registered;
  47 #endif
  48 static const char *RAS_FS_NAME = "ras";
  49
  50 const char *ras_error_string[] = {
  51         "none",
  52         "parity",
  53         "single_correctable",
  54         "multi_uncorrectable",
  55         "poison",
  56 };
  57
  58 const char *ras_block_string[] = {
  59         "umc",
  60         "sdma",
  61         "gfx",
  62         "mmhub",
  63         "athub",
  64         "pcie_bif",
  65         "hdp",
  66         "xgmi_wafl",
  67         "df",
  68         "smn",
  69         "sem",
  70         "mp0",
  71         "mp1",
  72         "fuse",
  73         "mca",
  74         "vcn",
  75         "jpeg",
  76 };
  77
  78 const char *ras_mca_block_string[] = {
  79         "mca_mp0",
  80         "mca_mp1",
  81         "mca_mpio",
  82         "mca_iohc",
  83 };
  84
  85 struct amdgpu_ras_block_list {
  86         /* ras block link */
  87         struct list_head node;
  88
  89         struct amdgpu_ras_block_object *ras_obj;
  90 };
  91
  92 const char *get_ras_block_str(struct ras_common_if *ras_block)
  93 {
  94         if (!ras_block)
  95                 return "NULL";
  96
  97         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  98                 return "OUT OF RANGE";
  99
 100         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
 101                 return ras_mca_block_string[ras_block->sub_block_index];
 102
 103         return ras_block_string[ras_block->block];
 104 }
 105
 106 #define ras_block_str(_BLOCK_) \
 107         (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
 108
 109 #define ras_err_str(i) (ras_error_string[ffs(i)])
 110
 111 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
 112
 113 /* inject address is 52 bits */
 114 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
 115
 116 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 117 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 118
 119 enum amdgpu_ras_retire_page_reservation {
 120         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 121         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 122         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 123 };
 124
 125 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 126
 127 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 128                                 uint64_t addr);
 129 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 130                                 uint64_t addr);
 131 #ifdef CONFIG_X86_MCE_AMD
 132 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 133 struct mce_notifier_adev_list {
 134         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 135         int num_gpu;
 136 };
 137 static struct mce_notifier_adev_list mce_adev_list;
 138 #endif
 139
 140 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 141 {
 142         if (adev && amdgpu_ras_get_context(adev))
 143                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 144 }
 145
 146 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 147 {
 148         if (adev && amdgpu_ras_get_context(adev))
 149                 return amdgpu_ras_get_context(adev)->error_query_ready;
 150
 151         return false;
 152 }
 153
 154 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 155 {
 156         struct ras_err_data err_data;
 157         struct eeprom_table_record err_rec;
 158         int ret;
 159
 160         if ((address >= adev->gmc.mc_vram_size) ||
 161             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 162                 dev_warn(adev->dev,
 163                          "RAS WARN: input address 0x%llx is invalid.\n",
 164                          address);
 165                 return -EINVAL;
 166         }
 167
 168         if (amdgpu_ras_check_bad_page(adev, address)) {
 169                 dev_warn(adev->dev,
 170                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 171                          address);
 172                 return 0;
 173         }
 174
 175         ret = amdgpu_ras_error_data_init(&err_data);
 176         if (ret)
 177                 return ret;
 178
 179         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 180         err_data.err_addr = &err_rec;
 181         amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
 182
 183         if (amdgpu_bad_page_threshold != 0) {
 184                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 185                                          err_data.err_addr_cnt);
 186                 amdgpu_ras_save_bad_pages(adev, NULL);
 187         }
 188
 189         amdgpu_ras_error_data_fini(&err_data);
 190
 191         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 192         dev_warn(adev->dev, "Clear EEPROM:\n");
 193         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 194
 195         return 0;
 196 }
 197
 198 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 199                                         size_t size, loff_t *pos)
 200 {
 201         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 202         struct ras_query_if info = {
 203                 .head = obj->head,
 204         };
 205         ssize_t s;
 206         char val[128];
 207
 208         if (amdgpu_ras_query_error_status(obj->adev, &info))
 209                 return -EINVAL;
 210
 211         /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
 212         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 213             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 214                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 215                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 216         }
 217
 218         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 219                         "ue", info.ue_count,
 220                         "ce", info.ce_count);
 221         if (*pos >= s)
 222                 return 0;
 223
 224         s -= *pos;
 225         s = min_t(u64, s, size);
 226
 227
 228         if (copy_to_user(buf, &val[*pos], s))
 229                 return -EINVAL;
 230
 231         *pos += s;
 232
 233         return s;
 234 }
 235
 236 static const struct file_operations amdgpu_ras_debugfs_ops = {
 237         .owner = THIS_MODULE,
 238         .read = amdgpu_ras_debugfs_read,
 239         .write = NULL,
 240         .llseek = default_llseek
 241 };
 242
 243 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 244 {
 245         int i;
 246
 247         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 248                 *block_id = i;
 249                 if (strcmp(name, ras_block_string[i]) == 0)
 250                         return 0;
 251         }
 252         return -EINVAL;
 253 }
 254
 255 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 256                 const char __user *buf, size_t size,
 257                 loff_t *pos, struct ras_debug_if *data)
 258 {
 259         ssize_t s = min_t(u64, 64, size);
 260         char str[65];
 261         char block_name[33];
 262         char err[9] = "ue";
 263         int op = -1;
 264         int block_id;
 265         uint32_t sub_block;
 266         u64 address, value;
 267         /* default value is 0 if the mask is not set by user */
 268         u32 instance_mask = 0;
 269
 270         if (*pos)
 271                 return -EINVAL;
 272         *pos = size;
 273
 274         memset(str, 0, sizeof(str));
 275         memset(data, 0, sizeof(*data));
 276
 277         if (copy_from_user(str, buf, s))
 278                 return -EINVAL;
 279
 280         if (sscanf(str, "disable %32s", block_name) == 1)
 281                 op = 0;
 282         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 283                 op = 1;
 284         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 285                 op = 2;
 286         else if (strstr(str, "retire_page") != NULL)
 287                 op = 3;
 288         else if (str[0] && str[1] && str[2] && str[3])
 289                 /* ascii string, but commands are not matched. */
 290                 return -EINVAL;
 291
 292         if (op != -1) {
 293                 if (op == 3) {
 294                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 295                             sscanf(str, "%*s %llu", &address) != 1)
 296                                 return -EINVAL;
 297
 298                         data->op = op;
 299                         data->inject.address = address;
 300
 301                         return 0;
 302                 }
 303
 304                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 305                         return -EINVAL;
 306
 307                 data->head.block = block_id;
 308                 /* only ue and ce errors are supported */
 309                 if (!memcmp("ue", err, 2))
 310                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 311                 else if (!memcmp("ce", err, 2))
 312                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 313                 else
 314                         return -EINVAL;
 315
 316                 data->op = op;
 317
 318                 if (op == 2) {
 319                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
 320                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 321                             sscanf(str, "%*s %*s %*s %u %llu %llu %u",
 322                                    &sub_block, &address, &value, &instance_mask) != 4 &&
 323                                 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 324                                    &sub_block, &address, &value) != 3 &&
 325                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 326                                    &sub_block, &address, &value) != 3)
 327                                 return -EINVAL;
 328                         data->head.sub_block_index = sub_block;
 329                         data->inject.address = address;
 330                         data->inject.value = value;
 331                         data->inject.instance_mask = instance_mask;
 332                 }
 333         } else {
 334                 if (size < sizeof(*data))
 335                         return -EINVAL;
 336
 337                 if (copy_from_user(data, buf, sizeof(*data)))
 338                         return -EINVAL;
 339         }
 340
 341         return 0;
 342 }
 343
 344 static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
 345                                 struct ras_debug_if *data)
 346 {
 347         int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 348         uint32_t mask, inst_mask = data->inject.instance_mask;
 349
 350         /* no need to set instance mask if there is only one instance */
 351         if (num_xcc <= 1 && inst_mask) {
 352                 data->inject.instance_mask = 0;
 353                 dev_dbg(adev->dev,
 354                         "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
 355                         inst_mask);
 356
 357                 return;
 358         }
 359
 360         switch (data->head.block) {
 361         case AMDGPU_RAS_BLOCK__GFX:
 362                 mask = GENMASK(num_xcc - 1, 0);
 363                 break;
 364         case AMDGPU_RAS_BLOCK__SDMA:
 365                 mask = GENMASK(adev->sdma.num_instances - 1, 0);
 366                 break;
 367         case AMDGPU_RAS_BLOCK__VCN:
 368         case AMDGPU_RAS_BLOCK__JPEG:
 369                 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
 370                 break;
 371         default:
 372                 mask = inst_mask;
 373                 break;
 374         }
 375
 376         /* remove invalid bits in instance mask */
 377         data->inject.instance_mask &= mask;
 378         if (inst_mask != data->inject.instance_mask)
 379                 dev_dbg(adev->dev,
 380                         "Adjust RAS inject mask 0x%x to 0x%x\n",
 381                         inst_mask, data->inject.instance_mask);
 382 }
 383
 384 /**
 385  * DOC: AMDGPU RAS debugfs control interface
 386  *
 387  * The control interface accepts struct ras_debug_if which has two members.
 388  *
 389  * First member: ras_debug_if::head or ras_debug_if::inject.
 390  *
 391  * head is used to indicate which IP block will be under control.
 392  *
 393  * head has four members, they are block, type, sub_block_index, name.
 394  * block: which IP will be under control.
 395  * type: what kind of error will be enabled/disabled/injected.
 396  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 397  * name: the name of IP.
 398  *
 399  * inject has three more members than head, they are address, value and mask.
 400  * As their names indicate, inject operation will write the
 401  * value to the address.
 402  *
 403  * The second member: struct ras_debug_if::op.
 404  * It has three kinds of operations.
 405  *
 406  * - 0: disable RAS on the block. Take ::head as its data.
 407  * - 1: enable RAS on the block. Take ::head as its data.
 408  * - 2: inject errors on the block. Take ::inject as its data.
 409  *
 410  * How to use the interface?
 411  *
 412  * In a program
 413  *
 414  * Copy the struct ras_debug_if in your code and initialize it.
 415  * Write the struct to the control interface.
 416  *
 417  * From shell
 418  *
 419  * .. code-block:: bash
 420  *
 421  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 422  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 423  *      echo "inject  <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 424  *
 425  * Where N, is the card which you want to affect.
 426  *
 427  * "disable" requires only the block.
 428  * "enable" requires the block and error type.
 429  * "inject" requires the block, error type, address, and value.
 430  *
 431  * The block is one of: umc, sdma, gfx, etc.
 432  *      see ras_block_string[] for details
 433  *
 434  * The error type is one of: ue, ce, where,
 435  *      ue is multi-uncorrectable
 436  *      ce is single-correctable
 437  *
 438  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 439  * The address and value are hexadecimal numbers, leading 0x is optional.
 440  * The mask means instance mask, is optional, default value is 0x1.
 441  *
 442  * For instance,
 443  *
 444  * .. code-block:: bash
 445  *
 446  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 447  *      echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 448  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 449  *
 450  * How to check the result of the operation?
 451  *
 452  * To check disable/enable, see "ras" features at,
 453  * /sys/class/drm/card[0/1/2...]/device/ras/features
 454  *
 455  * To check inject, see the corresponding error count at,
 456  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 457  *
 458  * .. note::
 459  *      Operations are only allowed on blocks which are supported.
 460  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 461  *      to see which blocks support RAS on a particular asic.
 462  *
 463  */
 464 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 465                                              const char __user *buf,
 466                                              size_t size, loff_t *pos)
 467 {
 468         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 469         struct ras_debug_if data;
 470         int ret = 0;
 471
 472         if (!amdgpu_ras_get_error_query_ready(adev)) {
 473                 dev_warn(adev->dev, "RAS WARN: error injection "
 474                                 "currently inaccessible\n");
 475                 return size;
 476         }
 477
 478         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 479         if (ret)
 480                 return ret;
 481
 482         if (data.op == 3) {
 483                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 484                 if (!ret)
 485                         return size;
 486                 else
 487                         return ret;
 488         }
 489
 490         if (!amdgpu_ras_is_supported(adev, data.head.block))
 491                 return -EINVAL;
 492
 493         switch (data.op) {
 494         case 0:
 495                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 496                 break;
 497         case 1:
 498                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 499                 break;
 500         case 2:
 501                 if ((data.inject.address >= adev->gmc.mc_vram_size &&
 502                     adev->gmc.mc_vram_size) ||
 503                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 504                         dev_warn(adev->dev, "RAS WARN: input address "
 505                                         "0x%llx is invalid.",
 506                                         data.inject.address);
 507                         ret = -EINVAL;
 508                         break;
 509                 }
 510
 511                 /* umc ce/ue error injection for a bad page is not allowed */
 512                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 513                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 514                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 515                                  "already been marked as bad!\n",
 516                                  data.inject.address);
 517                         break;
 518                 }
 519
 520                 amdgpu_ras_instance_mask_check(adev, &data);
 521
 522                 /* data.inject.address is offset instead of absolute gpu address */
 523                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 524                 break;
 525         default:
 526                 ret = -EINVAL;
 527                 break;
 528         }
 529
 530         if (ret)
 531                 return ret;
 532
 533         return size;
 534 }
 535
 536 /**
 537  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 538  *
 539  * Some boards contain an EEPROM which is used to persistently store a list of
 540  * bad pages which experiences ECC errors in vram.  This interface provides
 541  * a way to reset the EEPROM, e.g., after testing error injection.
 542  *
 543  * Usage:
 544  *
 545  * .. code-block:: bash
 546  *
 547  *      echo 1 > ../ras/ras_eeprom_reset
 548  *
 549  * will reset EEPROM table to 0 entries.
 550  *
 551  */
 552 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 553                                                const char __user *buf,
 554                                                size_t size, loff_t *pos)
 555 {
 556         struct amdgpu_device *adev =
 557                 (struct amdgpu_device *)file_inode(f)->i_private;
 558         int ret;
 559
 560         ret = amdgpu_ras_eeprom_reset_table(
 561                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 562
 563         if (!ret) {
 564                 /* Something was written to EEPROM.
 565                  */
 566                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 567                 return size;
 568         } else {
 569                 return ret;
 570         }
 571 }
 572
 573 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 574         .owner = THIS_MODULE,
 575         .read = NULL,
 576         .write = amdgpu_ras_debugfs_ctrl_write,
 577         .llseek = default_llseek
 578 };
 579
 580 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 581         .owner = THIS_MODULE,
 582         .read = NULL,
 583         .write = amdgpu_ras_debugfs_eeprom_write,
 584         .llseek = default_llseek
 585 };
 586
 587 /**
 588  * DOC: AMDGPU RAS sysfs Error Count Interface
 589  *
 590  * It allows the user to read the error count for each IP block on the gpu through
 591  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 592  *
 593  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 594  * (ce) error counts.
 595  *
 596  * The format of one line is below,
 597  *
 598  * [ce|ue]: count
 599  *
 600  * Example:
 601  *
 602  * .. code-block:: bash
 603  *
 604  *      ue: 0
 605  *      ce: 1
 606  *
 607  */
 608 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 609                 struct device_attribute *attr, char *buf)
 610 {
 611         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 612         struct ras_query_if info = {
 613                 .head = obj->head,
 614         };
 615
 616         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 617                 return sysfs_emit(buf, "Query currently inaccessible\n");
 618
 619         if (amdgpu_ras_query_error_status(obj->adev, &info))
 620                 return -EINVAL;
 621
 622         if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
 623             amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
 624                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 625                         dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
 626         }
 627
 628         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 629                           "ce", info.ce_count);
 630 }
 631
 632 /* obj begin */
 633
 634 #define get_obj(obj) do { (obj)->use++; } while (0)
 635 #define alive_obj(obj) ((obj)->use)
 636
 637 static inline void put_obj(struct ras_manager *obj)
 638 {
 639         if (obj && (--obj->use == 0)) {
 640                 list_del(&obj->node);
 641                 amdgpu_ras_error_data_fini(&obj->err_data);
 642         }
 643
 644         if (obj && (obj->use < 0))
 645                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 646 }
 647
 648 /* make one obj and return it. */
 649 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 650                 struct ras_common_if *head)
 651 {
 652         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 653         struct ras_manager *obj;
 654
 655         if (!adev->ras_enabled || !con)
 656                 return NULL;
 657
 658         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 659                 return NULL;
 660
 661         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 662                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 663                         return NULL;
 664
 665                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 666         } else
 667                 obj = &con->objs[head->block];
 668
 669         /* already exist. return obj? */
 670         if (alive_obj(obj))
 671                 return NULL;
 672
 673         if (amdgpu_ras_error_data_init(&obj->err_data))
 674                 return NULL;
 675
 676         obj->head = *head;
 677         obj->adev = adev;
 678         list_add(&obj->node, &con->head);
 679         get_obj(obj);
 680
 681         return obj;
 682 }
 683
 684 /* return an obj equal to head, or the first when head is NULL */
 685 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 686                 struct ras_common_if *head)
 687 {
 688         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 689         struct ras_manager *obj;
 690         int i;
 691
 692         if (!adev->ras_enabled || !con)
 693                 return NULL;
 694
 695         if (head) {
 696                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 697                         return NULL;
 698
 699                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 700                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 701                                 return NULL;
 702
 703                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 704                 } else
 705                         obj = &con->objs[head->block];
 706
 707                 if (alive_obj(obj))
 708                         return obj;
 709         } else {
 710                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 711                         obj = &con->objs[i];
 712                         if (alive_obj(obj))
 713                                 return obj;
 714                 }
 715         }
 716
 717         return NULL;
 718 }
 719 /* obj end */
 720
 721 /* feature ctl begin */
 722 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 723                                          struct ras_common_if *head)
 724 {
 725         return adev->ras_hw_enabled & BIT(head->block);
 726 }
 727
 728 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 729                 struct ras_common_if *head)
 730 {
 731         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 732
 733         return con->features & BIT(head->block);
 734 }
 735
 736 /*
 737  * if obj is not created, then create one.
 738  * set feature enable flag.
 739  */
 740 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 741                 struct ras_common_if *head, int enable)
 742 {
 743         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 744         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 745
 746         /* If hardware does not support ras, then do not create obj.
 747          * But if hardware support ras, we can create the obj.
 748          * Ras framework checks con->hw_supported to see if it need do
 749          * corresponding initialization.
 750          * IP checks con->support to see if it need disable ras.
 751          */
 752         if (!amdgpu_ras_is_feature_allowed(adev, head))
 753                 return 0;
 754
 755         if (enable) {
 756                 if (!obj) {
 757                         obj = amdgpu_ras_create_obj(adev, head);
 758                         if (!obj)
 759                                 return -EINVAL;
 760                 } else {
 761                         /* In case we create obj somewhere else */
 762                         get_obj(obj);
 763                 }
 764                 con->features |= BIT(head->block);
 765         } else {
 766                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 767                         con->features &= ~BIT(head->block);
 768                         put_obj(obj);
 769                 }
 770         }
 771
 772         return 0;
 773 }
 774
 775 /* wrapper of psp_ras_enable_features */
 776 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 777                 struct ras_common_if *head, bool enable)
 778 {
 779         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 780         union ta_ras_cmd_input *info;
 781         int ret;
 782
 783         if (!con)
 784                 return -EINVAL;
 785
 786         /* For non-gfx ip, do not enable ras feature if it is not allowed */
 787         /* For gfx ip, regardless of feature support status, */
 788         /* Force issue enable or disable ras feature commands */
 789         if (head->block != AMDGPU_RAS_BLOCK__GFX &&
 790             !amdgpu_ras_is_feature_allowed(adev, head))
 791                 return 0;
 792
 793         /* Only enable gfx ras feature from host side */
 794         if (head->block == AMDGPU_RAS_BLOCK__GFX &&
 795             !amdgpu_sriov_vf(adev) &&
 796             !amdgpu_ras_intr_triggered()) {
 797                 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 798                 if (!info)
 799                         return -ENOMEM;
 800
 801                 if (!enable) {
 802                         info->disable_features = (struct ta_ras_disable_features_input) {
 803                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 804                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 805                         };
 806                 } else {
 807                         info->enable_features = (struct ta_ras_enable_features_input) {
 808                                 .block_id =  amdgpu_ras_block_to_ta(head->block),
 809                                 .error_type = amdgpu_ras_error_to_ta(head->type),
 810                         };
 811                 }
 812
 813                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 814                 if (ret) {
 815                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 816                                 enable ? "enable":"disable",
 817                                 get_ras_block_str(head),
 818                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 819                         kfree(info);
 820                         return ret;
 821                 }
 822
 823                 kfree(info);
 824         }
 825
 826         /* setup the obj */
 827         __amdgpu_ras_feature_enable(adev, head, enable);
 828
 829         return 0;
 830 }
 831
 832 /* Only used in device probe stage and called only once. */
 833 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 834                 struct ras_common_if *head, bool enable)
 835 {
 836         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 837         int ret;
 838
 839         if (!con)
 840                 return -EINVAL;
 841
 842         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 843                 if (enable) {
 844                         /* There is no harm to issue a ras TA cmd regardless of
 845                          * the currecnt ras state.
 846                          * If current state == target state, it will do nothing
 847                          * But sometimes it requests driver to reset and repost
 848                          * with error code -EAGAIN.
 849                          */
 850                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 851                         /* With old ras TA, we might fail to enable ras.
 852                          * Log it and just setup the object.
 853                          * TODO need remove this WA in the future.
 854                          */
 855                         if (ret == -EINVAL) {
 856                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 857                                 if (!ret)
 858                                         dev_info(adev->dev,
 859                                                 "RAS INFO: %s setup object\n",
 860                                                 get_ras_block_str(head));
 861                         }
 862                 } else {
 863                         /* setup the object then issue a ras TA disable cmd.*/
 864                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 865                         if (ret)
 866                                 return ret;
 867
 868                         /* gfx block ras dsiable cmd must send to ras-ta */
 869                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 870                                 con->features |= BIT(head->block);
 871
 872                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 873
 874                         /* clean gfx block ras features flag */
 875                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 876                                 con->features &= ~BIT(head->block);
 877                 }
 878         } else
 879                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 880
 881         return ret;
 882 }
 883
 884 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 885                 bool bypass)
 886 {
 887         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 888         struct ras_manager *obj, *tmp;
 889
 890         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 891                 /* bypass psp.
 892                  * aka just release the obj and corresponding flags
 893                  */
 894                 if (bypass) {
 895                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 896                                 break;
 897                 } else {
 898                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 899                                 break;
 900                 }
 901         }
 902
 903         return con->features;
 904 }
 905
 906 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 907                 bool bypass)
 908 {
 909         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 910         int i;
 911         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 912
 913         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 914                 struct ras_common_if head = {
 915                         .block = i,
 916                         .type = default_ras_type,
 917                         .sub_block_index = 0,
 918                 };
 919
 920                 if (i == AMDGPU_RAS_BLOCK__MCA)
 921                         continue;
 922
 923                 if (bypass) {
 924                         /*
 925                          * bypass psp. vbios enable ras for us.
 926                          * so just create the obj
 927                          */
 928                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 929                                 break;
 930                 } else {
 931                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 932                                 break;
 933                 }
 934         }
 935
 936         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 937                 struct ras_common_if head = {
 938                         .block = AMDGPU_RAS_BLOCK__MCA,
 939                         .type = default_ras_type,
 940                         .sub_block_index = i,
 941                 };
 942
 943                 if (bypass) {
 944                         /*
 945                          * bypass psp. vbios enable ras for us.
 946                          * so just create the obj
 947                          */
 948                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 949                                 break;
 950                 } else {
 951                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 952                                 break;
 953                 }
 954         }
 955
 956         return con->features;
 957 }
 958 /* feature ctl end */
 959
 960 static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
 961                 enum amdgpu_ras_block block)
 962 {
 963         if (!block_obj)
 964                 return -EINVAL;
 965
 966         if (block_obj->ras_comm.block == block)
 967                 return 0;
 968
 969         return -EINVAL;
 970 }
 971
 972 static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
 973                                         enum amdgpu_ras_block block, uint32_t sub_block_index)
 974 {
 975         struct amdgpu_ras_block_list *node, *tmp;
 976         struct amdgpu_ras_block_object *obj;
 977
 978         if (block >= AMDGPU_RAS_BLOCK__LAST)
 979                 return NULL;
 980
 981         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
 982                 if (!node->ras_obj) {
 983                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
 984                         continue;
 985                 }
 986
 987                 obj = node->ras_obj;
 988                 if (obj->ras_block_match) {
 989                         if (obj->ras_block_match(obj, block, sub_block_index) == 0)
 990                                 return obj;
 991                 } else {
 992                         if (amdgpu_ras_block_match_default(obj, block) == 0)
 993                                 return obj;
 994                 }
 995         }
 996
 997         return NULL;
 998 }
 999
1000 static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
1001 {
1002         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1003         int ret = 0;
1004
1005         /*
1006          * choosing right query method according to
1007          * whether smu support query error information
1008          */
1009         ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
1010         if (ret == -EOPNOTSUPP) {
1011                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1012                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1013                         adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
1014
1015                 /* umc query_ras_error_address is also responsible for clearing
1016                  * error status
1017                  */
1018                 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1019                     adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1020                         adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
1021         } else if (!ret) {
1022                 if (adev->umc.ras &&
1023                         adev->umc.ras->ecc_info_query_ras_error_count)
1024                         adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
1025
1026                 if (adev->umc.ras &&
1027                         adev->umc.ras->ecc_info_query_ras_error_address)
1028                         adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
1029         }
1030 }
1031
1032 static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
1033                                               struct ras_manager *ras_mgr,
1034                                               struct ras_err_data *err_data,
1035                                               const char *blk_name,
1036                                               bool is_ue)
1037 {
1038         struct amdgpu_smuio_mcm_config_info *mcm_info;
1039         struct ras_err_node *err_node;
1040         struct ras_err_info *err_info;
1041
1042         if (is_ue) {
1043                 for_each_ras_error(err_node, err_data) {
1044                         err_info = &err_node->err_info;
1045                         mcm_info = &err_info->mcm_info;
1046                         if (err_info->ue_count) {
1047                                 dev_info(adev->dev, "socket: %d, die: %d, "
1048                                          "%lld new uncorrectable hardware errors detected in %s block\n",
1049                                          mcm_info->socket_id,
1050                                          mcm_info->die_id,
1051                                          err_info->ue_count,
1052                                          blk_name);
1053                         }
1054                 }
1055
1056                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1057                         err_info = &err_node->err_info;
1058                         mcm_info = &err_info->mcm_info;
1059                         dev_info(adev->dev, "socket: %d, die: %d, "
1060                                  "%lld uncorrectable hardware errors detected in total in %s block\n",
1061                                  mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name);
1062                 }
1063
1064         } else {
1065                 for_each_ras_error(err_node, err_data) {
1066                         err_info = &err_node->err_info;
1067                         mcm_info = &err_info->mcm_info;
1068                         if (err_info->ce_count) {
1069                                 dev_info(adev->dev, "socket: %d, die: %d, "
1070                                          "%lld new correctable hardware errors detected in %s block, "
1071                                          "no user action is needed\n",
1072                                          mcm_info->socket_id,
1073                                          mcm_info->die_id,
1074                                          err_info->ce_count,
1075                                          blk_name);
1076                         }
1077                 }
1078
1079                 for_each_ras_error(err_node, &ras_mgr->err_data) {
1080                         err_info = &err_node->err_info;
1081                         mcm_info = &err_info->mcm_info;
1082                         dev_info(adev->dev, "socket: %d, die: %d, "
1083                                  "%lld correctable hardware errors detected in total in %s block, "
1084                                  "no user action is needed\n",
1085                                  mcm_info->socket_id, mcm_info->die_id, err_info->ce_count, blk_name);
1086                 }
1087         }
1088 }
1089
1090 static inline bool err_data_has_source_info(struct ras_err_data *data)
1091 {
1092         return !list_empty(&data->err_node_list);
1093 }
1094
1095 static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1096                                              struct ras_query_if *query_if,
1097                                              struct ras_err_data *err_data)
1098 {
1099         struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1100         const char *blk_name = get_ras_block_str(&query_if->head);
1101
1102         if (err_data->ce_count) {
1103                 if (err_data_has_source_info(err_data)) {
1104                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, false);
1105                 } else if (!adev->aid_mask &&
1106                            adev->smuio.funcs &&
1107                            adev->smuio.funcs->get_socket_id &&
1108                            adev->smuio.funcs->get_die_id) {
1109                         dev_info(adev->dev, "socket: %d, die: %d "
1110                                  "%ld correctable hardware errors "
1111                                  "detected in %s block, no user "
1112                                  "action is needed.\n",
1113                                  adev->smuio.funcs->get_socket_id(adev),
1114                                  adev->smuio.funcs->get_die_id(adev),
1115                                  ras_mgr->err_data.ce_count,
1116                                  blk_name);
1117                 } else {
1118                         dev_info(adev->dev, "%ld correctable hardware errors "
1119                                  "detected in %s block, no user "
1120                                  "action is needed.\n",
1121                                  ras_mgr->err_data.ce_count,
1122                                  blk_name);
1123                 }
1124         }
1125
1126         if (err_data->ue_count) {
1127                 if (err_data_has_source_info(err_data)) {
1128                         amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, blk_name, true);
1129                 } else if (!adev->aid_mask &&
1130                            adev->smuio.funcs &&
1131                            adev->smuio.funcs->get_socket_id &&
1132                            adev->smuio.funcs->get_die_id) {
1133                         dev_info(adev->dev, "socket: %d, die: %d "
1134                                  "%ld uncorrectable hardware errors "
1135                                  "detected in %s block\n",
1136                                  adev->smuio.funcs->get_socket_id(adev),
1137                                  adev->smuio.funcs->get_die_id(adev),
1138                                  ras_mgr->err_data.ue_count,
1139                                  blk_name);
1140                 } else {
1141                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1142                                  "detected in %s block\n",
1143                                  ras_mgr->err_data.ue_count,
1144                                  blk_name);
1145                 }
1146         }
1147
1148 }
1149
1150 static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1151 {
1152         struct ras_err_node *err_node;
1153         struct ras_err_info *err_info;
1154
1155         if (err_data_has_source_info(err_data)) {
1156                 for_each_ras_error(err_node, err_data) {
1157                         err_info = &err_node->err_info;
1158
1159                         amdgpu_ras_error_statistic_ce_count(&obj->err_data,
1160                                         &err_info->mcm_info, NULL, err_info->ce_count);
1161                         amdgpu_ras_error_statistic_ue_count(&obj->err_data,
1162                                         &err_info->mcm_info, NULL, err_info->ue_count);
1163                 }
1164         } else {
1165                 /* for legacy asic path which doesn't has error source info */
1166                 obj->err_data.ue_count += err_data->ue_count;
1167                 obj->err_data.ce_count += err_data->ce_count;
1168         }
1169 }
1170
1171 static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
1172                                                 struct ras_query_if *info,
1173                                                 struct ras_err_data *err_data,
1174                                                 unsigned int error_query_mode)
1175 {
1176         enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT;
1177         struct amdgpu_ras_block_object *block_obj = NULL;
1178
1179         if (blk == AMDGPU_RAS_BLOCK_COUNT)
1180                 return -EINVAL;
1181
1182         if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
1183                 return -EINVAL;
1184
1185         if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
1186                 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1187                         amdgpu_ras_get_ecc_info(adev, err_data);
1188                 } else {
1189                         block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1190                         if (!block_obj || !block_obj->hw_ops) {
1191                                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1192                                              get_ras_block_str(&info->head));
1193                                 return -EINVAL;
1194                         }
1195
1196                         if (block_obj->hw_ops->query_ras_error_count)
1197                                 block_obj->hw_ops->query_ras_error_count(adev, err_data);
1198
1199                         if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1200                             (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1201                             (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1202                                 if (block_obj->hw_ops->query_ras_error_status)
1203                                         block_obj->hw_ops->query_ras_error_status(adev);
1204                         }
1205                 }
1206         } else {
1207                 /* FIXME: add code to check return value later */
1208                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data);
1209                 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data);
1210         }
1211
1212         return 0;
1213 }
1214
1215 /* query/inject/cure begin */
1216 int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
1217 {
1218         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1219         struct ras_err_data err_data;
1220         unsigned int error_query_mode;
1221         int ret;
1222
1223         if (!obj)
1224                 return -EINVAL;
1225
1226         ret = amdgpu_ras_error_data_init(&err_data);
1227         if (ret)
1228                 return ret;
1229
1230         if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode))
1231                 return -EINVAL;
1232
1233         ret = amdgpu_ras_query_error_status_helper(adev, info,
1234                                                    &err_data,
1235                                                    error_query_mode);
1236         if (ret)
1237                 goto out_fini_err_data;
1238
1239         amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
1240
1241         info->ue_count = obj->err_data.ue_count;
1242         info->ce_count = obj->err_data.ce_count;
1243
1244         amdgpu_ras_error_generate_report(adev, info, &err_data);
1245
1246 out_fini_err_data:
1247         amdgpu_ras_error_data_fini(&err_data);
1248
1249         return ret;
1250 }
1251
1252 int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
1253                 enum amdgpu_ras_block block)
1254 {
1255         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1256         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1257         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
1258         struct amdgpu_hive_info *hive;
1259         int hive_ras_recovery = 0;
1260
1261         if (!block_obj || !block_obj->hw_ops) {
1262                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1263                                 ras_block_str(block));
1264                 return -EOPNOTSUPP;
1265         }
1266
1267         if (!amdgpu_ras_is_supported(adev, block) ||
1268             !amdgpu_ras_get_mca_debug_mode(adev))
1269                 return -EOPNOTSUPP;
1270
1271         hive = amdgpu_get_xgmi_hive(adev);
1272         if (hive) {
1273                 hive_ras_recovery = atomic_read(&hive->ras_recovery);
1274                 amdgpu_put_xgmi_hive(hive);
1275         }
1276
1277         /* skip ras error reset in gpu reset */
1278         if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) ||
1279             hive_ras_recovery) &&
1280             mca_funcs && mca_funcs->mca_set_debug_mode)
1281                 return -EOPNOTSUPP;
1282
1283         if (block_obj->hw_ops->reset_ras_error_count)
1284                 block_obj->hw_ops->reset_ras_error_count(adev);
1285
1286         return 0;
1287 }
1288
1289 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1290                 enum amdgpu_ras_block block)
1291 {
1292         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1293
1294         if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1295                 return 0;
1296
1297         if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1298             (block == AMDGPU_RAS_BLOCK__MMHUB)) {
1299                 if (block_obj->hw_ops->reset_ras_error_status)
1300                         block_obj->hw_ops->reset_ras_error_status(adev);
1301         }
1302
1303         return 0;
1304 }
1305
1306 /* wrapper of psp_ras_trigger_error */
1307 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1308                 struct ras_inject_if *info)
1309 {
1310         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1311         struct ta_ras_trigger_error_input block_info = {
1312                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1313                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1314                 .sub_block_index = info->head.sub_block_index,
1315                 .address = info->address,
1316                 .value = info->value,
1317         };
1318         int ret = -EINVAL;
1319         struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1320                                                         info->head.block,
1321                                                         info->head.sub_block_index);
1322
1323         /* inject on guest isn't allowed, return success directly */
1324         if (amdgpu_sriov_vf(adev))
1325                 return 0;
1326
1327         if (!obj)
1328                 return -EINVAL;
1329
1330         if (!block_obj || !block_obj->hw_ops)   {
1331                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1332                              get_ras_block_str(&info->head));
1333                 return -EINVAL;
1334         }
1335
1336         /* Calculate XGMI relative offset */
1337         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1338             info->head.block != AMDGPU_RAS_BLOCK__GFX) {
1339                 block_info.address =
1340                         amdgpu_xgmi_get_relative_phy_addr(adev,
1341                                                           block_info.address);
1342         }
1343
1344         if (block_obj->hw_ops->ras_error_inject) {
1345                 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
1346                         ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
1347                 else /* Special ras_error_inject is defined (e.g: xgmi) */
1348                         ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1349                                                 info->instance_mask);
1350         } else {
1351                 /* default path */
1352                 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
1353         }
1354
1355         if (ret)
1356                 dev_err(adev->dev, "ras inject %s failed %d\n",
1357                         get_ras_block_str(&info->head), ret);
1358
1359         return ret;
1360 }
1361
1362 /**
1363  * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1364  * @adev: pointer to AMD GPU device
1365  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1366  * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1367  * @query_info: pointer to ras_query_if
1368  *
1369  * Return 0 for query success or do nothing, otherwise return an error
1370  * on failures
1371  */
1372 static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1373                                                unsigned long *ce_count,
1374                                                unsigned long *ue_count,
1375                                                struct ras_query_if *query_info)
1376 {
1377         int ret;
1378
1379         if (!query_info)
1380                 /* do nothing if query_info is not specified */
1381                 return 0;
1382
1383         ret = amdgpu_ras_query_error_status(adev, query_info);
1384         if (ret)
1385                 return ret;
1386
1387         *ce_count += query_info->ce_count;
1388         *ue_count += query_info->ue_count;
1389
1390         /* some hardware/IP supports read to clear
1391          * no need to explictly reset the err status after the query call */
1392         if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1393             amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1394                 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1395                         dev_warn(adev->dev,
1396                                  "Failed to reset error counter and error status\n");
1397         }
1398
1399         return 0;
1400 }
1401
1402 /**
1403  * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
1404  * @adev: pointer to AMD GPU device
1405  * @ce_count: pointer to an integer to be set to the count of correctible errors.
1406  * @ue_count: pointer to an integer to be set to the count of uncorrectible
1407  * errors.
1408  * @query_info: pointer to ras_query_if if the query request is only for
1409  * specific ip block; if info is NULL, then the qurey request is for
1410  * all the ip blocks that support query ras error counters/status
1411  *
1412  * If set, @ce_count or @ue_count, count and return the corresponding
1413  * error counts in those integer pointers. Return 0 if the device
1414  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1415  */
1416 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1417                                  unsigned long *ce_count,
1418                                  unsigned long *ue_count,
1419                                  struct ras_query_if *query_info)
1420 {
1421         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1422         struct ras_manager *obj;
1423         unsigned long ce, ue;
1424         int ret;
1425
1426         if (!adev->ras_enabled || !con)
1427                 return -EOPNOTSUPP;
1428
1429         /* Don't count since no reporting.
1430          */
1431         if (!ce_count && !ue_count)
1432                 return 0;
1433
1434         ce = 0;
1435         ue = 0;
1436         if (!query_info) {
1437                 /* query all the ip blocks that support ras query interface */
1438                 list_for_each_entry(obj, &con->head, node) {
1439                         struct ras_query_if info = {
1440                                 .head = obj->head,
1441                         };
1442
1443                         ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
1444                 }
1445         } else {
1446                 /* query specific ip block */
1447                 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
1448         }
1449
1450         if (ret)
1451                 return ret;
1452
1453         if (ce_count)
1454                 *ce_count = ce;
1455
1456         if (ue_count)
1457                 *ue_count = ue;
1458
1459         return 0;
1460 }
1461 /* query/inject/cure end */
1462
1463
1464 /* sysfs begin */
1465
1466 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1467                 struct ras_badpage **bps, unsigned int *count);
1468
1469 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1470 {
1471         switch (flags) {
1472         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1473                 return "R";
1474         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1475                 return "P";
1476         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1477         default:
1478                 return "F";
1479         }
1480 }
1481
1482 /**
1483  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1484  *
1485  * It allows user to read the bad pages of vram on the gpu through
1486  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1487  *
1488  * It outputs multiple lines, and each line stands for one gpu page.
1489  *
1490  * The format of one line is below,
1491  * gpu pfn : gpu page size : flags
1492  *
1493  * gpu pfn and gpu page size are printed in hex format.
1494  * flags can be one of below character,
1495  *
1496  * R: reserved, this gpu page is reserved and not able to use.
1497  *
1498  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1499  * in next window of page_reserve.
1500  *
1501  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1502  *
1503  * Examples:
1504  *
1505  * .. code-block:: bash
1506  *
1507  *      0x00000001 : 0x00001000 : R
1508  *      0x00000002 : 0x00001000 : P
1509  *
1510  */
1511
1512 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1513                 struct kobject *kobj, struct bin_attribute *attr,
1514                 char *buf, loff_t ppos, size_t count)
1515 {
1516         struct amdgpu_ras *con =
1517                 container_of(attr, struct amdgpu_ras, badpages_attr);
1518         struct amdgpu_device *adev = con->adev;
1519         const unsigned int element_size =
1520                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1521         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1522         unsigned int end = div64_ul(ppos + count - 1, element_size);
1523         ssize_t s = 0;
1524         struct ras_badpage *bps = NULL;
1525         unsigned int bps_count = 0;
1526
1527         memset(buf, 0, count);
1528
1529         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1530                 return 0;
1531
1532         for (; start < end && start < bps_count; start++)
1533                 s += scnprintf(&buf[s], element_size + 1,
1534                                 "0x%08x : 0x%08x : %1s\n",
1535                                 bps[start].bp,
1536                                 bps[start].size,
1537                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1538
1539         kfree(bps);
1540
1541         return s;
1542 }
1543
1544 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1545                 struct device_attribute *attr, char *buf)
1546 {
1547         struct amdgpu_ras *con =
1548                 container_of(attr, struct amdgpu_ras, features_attr);
1549
1550         return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
1551 }
1552
1553 static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1554                 struct device_attribute *attr, char *buf)
1555 {
1556         struct amdgpu_ras *con =
1557                 container_of(attr, struct amdgpu_ras, version_attr);
1558         return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1559 }
1560
1561 static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1562                 struct device_attribute *attr, char *buf)
1563 {
1564         struct amdgpu_ras *con =
1565                 container_of(attr, struct amdgpu_ras, schema_attr);
1566         return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1567 }
1568
1569 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1570 {
1571         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1572
1573         if (adev->dev->kobj.sd)
1574                 sysfs_remove_file_from_group(&adev->dev->kobj,
1575                                 &con->badpages_attr.attr,
1576                                 RAS_FS_NAME);
1577 }
1578
1579 static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
1580 {
1581         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1582         struct attribute *attrs[] = {
1583                 &con->features_attr.attr,
1584                 &con->version_attr.attr,
1585                 &con->schema_attr.attr,
1586                 NULL
1587         };
1588         struct attribute_group group = {
1589                 .name = RAS_FS_NAME,
1590                 .attrs = attrs,
1591         };
1592
1593         if (adev->dev->kobj.sd)
1594                 sysfs_remove_group(&adev->dev->kobj, &group);
1595
1596         return 0;
1597 }
1598
1599 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1600                 struct ras_common_if *head)
1601 {
1602         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1603
1604         if (!obj || obj->attr_inuse)
1605                 return -EINVAL;
1606
1607         get_obj(obj);
1608
1609         snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1610                 "%s_err_count", head->name);
1611
1612         obj->sysfs_attr = (struct device_attribute){
1613                 .attr = {
1614                         .name = obj->fs_data.sysfs_name,
1615                         .mode = S_IRUGO,
1616                 },
1617                         .show = amdgpu_ras_sysfs_read,
1618         };
1619         sysfs_attr_init(&obj->sysfs_attr.attr);
1620
1621         if (sysfs_add_file_to_group(&adev->dev->kobj,
1622                                 &obj->sysfs_attr.attr,
1623                                 RAS_FS_NAME)) {
1624                 put_obj(obj);
1625                 return -EINVAL;
1626         }
1627
1628         obj->attr_inuse = 1;
1629
1630         return 0;
1631 }
1632
1633 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1634                 struct ras_common_if *head)
1635 {
1636         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1637
1638         if (!obj || !obj->attr_inuse)
1639                 return -EINVAL;
1640
1641         if (adev->dev->kobj.sd)
1642                 sysfs_remove_file_from_group(&adev->dev->kobj,
1643                                 &obj->sysfs_attr.attr,
1644                                 RAS_FS_NAME);
1645         obj->attr_inuse = 0;
1646         put_obj(obj);
1647
1648         return 0;
1649 }
1650
1651 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1652 {
1653         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1654         struct ras_manager *obj, *tmp;
1655
1656         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1657                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1658         }
1659
1660         if (amdgpu_bad_page_threshold != 0)
1661                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1662
1663         amdgpu_ras_sysfs_remove_dev_attr_node(adev);
1664
1665         return 0;
1666 }
1667 /* sysfs end */
1668
1669 /**
1670  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1671  *
1672  * Normally when there is an uncorrectable error, the driver will reset
1673  * the GPU to recover.  However, in the event of an unrecoverable error,
1674  * the driver provides an interface to reboot the system automatically
1675  * in that event.
1676  *
1677  * The following file in debugfs provides that interface:
1678  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1679  *
1680  * Usage:
1681  *
1682  * .. code-block:: bash
1683  *
1684  *      echo true > .../ras/auto_reboot
1685  *
1686  */
1687 /* debugfs begin */
1688 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1689 {
1690         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1691         struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
1692         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1693         struct dentry     *dir;
1694
1695         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1696         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1697                             &amdgpu_ras_debugfs_ctrl_ops);
1698         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1699                             &amdgpu_ras_debugfs_eeprom_ops);
1700         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1701                            &con->bad_page_cnt_threshold);
1702         debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
1703         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1704         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1705         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1706                             &amdgpu_ras_debugfs_eeprom_size_ops);
1707         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1708                                                        S_IRUGO, dir, adev,
1709                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1710         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1711
1712         /*
1713          * After one uncorrectable error happens, usually GPU recovery will
1714          * be scheduled. But due to the known problem in GPU recovery failing
1715          * to bring GPU back, below interface provides one direct way to
1716          * user to reboot system automatically in such case within
1717          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1718          * will never be called.
1719          */
1720         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1721
1722         /*
1723          * User could set this not to clean up hardware's error count register
1724          * of RAS IPs during ras recovery.
1725          */
1726         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1727                             &con->disable_ras_err_cnt_harvest);
1728         return dir;
1729 }
1730
1731 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1732                                       struct ras_fs_if *head,
1733                                       struct dentry *dir)
1734 {
1735         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1736
1737         if (!obj || !dir)
1738                 return;
1739
1740         get_obj(obj);
1741
1742         memcpy(obj->fs_data.debugfs_name,
1743                         head->debugfs_name,
1744                         sizeof(obj->fs_data.debugfs_name));
1745
1746         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1747                             obj, &amdgpu_ras_debugfs_ops);
1748 }
1749
1750 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1751 {
1752         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1753         struct dentry *dir;
1754         struct ras_manager *obj;
1755         struct ras_fs_if fs_info;
1756
1757         /*
1758          * it won't be called in resume path, no need to check
1759          * suspend and gpu reset status
1760          */
1761         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1762                 return;
1763
1764         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1765
1766         list_for_each_entry(obj, &con->head, node) {
1767                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1768                         (obj->attr_inuse == 1)) {
1769                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1770                                         get_ras_block_str(&obj->head));
1771                         fs_info.head = obj->head;
1772                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1773                 }
1774         }
1775
1776         amdgpu_mca_smu_debugfs_init(adev, dir);
1777 }
1778
1779 /* debugfs end */
1780
1781 /* ras fs */
1782 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1783                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1784 static DEVICE_ATTR(features, S_IRUGO,
1785                 amdgpu_ras_sysfs_features_read, NULL);
1786 static DEVICE_ATTR(version, 0444,
1787                 amdgpu_ras_sysfs_version_show, NULL);
1788 static DEVICE_ATTR(schema, 0444,
1789                 amdgpu_ras_sysfs_schema_show, NULL);
1790 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1791 {
1792         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1793         struct attribute_group group = {
1794                 .name = RAS_FS_NAME,
1795         };
1796         struct attribute *attrs[] = {
1797                 &con->features_attr.attr,
1798                 &con->version_attr.attr,
1799                 &con->schema_attr.attr,
1800                 NULL
1801         };
1802         struct bin_attribute *bin_attrs[] = {
1803                 NULL,
1804                 NULL,
1805         };
1806         int r;
1807
1808         group.attrs = attrs;
1809
1810         /* add features entry */
1811         con->features_attr = dev_attr_features;
1812         sysfs_attr_init(attrs[0]);
1813
1814         /* add version entry */
1815         con->version_attr = dev_attr_version;
1816         sysfs_attr_init(attrs[1]);
1817
1818         /* add schema entry */
1819         con->schema_attr = dev_attr_schema;
1820         sysfs_attr_init(attrs[2]);
1821
1822         if (amdgpu_bad_page_threshold != 0) {
1823                 /* add bad_page_features entry */
1824                 bin_attr_gpu_vram_bad_pages.private = NULL;
1825                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1826                 bin_attrs[0] = &con->badpages_attr;
1827                 group.bin_attrs = bin_attrs;
1828                 sysfs_bin_attr_init(bin_attrs[0]);
1829         }
1830
1831         r = sysfs_create_group(&adev->dev->kobj, &group);
1832         if (r)
1833                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1834
1835         return 0;
1836 }
1837
1838 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1839 {
1840         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1841         struct ras_manager *con_obj, *ip_obj, *tmp;
1842
1843         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1844                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1845                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1846                         if (ip_obj)
1847                                 put_obj(ip_obj);
1848                 }
1849         }
1850
1851         amdgpu_ras_sysfs_remove_all(adev);
1852         return 0;
1853 }
1854 /* ras fs end */
1855
1856 /* ih begin */
1857
1858 /* For the hardware that cannot enable bif ring for both ras_controller_irq
1859  * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1860  * register to check whether the interrupt is triggered or not, and properly
1861  * ack the interrupt if it is there
1862  */
1863 void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1864 {
1865         /* Fatal error events are handled on host side */
1866         if (amdgpu_sriov_vf(adev))
1867                 return;
1868
1869         if (adev->nbio.ras &&
1870             adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1871                 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1872
1873         if (adev->nbio.ras &&
1874             adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1875                 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1876 }
1877
1878 static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1879                                 struct amdgpu_iv_entry *entry)
1880 {
1881         bool poison_stat = false;
1882         struct amdgpu_device *adev = obj->adev;
1883         struct amdgpu_ras_block_object *block_obj =
1884                 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1885
1886         if (!block_obj)
1887                 return;
1888
1889         /* both query_poison_status and handle_poison_consumption are optional,
1890          * but at least one of them should be implemented if we need poison
1891          * consumption handler
1892          */
1893         if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
1894                 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1895                 if (!poison_stat) {
1896                         /* Not poison consumption interrupt, no need to handle it */
1897                         dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1898                                         block_obj->ras_comm.name);
1899
1900                         return;
1901                 }
1902         }
1903
1904         amdgpu_umc_poison_handler(adev, false);
1905
1906         if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
1907                 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1908
1909         /* gpu reset is fallback for failed and default cases */
1910         if (poison_stat) {
1911                 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1912                                 block_obj->ras_comm.name);
1913                 amdgpu_ras_reset_gpu(adev);
1914         } else {
1915                 amdgpu_gfx_poison_consumption_handler(adev, entry);
1916         }
1917 }
1918
1919 static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1920                                 struct amdgpu_iv_entry *entry)
1921 {
1922         dev_info(obj->adev->dev,
1923                 "Poison is created, no user action is needed.\n");
1924 }
1925
1926 static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1927                                 struct amdgpu_iv_entry *entry)
1928 {
1929         struct ras_ih_data *data = &obj->ih_data;
1930         struct ras_err_data err_data;
1931         int ret;
1932
1933         if (!data->cb)
1934                 return;
1935
1936         ret = amdgpu_ras_error_data_init(&err_data);
1937         if (ret)
1938                 return;
1939
1940         /* Let IP handle its data, maybe we need get the output
1941          * from the callback to update the error type/count, etc
1942          */
1943         ret = data->cb(obj->adev, &err_data, entry);
1944         /* ue will trigger an interrupt, and in that case
1945          * we need do a reset to recovery the whole system.
1946          * But leave IP do that recovery, here we just dispatch
1947          * the error.
1948          */
1949         if (ret == AMDGPU_RAS_SUCCESS) {
1950                 /* these counts could be left as 0 if
1951                  * some blocks do not count error number
1952                  */
1953                 obj->err_data.ue_count += err_data.ue_count;
1954                 obj->err_data.ce_count += err_data.ce_count;
1955         }
1956
1957         amdgpu_ras_error_data_fini(&err_data);
1958 }
1959
1960 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1961 {
1962         struct ras_ih_data *data = &obj->ih_data;
1963         struct amdgpu_iv_entry entry;
1964
1965         while (data->rptr != data->wptr) {
1966                 rmb();
1967                 memcpy(&entry, &data->ring[data->rptr],
1968                                 data->element_size);
1969
1970                 wmb();
1971                 data->rptr = (data->aligned_element_size +
1972                                 data->rptr) % data->ring_size;
1973
1974                 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1975                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1976                                 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
1977                         else
1978                                 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
1979                 } else {
1980                         if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1981                                 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1982                         else
1983                                 dev_warn(obj->adev->dev,
1984                                         "No RAS interrupt handler for non-UMC block with poison disabled.\n");
1985                 }
1986         }
1987 }
1988
1989 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1990 {
1991         struct ras_ih_data *data =
1992                 container_of(work, struct ras_ih_data, ih_work);
1993         struct ras_manager *obj =
1994                 container_of(data, struct ras_manager, ih_data);
1995
1996         amdgpu_ras_interrupt_handler(obj);
1997 }
1998
1999 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
2000                 struct ras_dispatch_if *info)
2001 {
2002         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
2003         struct ras_ih_data *data = &obj->ih_data;
2004
2005         if (!obj)
2006                 return -EINVAL;
2007
2008         if (data->inuse == 0)
2009                 return 0;
2010
2011         /* Might be overflow... */
2012         memcpy(&data->ring[data->wptr], info->entry,
2013                         data->element_size);
2014
2015         wmb();
2016         data->wptr = (data->aligned_element_size +
2017                         data->wptr) % data->ring_size;
2018
2019         schedule_work(&data->ih_work);
2020
2021         return 0;
2022 }
2023
2024 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
2025                 struct ras_common_if *head)
2026 {
2027         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2028         struct ras_ih_data *data;
2029
2030         if (!obj)
2031                 return -EINVAL;
2032
2033         data = &obj->ih_data;
2034         if (data->inuse == 0)
2035                 return 0;
2036
2037         cancel_work_sync(&data->ih_work);
2038
2039         kfree(data->ring);
2040         memset(data, 0, sizeof(*data));
2041         put_obj(obj);
2042
2043         return 0;
2044 }
2045
2046 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
2047                 struct ras_common_if *head)
2048 {
2049         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
2050         struct ras_ih_data *data;
2051         struct amdgpu_ras_block_object *ras_obj;
2052
2053         if (!obj) {
2054                 /* in case we registe the IH before enable ras feature */
2055                 obj = amdgpu_ras_create_obj(adev, head);
2056                 if (!obj)
2057                         return -EINVAL;
2058         } else
2059                 get_obj(obj);
2060
2061         ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
2062
2063         data = &obj->ih_data;
2064         /* add the callback.etc */
2065         *data = (struct ras_ih_data) {
2066                 .inuse = 0,
2067                 .cb = ras_obj->ras_cb,
2068                 .element_size = sizeof(struct amdgpu_iv_entry),
2069                 .rptr = 0,
2070                 .wptr = 0,
2071         };
2072
2073         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
2074
2075         data->aligned_element_size = ALIGN(data->element_size, 8);
2076         /* the ring can store 64 iv entries. */
2077         data->ring_size = 64 * data->aligned_element_size;
2078         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
2079         if (!data->ring) {
2080                 put_obj(obj);
2081                 return -ENOMEM;
2082         }
2083
2084         /* IH is ready */
2085         data->inuse = 1;
2086
2087         return 0;
2088 }
2089
2090 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
2091 {
2092         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2093         struct ras_manager *obj, *tmp;
2094
2095         list_for_each_entry_safe(obj, tmp, &con->head, node) {
2096                 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
2097         }
2098
2099         return 0;
2100 }
2101 /* ih end */
2102
2103 /* traversal all IPs except NBIO to query error counter */
2104 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
2105 {
2106         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2107         struct ras_manager *obj;
2108
2109         if (!adev->ras_enabled || !con)
2110                 return;
2111
2112         list_for_each_entry(obj, &con->head, node) {
2113                 struct ras_query_if info = {
2114                         .head = obj->head,
2115                 };
2116
2117                 /*
2118                  * PCIE_BIF IP has one different isr by ras controller
2119                  * interrupt, the specific ras counter query will be
2120                  * done in that isr. So skip such block from common
2121                  * sync flood interrupt isr calling.
2122                  */
2123                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2124                         continue;
2125
2126                 /*
2127                  * this is a workaround for aldebaran, skip send msg to
2128                  * smu to get ecc_info table due to smu handle get ecc
2129                  * info table failed temporarily.
2130                  * should be removed until smu fix handle ecc_info table.
2131                  */
2132                 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
2133                     (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2134                      IP_VERSION(13, 0, 2)))
2135                         continue;
2136
2137                 amdgpu_ras_query_error_status(adev, &info);
2138
2139                 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2140                             IP_VERSION(11, 0, 2) &&
2141                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2142                             IP_VERSION(11, 0, 4) &&
2143                     amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2144                             IP_VERSION(13, 0, 0)) {
2145                         if (amdgpu_ras_reset_error_status(adev, info.head.block))
2146                                 dev_warn(adev->dev, "Failed to reset error counter and error status");
2147                 }
2148         }
2149 }
2150
2151 /* Parse RdRspStatus and WrRspStatus */
2152 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2153                                           struct ras_query_if *info)
2154 {
2155         struct amdgpu_ras_block_object *block_obj;
2156         /*
2157          * Only two block need to query read/write
2158          * RspStatus at current state
2159          */
2160         if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2161                 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
2162                 return;
2163
2164         block_obj = amdgpu_ras_get_ras_block(adev,
2165                                         info->head.block,
2166                                         info->head.sub_block_index);
2167
2168         if (!block_obj || !block_obj->hw_ops) {
2169                 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2170                              get_ras_block_str(&info->head));
2171                 return;
2172         }
2173
2174         if (block_obj->hw_ops->query_ras_error_status)
2175                 block_obj->hw_ops->query_ras_error_status(adev);
2176
2177 }
2178
2179 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2180 {
2181         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2182         struct ras_manager *obj;
2183
2184         if (!adev->ras_enabled || !con)
2185                 return;
2186
2187         list_for_each_entry(obj, &con->head, node) {
2188                 struct ras_query_if info = {
2189                         .head = obj->head,
2190                 };
2191
2192                 amdgpu_ras_error_status_query(adev, &info);
2193         }
2194 }
2195
2196 /* recovery begin */
2197
2198 /* return 0 on success.
2199  * caller need free bps.
2200  */
2201 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2202                 struct ras_badpage **bps, unsigned int *count)
2203 {
2204         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2205         struct ras_err_handler_data *data;
2206         int i = 0;
2207         int ret = 0, status;
2208
2209         if (!con || !con->eh_data || !bps || !count)
2210                 return -EINVAL;
2211
2212         mutex_lock(&con->recovery_lock);
2213         data = con->eh_data;
2214         if (!data || data->count == 0) {
2215                 *bps = NULL;
2216                 ret = -EINVAL;
2217                 goto out;
2218         }
2219
2220         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2221         if (!*bps) {
2222                 ret = -ENOMEM;
2223                 goto out;
2224         }
2225
2226         for (; i < data->count; i++) {
2227                 (*bps)[i] = (struct ras_badpage){
2228                         .bp = data->bps[i].retired_page,
2229                         .size = AMDGPU_GPU_PAGE_SIZE,
2230                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
2231                 };
2232                 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
2233                                 data->bps[i].retired_page);
2234                 if (status == -EBUSY)
2235                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
2236                 else if (status == -ENOENT)
2237                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
2238         }
2239
2240         *count = data->count;
2241 out:
2242         mutex_unlock(&con->recovery_lock);
2243         return ret;
2244 }
2245
2246 static void amdgpu_ras_do_recovery(struct work_struct *work)
2247 {
2248         struct amdgpu_ras *ras =
2249                 container_of(work, struct amdgpu_ras, recovery_work);
2250         struct amdgpu_device *remote_adev = NULL;
2251         struct amdgpu_device *adev = ras->adev;
2252         struct list_head device_list, *device_list_handle =  NULL;
2253         struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2254
2255         if (hive)
2256                 atomic_set(&hive->ras_recovery, 1);
2257         if (!ras->disable_ras_err_cnt_harvest) {
2258
2259                 /* Build list of devices to query RAS related errors */
2260                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2261                         device_list_handle = &hive->device_list;
2262                 } else {
2263                         INIT_LIST_HEAD(&device_list);
2264                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
2265                         device_list_handle = &device_list;
2266                 }
2267
2268                 list_for_each_entry(remote_adev,
2269                                 device_list_handle, gmc.xgmi.head) {
2270                         amdgpu_ras_query_err_status(remote_adev);
2271                         amdgpu_ras_log_on_err_counter(remote_adev);
2272                 }
2273
2274         }
2275
2276         if (amdgpu_device_should_recover_gpu(ras->adev)) {
2277                 struct amdgpu_reset_context reset_context;
2278                 memset(&reset_context, 0, sizeof(reset_context));
2279
2280                 reset_context.method = AMD_RESET_METHOD_NONE;
2281                 reset_context.reset_req_dev = adev;
2282
2283                 /* Perform full reset in fatal error mode */
2284                 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2285                         set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2286                 else {
2287                         clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2288
2289                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2290                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2291                                 reset_context.method = AMD_RESET_METHOD_MODE2;
2292                         }
2293
2294                         /* Fatal error occurs in poison mode, mode1 reset is used to
2295                          * recover gpu.
2296                          */
2297                         if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2298                                 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2299                                 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2300
2301                                 psp_fatal_error_recovery_quirk(&adev->psp);
2302                         }
2303                 }
2304
2305                 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2306         }
2307         atomic_set(&ras->in_recovery, 0);
2308         if (hive) {
2309                 atomic_set(&hive->ras_recovery, 0);
2310                 amdgpu_put_xgmi_hive(hive);
2311         }
2312 }
2313
2314 /* alloc/realloc bps array */
2315 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2316                 struct ras_err_handler_data *data, int pages)
2317 {
2318         unsigned int old_space = data->count + data->space_left;
2319         unsigned int new_space = old_space + pages;
2320         unsigned int align_space = ALIGN(new_space, 512);
2321         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
2322
2323         if (!bps) {
2324                 return -ENOMEM;
2325         }
2326
2327         if (data->bps) {
2328                 memcpy(bps, data->bps,
2329                                 data->count * sizeof(*data->bps));
2330                 kfree(data->bps);
2331         }
2332
2333         data->bps = bps;
2334         data->space_left += align_space - old_space;
2335         return 0;
2336 }
2337
2338 /* it deal with vram only. */
2339 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
2340                 struct eeprom_table_record *bps, int pages)
2341 {
2342         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2343         struct ras_err_handler_data *data;
2344         int ret = 0;
2345         uint32_t i;
2346
2347         if (!con || !con->eh_data || !bps || pages <= 0)
2348                 return 0;
2349
2350         mutex_lock(&con->recovery_lock);
2351         data = con->eh_data;
2352         if (!data)
2353                 goto out;
2354
2355         for (i = 0; i < pages; i++) {
2356                 if (amdgpu_ras_check_bad_page_unlock(con,
2357                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2358                         continue;
2359
2360                 if (!data->space_left &&
2361                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
2362                         ret = -ENOMEM;
2363                         goto out;
2364                 }
2365
2366                 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
2367                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2368                         AMDGPU_GPU_PAGE_SIZE);
2369
2370                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2371                 data->count++;
2372                 data->space_left--;
2373         }
2374 out:
2375         mutex_unlock(&con->recovery_lock);
2376
2377         return ret;
2378 }
2379
2380 /*
2381  * write error record array to eeprom, the function should be
2382  * protected by recovery_lock
2383  * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
2384  */
2385 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2386                 unsigned long *new_cnt)
2387 {
2388         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2389         struct ras_err_handler_data *data;
2390         struct amdgpu_ras_eeprom_control *control;
2391         int save_count;
2392
2393         if (!con || !con->eh_data) {
2394                 if (new_cnt)
2395                         *new_cnt = 0;
2396
2397                 return 0;
2398         }
2399
2400         mutex_lock(&con->recovery_lock);
2401         control = &con->eeprom_control;
2402         data = con->eh_data;
2403         save_count = data->count - control->ras_num_recs;
2404         mutex_unlock(&con->recovery_lock);
2405
2406         if (new_cnt)
2407                 *new_cnt = save_count / adev->umc.retire_unit;
2408
2409         /* only new entries are saved */
2410         if (save_count > 0) {
2411                 if (amdgpu_ras_eeprom_append(control,
2412                                              &data->bps[control->ras_num_recs],
2413                                              save_count)) {
2414                         dev_err(adev->dev, "Failed to save EEPROM table data!");
2415                         return -EIO;
2416                 }
2417
2418                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2419         }
2420
2421         return 0;
2422 }
2423
2424 /*
2425  * read error record array in eeprom and reserve enough space for
2426  * storing new bad pages
2427  */
2428 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2429 {
2430         struct amdgpu_ras_eeprom_control *control =
2431                 &adev->psp.ras_context.ras->eeprom_control;
2432         struct eeprom_table_record *bps;
2433         int ret;
2434
2435         /* no bad page record, skip eeprom access */
2436         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
2437                 return 0;
2438
2439         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
2440         if (!bps)
2441                 return -ENOMEM;
2442
2443         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
2444         if (ret)
2445                 dev_err(adev->dev, "Failed to load EEPROM table records!");
2446         else
2447                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
2448
2449         kfree(bps);
2450         return ret;
2451 }
2452
2453 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2454                                 uint64_t addr)
2455 {
2456         struct ras_err_handler_data *data = con->eh_data;
2457         int i;
2458
2459         addr >>= AMDGPU_GPU_PAGE_SHIFT;
2460         for (i = 0; i < data->count; i++)
2461                 if (addr == data->bps[i].retired_page)
2462                         return true;
2463
2464         return false;
2465 }
2466
2467 /*
2468  * check if an address belongs to bad page
2469  *
2470  * Note: this check is only for umc block
2471  */
2472 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2473                                 uint64_t addr)
2474 {
2475         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2476         bool ret = false;
2477
2478         if (!con || !con->eh_data)
2479                 return ret;
2480
2481         mutex_lock(&con->recovery_lock);
2482         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2483         mutex_unlock(&con->recovery_lock);
2484         return ret;
2485 }
2486
2487 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2488                                           uint32_t max_count)
2489 {
2490         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2491
2492         /*
2493          * Justification of value bad_page_cnt_threshold in ras structure
2494          *
2495          * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2496          * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2497          * scenarios accordingly.
2498          *
2499          * Bad page retirement enablement:
2500          *    - If amdgpu_bad_page_threshold = -2,
2501          *      bad_page_cnt_threshold = typical value by formula.
2502          *
2503          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2504          *      max record length in eeprom, use it directly.
2505          *
2506          * Bad page retirement disablement:
2507          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2508          *      functionality is disabled, and bad_page_cnt_threshold will
2509          *      take no effect.
2510          */
2511
2512         if (amdgpu_bad_page_threshold < 0) {
2513                 u64 val = adev->gmc.mc_vram_size;
2514
2515                 do_div(val, RAS_BAD_PAGE_COVER);
2516                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2517                                                   max_count);
2518         } else {
2519                 con->bad_page_cnt_threshold = min_t(int, max_count,
2520                                                     amdgpu_bad_page_threshold);
2521         }
2522 }
2523
2524 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2525 {
2526         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2527         struct ras_err_handler_data **data;
2528         u32  max_eeprom_records_count = 0;
2529         bool exc_err_limit = false;
2530         int ret;
2531
2532         if (!con || amdgpu_sriov_vf(adev))
2533                 return 0;
2534
2535         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2536          * supports RAS and debugfs is enabled, but when
2537          * adev->ras_enabled is unset, i.e. when "ras_enable"
2538          * module parameter is set to 0.
2539          */
2540         con->adev = adev;
2541
2542         if (!adev->ras_enabled)
2543                 return 0;
2544
2545         data = &con->eh_data;
2546         *data = kzalloc(sizeof(**data), GFP_KERNEL);
2547         if (!*data) {
2548                 ret = -ENOMEM;
2549                 goto out;
2550         }
2551
2552         mutex_init(&con->recovery_lock);
2553         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2554         atomic_set(&con->in_recovery, 0);
2555         con->eeprom_control.bad_channel_bitmap = 0;
2556
2557         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
2558         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2559
2560         /* Todo: During test the SMU might fail to read the eeprom through I2C
2561          * when the GPU is pending on XGMI reset during probe time
2562          * (Mostly after second bus reset), skip it now
2563          */
2564         if (adev->gmc.xgmi.pending_reset)
2565                 return 0;
2566         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2567         /*
2568          * This calling fails when exc_err_limit is true or
2569          * ret != 0.
2570          */
2571         if (exc_err_limit || ret)
2572                 goto free;
2573
2574         if (con->eeprom_control.ras_num_recs) {
2575                 ret = amdgpu_ras_load_bad_pages(adev);
2576                 if (ret)
2577                         goto free;
2578
2579                 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
2580
2581                 if (con->update_channel_flag == true) {
2582                         amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2583                         con->update_channel_flag = false;
2584                 }
2585         }
2586
2587 #ifdef CONFIG_X86_MCE_AMD
2588         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2589             (adev->gmc.xgmi.connected_to_cpu))
2590                 amdgpu_register_bad_pages_mca_notifier(adev);
2591 #endif
2592         return 0;
2593
2594 free:
2595         kfree((*data)->bps);
2596         kfree(*data);
2597         con->eh_data = NULL;
2598 out:
2599         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2600
2601         /*
2602          * Except error threshold exceeding case, other failure cases in this
2603          * function would not fail amdgpu driver init.
2604          */
2605         if (!exc_err_limit)
2606                 ret = 0;
2607         else
2608                 ret = -EINVAL;
2609
2610         return ret;
2611 }
2612
2613 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2614 {
2615         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2616         struct ras_err_handler_data *data = con->eh_data;
2617
2618         /* recovery_init failed to init it, fini is useless */
2619         if (!data)
2620                 return 0;
2621
2622         cancel_work_sync(&con->recovery_work);
2623
2624         mutex_lock(&con->recovery_lock);
2625         con->eh_data = NULL;
2626         kfree(data->bps);
2627         kfree(data);
2628         mutex_unlock(&con->recovery_lock);
2629
2630         return 0;
2631 }
2632 /* recovery end */
2633
2634 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2635 {
2636         if (amdgpu_sriov_vf(adev)) {
2637                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2638                 case IP_VERSION(13, 0, 2):
2639                 case IP_VERSION(13, 0, 6):
2640                         return true;
2641                 default:
2642                         return false;
2643                 }
2644         }
2645
2646         if (adev->asic_type == CHIP_IP_DISCOVERY) {
2647                 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2648                 case IP_VERSION(13, 0, 0):
2649                 case IP_VERSION(13, 0, 6):
2650                 case IP_VERSION(13, 0, 10):
2651                         return true;
2652                 default:
2653                         return false;
2654                 }
2655         }
2656
2657         return adev->asic_type == CHIP_VEGA10 ||
2658                 adev->asic_type == CHIP_VEGA20 ||
2659                 adev->asic_type == CHIP_ARCTURUS ||
2660                 adev->asic_type == CHIP_ALDEBARAN ||
2661                 adev->asic_type == CHIP_SIENNA_CICHLID;
2662 }
2663
2664 /*
2665  * this is workaround for vega20 workstation sku,
2666  * force enable gfx ras, ignore vbios gfx ras flag
2667  * due to GC EDC can not write
2668  */
2669 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2670 {
2671         struct atom_context *ctx = adev->mode_info.atom_context;
2672
2673         if (!ctx)
2674                 return;
2675
2676         if (strnstr(ctx->vbios_pn, "D16406",
2677                     sizeof(ctx->vbios_pn)) ||
2678                 strnstr(ctx->vbios_pn, "D36002",
2679                         sizeof(ctx->vbios_pn)))
2680                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2681 }
2682
2683 /*
2684  * check hardware's ras ability which will be saved in hw_supported.
2685  * if hardware does not support ras, we can skip some ras initializtion and
2686  * forbid some ras operations from IP.
2687  * if software itself, say boot parameter, limit the ras ability. We still
2688  * need allow IP do some limited operations, like disable. In such case,
2689  * we have to initialize ras as normal. but need check if operation is
2690  * allowed or not in each function.
2691  */
2692 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2693 {
2694         adev->ras_hw_enabled = adev->ras_enabled = 0;
2695
2696         if (!amdgpu_ras_asic_supported(adev))
2697                 return;
2698
2699         if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
2700                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2701                         dev_info(adev->dev, "MEM ECC is active.\n");
2702                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2703                                                    1 << AMDGPU_RAS_BLOCK__DF);
2704                 } else {
2705                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2706                 }
2707
2708                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2709                         dev_info(adev->dev, "SRAM ECC is active.\n");
2710                         if (!amdgpu_sriov_vf(adev))
2711                                 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2712                                                             1 << AMDGPU_RAS_BLOCK__DF);
2713                         else
2714                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2715                                                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2716                                                                 1 << AMDGPU_RAS_BLOCK__GFX);
2717
2718                         /* VCN/JPEG RAS can be supported on both bare metal and
2719                          * SRIOV environment
2720                          */
2721                         if (amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2722                                     IP_VERSION(2, 6, 0) ||
2723                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2724                                     IP_VERSION(4, 0, 0) ||
2725                             amdgpu_ip_version(adev, VCN_HWIP, 0) ==
2726                                     IP_VERSION(4, 0, 3))
2727                                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2728                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2729                         else
2730                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2731                                                         1 << AMDGPU_RAS_BLOCK__JPEG);
2732
2733                         /*
2734                          * XGMI RAS is not supported if xgmi num physical nodes
2735                          * is zero
2736                          */
2737                         if (!adev->gmc.xgmi.num_physical_nodes)
2738                                 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
2739                 } else {
2740                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2741                 }
2742         } else {
2743                 /* driver only manages a few IP blocks RAS feature
2744                  * when GPU is connected cpu through XGMI */
2745                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2746                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2747                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2748         }
2749
2750         amdgpu_ras_get_quirks(adev);
2751
2752         /* hw_supported needs to be aligned with RAS block mask. */
2753         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2754
2755         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2756                 adev->ras_hw_enabled & amdgpu_ras_mask;
2757 }
2758
2759 static void amdgpu_ras_counte_dw(struct work_struct *work)
2760 {
2761         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2762                                               ras_counte_delay_work.work);
2763         struct amdgpu_device *adev = con->adev;
2764         struct drm_device *dev = adev_to_drm(adev);
2765         unsigned long ce_count, ue_count;
2766         int res;
2767
2768         res = pm_runtime_get_sync(dev->dev);
2769         if (res < 0)
2770                 goto Out;
2771
2772         /* Cache new values.
2773          */
2774         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
2775                 atomic_set(&con->ras_ce_count, ce_count);
2776                 atomic_set(&con->ras_ue_count, ue_count);
2777         }
2778
2779         pm_runtime_mark_last_busy(dev->dev);
2780 Out:
2781         pm_runtime_put_autosuspend(dev->dev);
2782 }
2783
2784 static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2785 {
2786         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2787         bool df_poison, umc_poison;
2788
2789         /* poison setting is useless on SRIOV guest */
2790         if (amdgpu_sriov_vf(adev) || !con)
2791                 return;
2792
2793         /* Init poison supported flag, the default value is false */
2794         if (adev->gmc.xgmi.connected_to_cpu ||
2795             adev->gmc.is_app_apu) {
2796                 /* enabled by default when GPU is connected to CPU */
2797                 con->poison_supported = true;
2798         } else if (adev->df.funcs &&
2799             adev->df.funcs->query_ras_poison_mode &&
2800             adev->umc.ras &&
2801             adev->umc.ras->query_ras_poison_mode) {
2802                 df_poison =
2803                         adev->df.funcs->query_ras_poison_mode(adev);
2804                 umc_poison =
2805                         adev->umc.ras->query_ras_poison_mode(adev);
2806
2807                 /* Only poison is set in both DF and UMC, we can support it */
2808                 if (df_poison && umc_poison)
2809                         con->poison_supported = true;
2810                 else if (df_poison != umc_poison)
2811                         dev_warn(adev->dev,
2812                                 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2813                                 df_poison, umc_poison);
2814         }
2815 }
2816
2817 static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
2818 {
2819         return  amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
2820                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
2821                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
2822                         AMDGPU_RAS_ERROR__PARITY;
2823 }
2824
2825 int amdgpu_ras_init(struct amdgpu_device *adev)
2826 {
2827         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2828         int r;
2829
2830         if (con)
2831                 return 0;
2832
2833         con = kzalloc(sizeof(*con) +
2834                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2835                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2836                         GFP_KERNEL);
2837         if (!con)
2838                 return -ENOMEM;
2839
2840         con->adev = adev;
2841         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2842         atomic_set(&con->ras_ce_count, 0);
2843         atomic_set(&con->ras_ue_count, 0);
2844
2845         con->objs = (struct ras_manager *)(con + 1);
2846
2847         amdgpu_ras_set_context(adev, con);
2848
2849         amdgpu_ras_check_supported(adev);
2850
2851         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2852                 /* set gfx block ras context feature for VEGA20 Gaming
2853                  * send ras disable cmd to ras ta during ras late init.
2854                  */
2855                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2856                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2857
2858                         return 0;
2859                 }
2860
2861                 r = 0;
2862                 goto release_con;
2863         }
2864
2865         con->update_channel_flag = false;
2866         con->features = 0;
2867         con->schema = 0;
2868         INIT_LIST_HEAD(&con->head);
2869         /* Might need get this flag from vbios. */
2870         con->flags = RAS_DEFAULT_FLAGS;
2871
2872         /* initialize nbio ras function ahead of any other
2873          * ras functions so hardware fatal error interrupt
2874          * can be enabled as early as possible */
2875         switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
2876         case IP_VERSION(7, 4, 0):
2877         case IP_VERSION(7, 4, 1):
2878         case IP_VERSION(7, 4, 4):
2879                 if (!adev->gmc.xgmi.connected_to_cpu)
2880                         adev->nbio.ras = &nbio_v7_4_ras;
2881                 break;
2882         case IP_VERSION(4, 3, 0):
2883                 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2884                         /* unlike other generation of nbio ras,
2885                          * nbio v4_3 only support fatal error interrupt
2886                          * to inform software that DF is freezed due to
2887                          * system fatal error event. driver should not
2888                          * enable nbio ras in such case. Instead,
2889                          * check DF RAS */
2890                         adev->nbio.ras = &nbio_v4_3_ras;
2891                 break;
2892         case IP_VERSION(7, 9, 0):
2893                 if (!adev->gmc.is_app_apu)
2894                         adev->nbio.ras = &nbio_v7_9_ras;
2895                 break;
2896         default:
2897                 /* nbio ras is not available */
2898                 break;
2899         }
2900
2901         /* nbio ras block needs to be enabled ahead of other ras blocks
2902          * to handle fatal error */
2903         r = amdgpu_nbio_ras_sw_init(adev);
2904         if (r)
2905                 return r;
2906
2907         if (adev->nbio.ras &&
2908             adev->nbio.ras->init_ras_controller_interrupt) {
2909                 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
2910                 if (r)
2911                         goto release_con;
2912         }
2913
2914         if (adev->nbio.ras &&
2915             adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2916                 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
2917                 if (r)
2918                         goto release_con;
2919         }
2920
2921         amdgpu_ras_query_poison_mode(adev);
2922
2923         /* Get RAS schema for particular SOC */
2924         con->schema = amdgpu_get_ras_schema(adev);
2925
2926         if (amdgpu_ras_fs_init(adev)) {
2927                 r = -EINVAL;
2928                 goto release_con;
2929         }
2930
2931         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2932                  "hardware ability[%x] ras_mask[%x]\n",
2933                  adev->ras_hw_enabled, adev->ras_enabled);
2934
2935         return 0;
2936 release_con:
2937         amdgpu_ras_set_context(adev, NULL);
2938         kfree(con);
2939
2940         return r;
2941 }
2942
2943 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2944 {
2945         if (adev->gmc.xgmi.connected_to_cpu ||
2946             adev->gmc.is_app_apu)
2947                 return 1;
2948         return 0;
2949 }
2950
2951 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2952                                         struct ras_common_if *ras_block)
2953 {
2954         struct ras_query_if info = {
2955                 .head = *ras_block,
2956         };
2957
2958         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2959                 return 0;
2960
2961         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2962                 DRM_WARN("RAS init harvest failure");
2963
2964         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2965                 DRM_WARN("RAS init harvest reset failure");
2966
2967         return 0;
2968 }
2969
2970 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2971 {
2972        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2973
2974        if (!con)
2975                return false;
2976
2977        return con->poison_supported;
2978 }
2979
2980 /* helper function to handle common stuff in ip late init phase */
2981 int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2982                          struct ras_common_if *ras_block)
2983 {
2984         struct amdgpu_ras_block_object *ras_obj = NULL;
2985         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2986         struct ras_query_if *query_info;
2987         unsigned long ue_count, ce_count;
2988         int r;
2989
2990         /* disable RAS feature per IP block if it is not supported */
2991         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2992                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2993                 return 0;
2994         }
2995
2996         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2997         if (r) {
2998                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2999                         /* in resume phase, if fail to enable ras,
3000                          * clean up all ras fs nodes, and disable ras */
3001                         goto cleanup;
3002                 } else
3003                         return r;
3004         }
3005
3006         /* check for errors on warm reset edc persisant supported ASIC */
3007         amdgpu_persistent_edc_harvesting(adev, ras_block);
3008
3009         /* in resume phase, no need to create ras fs node */
3010         if (adev->in_suspend || amdgpu_in_reset(adev))
3011                 return 0;
3012
3013         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3014         if (ras_obj->ras_cb || (ras_obj->hw_ops &&
3015             (ras_obj->hw_ops->query_poison_status ||
3016             ras_obj->hw_ops->handle_poison_consumption))) {
3017                 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
3018                 if (r)
3019                         goto cleanup;
3020         }
3021
3022         if (ras_obj->hw_ops &&
3023             (ras_obj->hw_ops->query_ras_error_count ||
3024              ras_obj->hw_ops->query_ras_error_status)) {
3025                 r = amdgpu_ras_sysfs_create(adev, ras_block);
3026                 if (r)
3027                         goto interrupt;
3028
3029                 /* Those are the cached values at init.
3030                  */
3031                 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
3032                 if (!query_info)
3033                         return -ENOMEM;
3034                 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
3035
3036                 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
3037                         atomic_set(&con->ras_ce_count, ce_count);
3038                         atomic_set(&con->ras_ue_count, ue_count);
3039                 }
3040
3041                 kfree(query_info);
3042         }
3043
3044         return 0;
3045
3046 interrupt:
3047         if (ras_obj->ras_cb)
3048                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3049 cleanup:
3050         amdgpu_ras_feature_enable(adev, ras_block, 0);
3051         return r;
3052 }
3053
3054 static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
3055                          struct ras_common_if *ras_block)
3056 {
3057         return amdgpu_ras_block_late_init(adev, ras_block);
3058 }
3059
3060 /* helper function to remove ras fs node and interrupt handler */
3061 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
3062                           struct ras_common_if *ras_block)
3063 {
3064         struct amdgpu_ras_block_object *ras_obj;
3065         if (!ras_block)
3066                 return;
3067
3068         amdgpu_ras_sysfs_remove(adev, ras_block);
3069
3070         ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3071         if (ras_obj->ras_cb)
3072                 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
3073 }
3074
3075 static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
3076                           struct ras_common_if *ras_block)
3077 {
3078         return amdgpu_ras_block_late_fini(adev, ras_block);
3079 }
3080
3081 /* do some init work after IP late init as dependence.
3082  * and it runs in resume/gpu reset/booting up cases.
3083  */
3084 void amdgpu_ras_resume(struct amdgpu_device *adev)
3085 {
3086         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3087         struct ras_manager *obj, *tmp;
3088
3089         if (!adev->ras_enabled || !con) {
3090                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
3091                 amdgpu_release_ras_context(adev);
3092
3093                 return;
3094         }
3095
3096         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
3097                 /* Set up all other IPs which are not implemented. There is a
3098                  * tricky thing that IP's actual ras error type should be
3099                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3100                  * ERROR_NONE make sense anyway.
3101                  */
3102                 amdgpu_ras_enable_all_features(adev, 1);
3103
3104                 /* We enable ras on all hw_supported block, but as boot
3105                  * parameter might disable some of them and one or more IP has
3106                  * not implemented yet. So we disable them on behalf.
3107                  */
3108                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3109                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3110                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3111                                 /* there should be no any reference. */
3112                                 WARN_ON(alive_obj(obj));
3113                         }
3114                 }
3115         }
3116 }
3117
3118 void amdgpu_ras_suspend(struct amdgpu_device *adev)
3119 {
3120         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3121
3122         if (!adev->ras_enabled || !con)
3123                 return;
3124
3125         amdgpu_ras_disable_all_features(adev, 0);
3126         /* Make sure all ras objects are disabled. */
3127         if (con->features)
3128                 amdgpu_ras_disable_all_features(adev, 1);
3129 }
3130
3131 int amdgpu_ras_late_init(struct amdgpu_device *adev)
3132 {
3133         struct amdgpu_ras_block_list *node, *tmp;
3134         struct amdgpu_ras_block_object *obj;
3135         int r;
3136
3137         /* Guest side doesn't need init ras feature */
3138         if (amdgpu_sriov_vf(adev))
3139                 return 0;
3140
3141         amdgpu_ras_set_mca_debug_mode(adev, false);
3142
3143         list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
3144                 if (!node->ras_obj) {
3145                         dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3146                         continue;
3147                 }
3148
3149                 obj = node->ras_obj;
3150                 if (obj->ras_late_init) {
3151                         r = obj->ras_late_init(adev, &obj->ras_comm);
3152                         if (r) {
3153                                 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3154                                         obj->ras_comm.name, r);
3155                                 return r;
3156                         }
3157                 } else
3158                         amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
3159         }
3160
3161         return 0;
3162 }
3163
3164 /* do some fini work before IP fini as dependence */
3165 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3166 {
3167         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3168
3169         if (!adev->ras_enabled || !con)
3170                 return 0;
3171
3172
3173         /* Need disable ras on all IPs here before ip [hw/sw]fini */
3174         if (con->features)
3175                 amdgpu_ras_disable_all_features(adev, 0);
3176         amdgpu_ras_recovery_fini(adev);
3177         return 0;
3178 }
3179
3180 int amdgpu_ras_fini(struct amdgpu_device *adev)
3181 {
3182         struct amdgpu_ras_block_list *ras_node, *tmp;
3183         struct amdgpu_ras_block_object *obj = NULL;
3184         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3185
3186         if (!adev->ras_enabled || !con)
3187                 return 0;
3188
3189         list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3190                 if (ras_node->ras_obj) {
3191                         obj = ras_node->ras_obj;
3192                         if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3193                             obj->ras_fini)
3194                                 obj->ras_fini(adev, &obj->ras_comm);
3195                         else
3196                                 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
3197                 }
3198
3199                 /* Clear ras blocks from ras_list and free ras block list node */
3200                 list_del(&ras_node->node);
3201                 kfree(ras_node);
3202         }
3203
3204         amdgpu_ras_fs_fini(adev);
3205         amdgpu_ras_interrupt_remove_all(adev);
3206
3207         WARN(con->features, "Feature mask is not cleared");
3208
3209         if (con->features)
3210                 amdgpu_ras_disable_all_features(adev, 1);
3211
3212         cancel_delayed_work_sync(&con->ras_counte_delay_work);
3213
3214         amdgpu_ras_set_context(adev, NULL);
3215         kfree(con);
3216
3217         return 0;
3218 }
3219
3220 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3221 {
3222         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
3223                 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3224
3225                 dev_info(adev->dev, "uncorrectable hardware error"
3226                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
3227
3228                 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
3229                 amdgpu_ras_reset_gpu(adev);
3230         }
3231 }
3232
3233 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3234 {
3235         if (adev->asic_type == CHIP_VEGA20 &&
3236             adev->pm.fw_version <= 0x283400) {
3237                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3238                                 amdgpu_ras_intr_triggered();
3239         }
3240
3241         return false;
3242 }
3243
3244 void amdgpu_release_ras_context(struct amdgpu_device *adev)
3245 {
3246         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3247
3248         if (!con)
3249                 return;
3250
3251         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
3252                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3253                 amdgpu_ras_set_context(adev, NULL);
3254                 kfree(con);
3255         }
3256 }
3257
3258 #ifdef CONFIG_X86_MCE_AMD
3259 static struct amdgpu_device *find_adev(uint32_t node_id)
3260 {
3261         int i;
3262         struct amdgpu_device *adev = NULL;
3263
3264         for (i = 0; i < mce_adev_list.num_gpu; i++) {
3265                 adev = mce_adev_list.devs[i];
3266
3267                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
3268                     adev->gmc.xgmi.physical_node_id == node_id)
3269                         break;
3270                 adev = NULL;
3271         }
3272
3273         return adev;
3274 }
3275
3276 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
3277 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
3278 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3279 #define GPU_ID_OFFSET           8
3280
3281 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3282                                     unsigned long val, void *data)
3283 {
3284         struct mce *m = (struct mce *)data;
3285         struct amdgpu_device *adev = NULL;
3286         uint32_t gpu_id = 0;
3287         uint32_t umc_inst = 0, ch_inst = 0;
3288
3289         /*
3290          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3291          * and error occurred in DramECC (Extended error code = 0) then only
3292          * process the error, else bail out.
3293          */
3294         if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
3295                     (XEC(m->status, 0x3f) == 0x0)))
3296                 return NOTIFY_DONE;
3297
3298         /*
3299          * If it is correctable error, return.
3300          */
3301         if (mce_is_correctable(m))
3302                 return NOTIFY_OK;
3303
3304         /*
3305          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3306          */
3307         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3308
3309         adev = find_adev(gpu_id);
3310         if (!adev) {
3311                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3312                                                                 gpu_id);
3313                 return NOTIFY_DONE;
3314         }
3315
3316         /*
3317          * If it is uncorrectable error, then find out UMC instance and
3318          * channel index.
3319          */
3320         umc_inst = GET_UMC_INST(m->ipid);
3321         ch_inst = GET_CHAN_INDEX(m->ipid);
3322
3323         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3324                              umc_inst, ch_inst);
3325
3326         if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3327                 return NOTIFY_OK;
3328         else
3329                 return NOTIFY_DONE;
3330 }
3331
3332 static struct notifier_block amdgpu_bad_page_nb = {
3333         .notifier_call  = amdgpu_bad_page_notifier,
3334         .priority       = MCE_PRIO_UC,
3335 };
3336
3337 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
3338 {
3339         /*
3340          * Add the adev to the mce_adev_list.
3341          * During mode2 reset, amdgpu device is temporarily
3342          * removed from the mgpu_info list which can cause
3343          * page retirement to fail.
3344          * Use this list instead of mgpu_info to find the amdgpu
3345          * device on which the UMC error was reported.
3346          */
3347         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3348
3349         /*
3350          * Register the x86 notifier only once
3351          * with MCE subsystem.
3352          */
3353         if (notifier_registered == false) {
3354                 mce_register_decode_chain(&amdgpu_bad_page_nb);
3355                 notifier_registered = true;
3356         }
3357 }
3358 #endif
3359
3360 struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
3361 {
3362         if (!adev)
3363                 return NULL;
3364
3365         return adev->psp.ras_context.ras;
3366 }
3367
3368 int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
3369 {
3370         if (!adev)
3371                 return -EINVAL;
3372
3373         adev->psp.ras_context.ras = ras_con;
3374         return 0;
3375 }
3376
3377 /* check if ras is supported on block, say, sdma, gfx */
3378 int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3379                 unsigned int block)
3380 {
3381         int ret = 0;
3382         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3383
3384         if (block >= AMDGPU_RAS_BLOCK_COUNT)
3385                 return 0;
3386
3387         ret = ras && (adev->ras_enabled & (1 << block));
3388
3389         /* For the special asic with mem ecc enabled but sram ecc
3390          * not enabled, even if the ras block is not supported on
3391          * .ras_enabled, if the asic supports poison mode and the
3392          * ras block has ras configuration, it can be considered
3393          * that the ras block supports ras function.
3394          */
3395         if (!ret &&
3396             (block == AMDGPU_RAS_BLOCK__GFX ||
3397              block == AMDGPU_RAS_BLOCK__SDMA ||
3398              block == AMDGPU_RAS_BLOCK__VCN ||
3399              block == AMDGPU_RAS_BLOCK__JPEG) &&
3400             amdgpu_ras_is_poison_mode_supported(adev) &&
3401             amdgpu_ras_get_ras_block(adev, block, 0))
3402                 ret = 1;
3403
3404         return ret;
3405 }
3406
3407 int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3408 {
3409         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3410
3411         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
3412                 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
3413         return 0;
3414 }
3415
3416 int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
3417 {
3418         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3419         int ret = 0;
3420
3421         if (con) {
3422                 ret = amdgpu_mca_smu_set_debug_mode(adev, enable);
3423                 if (!ret)
3424                         con->is_mca_debug_mode = enable;
3425         }
3426
3427         return ret;
3428 }
3429
3430 bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev)
3431 {
3432         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3433         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3434
3435         if (!con)
3436                 return false;
3437
3438         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3439                 return con->is_mca_debug_mode;
3440         else
3441                 return true;
3442 }
3443
3444 bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
3445                                      unsigned int *error_query_mode)
3446 {
3447         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3448         const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3449
3450         if (!con) {
3451                 *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY;
3452                 return false;
3453         }
3454
3455         if (mca_funcs && mca_funcs->mca_set_debug_mode)
3456                 *error_query_mode =
3457                         (con->is_mca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY;
3458         else
3459                 *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY;
3460
3461         return true;
3462 }
3463
3464 /* Register each ip ras block into amdgpu ras */
3465 int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
3466                 struct amdgpu_ras_block_object *ras_block_obj)
3467 {
3468         struct amdgpu_ras_block_list *ras_node;
3469         if (!adev || !ras_block_obj)
3470                 return -EINVAL;
3471
3472         ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3473         if (!ras_node)
3474                 return -ENOMEM;
3475
3476         INIT_LIST_HEAD(&ras_node->node);
3477         ras_node->ras_obj = ras_block_obj;
3478         list_add_tail(&ras_node->node, &adev->ras_list);
3479
3480         return 0;
3481 }
3482
3483 void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3484 {
3485         if (!err_type_name)
3486                 return;
3487
3488         switch (err_type) {
3489         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3490                 sprintf(err_type_name, "correctable");
3491                 break;
3492         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3493                 sprintf(err_type_name, "uncorrectable");
3494                 break;
3495         default:
3496                 sprintf(err_type_name, "unknown");
3497                 break;
3498         }
3499 }
3500
3501 bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3502                                          const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3503                                          uint32_t instance,
3504                                          uint32_t *memory_id)
3505 {
3506         uint32_t err_status_lo_data, err_status_lo_offset;
3507
3508         if (!reg_entry)
3509                 return false;
3510
3511         err_status_lo_offset =
3512                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3513                                             reg_entry->seg_lo, reg_entry->reg_lo);
3514         err_status_lo_data = RREG32(err_status_lo_offset);
3515
3516         if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3517             !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3518                 return false;
3519
3520         *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3521
3522         return true;
3523 }
3524
3525 bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3526                                        const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3527                                        uint32_t instance,
3528                                        unsigned long *err_cnt)
3529 {
3530         uint32_t err_status_hi_data, err_status_hi_offset;
3531
3532         if (!reg_entry)
3533                 return false;
3534
3535         err_status_hi_offset =
3536                 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3537                                             reg_entry->seg_hi, reg_entry->reg_hi);
3538         err_status_hi_data = RREG32(err_status_hi_offset);
3539
3540         if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3541             !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
3542                 /* keep the check here in case we need to refer to the result later */
3543                 dev_dbg(adev->dev, "Invalid err_info field\n");
3544
3545         /* read err count */
3546         *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3547
3548         return true;
3549 }
3550
3551 void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3552                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3553                                            uint32_t reg_list_size,
3554                                            const struct amdgpu_ras_memory_id_entry *mem_list,
3555                                            uint32_t mem_list_size,
3556                                            uint32_t instance,
3557                                            uint32_t err_type,
3558                                            unsigned long *err_count)
3559 {
3560         uint32_t memory_id;
3561         unsigned long err_cnt;
3562         char err_type_name[16];
3563         uint32_t i, j;
3564
3565         for (i = 0; i < reg_list_size; i++) {
3566                 /* query memory_id from err_status_lo */
3567                 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3568                                                          instance, &memory_id))
3569                         continue;
3570
3571                 /* query err_cnt from err_status_hi */
3572                 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3573                                                        instance, &err_cnt) ||
3574                     !err_cnt)
3575                         continue;
3576
3577                 *err_count += err_cnt;
3578
3579                 /* log the errors */
3580                 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3581                 if (!mem_list) {
3582                         /* memory_list is not supported */
3583                         dev_info(adev->dev,
3584                                  "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3585                                  err_cnt, err_type_name,
3586                                  reg_list[i].block_name,
3587                                  instance, memory_id);
3588                 } else {
3589                         for (j = 0; j < mem_list_size; j++) {
3590                                 if (memory_id == mem_list[j].memory_id) {
3591                                         dev_info(adev->dev,
3592                                                  "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3593                                                  err_cnt, err_type_name,
3594                                                  reg_list[i].block_name,
3595                                                  instance, mem_list[j].name);
3596                                         break;
3597                                 }
3598                         }
3599                 }
3600         }
3601 }
3602
3603 void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3604                                            const struct amdgpu_ras_err_status_reg_entry *reg_list,
3605                                            uint32_t reg_list_size,
3606                                            uint32_t instance)
3607 {
3608         uint32_t err_status_lo_offset, err_status_hi_offset;
3609         uint32_t i;
3610
3611         for (i = 0; i < reg_list_size; i++) {
3612                 err_status_lo_offset =
3613                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3614                                                     reg_list[i].seg_lo, reg_list[i].reg_lo);
3615                 err_status_hi_offset =
3616                         AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3617                                                     reg_list[i].seg_hi, reg_list[i].reg_hi);
3618                 WREG32(err_status_lo_offset, 0);
3619                 WREG32(err_status_hi_offset, 0);
3620         }
3621 }
3622
3623 int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
3624 {
3625         memset(err_data, 0, sizeof(*err_data));
3626
3627         INIT_LIST_HEAD(&err_data->err_node_list);
3628
3629         return 0;
3630 }
3631
3632 static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
3633 {
3634         if (!err_node)
3635                 return;
3636
3637         list_del(&err_node->node);
3638         kvfree(err_node);
3639 }
3640
3641 void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
3642 {
3643         struct ras_err_node *err_node, *tmp;
3644
3645         list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
3646                 amdgpu_ras_error_node_release(err_node);
3647 }
3648
3649 static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
3650                                                              struct amdgpu_smuio_mcm_config_info *mcm_info)
3651 {
3652         struct ras_err_node *err_node;
3653         struct amdgpu_smuio_mcm_config_info *ref_id;
3654
3655         if (!err_data || !mcm_info)
3656                 return NULL;
3657
3658         for_each_ras_error(err_node, err_data) {
3659                 ref_id = &err_node->err_info.mcm_info;
3660
3661                 if (mcm_info->socket_id == ref_id->socket_id &&
3662                     mcm_info->die_id == ref_id->die_id)
3663                         return err_node;
3664         }
3665
3666         return NULL;
3667 }
3668
3669 static struct ras_err_node *amdgpu_ras_error_node_new(void)
3670 {
3671         struct ras_err_node *err_node;
3672
3673         err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
3674         if (!err_node)
3675                 return NULL;
3676
3677         INIT_LIST_HEAD(&err_node->node);
3678
3679         return err_node;
3680 }
3681
3682 static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)
3683 {
3684         struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);
3685         struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);
3686         struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info;
3687         struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info;
3688
3689         if (unlikely(infoa->socket_id != infob->socket_id))
3690                 return infoa->socket_id - infob->socket_id;
3691         else
3692                 return infoa->die_id - infob->die_id;
3693
3694         return 0;
3695 }
3696
3697 static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
3698                                 struct amdgpu_smuio_mcm_config_info *mcm_info,
3699                                 struct ras_err_addr *err_addr)
3700 {
3701         struct ras_err_node *err_node;
3702
3703         err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
3704         if (err_node)
3705                 return &err_node->err_info;
3706
3707         err_node = amdgpu_ras_error_node_new();
3708         if (!err_node)
3709                 return NULL;
3710
3711         memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
3712
3713         if (err_addr)
3714                 memcpy(&err_node->err_info.err_addr, err_addr, sizeof(*err_addr));
3715
3716         err_data->err_list_count++;
3717         list_add_tail(&err_node->node, &err_data->err_node_list);
3718         list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp);
3719
3720         return &err_node->err_info;
3721 }
3722
3723 int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
3724                 struct amdgpu_smuio_mcm_config_info *mcm_info,
3725                 struct ras_err_addr *err_addr, u64 count)
3726 {
3727         struct ras_err_info *err_info;
3728
3729         if (!err_data || !mcm_info)
3730                 return -EINVAL;
3731
3732         if (!count)
3733                 return 0;
3734
3735         err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);
3736         if (!err_info)
3737                 return -EINVAL;
3738
3739         err_info->ue_count += count;
3740         err_data->ue_count += count;
3741
3742         return 0;
3743 }
3744
3745 int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
3746                 struct amdgpu_smuio_mcm_config_info *mcm_info,
3747                 struct ras_err_addr *err_addr, u64 count)
3748 {
3749         struct ras_err_info *err_info;
3750
3751         if (!err_data || !mcm_info)
3752                 return -EINVAL;
3753
3754         if (!count)
3755                 return 0;
3756
3757         err_info = amdgpu_ras_error_get_info(err_data, mcm_info, err_addr);
3758         if (!err_info)
3759                 return -EINVAL;
3760
3761         err_info->ce_count += count;
3762         err_data->ce_count += count;
3763
3764         return 0;
3765 }