drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2014-2018 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <linux/dma-buf.h>
  24 #include <linux/list.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/sched/mm.h>
  27 #include <linux/sched/task.h>
  28 #include <linux/fdtable.h>
  29 #include <drm/ttm/ttm_tt.h>
  30
  31 #include <drm/drm_exec.h>
  32
  33 #include "amdgpu_object.h"
  34 #include "amdgpu_gem.h"
  35 #include "amdgpu_vm.h"
  36 #include "amdgpu_hmm.h"
  37 #include "amdgpu_amdkfd.h"
  38 #include "amdgpu_dma_buf.h"
  39 #include <uapi/linux/kfd_ioctl.h>
  40 #include "amdgpu_xgmi.h"
  41 #include "kfd_priv.h"
  42 #include "kfd_smi_events.h"
  43
  44 /* Userptr restore delay, just long enough to allow consecutive VM
  45  * changes to accumulate
  46  */
  47 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1
  48 #define AMDGPU_RESERVE_MEM_LIMIT                        (3UL << 29)
  49
  50 /*
  51  * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB
  52  * BO chunk
  53  */
  54 #define VRAM_AVAILABLITY_ALIGN (1 << 21)
  55
  56 /* Impose limit on how much memory KFD can use */
  57 static struct {
  58         uint64_t max_system_mem_limit;
  59         uint64_t max_ttm_mem_limit;
  60         int64_t system_mem_used;
  61         int64_t ttm_mem_used;
  62         spinlock_t mem_limit_lock;
  63 } kfd_mem_limit;
  64
  65 static const char * const domain_bit_to_string[] = {
  66                 "CPU",
  67                 "GTT",
  68                 "VRAM",
  69                 "GDS",
  70                 "GWS",
  71                 "OA"
  72 };
  73
  74 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1]
  75
  76 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work);
  77
  78 static bool kfd_mem_is_attached(struct amdgpu_vm *avm,
  79                 struct kgd_mem *mem)
  80 {
  81         struct kfd_mem_attachment *entry;
  82
  83         list_for_each_entry(entry, &mem->attachments, list)
  84                 if (entry->bo_va->base.vm == avm)
  85                         return true;
  86
  87         return false;
  88 }
  89
  90 /**
  91  * reuse_dmamap() - Check whether adev can share the original
  92  * userptr BO
  93  *
  94  * If both adev and bo_adev are in direct mapping or
  95  * in the same iommu group, they can share the original BO.
  96  *
  97  * @adev: Device to which can or cannot share the original BO
  98  * @bo_adev: Device to which allocated BO belongs to
  99  *
 100  * Return: returns true if adev can share original userptr BO,
 101  * false otherwise.
 102  */
 103 static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev)
 104 {
 105         return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) ||
 106                         (adev->dev->iommu_group == bo_adev->dev->iommu_group);
 107 }
 108
 109 /* Set memory usage limits. Current, limits are
 110  *  System (TTM + userptr) memory - 15/16th System RAM
 111  *  TTM memory - 3/8th System RAM
 112  */
 113 void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
 114 {
 115         struct sysinfo si;
 116         uint64_t mem;
 117
 118         if (kfd_mem_limit.max_system_mem_limit)
 119                 return;
 120
 121         si_meminfo(&si);
 122         mem = si.totalram - si.totalhigh;
 123         mem *= si.mem_unit;
 124
 125         spin_lock_init(&kfd_mem_limit.mem_limit_lock);
 126         kfd_mem_limit.max_system_mem_limit = mem - (mem >> 6);
 127         if (kfd_mem_limit.max_system_mem_limit < 2 * AMDGPU_RESERVE_MEM_LIMIT)
 128                 kfd_mem_limit.max_system_mem_limit >>= 1;
 129         else
 130                 kfd_mem_limit.max_system_mem_limit -= AMDGPU_RESERVE_MEM_LIMIT;
 131
 132         kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT;
 133         pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n",
 134                 (kfd_mem_limit.max_system_mem_limit >> 20),
 135                 (kfd_mem_limit.max_ttm_mem_limit >> 20));
 136 }
 137
 138 void amdgpu_amdkfd_reserve_system_mem(uint64_t size)
 139 {
 140         kfd_mem_limit.system_mem_used += size;
 141 }
 142
 143 /* Estimate page table size needed to represent a given memory size
 144  *
 145  * With 4KB pages, we need one 8 byte PTE for each 4KB of memory
 146  * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB
 147  * of memory (factor 256K, >> 18). ROCm user mode tries to optimize
 148  * for 2MB pages for TLB efficiency. However, small allocations and
 149  * fragmented system memory still need some 4KB pages. We choose a
 150  * compromise that should work in most cases without reserving too
 151  * much memory for page tables unnecessarily (factor 16K, >> 14).
 152  */
 153
 154 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM)
 155
 156 /**
 157  * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size
 158  * of buffer.
 159  *
 160  * @adev: Device to which allocated BO belongs to
 161  * @size: Size of buffer, in bytes, encapsulated by B0. This should be
 162  * equivalent to amdgpu_bo_size(BO)
 163  * @alloc_flag: Flag used in allocating a BO as noted above
 164  * @xcp_id: xcp_id is used to get xcp from xcp manager, one xcp is
 165  * managed as one compute node in driver for app
 166  *
 167  * Return:
 168  *      returns -ENOMEM in case of error, ZERO otherwise
 169  */
 170 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
 171                 uint64_t size, u32 alloc_flag, int8_t xcp_id)
 172 {
 173         uint64_t reserved_for_pt =
 174                 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
 175         size_t system_mem_needed, ttm_mem_needed, vram_needed;
 176         int ret = 0;
 177         uint64_t vram_size = 0;
 178
 179         system_mem_needed = 0;
 180         ttm_mem_needed = 0;
 181         vram_needed = 0;
 182         if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
 183                 system_mem_needed = size;
 184                 ttm_mem_needed = size;
 185         } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 186                 /*
 187                  * Conservatively round up the allocation requirement to 2 MB
 188                  * to avoid fragmentation caused by 4K allocations in the tail
 189                  * 2M BO chunk.
 190                  */
 191                 vram_needed = size;
 192                 /*
 193                  * For GFX 9.4.3, get the VRAM size from XCP structs
 194                  */
 195                 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
 196                         return -EINVAL;
 197
 198                 vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
 199                 if (adev->gmc.is_app_apu) {
 200                         system_mem_needed = size;
 201                         ttm_mem_needed = size;
 202                 }
 203         } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
 204                 system_mem_needed = size;
 205         } else if (!(alloc_flag &
 206                                 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
 207                                  KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
 208                 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
 209                 return -ENOMEM;
 210         }
 211
 212         spin_lock(&kfd_mem_limit.mem_limit_lock);
 213
 214         if (kfd_mem_limit.system_mem_used + system_mem_needed >
 215             kfd_mem_limit.max_system_mem_limit)
 216                 pr_debug("Set no_system_mem_limit=1 if using shared memory\n");
 217
 218         if ((kfd_mem_limit.system_mem_used + system_mem_needed >
 219              kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) ||
 220             (kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
 221              kfd_mem_limit.max_ttm_mem_limit) ||
 222             (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed >
 223              vram_size - reserved_for_pt)) {
 224                 ret = -ENOMEM;
 225                 goto release;
 226         }
 227
 228         /* Update memory accounting by decreasing available system
 229          * memory, TTM memory and GPU memory as computed above
 230          */
 231         WARN_ONCE(vram_needed && !adev,
 232                   "adev reference can't be null when vram is used");
 233         if (adev && xcp_id >= 0) {
 234                 adev->kfd.vram_used[xcp_id] += vram_needed;
 235                 adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
 236                                 vram_needed :
 237                                 ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
 238         }
 239         kfd_mem_limit.system_mem_used += system_mem_needed;
 240         kfd_mem_limit.ttm_mem_used += ttm_mem_needed;
 241
 242 release:
 243         spin_unlock(&kfd_mem_limit.mem_limit_lock);
 244         return ret;
 245 }
 246
 247 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
 248                 uint64_t size, u32 alloc_flag, int8_t xcp_id)
 249 {
 250         spin_lock(&kfd_mem_limit.mem_limit_lock);
 251
 252         if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
 253                 kfd_mem_limit.system_mem_used -= size;
 254                 kfd_mem_limit.ttm_mem_used -= size;
 255         } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
 256                 WARN_ONCE(!adev,
 257                           "adev reference can't be null when alloc mem flags vram is set");
 258                 if (WARN_ONCE(xcp_id < 0, "invalid XCP ID %d", xcp_id))
 259                         goto release;
 260
 261                 if (adev) {
 262                         adev->kfd.vram_used[xcp_id] -= size;
 263                         if (adev->gmc.is_app_apu) {
 264                                 adev->kfd.vram_used_aligned[xcp_id] -= size;
 265                                 kfd_mem_limit.system_mem_used -= size;
 266                                 kfd_mem_limit.ttm_mem_used -= size;
 267                         } else {
 268                                 adev->kfd.vram_used_aligned[xcp_id] -=
 269                                         ALIGN(size, VRAM_AVAILABLITY_ALIGN);
 270                         }
 271                 }
 272         } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
 273                 kfd_mem_limit.system_mem_used -= size;
 274         } else if (!(alloc_flag &
 275                                 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
 276                                  KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
 277                 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag);
 278                 goto release;
 279         }
 280         WARN_ONCE(adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] < 0,
 281                   "KFD VRAM memory accounting unbalanced for xcp: %d", xcp_id);
 282         WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0,
 283                   "KFD TTM memory accounting unbalanced");
 284         WARN_ONCE(kfd_mem_limit.system_mem_used < 0,
 285                   "KFD system memory accounting unbalanced");
 286
 287 release:
 288         spin_unlock(&kfd_mem_limit.mem_limit_lock);
 289 }
 290
 291 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
 292 {
 293         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 294         u32 alloc_flags = bo->kfd_bo->alloc_flags;
 295         u64 size = amdgpu_bo_size(bo);
 296
 297         amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags,
 298                                           bo->xcp_id);
 299
 300         kfree(bo->kfd_bo);
 301 }
 302
 303 /**
 304  * create_dmamap_sg_bo() - Creates a amdgpu_bo object to reflect information
 305  * about USERPTR or DOOREBELL or MMIO BO.
 306  *
 307  * @adev: Device for which dmamap BO is being created
 308  * @mem: BO of peer device that is being DMA mapped. Provides parameters
 309  *       in building the dmamap BO
 310  * @bo_out: Output parameter updated with handle of dmamap BO
 311  */
 312 static int
 313 create_dmamap_sg_bo(struct amdgpu_device *adev,
 314                  struct kgd_mem *mem, struct amdgpu_bo **bo_out)
 315 {
 316         struct drm_gem_object *gem_obj;
 317         int ret;
 318         uint64_t flags = 0;
 319
 320         ret = amdgpu_bo_reserve(mem->bo, false);
 321         if (ret)
 322                 return ret;
 323
 324         if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)
 325                 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
 326                                         AMDGPU_GEM_CREATE_UNCACHED);
 327
 328         ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1,
 329                         AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags,
 330                         ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0);
 331
 332         amdgpu_bo_unreserve(mem->bo);
 333
 334         if (ret) {
 335                 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret);
 336                 return -EINVAL;
 337         }
 338
 339         *bo_out = gem_to_amdgpu_bo(gem_obj);
 340         (*bo_out)->parent = amdgpu_bo_ref(mem->bo);
 341         return ret;
 342 }
 343
 344 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's
 345  *  reservation object.
 346  *
 347  * @bo: [IN] Remove eviction fence(s) from this BO
 348  * @ef: [IN] This eviction fence is removed if it
 349  *  is present in the shared list.
 350  *
 351  * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held.
 352  */
 353 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
 354                                         struct amdgpu_amdkfd_fence *ef)
 355 {
 356         struct dma_fence *replacement;
 357
 358         if (!ef)
 359                 return -EINVAL;
 360
 361         /* TODO: Instead of block before we should use the fence of the page
 362          * table update and TLB flush here directly.
 363          */
 364         replacement = dma_fence_get_stub();
 365         dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context,
 366                                 replacement, DMA_RESV_USAGE_BOOKKEEP);
 367         dma_fence_put(replacement);
 368         return 0;
 369 }
 370
 371 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
 372 {
 373         struct amdgpu_bo *root = bo;
 374         struct amdgpu_vm_bo_base *vm_bo;
 375         struct amdgpu_vm *vm;
 376         struct amdkfd_process_info *info;
 377         struct amdgpu_amdkfd_fence *ef;
 378         int ret;
 379
 380         /* we can always get vm_bo from root PD bo.*/
 381         while (root->parent)
 382                 root = root->parent;
 383
 384         vm_bo = root->vm_bo;
 385         if (!vm_bo)
 386                 return 0;
 387
 388         vm = vm_bo->vm;
 389         if (!vm)
 390                 return 0;
 391
 392         info = vm->process_info;
 393         if (!info || !info->eviction_fence)
 394                 return 0;
 395
 396         ef = container_of(dma_fence_get(&info->eviction_fence->base),
 397                         struct amdgpu_amdkfd_fence, base);
 398
 399         BUG_ON(!dma_resv_trylock(bo->tbo.base.resv));
 400         ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef);
 401         dma_resv_unlock(bo->tbo.base.resv);
 402
 403         dma_fence_put(&ef->base);
 404         return ret;
 405 }
 406
 407 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain,
 408                                      bool wait)
 409 {
 410         struct ttm_operation_ctx ctx = { false, false };
 411         int ret;
 412
 413         if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm),
 414                  "Called with userptr BO"))
 415                 return -EINVAL;
 416
 417         amdgpu_bo_placement_from_domain(bo, domain);
 418
 419         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 420         if (ret)
 421                 goto validate_fail;
 422         if (wait)
 423                 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
 424
 425 validate_fail:
 426         return ret;
 427 }
 428
 429 static int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
 430                                                uint32_t domain,
 431                                                struct dma_fence *fence)
 432 {
 433         int ret = amdgpu_bo_reserve(bo, false);
 434
 435         if (ret)
 436                 return ret;
 437
 438         ret = amdgpu_amdkfd_bo_validate(bo, domain, true);
 439         if (ret)
 440                 goto unreserve_out;
 441
 442         ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
 443         if (ret)
 444                 goto unreserve_out;
 445
 446         dma_resv_add_fence(bo->tbo.base.resv, fence,
 447                            DMA_RESV_USAGE_BOOKKEEP);
 448
 449 unreserve_out:
 450         amdgpu_bo_unreserve(bo);
 451
 452         return ret;
 453 }
 454
 455 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo)
 456 {
 457         return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false);
 458 }
 459
 460 /* vm_validate_pt_pd_bos - Validate page table and directory BOs
 461  *
 462  * Page directories are not updated here because huge page handling
 463  * during page table updates can invalidate page directory entries
 464  * again. Page directories are only updated after updating page
 465  * tables.
 466  */
 467 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 468 {
 469         struct amdgpu_bo *pd = vm->root.bo;
 470         struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 471         int ret;
 472
 473         ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL);
 474         if (ret) {
 475                 pr_err("failed to validate PT BOs\n");
 476                 return ret;
 477         }
 478
 479         vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 480
 481         return 0;
 482 }
 483
 484 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync)
 485 {
 486         struct amdgpu_bo *pd = vm->root.bo;
 487         struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 488         int ret;
 489
 490         ret = amdgpu_vm_update_pdes(adev, vm, false);
 491         if (ret)
 492                 return ret;
 493
 494         return amdgpu_sync_fence(sync, vm->last_update);
 495 }
 496
 497 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem)
 498 {
 499         uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE |
 500                                  AMDGPU_VM_MTYPE_DEFAULT;
 501
 502         if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE)
 503                 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE;
 504         if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE)
 505                 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE;
 506
 507         return amdgpu_gem_va_map_flags(adev, mapping_flags);
 508 }
 509
 510 /**
 511  * create_sg_table() - Create an sg_table for a contiguous DMA addr range
 512  * @addr: The starting address to point to
 513  * @size: Size of memory area in bytes being pointed to
 514  *
 515  * Allocates an instance of sg_table and initializes it to point to memory
 516  * area specified by input parameters. The address used to build is assumed
 517  * to be DMA mapped, if needed.
 518  *
 519  * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table
 520  * because they are physically contiguous.
 521  *
 522  * Return: Initialized instance of SG Table or NULL
 523  */
 524 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size)
 525 {
 526         struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL);
 527
 528         if (!sg)
 529                 return NULL;
 530         if (sg_alloc_table(sg, 1, GFP_KERNEL)) {
 531                 kfree(sg);
 532                 return NULL;
 533         }
 534         sg_dma_address(sg->sgl) = addr;
 535         sg->sgl->length = size;
 536 #ifdef CONFIG_NEED_SG_DMA_LENGTH
 537         sg->sgl->dma_length = size;
 538 #endif
 539         return sg;
 540 }
 541
 542 static int
 543 kfd_mem_dmamap_userptr(struct kgd_mem *mem,
 544                        struct kfd_mem_attachment *attachment)
 545 {
 546         enum dma_data_direction direction =
 547                 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 548                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 549         struct ttm_operation_ctx ctx = {.interruptible = true};
 550         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 551         struct amdgpu_device *adev = attachment->adev;
 552         struct ttm_tt *src_ttm = mem->bo->tbo.ttm;
 553         struct ttm_tt *ttm = bo->tbo.ttm;
 554         int ret;
 555
 556         if (WARN_ON(ttm->num_pages != src_ttm->num_pages))
 557                 return -EINVAL;
 558
 559         ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL);
 560         if (unlikely(!ttm->sg))
 561                 return -ENOMEM;
 562
 563         /* Same sequence as in amdgpu_ttm_tt_pin_userptr */
 564         ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages,
 565                                         ttm->num_pages, 0,
 566                                         (u64)ttm->num_pages << PAGE_SHIFT,
 567                                         GFP_KERNEL);
 568         if (unlikely(ret))
 569                 goto free_sg;
 570
 571         ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 572         if (unlikely(ret))
 573                 goto release_sg;
 574
 575         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 576         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 577         if (ret)
 578                 goto unmap_sg;
 579
 580         return 0;
 581
 582 unmap_sg:
 583         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 584 release_sg:
 585         pr_err("DMA map userptr failed: %d\n", ret);
 586         sg_free_table(ttm->sg);
 587 free_sg:
 588         kfree(ttm->sg);
 589         ttm->sg = NULL;
 590         return ret;
 591 }
 592
 593 static int
 594 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment)
 595 {
 596         struct ttm_operation_ctx ctx = {.interruptible = true};
 597         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 598         int ret;
 599
 600         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
 601         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 602         if (ret)
 603                 return ret;
 604
 605         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 606         return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 607 }
 608
 609 /**
 610  * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO
 611  * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
 612  * @attachment: Virtual address attachment of the BO on accessing device
 613  *
 614  * An access request from the device that owns DOORBELL does not require DMA mapping.
 615  * This is because the request doesn't go through PCIe root complex i.e. it instead
 616  * loops back. The need to DMA map arises only when accessing peer device's DOORBELL
 617  *
 618  * In contrast, all access requests for MMIO need to be DMA mapped without regard to
 619  * device ownership. This is because access requests for MMIO go through PCIe root
 620  * complex.
 621  *
 622  * This is accomplished in two steps:
 623  *   - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used
 624  *         in updating requesting device's page table
 625  *   - Signal TTM to mark memory pointed to by requesting device's BO as GPU
 626  *         accessible. This allows an update of requesting device's page table
 627  *         with entries associated with DOOREBELL or MMIO memory
 628  *
 629  * This method is invoked in the following contexts:
 630  *   - Mapping of DOORBELL or MMIO BO of same or peer device
 631  *   - Validating an evicted DOOREBELL or MMIO BO on device seeking access
 632  *
 633  * Return: ZERO if successful, NON-ZERO otherwise
 634  */
 635 static int
 636 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem,
 637                      struct kfd_mem_attachment *attachment)
 638 {
 639         struct ttm_operation_ctx ctx = {.interruptible = true};
 640         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 641         struct amdgpu_device *adev = attachment->adev;
 642         struct ttm_tt *ttm = bo->tbo.ttm;
 643         enum dma_data_direction dir;
 644         dma_addr_t dma_addr;
 645         bool mmio;
 646         int ret;
 647
 648         /* Expect SG Table of dmapmap BO to be NULL */
 649         mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP);
 650         if (unlikely(ttm->sg)) {
 651                 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio);
 652                 return -EINVAL;
 653         }
 654
 655         dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 656                         DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 657         dma_addr = mem->bo->tbo.sg->sgl->dma_address;
 658         pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length);
 659         pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr);
 660         dma_addr = dma_map_resource(adev->dev, dma_addr,
 661                         mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
 662         ret = dma_mapping_error(adev->dev, dma_addr);
 663         if (unlikely(ret))
 664                 return ret;
 665         pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr);
 666
 667         ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length);
 668         if (unlikely(!ttm->sg)) {
 669                 ret = -ENOMEM;
 670                 goto unmap_sg;
 671         }
 672
 673         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
 674         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 675         if (unlikely(ret))
 676                 goto free_sg;
 677
 678         return ret;
 679
 680 free_sg:
 681         sg_free_table(ttm->sg);
 682         kfree(ttm->sg);
 683         ttm->sg = NULL;
 684 unmap_sg:
 685         dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length,
 686                            dir, DMA_ATTR_SKIP_CPU_SYNC);
 687         return ret;
 688 }
 689
 690 static int
 691 kfd_mem_dmamap_attachment(struct kgd_mem *mem,
 692                           struct kfd_mem_attachment *attachment)
 693 {
 694         switch (attachment->type) {
 695         case KFD_MEM_ATT_SHARED:
 696                 return 0;
 697         case KFD_MEM_ATT_USERPTR:
 698                 return kfd_mem_dmamap_userptr(mem, attachment);
 699         case KFD_MEM_ATT_DMABUF:
 700                 return kfd_mem_dmamap_dmabuf(attachment);
 701         case KFD_MEM_ATT_SG:
 702                 return kfd_mem_dmamap_sg_bo(mem, attachment);
 703         default:
 704                 WARN_ON_ONCE(1);
 705         }
 706         return -EINVAL;
 707 }
 708
 709 static void
 710 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem,
 711                          struct kfd_mem_attachment *attachment)
 712 {
 713         enum dma_data_direction direction =
 714                 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 715                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 716         struct ttm_operation_ctx ctx = {.interruptible = false};
 717         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 718         struct amdgpu_device *adev = attachment->adev;
 719         struct ttm_tt *ttm = bo->tbo.ttm;
 720
 721         if (unlikely(!ttm->sg))
 722                 return;
 723
 724         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
 725         ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 726
 727         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 728         sg_free_table(ttm->sg);
 729         kfree(ttm->sg);
 730         ttm->sg = NULL;
 731 }
 732
 733 static void
 734 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment)
 735 {
 736         /* This is a no-op. We don't want to trigger eviction fences when
 737          * unmapping DMABufs. Therefore the invalidation (moving to system
 738          * domain) is done in kfd_mem_dmamap_dmabuf.
 739          */
 740 }
 741
 742 /**
 743  * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO
 744  * @mem: SG BO of the DOORBELL or MMIO resource on the owning device
 745  * @attachment: Virtual address attachment of the BO on accessing device
 746  *
 747  * The method performs following steps:
 748  *   - Signal TTM to mark memory pointed to by BO as GPU inaccessible
 749  *   - Free SG Table that is used to encapsulate DMA mapped memory of
 750  *          peer device's DOORBELL or MMIO memory
 751  *
 752  * This method is invoked in the following contexts:
 753  *     UNMapping of DOORBELL or MMIO BO on a device having access to its memory
 754  *     Eviction of DOOREBELL or MMIO BO on device having access to its memory
 755  *
 756  * Return: void
 757  */
 758 static void
 759 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem,
 760                        struct kfd_mem_attachment *attachment)
 761 {
 762         struct ttm_operation_ctx ctx = {.interruptible = true};
 763         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
 764         struct amdgpu_device *adev = attachment->adev;
 765         struct ttm_tt *ttm = bo->tbo.ttm;
 766         enum dma_data_direction dir;
 767
 768         if (unlikely(!ttm->sg)) {
 769                 pr_debug("SG Table of BO is NULL");
 770                 return;
 771         }
 772
 773         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
 774         ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 775
 776         dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 777                                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 778         dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address,
 779                         ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC);
 780         sg_free_table(ttm->sg);
 781         kfree(ttm->sg);
 782         ttm->sg = NULL;
 783         bo->tbo.sg = NULL;
 784 }
 785
 786 static void
 787 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem,
 788                             struct kfd_mem_attachment *attachment)
 789 {
 790         switch (attachment->type) {
 791         case KFD_MEM_ATT_SHARED:
 792                 break;
 793         case KFD_MEM_ATT_USERPTR:
 794                 kfd_mem_dmaunmap_userptr(mem, attachment);
 795                 break;
 796         case KFD_MEM_ATT_DMABUF:
 797                 kfd_mem_dmaunmap_dmabuf(attachment);
 798                 break;
 799         case KFD_MEM_ATT_SG:
 800                 kfd_mem_dmaunmap_sg_bo(mem, attachment);
 801                 break;
 802         default:
 803                 WARN_ON_ONCE(1);
 804         }
 805 }
 806
 807 static int kfd_mem_export_dmabuf(struct kgd_mem *mem)
 808 {
 809         if (!mem->dmabuf) {
 810                 struct amdgpu_device *bo_adev;
 811                 struct dma_buf *dmabuf;
 812                 int r, fd;
 813
 814                 bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
 815                 r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file,
 816                                                mem->gem_handle,
 817                         mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ?
 818                                                DRM_RDWR : 0, &fd);
 819                 if (r)
 820                         return r;
 821                 dmabuf = dma_buf_get(fd);
 822                 close_fd(fd);
 823                 if (WARN_ON_ONCE(IS_ERR(dmabuf)))
 824                         return PTR_ERR(dmabuf);
 825                 mem->dmabuf = dmabuf;
 826         }
 827
 828         return 0;
 829 }
 830
 831 static int
 832 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem,
 833                       struct amdgpu_bo **bo)
 834 {
 835         struct drm_gem_object *gobj;
 836         int ret;
 837
 838         ret = kfd_mem_export_dmabuf(mem);
 839         if (ret)
 840                 return ret;
 841
 842         gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf);
 843         if (IS_ERR(gobj))
 844                 return PTR_ERR(gobj);
 845
 846         *bo = gem_to_amdgpu_bo(gobj);
 847         (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE;
 848
 849         return 0;
 850 }
 851
 852 /* kfd_mem_attach - Add a BO to a VM
 853  *
 854  * Everything that needs to bo done only once when a BO is first added
 855  * to a VM. It can later be mapped and unmapped many times without
 856  * repeating these steps.
 857  *
 858  * 0. Create BO for DMA mapping, if needed
 859  * 1. Allocate and initialize BO VA entry data structure
 860  * 2. Add BO to the VM
 861  * 3. Determine ASIC-specific PTE flags
 862  * 4. Alloc page tables and directories if needed
 863  * 4a.  Validate new page tables and directories
 864  */
 865 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
 866                 struct amdgpu_vm *vm, bool is_aql)
 867 {
 868         struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev);
 869         unsigned long bo_size = mem->bo->tbo.base.size;
 870         uint64_t va = mem->va;
 871         struct kfd_mem_attachment *attachment[2] = {NULL, NULL};
 872         struct amdgpu_bo *bo[2] = {NULL, NULL};
 873         struct amdgpu_bo_va *bo_va;
 874         bool same_hive = false;
 875         int i, ret;
 876
 877         if (!va) {
 878                 pr_err("Invalid VA when adding BO to VM\n");
 879                 return -EINVAL;
 880         }
 881
 882         /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices
 883          *
 884          * The access path of MMIO and DOORBELL BOs of is always over PCIe.
 885          * In contrast the access path of VRAM BOs depens upon the type of
 886          * link that connects the peer device. Access over PCIe is allowed
 887          * if peer device has large BAR. In contrast, access over xGMI is
 888          * allowed for both small and large BAR configurations of peer device
 889          */
 890         if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
 891             ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
 892              (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
 893              (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
 894                 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM)
 895                         same_hive = amdgpu_xgmi_same_hive(adev, bo_adev);
 896                 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev))
 897                         return -EINVAL;
 898         }
 899
 900         for (i = 0; i <= is_aql; i++) {
 901                 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL);
 902                 if (unlikely(!attachment[i])) {
 903                         ret = -ENOMEM;
 904                         goto unwind;
 905                 }
 906
 907                 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va,
 908                          va + bo_size, vm);
 909
 910                 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) ||
 911                     (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) ||
 912                     (mem->domain == AMDGPU_GEM_DOMAIN_GTT && reuse_dmamap(adev, bo_adev)) ||
 913                     same_hive) {
 914                         /* Mappings on the local GPU, or VRAM mappings in the
 915                          * local hive, or userptr, or GTT mapping can reuse dma map
 916                          * address space share the original BO
 917                          */
 918                         attachment[i]->type = KFD_MEM_ATT_SHARED;
 919                         bo[i] = mem->bo;
 920                         drm_gem_object_get(&bo[i]->tbo.base);
 921                 } else if (i > 0) {
 922                         /* Multiple mappings on the same GPU share the BO */
 923                         attachment[i]->type = KFD_MEM_ATT_SHARED;
 924                         bo[i] = bo[0];
 925                         drm_gem_object_get(&bo[i]->tbo.base);
 926                 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
 927                         /* Create an SG BO to DMA-map userptrs on other GPUs */
 928                         attachment[i]->type = KFD_MEM_ATT_USERPTR;
 929                         ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
 930                         if (ret)
 931                                 goto unwind;
 932                 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */
 933                 } else if (mem->bo->tbo.type == ttm_bo_type_sg) {
 934                         WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL ||
 935                                     mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP),
 936                                   "Handing invalid SG BO in ATTACH request");
 937                         attachment[i]->type = KFD_MEM_ATT_SG;
 938                         ret = create_dmamap_sg_bo(adev, mem, &bo[i]);
 939                         if (ret)
 940                                 goto unwind;
 941                 /* Enable acces to GTT and VRAM BOs of peer devices */
 942                 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT ||
 943                            mem->domain == AMDGPU_GEM_DOMAIN_VRAM) {
 944                         attachment[i]->type = KFD_MEM_ATT_DMABUF;
 945                         ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]);
 946                         if (ret)
 947                                 goto unwind;
 948                         pr_debug("Employ DMABUF mechanism to enable peer GPU access\n");
 949                 } else {
 950                         WARN_ONCE(true, "Handling invalid ATTACH request");
 951                         ret = -EINVAL;
 952                         goto unwind;
 953                 }
 954
 955                 /* Add BO to VM internal data structures */
 956                 ret = amdgpu_bo_reserve(bo[i], false);
 957                 if (ret) {
 958                         pr_debug("Unable to reserve BO during memory attach");
 959                         goto unwind;
 960                 }
 961                 bo_va = amdgpu_vm_bo_find(vm, bo[i]);
 962                 if (!bo_va)
 963                         bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]);
 964                 else
 965                         ++bo_va->ref_count;
 966                 attachment[i]->bo_va = bo_va;
 967                 amdgpu_bo_unreserve(bo[i]);
 968                 if (unlikely(!attachment[i]->bo_va)) {
 969                         ret = -ENOMEM;
 970                         pr_err("Failed to add BO object to VM. ret == %d\n",
 971                                ret);
 972                         goto unwind;
 973                 }
 974                 attachment[i]->va = va;
 975                 attachment[i]->pte_flags = get_pte_flags(adev, mem);
 976                 attachment[i]->adev = adev;
 977                 list_add(&attachment[i]->list, &mem->attachments);
 978
 979                 va += bo_size;
 980         }
 981
 982         return 0;
 983
 984 unwind:
 985         for (; i >= 0; i--) {
 986                 if (!attachment[i])
 987                         continue;
 988                 if (attachment[i]->bo_va) {
 989                         amdgpu_bo_reserve(bo[i], true);
 990                         if (--attachment[i]->bo_va->ref_count == 0)
 991                                 amdgpu_vm_bo_del(adev, attachment[i]->bo_va);
 992                         amdgpu_bo_unreserve(bo[i]);
 993                         list_del(&attachment[i]->list);
 994                 }
 995                 if (bo[i])
 996                         drm_gem_object_put(&bo[i]->tbo.base);
 997                 kfree(attachment[i]);
 998         }
 999         return ret;
1000 }
1001
1002 static void kfd_mem_detach(struct kfd_mem_attachment *attachment)
1003 {
1004         struct amdgpu_bo *bo = attachment->bo_va->base.bo;
1005
1006         pr_debug("\t remove VA 0x%llx in entry %p\n",
1007                         attachment->va, attachment);
1008         if (--attachment->bo_va->ref_count == 0)
1009                 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va);
1010         drm_gem_object_put(&bo->tbo.base);
1011         list_del(&attachment->list);
1012         kfree(attachment);
1013 }
1014
1015 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem,
1016                                 struct amdkfd_process_info *process_info,
1017                                 bool userptr)
1018 {
1019         mutex_lock(&process_info->lock);
1020         if (userptr)
1021                 list_add_tail(&mem->validate_list,
1022                               &process_info->userptr_valid_list);
1023         else
1024                 list_add_tail(&mem->validate_list, &process_info->kfd_bo_list);
1025         mutex_unlock(&process_info->lock);
1026 }
1027
1028 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem,
1029                 struct amdkfd_process_info *process_info)
1030 {
1031         mutex_lock(&process_info->lock);
1032         list_del(&mem->validate_list);
1033         mutex_unlock(&process_info->lock);
1034 }
1035
1036 /* Initializes user pages. It registers the MMU notifier and validates
1037  * the userptr BO in the GTT domain.
1038  *
1039  * The BO must already be on the userptr_valid_list. Otherwise an
1040  * eviction and restore may happen that leaves the new BO unmapped
1041  * with the user mode queues running.
1042  *
1043  * Takes the process_info->lock to protect against concurrent restore
1044  * workers.
1045  *
1046  * Returns 0 for success, negative errno for errors.
1047  */
1048 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr,
1049                            bool criu_resume)
1050 {
1051         struct amdkfd_process_info *process_info = mem->process_info;
1052         struct amdgpu_bo *bo = mem->bo;
1053         struct ttm_operation_ctx ctx = { true, false };
1054         struct hmm_range *range;
1055         int ret = 0;
1056
1057         mutex_lock(&process_info->lock);
1058
1059         ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0);
1060         if (ret) {
1061                 pr_err("%s: Failed to set userptr: %d\n", __func__, ret);
1062                 goto out;
1063         }
1064
1065         ret = amdgpu_hmm_register(bo, user_addr);
1066         if (ret) {
1067                 pr_err("%s: Failed to register MMU notifier: %d\n",
1068                        __func__, ret);
1069                 goto out;
1070         }
1071
1072         if (criu_resume) {
1073                 /*
1074                  * During a CRIU restore operation, the userptr buffer objects
1075                  * will be validated in the restore_userptr_work worker at a
1076                  * later stage when it is scheduled by another ioctl called by
1077                  * CRIU master process for the target pid for restore.
1078                  */
1079                 mutex_lock(&process_info->notifier_lock);
1080                 mem->invalid++;
1081                 mutex_unlock(&process_info->notifier_lock);
1082                 mutex_unlock(&process_info->lock);
1083                 return 0;
1084         }
1085
1086         ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range);
1087         if (ret) {
1088                 pr_err("%s: Failed to get user pages: %d\n", __func__, ret);
1089                 goto unregister_out;
1090         }
1091
1092         ret = amdgpu_bo_reserve(bo, true);
1093         if (ret) {
1094                 pr_err("%s: Failed to reserve BO\n", __func__);
1095                 goto release_out;
1096         }
1097         amdgpu_bo_placement_from_domain(bo, mem->domain);
1098         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1099         if (ret)
1100                 pr_err("%s: failed to validate BO\n", __func__);
1101         amdgpu_bo_unreserve(bo);
1102
1103 release_out:
1104         amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range);
1105 unregister_out:
1106         if (ret)
1107                 amdgpu_hmm_unregister(bo);
1108 out:
1109         mutex_unlock(&process_info->lock);
1110         return ret;
1111 }
1112
1113 /* Reserving a BO and its page table BOs must happen atomically to
1114  * avoid deadlocks. Some operations update multiple VMs at once. Track
1115  * all the reservation info in a context structure. Optionally a sync
1116  * object can track VM updates.
1117  */
1118 struct bo_vm_reservation_context {
1119         /* DRM execution context for the reservation */
1120         struct drm_exec exec;
1121         /* Number of VMs reserved */
1122         unsigned int n_vms;
1123         /* Pointer to sync object */
1124         struct amdgpu_sync *sync;
1125 };
1126
1127 enum bo_vm_match {
1128         BO_VM_NOT_MAPPED = 0,   /* Match VMs where a BO is not mapped */
1129         BO_VM_MAPPED,           /* Match VMs where a BO is mapped     */
1130         BO_VM_ALL,              /* Match all VMs a BO was added to    */
1131 };
1132
1133 /**
1134  * reserve_bo_and_vm - reserve a BO and a VM unconditionally.
1135  * @mem: KFD BO structure.
1136  * @vm: the VM to reserve.
1137  * @ctx: the struct that will be used in unreserve_bo_and_vms().
1138  */
1139 static int reserve_bo_and_vm(struct kgd_mem *mem,
1140                               struct amdgpu_vm *vm,
1141                               struct bo_vm_reservation_context *ctx)
1142 {
1143         struct amdgpu_bo *bo = mem->bo;
1144         int ret;
1145
1146         WARN_ON(!vm);
1147
1148         ctx->n_vms = 1;
1149         ctx->sync = &mem->sync;
1150         drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1151         drm_exec_until_all_locked(&ctx->exec) {
1152                 ret = amdgpu_vm_lock_pd(vm, &ctx->exec, 2);
1153                 drm_exec_retry_on_contention(&ctx->exec);
1154                 if (unlikely(ret))
1155                         goto error;
1156
1157                 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1158                 drm_exec_retry_on_contention(&ctx->exec);
1159                 if (unlikely(ret))
1160                         goto error;
1161         }
1162         return 0;
1163
1164 error:
1165         pr_err("Failed to reserve buffers in ttm.\n");
1166         drm_exec_fini(&ctx->exec);
1167         return ret;
1168 }
1169
1170 /**
1171  * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally
1172  * @mem: KFD BO structure.
1173  * @vm: the VM to reserve. If NULL, then all VMs associated with the BO
1174  * is used. Otherwise, a single VM associated with the BO.
1175  * @map_type: the mapping status that will be used to filter the VMs.
1176  * @ctx: the struct that will be used in unreserve_bo_and_vms().
1177  *
1178  * Returns 0 for success, negative for failure.
1179  */
1180 static int reserve_bo_and_cond_vms(struct kgd_mem *mem,
1181                                 struct amdgpu_vm *vm, enum bo_vm_match map_type,
1182                                 struct bo_vm_reservation_context *ctx)
1183 {
1184         struct kfd_mem_attachment *entry;
1185         struct amdgpu_bo *bo = mem->bo;
1186         int ret;
1187
1188         ctx->sync = &mem->sync;
1189         drm_exec_init(&ctx->exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
1190         drm_exec_until_all_locked(&ctx->exec) {
1191                 ctx->n_vms = 0;
1192                 list_for_each_entry(entry, &mem->attachments, list) {
1193                         if ((vm && vm != entry->bo_va->base.vm) ||
1194                                 (entry->is_mapped != map_type
1195                                 && map_type != BO_VM_ALL))
1196                                 continue;
1197
1198                         ret = amdgpu_vm_lock_pd(entry->bo_va->base.vm,
1199                                                 &ctx->exec, 2);
1200                         drm_exec_retry_on_contention(&ctx->exec);
1201                         if (unlikely(ret))
1202                                 goto error;
1203                         ++ctx->n_vms;
1204                 }
1205
1206                 ret = drm_exec_prepare_obj(&ctx->exec, &bo->tbo.base, 1);
1207                 drm_exec_retry_on_contention(&ctx->exec);
1208                 if (unlikely(ret))
1209                         goto error;
1210         }
1211         return 0;
1212
1213 error:
1214         pr_err("Failed to reserve buffers in ttm.\n");
1215         drm_exec_fini(&ctx->exec);
1216         return ret;
1217 }
1218
1219 /**
1220  * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context
1221  * @ctx: Reservation context to unreserve
1222  * @wait: Optionally wait for a sync object representing pending VM updates
1223  * @intr: Whether the wait is interruptible
1224  *
1225  * Also frees any resources allocated in
1226  * reserve_bo_and_(cond_)vm(s). Returns the status from
1227  * amdgpu_sync_wait.
1228  */
1229 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx,
1230                                  bool wait, bool intr)
1231 {
1232         int ret = 0;
1233
1234         if (wait)
1235                 ret = amdgpu_sync_wait(ctx->sync, intr);
1236
1237         drm_exec_fini(&ctx->exec);
1238         ctx->sync = NULL;
1239         return ret;
1240 }
1241
1242 static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
1243                                 struct kfd_mem_attachment *entry,
1244                                 struct amdgpu_sync *sync)
1245 {
1246         struct amdgpu_bo_va *bo_va = entry->bo_va;
1247         struct amdgpu_device *adev = entry->adev;
1248         struct amdgpu_vm *vm = bo_va->base.vm;
1249
1250         amdgpu_vm_bo_unmap(adev, bo_va, entry->va);
1251
1252         amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update);
1253
1254         amdgpu_sync_fence(sync, bo_va->last_pt_update);
1255 }
1256
1257 static int update_gpuvm_pte(struct kgd_mem *mem,
1258                             struct kfd_mem_attachment *entry,
1259                             struct amdgpu_sync *sync)
1260 {
1261         struct amdgpu_bo_va *bo_va = entry->bo_va;
1262         struct amdgpu_device *adev = entry->adev;
1263         int ret;
1264
1265         ret = kfd_mem_dmamap_attachment(mem, entry);
1266         if (ret)
1267                 return ret;
1268
1269         /* Update the page tables  */
1270         ret = amdgpu_vm_bo_update(adev, bo_va, false);
1271         if (ret) {
1272                 pr_err("amdgpu_vm_bo_update failed\n");
1273                 return ret;
1274         }
1275
1276         return amdgpu_sync_fence(sync, bo_va->last_pt_update);
1277 }
1278
1279 static int map_bo_to_gpuvm(struct kgd_mem *mem,
1280                            struct kfd_mem_attachment *entry,
1281                            struct amdgpu_sync *sync,
1282                            bool no_update_pte)
1283 {
1284         int ret;
1285
1286         /* Set virtual address for the allocation */
1287         ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0,
1288                                amdgpu_bo_size(entry->bo_va->base.bo),
1289                                entry->pte_flags);
1290         if (ret) {
1291                 pr_err("Failed to map VA 0x%llx in vm. ret %d\n",
1292                                 entry->va, ret);
1293                 return ret;
1294         }
1295
1296         if (no_update_pte)
1297                 return 0;
1298
1299         ret = update_gpuvm_pte(mem, entry, sync);
1300         if (ret) {
1301                 pr_err("update_gpuvm_pte() failed\n");
1302                 goto update_gpuvm_pte_failed;
1303         }
1304
1305         return 0;
1306
1307 update_gpuvm_pte_failed:
1308         unmap_bo_from_gpuvm(mem, entry, sync);
1309         kfd_mem_dmaunmap_attachment(mem, entry);
1310         return ret;
1311 }
1312
1313 static int process_validate_vms(struct amdkfd_process_info *process_info)
1314 {
1315         struct amdgpu_vm *peer_vm;
1316         int ret;
1317
1318         list_for_each_entry(peer_vm, &process_info->vm_list_head,
1319                             vm_list_node) {
1320                 ret = vm_validate_pt_pd_bos(peer_vm);
1321                 if (ret)
1322                         return ret;
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int process_sync_pds_resv(struct amdkfd_process_info *process_info,
1329                                  struct amdgpu_sync *sync)
1330 {
1331         struct amdgpu_vm *peer_vm;
1332         int ret;
1333
1334         list_for_each_entry(peer_vm, &process_info->vm_list_head,
1335                             vm_list_node) {
1336                 struct amdgpu_bo *pd = peer_vm->root.bo;
1337
1338                 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv,
1339                                        AMDGPU_SYNC_NE_OWNER,
1340                                        AMDGPU_FENCE_OWNER_KFD);
1341                 if (ret)
1342                         return ret;
1343         }
1344
1345         return 0;
1346 }
1347
1348 static int process_update_pds(struct amdkfd_process_info *process_info,
1349                               struct amdgpu_sync *sync)
1350 {
1351         struct amdgpu_vm *peer_vm;
1352         int ret;
1353
1354         list_for_each_entry(peer_vm, &process_info->vm_list_head,
1355                             vm_list_node) {
1356                 ret = vm_update_pds(peer_vm, sync);
1357                 if (ret)
1358                         return ret;
1359         }
1360
1361         return 0;
1362 }
1363
1364 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info,
1365                        struct dma_fence **ef)
1366 {
1367         struct amdkfd_process_info *info = NULL;
1368         int ret;
1369
1370         if (!*process_info) {
1371                 info = kzalloc(sizeof(*info), GFP_KERNEL);
1372                 if (!info)
1373                         return -ENOMEM;
1374
1375                 mutex_init(&info->lock);
1376                 mutex_init(&info->notifier_lock);
1377                 INIT_LIST_HEAD(&info->vm_list_head);
1378                 INIT_LIST_HEAD(&info->kfd_bo_list);
1379                 INIT_LIST_HEAD(&info->userptr_valid_list);
1380                 INIT_LIST_HEAD(&info->userptr_inval_list);
1381
1382                 info->eviction_fence =
1383                         amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1),
1384                                                    current->mm,
1385                                                    NULL);
1386                 if (!info->eviction_fence) {
1387                         pr_err("Failed to create eviction fence\n");
1388                         ret = -ENOMEM;
1389                         goto create_evict_fence_fail;
1390                 }
1391
1392                 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID);
1393                 INIT_DELAYED_WORK(&info->restore_userptr_work,
1394                                   amdgpu_amdkfd_restore_userptr_worker);
1395
1396                 *process_info = info;
1397         }
1398
1399         vm->process_info = *process_info;
1400
1401         /* Validate page directory and attach eviction fence */
1402         ret = amdgpu_bo_reserve(vm->root.bo, true);
1403         if (ret)
1404                 goto reserve_pd_fail;
1405         ret = vm_validate_pt_pd_bos(vm);
1406         if (ret) {
1407                 pr_err("validate_pt_pd_bos() failed\n");
1408                 goto validate_pd_fail;
1409         }
1410         ret = amdgpu_bo_sync_wait(vm->root.bo,
1411                                   AMDGPU_FENCE_OWNER_KFD, false);
1412         if (ret)
1413                 goto wait_pd_fail;
1414         ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1);
1415         if (ret)
1416                 goto reserve_shared_fail;
1417         dma_resv_add_fence(vm->root.bo->tbo.base.resv,
1418                            &vm->process_info->eviction_fence->base,
1419                            DMA_RESV_USAGE_BOOKKEEP);
1420         amdgpu_bo_unreserve(vm->root.bo);
1421
1422         /* Update process info */
1423         mutex_lock(&vm->process_info->lock);
1424         list_add_tail(&vm->vm_list_node,
1425                         &(vm->process_info->vm_list_head));
1426         vm->process_info->n_vms++;
1427
1428         *ef = dma_fence_get(&vm->process_info->eviction_fence->base);
1429         mutex_unlock(&vm->process_info->lock);
1430
1431         return 0;
1432
1433 reserve_shared_fail:
1434 wait_pd_fail:
1435 validate_pd_fail:
1436         amdgpu_bo_unreserve(vm->root.bo);
1437 reserve_pd_fail:
1438         vm->process_info = NULL;
1439         if (info) {
1440                 dma_fence_put(&info->eviction_fence->base);
1441                 *process_info = NULL;
1442                 put_pid(info->pid);
1443 create_evict_fence_fail:
1444                 mutex_destroy(&info->lock);
1445                 mutex_destroy(&info->notifier_lock);
1446                 kfree(info);
1447         }
1448         return ret;
1449 }
1450
1451 /**
1452  * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria
1453  * @bo: Handle of buffer object being pinned
1454  * @domain: Domain into which BO should be pinned
1455  *
1456  *   - USERPTR BOs are UNPINNABLE and will return error
1457  *   - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1458  *     PIN count incremented. It is valid to PIN a BO multiple times
1459  *
1460  * Return: ZERO if successful in pinning, Non-Zero in case of error.
1461  */
1462 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain)
1463 {
1464         int ret = 0;
1465
1466         ret = amdgpu_bo_reserve(bo, false);
1467         if (unlikely(ret))
1468                 return ret;
1469
1470         ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1471         if (ret)
1472                 pr_err("Error in Pinning BO to domain: %d\n", domain);
1473
1474         amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false);
1475         amdgpu_bo_unreserve(bo);
1476
1477         return ret;
1478 }
1479
1480 /**
1481  * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria
1482  * @bo: Handle of buffer object being unpinned
1483  *
1484  *   - Is a illegal request for USERPTR BOs and is ignored
1485  *   - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their
1486  *     PIN count decremented. Calls to UNPIN must balance calls to PIN
1487  */
1488 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo)
1489 {
1490         int ret = 0;
1491
1492         ret = amdgpu_bo_reserve(bo, false);
1493         if (unlikely(ret))
1494                 return;
1495
1496         amdgpu_bo_unpin(bo);
1497         amdgpu_bo_unreserve(bo);
1498 }
1499
1500 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
1501                                      struct amdgpu_vm *avm, u32 pasid)
1502
1503 {
1504         int ret;
1505
1506         /* Free the original amdgpu allocated pasid,
1507          * will be replaced with kfd allocated pasid.
1508          */
1509         if (avm->pasid) {
1510                 amdgpu_pasid_free(avm->pasid);
1511                 amdgpu_vm_set_pasid(adev, avm, 0);
1512         }
1513
1514         ret = amdgpu_vm_set_pasid(adev, avm, pasid);
1515         if (ret)
1516                 return ret;
1517
1518         return 0;
1519 }
1520
1521 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
1522                                            struct amdgpu_vm *avm,
1523                                            void **process_info,
1524                                            struct dma_fence **ef)
1525 {
1526         int ret;
1527
1528         /* Already a compute VM? */
1529         if (avm->process_info)
1530                 return -EINVAL;
1531
1532         /* Convert VM into a compute VM */
1533         ret = amdgpu_vm_make_compute(adev, avm);
1534         if (ret)
1535                 return ret;
1536
1537         /* Initialize KFD part of the VM and process info */
1538         ret = init_kfd_vm(avm, process_info, ef);
1539         if (ret)
1540                 return ret;
1541
1542         amdgpu_vm_set_task_info(avm);
1543
1544         return 0;
1545 }
1546
1547 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
1548                                     struct amdgpu_vm *vm)
1549 {
1550         struct amdkfd_process_info *process_info = vm->process_info;
1551
1552         if (!process_info)
1553                 return;
1554
1555         /* Update process info */
1556         mutex_lock(&process_info->lock);
1557         process_info->n_vms--;
1558         list_del(&vm->vm_list_node);
1559         mutex_unlock(&process_info->lock);
1560
1561         vm->process_info = NULL;
1562
1563         /* Release per-process resources when last compute VM is destroyed */
1564         if (!process_info->n_vms) {
1565                 WARN_ON(!list_empty(&process_info->kfd_bo_list));
1566                 WARN_ON(!list_empty(&process_info->userptr_valid_list));
1567                 WARN_ON(!list_empty(&process_info->userptr_inval_list));
1568
1569                 dma_fence_put(&process_info->eviction_fence->base);
1570                 cancel_delayed_work_sync(&process_info->restore_userptr_work);
1571                 put_pid(process_info->pid);
1572                 mutex_destroy(&process_info->lock);
1573                 mutex_destroy(&process_info->notifier_lock);
1574                 kfree(process_info);
1575         }
1576 }
1577
1578 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
1579                                             void *drm_priv)
1580 {
1581         struct amdgpu_vm *avm;
1582
1583         if (WARN_ON(!adev || !drm_priv))
1584                 return;
1585
1586         avm = drm_priv_to_vm(drm_priv);
1587
1588         pr_debug("Releasing process vm %p\n", avm);
1589
1590         /* The original pasid of amdgpu vm has already been
1591          * released during making a amdgpu vm to a compute vm
1592          * The current pasid is managed by kfd and will be
1593          * released on kfd process destroy. Set amdgpu pasid
1594          * to 0 to avoid duplicate release.
1595          */
1596         amdgpu_vm_release_compute(adev, avm);
1597 }
1598
1599 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv)
1600 {
1601         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1602         struct amdgpu_bo *pd = avm->root.bo;
1603         struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
1604
1605         if (adev->asic_type < CHIP_VEGA10)
1606                 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT;
1607         return avm->pd_phys_addr;
1608 }
1609
1610 void amdgpu_amdkfd_block_mmu_notifications(void *p)
1611 {
1612         struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1613
1614         mutex_lock(&pinfo->lock);
1615         WRITE_ONCE(pinfo->block_mmu_notifications, true);
1616         mutex_unlock(&pinfo->lock);
1617 }
1618
1619 int amdgpu_amdkfd_criu_resume(void *p)
1620 {
1621         int ret = 0;
1622         struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p;
1623
1624         mutex_lock(&pinfo->lock);
1625         pr_debug("scheduling work\n");
1626         mutex_lock(&pinfo->notifier_lock);
1627         pinfo->evicted_bos++;
1628         mutex_unlock(&pinfo->notifier_lock);
1629         if (!READ_ONCE(pinfo->block_mmu_notifications)) {
1630                 ret = -EINVAL;
1631                 goto out_unlock;
1632         }
1633         WRITE_ONCE(pinfo->block_mmu_notifications, false);
1634         queue_delayed_work(system_freezable_wq,
1635                            &pinfo->restore_userptr_work, 0);
1636
1637 out_unlock:
1638         mutex_unlock(&pinfo->lock);
1639         return ret;
1640 }
1641
1642 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
1643                                           uint8_t xcp_id)
1644 {
1645         uint64_t reserved_for_pt =
1646                 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size);
1647         ssize_t available;
1648         uint64_t vram_available, system_mem_available, ttm_mem_available;
1649
1650         spin_lock(&kfd_mem_limit.mem_limit_lock);
1651         vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id)
1652                 - adev->kfd.vram_used_aligned[xcp_id]
1653                 - atomic64_read(&adev->vram_pin_size)
1654                 - reserved_for_pt;
1655
1656         if (adev->gmc.is_app_apu) {
1657                 system_mem_available = no_system_mem_limit ?
1658                                         kfd_mem_limit.max_system_mem_limit :
1659                                         kfd_mem_limit.max_system_mem_limit -
1660                                         kfd_mem_limit.system_mem_used;
1661
1662                 ttm_mem_available = kfd_mem_limit.max_ttm_mem_limit -
1663                                 kfd_mem_limit.ttm_mem_used;
1664
1665                 available = min3(system_mem_available, ttm_mem_available,
1666                                  vram_available);
1667                 available = ALIGN_DOWN(available, PAGE_SIZE);
1668         } else {
1669                 available = ALIGN_DOWN(vram_available, VRAM_AVAILABLITY_ALIGN);
1670         }
1671
1672         spin_unlock(&kfd_mem_limit.mem_limit_lock);
1673
1674         if (available < 0)
1675                 available = 0;
1676
1677         return available;
1678 }
1679
1680 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1681                 struct amdgpu_device *adev, uint64_t va, uint64_t size,
1682                 void *drm_priv, struct kgd_mem **mem,
1683                 uint64_t *offset, uint32_t flags, bool criu_resume)
1684 {
1685         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1686         struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm);
1687         enum ttm_bo_type bo_type = ttm_bo_type_device;
1688         struct sg_table *sg = NULL;
1689         uint64_t user_addr = 0;
1690         struct amdgpu_bo *bo;
1691         struct drm_gem_object *gobj = NULL;
1692         u32 domain, alloc_domain;
1693         uint64_t aligned_size;
1694         int8_t xcp_id = -1;
1695         u64 alloc_flags;
1696         int ret;
1697
1698         /*
1699          * Check on which domain to allocate BO
1700          */
1701         if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1702                 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
1703
1704                 if (adev->gmc.is_app_apu) {
1705                         domain = AMDGPU_GEM_DOMAIN_GTT;
1706                         alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1707                         alloc_flags = 0;
1708                 } else {
1709                         alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
1710                         alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ?
1711                         AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0;
1712                 }
1713                 xcp_id = fpriv->xcp_id == AMDGPU_XCP_NO_PARTITION ?
1714                                         0 : fpriv->xcp_id;
1715         } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
1716                 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
1717                 alloc_flags = 0;
1718         } else {
1719                 domain = AMDGPU_GEM_DOMAIN_GTT;
1720                 alloc_domain = AMDGPU_GEM_DOMAIN_CPU;
1721                 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE;
1722
1723                 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1724                         if (!offset || !*offset)
1725                                 return -EINVAL;
1726                         user_addr = untagged_addr(*offset);
1727                 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1728                                     KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1729                         bo_type = ttm_bo_type_sg;
1730                         if (size > UINT_MAX)
1731                                 return -EINVAL;
1732                         sg = create_sg_table(*offset, size);
1733                         if (!sg)
1734                                 return -ENOMEM;
1735                 } else {
1736                         return -EINVAL;
1737                 }
1738         }
1739
1740         if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT)
1741                 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT;
1742         if (flags & KFD_IOC_ALLOC_MEM_FLAGS_EXT_COHERENT)
1743                 alloc_flags |= AMDGPU_GEM_CREATE_EXT_COHERENT;
1744         if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED)
1745                 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED;
1746
1747         *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
1748         if (!*mem) {
1749                 ret = -ENOMEM;
1750                 goto err;
1751         }
1752         INIT_LIST_HEAD(&(*mem)->attachments);
1753         mutex_init(&(*mem)->lock);
1754         (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM);
1755
1756         /* Workaround for AQL queue wraparound bug. Map the same
1757          * memory twice. That means we only actually allocate half
1758          * the memory.
1759          */
1760         if ((*mem)->aql_queue)
1761                 size >>= 1;
1762         aligned_size = PAGE_ALIGN(size);
1763
1764         (*mem)->alloc_flags = flags;
1765
1766         amdgpu_sync_create(&(*mem)->sync);
1767
1768         ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags,
1769                                               xcp_id);
1770         if (ret) {
1771                 pr_debug("Insufficient memory\n");
1772                 goto err_reserve_limit;
1773         }
1774
1775         pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s xcp_id %d\n",
1776                  va, (*mem)->aql_queue ? size << 1 : size,
1777                  domain_string(alloc_domain), xcp_id);
1778
1779         ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags,
1780                                        bo_type, NULL, &gobj, xcp_id + 1);
1781         if (ret) {
1782                 pr_debug("Failed to create BO on domain %s. ret %d\n",
1783                          domain_string(alloc_domain), ret);
1784                 goto err_bo_create;
1785         }
1786         ret = drm_vma_node_allow(&gobj->vma_node, drm_priv);
1787         if (ret) {
1788                 pr_debug("Failed to allow vma node access. ret %d\n", ret);
1789                 goto err_node_allow;
1790         }
1791         ret = drm_gem_handle_create(adev->kfd.client.file, gobj, &(*mem)->gem_handle);
1792         if (ret)
1793                 goto err_gem_handle_create;
1794         bo = gem_to_amdgpu_bo(gobj);
1795         if (bo_type == ttm_bo_type_sg) {
1796                 bo->tbo.sg = sg;
1797                 bo->tbo.ttm->sg = sg;
1798         }
1799         bo->kfd_bo = *mem;
1800         (*mem)->bo = bo;
1801         if (user_addr)
1802                 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO;
1803
1804         (*mem)->va = va;
1805         (*mem)->domain = domain;
1806         (*mem)->mapped_to_gpu_memory = 0;
1807         (*mem)->process_info = avm->process_info;
1808
1809         add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
1810
1811         if (user_addr) {
1812                 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
1813                 ret = init_user_pages(*mem, user_addr, criu_resume);
1814                 if (ret)
1815                         goto allocate_init_user_pages_failed;
1816         } else  if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1817                                 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1818                 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT);
1819                 if (ret) {
1820                         pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n");
1821                         goto err_pin_bo;
1822                 }
1823                 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
1824                 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
1825         } else {
1826                 mutex_lock(&avm->process_info->lock);
1827                 if (avm->process_info->eviction_fence &&
1828                     !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
1829                         ret = amdgpu_amdkfd_bo_validate_and_fence(bo, domain,
1830                                 &avm->process_info->eviction_fence->base);
1831                 mutex_unlock(&avm->process_info->lock);
1832                 if (ret)
1833                         goto err_validate_bo;
1834         }
1835
1836         if (offset)
1837                 *offset = amdgpu_bo_mmap_offset(bo);
1838
1839         return 0;
1840
1841 allocate_init_user_pages_failed:
1842 err_pin_bo:
1843 err_validate_bo:
1844         remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
1845         drm_gem_handle_delete(adev->kfd.client.file, (*mem)->gem_handle);
1846 err_gem_handle_create:
1847         drm_vma_node_revoke(&gobj->vma_node, drm_priv);
1848 err_node_allow:
1849         /* Don't unreserve system mem limit twice */
1850         goto err_reserve_limit;
1851 err_bo_create:
1852         amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags, xcp_id);
1853 err_reserve_limit:
1854         mutex_destroy(&(*mem)->lock);
1855         if (gobj)
1856                 drm_gem_object_put(gobj);
1857         else
1858                 kfree(*mem);
1859 err:
1860         if (sg) {
1861                 sg_free_table(sg);
1862                 kfree(sg);
1863         }
1864         return ret;
1865 }
1866
1867 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
1868                 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
1869                 uint64_t *size)
1870 {
1871         struct amdkfd_process_info *process_info = mem->process_info;
1872         unsigned long bo_size = mem->bo->tbo.base.size;
1873         bool use_release_notifier = (mem->bo->kfd_bo == mem);
1874         struct kfd_mem_attachment *entry, *tmp;
1875         struct bo_vm_reservation_context ctx;
1876         unsigned int mapped_to_gpu_memory;
1877         int ret;
1878         bool is_imported = false;
1879
1880         mutex_lock(&mem->lock);
1881
1882         /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */
1883         if (mem->alloc_flags &
1884             (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL |
1885              KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) {
1886                 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo);
1887         }
1888
1889         mapped_to_gpu_memory = mem->mapped_to_gpu_memory;
1890         is_imported = mem->is_imported;
1891         mutex_unlock(&mem->lock);
1892         /* lock is not needed after this, since mem is unused and will
1893          * be freed anyway
1894          */
1895
1896         if (mapped_to_gpu_memory > 0) {
1897                 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",
1898                                 mem->va, bo_size);
1899                 return -EBUSY;
1900         }
1901
1902         /* Make sure restore workers don't access the BO any more */
1903         mutex_lock(&process_info->lock);
1904         list_del(&mem->validate_list);
1905         mutex_unlock(&process_info->lock);
1906
1907         /* Cleanup user pages and MMU notifiers */
1908         if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) {
1909                 amdgpu_hmm_unregister(mem->bo);
1910                 mutex_lock(&process_info->notifier_lock);
1911                 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range);
1912                 mutex_unlock(&process_info->notifier_lock);
1913         }
1914
1915         ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx);
1916         if (unlikely(ret))
1917                 return ret;
1918
1919         amdgpu_amdkfd_remove_eviction_fence(mem->bo,
1920                                         process_info->eviction_fence);
1921         pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va,
1922                 mem->va + bo_size * (1 + mem->aql_queue));
1923
1924         /* Remove from VM internal data structures */
1925         list_for_each_entry_safe(entry, tmp, &mem->attachments, list) {
1926                 kfd_mem_dmaunmap_attachment(mem, entry);
1927                 kfd_mem_detach(entry);
1928         }
1929
1930         ret = unreserve_bo_and_vms(&ctx, false, false);
1931
1932         /* Free the sync object */
1933         amdgpu_sync_free(&mem->sync);
1934
1935         /* If the SG is not NULL, it's one we created for a doorbell or mmio
1936          * remap BO. We need to free it.
1937          */
1938         if (mem->bo->tbo.sg) {
1939                 sg_free_table(mem->bo->tbo.sg);
1940                 kfree(mem->bo->tbo.sg);
1941         }
1942
1943         /* Update the size of the BO being freed if it was allocated from
1944          * VRAM and is not imported. For APP APU VRAM allocations are done
1945          * in GTT domain
1946          */
1947         if (size) {
1948                 if (!is_imported &&
1949                    (mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
1950                    (adev->gmc.is_app_apu &&
1951                     mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
1952                         *size = bo_size;
1953                 else
1954                         *size = 0;
1955         }
1956
1957         /* Free the BO*/
1958         drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv);
1959         drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle);
1960         if (mem->dmabuf) {
1961                 dma_buf_put(mem->dmabuf);
1962                 mem->dmabuf = NULL;
1963         }
1964         mutex_destroy(&mem->lock);
1965
1966         /* If this releases the last reference, it will end up calling
1967          * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why
1968          * this needs to be the last call here.
1969          */
1970         drm_gem_object_put(&mem->bo->tbo.base);
1971
1972         /*
1973          * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(),
1974          * explicitly free it here.
1975          */
1976         if (!use_release_notifier)
1977                 kfree(mem);
1978
1979         return ret;
1980 }
1981
1982 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1983                 struct amdgpu_device *adev, struct kgd_mem *mem,
1984                 void *drm_priv)
1985 {
1986         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
1987         int ret;
1988         struct amdgpu_bo *bo;
1989         uint32_t domain;
1990         struct kfd_mem_attachment *entry;
1991         struct bo_vm_reservation_context ctx;
1992         unsigned long bo_size;
1993         bool is_invalid_userptr = false;
1994
1995         bo = mem->bo;
1996         if (!bo) {
1997                 pr_err("Invalid BO when mapping memory to GPU\n");
1998                 return -EINVAL;
1999         }
2000
2001         /* Make sure restore is not running concurrently. Since we
2002          * don't map invalid userptr BOs, we rely on the next restore
2003          * worker to do the mapping
2004          */
2005         mutex_lock(&mem->process_info->lock);
2006
2007         /* Lock notifier lock. If we find an invalid userptr BO, we can be
2008          * sure that the MMU notifier is no longer running
2009          * concurrently and the queues are actually stopped
2010          */
2011         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2012                 mutex_lock(&mem->process_info->notifier_lock);
2013                 is_invalid_userptr = !!mem->invalid;
2014                 mutex_unlock(&mem->process_info->notifier_lock);
2015         }
2016
2017         mutex_lock(&mem->lock);
2018
2019         domain = mem->domain;
2020         bo_size = bo->tbo.base.size;
2021
2022         pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n",
2023                         mem->va,
2024                         mem->va + bo_size * (1 + mem->aql_queue),
2025                         avm, domain_string(domain));
2026
2027         if (!kfd_mem_is_attached(avm, mem)) {
2028                 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue);
2029                 if (ret)
2030                         goto out;
2031         }
2032
2033         ret = reserve_bo_and_vm(mem, avm, &ctx);
2034         if (unlikely(ret))
2035                 goto out;
2036
2037         /* Userptr can be marked as "not invalid", but not actually be
2038          * validated yet (still in the system domain). In that case
2039          * the queues are still stopped and we can leave mapping for
2040          * the next restore worker
2041          */
2042         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) &&
2043             bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
2044                 is_invalid_userptr = true;
2045
2046         ret = vm_validate_pt_pd_bos(avm);
2047         if (unlikely(ret))
2048                 goto out_unreserve;
2049
2050         list_for_each_entry(entry, &mem->attachments, list) {
2051                 if (entry->bo_va->base.vm != avm || entry->is_mapped)
2052                         continue;
2053
2054                 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n",
2055                          entry->va, entry->va + bo_size, entry);
2056
2057                 ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
2058                                       is_invalid_userptr);
2059                 if (ret) {
2060                         pr_err("Failed to map bo to gpuvm\n");
2061                         goto out_unreserve;
2062                 }
2063
2064                 ret = vm_update_pds(avm, ctx.sync);
2065                 if (ret) {
2066                         pr_err("Failed to update page directories\n");
2067                         goto out_unreserve;
2068                 }
2069
2070                 entry->is_mapped = true;
2071                 mem->mapped_to_gpu_memory++;
2072                 pr_debug("\t INC mapping count %d\n",
2073                          mem->mapped_to_gpu_memory);
2074         }
2075
2076         ret = unreserve_bo_and_vms(&ctx, false, false);
2077
2078         goto out;
2079
2080 out_unreserve:
2081         unreserve_bo_and_vms(&ctx, false, false);
2082 out:
2083         mutex_unlock(&mem->process_info->lock);
2084         mutex_unlock(&mem->lock);
2085         return ret;
2086 }
2087
2088 void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv)
2089 {
2090         struct kfd_mem_attachment *entry;
2091         struct amdgpu_vm *vm;
2092
2093         vm = drm_priv_to_vm(drm_priv);
2094
2095         mutex_lock(&mem->lock);
2096
2097         list_for_each_entry(entry, &mem->attachments, list) {
2098                 if (entry->bo_va->base.vm == vm)
2099                         kfd_mem_dmaunmap_attachment(mem, entry);
2100         }
2101
2102         mutex_unlock(&mem->lock);
2103 }
2104
2105 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
2106                 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv)
2107 {
2108         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2109         unsigned long bo_size = mem->bo->tbo.base.size;
2110         struct kfd_mem_attachment *entry;
2111         struct bo_vm_reservation_context ctx;
2112         int ret;
2113
2114         mutex_lock(&mem->lock);
2115
2116         ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx);
2117         if (unlikely(ret))
2118                 goto out;
2119         /* If no VMs were reserved, it means the BO wasn't actually mapped */
2120         if (ctx.n_vms == 0) {
2121                 ret = -EINVAL;
2122                 goto unreserve_out;
2123         }
2124
2125         ret = vm_validate_pt_pd_bos(avm);
2126         if (unlikely(ret))
2127                 goto unreserve_out;
2128
2129         pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n",
2130                 mem->va,
2131                 mem->va + bo_size * (1 + mem->aql_queue),
2132                 avm);
2133
2134         list_for_each_entry(entry, &mem->attachments, list) {
2135                 if (entry->bo_va->base.vm != avm || !entry->is_mapped)
2136                         continue;
2137
2138                 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n",
2139                          entry->va, entry->va + bo_size, entry);
2140
2141                 unmap_bo_from_gpuvm(mem, entry, ctx.sync);
2142                 entry->is_mapped = false;
2143
2144                 mem->mapped_to_gpu_memory--;
2145                 pr_debug("\t DEC mapping count %d\n",
2146                          mem->mapped_to_gpu_memory);
2147         }
2148
2149 unreserve_out:
2150         unreserve_bo_and_vms(&ctx, false, false);
2151 out:
2152         mutex_unlock(&mem->lock);
2153         return ret;
2154 }
2155
2156 int amdgpu_amdkfd_gpuvm_sync_memory(
2157                 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr)
2158 {
2159         struct amdgpu_sync sync;
2160         int ret;
2161
2162         amdgpu_sync_create(&sync);
2163
2164         mutex_lock(&mem->lock);
2165         amdgpu_sync_clone(&mem->sync, &sync);
2166         mutex_unlock(&mem->lock);
2167
2168         ret = amdgpu_sync_wait(&sync, intr);
2169         amdgpu_sync_free(&sync);
2170         return ret;
2171 }
2172
2173 /**
2174  * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count
2175  * @adev: Device to which allocated BO belongs
2176  * @bo: Buffer object to be mapped
2177  *
2178  * Before return, bo reference count is incremented. To release the reference and unpin/
2179  * unmap the BO, call amdgpu_amdkfd_free_gtt_mem.
2180  */
2181 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo)
2182 {
2183         int ret;
2184
2185         ret = amdgpu_bo_reserve(bo, true);
2186         if (ret) {
2187                 pr_err("Failed to reserve bo. ret %d\n", ret);
2188                 goto err_reserve_bo_failed;
2189         }
2190
2191         ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2192         if (ret) {
2193                 pr_err("Failed to pin bo. ret %d\n", ret);
2194                 goto err_pin_bo_failed;
2195         }
2196
2197         ret = amdgpu_ttm_alloc_gart(&bo->tbo);
2198         if (ret) {
2199                 pr_err("Failed to bind bo to GART. ret %d\n", ret);
2200                 goto err_map_bo_gart_failed;
2201         }
2202
2203         amdgpu_amdkfd_remove_eviction_fence(
2204                 bo, bo->vm_bo->vm->process_info->eviction_fence);
2205
2206         amdgpu_bo_unreserve(bo);
2207
2208         bo = amdgpu_bo_ref(bo);
2209
2210         return 0;
2211
2212 err_map_bo_gart_failed:
2213         amdgpu_bo_unpin(bo);
2214 err_pin_bo_failed:
2215         amdgpu_bo_unreserve(bo);
2216 err_reserve_bo_failed:
2217
2218         return ret;
2219 }
2220
2221 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access
2222  *
2223  * @mem: Buffer object to be mapped for CPU access
2224  * @kptr[out]: pointer in kernel CPU address space
2225  * @size[out]: size of the buffer
2226  *
2227  * Pins the BO and maps it for kernel CPU access. The eviction fence is removed
2228  * from the BO, since pinned BOs cannot be evicted. The bo must remain on the
2229  * validate_list, so the GPU mapping can be restored after a page table was
2230  * evicted.
2231  *
2232  * Return: 0 on success, error code on failure
2233  */
2234 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
2235                                              void **kptr, uint64_t *size)
2236 {
2237         int ret;
2238         struct amdgpu_bo *bo = mem->bo;
2239
2240         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
2241                 pr_err("userptr can't be mapped to kernel\n");
2242                 return -EINVAL;
2243         }
2244
2245         mutex_lock(&mem->process_info->lock);
2246
2247         ret = amdgpu_bo_reserve(bo, true);
2248         if (ret) {
2249                 pr_err("Failed to reserve bo. ret %d\n", ret);
2250                 goto bo_reserve_failed;
2251         }
2252
2253         ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
2254         if (ret) {
2255                 pr_err("Failed to pin bo. ret %d\n", ret);
2256                 goto pin_failed;
2257         }
2258
2259         ret = amdgpu_bo_kmap(bo, kptr);
2260         if (ret) {
2261                 pr_err("Failed to map bo to kernel. ret %d\n", ret);
2262                 goto kmap_failed;
2263         }
2264
2265         amdgpu_amdkfd_remove_eviction_fence(
2266                 bo, mem->process_info->eviction_fence);
2267
2268         if (size)
2269                 *size = amdgpu_bo_size(bo);
2270
2271         amdgpu_bo_unreserve(bo);
2272
2273         mutex_unlock(&mem->process_info->lock);
2274         return 0;
2275
2276 kmap_failed:
2277         amdgpu_bo_unpin(bo);
2278 pin_failed:
2279         amdgpu_bo_unreserve(bo);
2280 bo_reserve_failed:
2281         mutex_unlock(&mem->process_info->lock);
2282
2283         return ret;
2284 }
2285
2286 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access
2287  *
2288  * @mem: Buffer object to be unmapped for CPU access
2289  *
2290  * Removes the kernel CPU mapping and unpins the BO. It does not restore the
2291  * eviction fence, so this function should only be used for cleanup before the
2292  * BO is destroyed.
2293  */
2294 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem)
2295 {
2296         struct amdgpu_bo *bo = mem->bo;
2297
2298         amdgpu_bo_reserve(bo, true);
2299         amdgpu_bo_kunmap(bo);
2300         amdgpu_bo_unpin(bo);
2301         amdgpu_bo_unreserve(bo);
2302 }
2303
2304 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
2305                                           struct kfd_vm_fault_info *mem)
2306 {
2307         if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) {
2308                 *mem = *adev->gmc.vm_fault_info;
2309                 mb(); /* make sure read happened */
2310                 atomic_set(&adev->gmc.vm_fault_info_updated, 0);
2311         }
2312         return 0;
2313 }
2314
2315 static int import_obj_create(struct amdgpu_device *adev,
2316                              struct dma_buf *dma_buf,
2317                              struct drm_gem_object *obj,
2318                              uint64_t va, void *drm_priv,
2319                              struct kgd_mem **mem, uint64_t *size,
2320                              uint64_t *mmap_offset)
2321 {
2322         struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
2323         struct amdgpu_bo *bo;
2324         int ret;
2325
2326         bo = gem_to_amdgpu_bo(obj);
2327         if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
2328                                     AMDGPU_GEM_DOMAIN_GTT)))
2329                 /* Only VRAM and GTT BOs are supported */
2330                 return -EINVAL;
2331
2332         *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
2333         if (!*mem)
2334                 return -ENOMEM;
2335
2336         ret = drm_vma_node_allow(&obj->vma_node, drm_priv);
2337         if (ret)
2338                 goto err_free_mem;
2339
2340         if (size)
2341                 *size = amdgpu_bo_size(bo);
2342
2343         if (mmap_offset)
2344                 *mmap_offset = amdgpu_bo_mmap_offset(bo);
2345
2346         INIT_LIST_HEAD(&(*mem)->attachments);
2347         mutex_init(&(*mem)->lock);
2348
2349         (*mem)->alloc_flags =
2350                 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
2351                 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT)
2352                 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE
2353                 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE;
2354
2355         get_dma_buf(dma_buf);
2356         (*mem)->dmabuf = dma_buf;
2357         (*mem)->bo = bo;
2358         (*mem)->va = va;
2359         (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
2360                 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
2361
2362         (*mem)->mapped_to_gpu_memory = 0;
2363         (*mem)->process_info = avm->process_info;
2364         add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false);
2365         amdgpu_sync_create(&(*mem)->sync);
2366         (*mem)->is_imported = true;
2367
2368         mutex_lock(&avm->process_info->lock);
2369         if (avm->process_info->eviction_fence &&
2370             !dma_fence_is_signaled(&avm->process_info->eviction_fence->base))
2371                 ret = amdgpu_amdkfd_bo_validate_and_fence(bo, (*mem)->domain,
2372                                 &avm->process_info->eviction_fence->base);
2373         mutex_unlock(&avm->process_info->lock);
2374         if (ret)
2375                 goto err_remove_mem;
2376
2377         return 0;
2378
2379 err_remove_mem:
2380         remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info);
2381         drm_vma_node_revoke(&obj->vma_node, drm_priv);
2382 err_free_mem:
2383         kfree(*mem);
2384         return ret;
2385 }
2386
2387 int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
2388                                          uint64_t va, void *drm_priv,
2389                                          struct kgd_mem **mem, uint64_t *size,
2390                                          uint64_t *mmap_offset)
2391 {
2392         struct drm_gem_object *obj;
2393         uint32_t handle;
2394         int ret;
2395
2396         ret = drm_gem_prime_fd_to_handle(&adev->ddev, adev->kfd.client.file, fd,
2397                                          &handle);
2398         if (ret)
2399                 return ret;
2400         obj = drm_gem_object_lookup(adev->kfd.client.file, handle);
2401         if (!obj) {
2402                 ret = -EINVAL;
2403                 goto err_release_handle;
2404         }
2405
2406         ret = import_obj_create(adev, obj->dma_buf, obj, va, drm_priv, mem, size,
2407                                 mmap_offset);
2408         if (ret)
2409                 goto err_put_obj;
2410
2411         (*mem)->gem_handle = handle;
2412
2413         return 0;
2414
2415 err_put_obj:
2416         drm_gem_object_put(obj);
2417 err_release_handle:
2418         drm_gem_handle_delete(adev->kfd.client.file, handle);
2419         return ret;
2420 }
2421
2422 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
2423                                       struct dma_buf **dma_buf)
2424 {
2425         int ret;
2426
2427         mutex_lock(&mem->lock);
2428         ret = kfd_mem_export_dmabuf(mem);
2429         if (ret)
2430                 goto out;
2431
2432         get_dma_buf(mem->dmabuf);
2433         *dma_buf = mem->dmabuf;
2434 out:
2435         mutex_unlock(&mem->lock);
2436         return ret;
2437 }
2438
2439 /* Evict a userptr BO by stopping the queues if necessary
2440  *
2441  * Runs in MMU notifier, may be in RECLAIM_FS context. This means it
2442  * cannot do any memory allocations, and cannot take any locks that
2443  * are held elsewhere while allocating memory.
2444  *
2445  * It doesn't do anything to the BO itself. The real work happens in
2446  * restore, where we get updated page addresses. This function only
2447  * ensures that GPU access to the BO is stopped.
2448  */
2449 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
2450                                 unsigned long cur_seq, struct kgd_mem *mem)
2451 {
2452         struct amdkfd_process_info *process_info = mem->process_info;
2453         int r = 0;
2454
2455         /* Do not process MMU notifications during CRIU restore until
2456          * KFD_CRIU_OP_RESUME IOCTL is received
2457          */
2458         if (READ_ONCE(process_info->block_mmu_notifications))
2459                 return 0;
2460
2461         mutex_lock(&process_info->notifier_lock);
2462         mmu_interval_set_seq(mni, cur_seq);
2463
2464         mem->invalid++;
2465         if (++process_info->evicted_bos == 1) {
2466                 /* First eviction, stop the queues */
2467                 r = kgd2kfd_quiesce_mm(mni->mm,
2468                                        KFD_QUEUE_EVICTION_TRIGGER_USERPTR);
2469                 if (r)
2470                         pr_err("Failed to quiesce KFD\n");
2471                 queue_delayed_work(system_freezable_wq,
2472                         &process_info->restore_userptr_work,
2473                         msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2474         }
2475         mutex_unlock(&process_info->notifier_lock);
2476
2477         return r;
2478 }
2479
2480 /* Update invalid userptr BOs
2481  *
2482  * Moves invalidated (evicted) userptr BOs from userptr_valid_list to
2483  * userptr_inval_list and updates user pages for all BOs that have
2484  * been invalidated since their last update.
2485  */
2486 static int update_invalid_user_pages(struct amdkfd_process_info *process_info,
2487                                      struct mm_struct *mm)
2488 {
2489         struct kgd_mem *mem, *tmp_mem;
2490         struct amdgpu_bo *bo;
2491         struct ttm_operation_ctx ctx = { false, false };
2492         uint32_t invalid;
2493         int ret = 0;
2494
2495         mutex_lock(&process_info->notifier_lock);
2496
2497         /* Move all invalidated BOs to the userptr_inval_list */
2498         list_for_each_entry_safe(mem, tmp_mem,
2499                                  &process_info->userptr_valid_list,
2500                                  validate_list)
2501                 if (mem->invalid)
2502                         list_move_tail(&mem->validate_list,
2503                                        &process_info->userptr_inval_list);
2504
2505         /* Go through userptr_inval_list and update any invalid user_pages */
2506         list_for_each_entry(mem, &process_info->userptr_inval_list,
2507                             validate_list) {
2508                 invalid = mem->invalid;
2509                 if (!invalid)
2510                         /* BO hasn't been invalidated since the last
2511                          * revalidation attempt. Keep its page list.
2512                          */
2513                         continue;
2514
2515                 bo = mem->bo;
2516
2517                 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range);
2518                 mem->range = NULL;
2519
2520                 /* BO reservations and getting user pages (hmm_range_fault)
2521                  * must happen outside the notifier lock
2522                  */
2523                 mutex_unlock(&process_info->notifier_lock);
2524
2525                 /* Move the BO to system (CPU) domain if necessary to unmap
2526                  * and free the SG table
2527                  */
2528                 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) {
2529                         if (amdgpu_bo_reserve(bo, true))
2530                                 return -EAGAIN;
2531                         amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
2532                         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2533                         amdgpu_bo_unreserve(bo);
2534                         if (ret) {
2535                                 pr_err("%s: Failed to invalidate userptr BO\n",
2536                                        __func__);
2537                                 return -EAGAIN;
2538                         }
2539                 }
2540
2541                 /* Get updated user pages */
2542                 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages,
2543                                                    &mem->range);
2544                 if (ret) {
2545                         pr_debug("Failed %d to get user pages\n", ret);
2546
2547                         /* Return -EFAULT bad address error as success. It will
2548                          * fail later with a VM fault if the GPU tries to access
2549                          * it. Better than hanging indefinitely with stalled
2550                          * user mode queues.
2551                          *
2552                          * Return other error -EBUSY or -ENOMEM to retry restore
2553                          */
2554                         if (ret != -EFAULT)
2555                                 return ret;
2556
2557                         ret = 0;
2558                 }
2559
2560                 mutex_lock(&process_info->notifier_lock);
2561
2562                 /* Mark the BO as valid unless it was invalidated
2563                  * again concurrently.
2564                  */
2565                 if (mem->invalid != invalid) {
2566                         ret = -EAGAIN;
2567                         goto unlock_out;
2568                 }
2569                  /* set mem valid if mem has hmm range associated */
2570                 if (mem->range)
2571                         mem->invalid = 0;
2572         }
2573
2574 unlock_out:
2575         mutex_unlock(&process_info->notifier_lock);
2576
2577         return ret;
2578 }
2579
2580 /* Validate invalid userptr BOs
2581  *
2582  * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables
2583  * with new page addresses and waits for the page table updates to complete.
2584  */
2585 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
2586 {
2587         struct ttm_operation_ctx ctx = { false, false };
2588         struct amdgpu_sync sync;
2589         struct drm_exec exec;
2590
2591         struct amdgpu_vm *peer_vm;
2592         struct kgd_mem *mem, *tmp_mem;
2593         struct amdgpu_bo *bo;
2594         int ret;
2595
2596         amdgpu_sync_create(&sync);
2597
2598         drm_exec_init(&exec, 0, 0);
2599         /* Reserve all BOs and page tables for validation */
2600         drm_exec_until_all_locked(&exec) {
2601                 /* Reserve all the page directories */
2602                 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2603                                     vm_list_node) {
2604                         ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2605                         drm_exec_retry_on_contention(&exec);
2606                         if (unlikely(ret))
2607                                 goto unreserve_out;
2608                 }
2609
2610                 /* Reserve the userptr_inval_list entries to resv_list */
2611                 list_for_each_entry(mem, &process_info->userptr_inval_list,
2612                                     validate_list) {
2613                         struct drm_gem_object *gobj;
2614
2615                         gobj = &mem->bo->tbo.base;
2616                         ret = drm_exec_prepare_obj(&exec, gobj, 1);
2617                         drm_exec_retry_on_contention(&exec);
2618                         if (unlikely(ret))
2619                                 goto unreserve_out;
2620                 }
2621         }
2622
2623         ret = process_validate_vms(process_info);
2624         if (ret)
2625                 goto unreserve_out;
2626
2627         /* Validate BOs and update GPUVM page tables */
2628         list_for_each_entry_safe(mem, tmp_mem,
2629                                  &process_info->userptr_inval_list,
2630                                  validate_list) {
2631                 struct kfd_mem_attachment *attachment;
2632
2633                 bo = mem->bo;
2634
2635                 /* Validate the BO if we got user pages */
2636                 if (bo->tbo.ttm->pages[0]) {
2637                         amdgpu_bo_placement_from_domain(bo, mem->domain);
2638                         ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
2639                         if (ret) {
2640                                 pr_err("%s: failed to validate BO\n", __func__);
2641                                 goto unreserve_out;
2642                         }
2643                 }
2644
2645                 /* Update mapping. If the BO was not validated
2646                  * (because we couldn't get user pages), this will
2647                  * clear the page table entries, which will result in
2648                  * VM faults if the GPU tries to access the invalid
2649                  * memory.
2650                  */
2651                 list_for_each_entry(attachment, &mem->attachments, list) {
2652                         if (!attachment->is_mapped)
2653                                 continue;
2654
2655                         kfd_mem_dmaunmap_attachment(mem, attachment);
2656                         ret = update_gpuvm_pte(mem, attachment, &sync);
2657                         if (ret) {
2658                                 pr_err("%s: update PTE failed\n", __func__);
2659                                 /* make sure this gets validated again */
2660                                 mutex_lock(&process_info->notifier_lock);
2661                                 mem->invalid++;
2662                                 mutex_unlock(&process_info->notifier_lock);
2663                                 goto unreserve_out;
2664                         }
2665                 }
2666         }
2667
2668         /* Update page directories */
2669         ret = process_update_pds(process_info, &sync);
2670
2671 unreserve_out:
2672         drm_exec_fini(&exec);
2673         amdgpu_sync_wait(&sync, false);
2674         amdgpu_sync_free(&sync);
2675
2676         return ret;
2677 }
2678
2679 /* Confirm that all user pages are valid while holding the notifier lock
2680  *
2681  * Moves valid BOs from the userptr_inval_list back to userptr_val_list.
2682  */
2683 static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info)
2684 {
2685         struct kgd_mem *mem, *tmp_mem;
2686         int ret = 0;
2687
2688         list_for_each_entry_safe(mem, tmp_mem,
2689                                  &process_info->userptr_inval_list,
2690                                  validate_list) {
2691                 bool valid;
2692
2693                 /* keep mem without hmm range at userptr_inval_list */
2694                 if (!mem->range)
2695                          continue;
2696
2697                 /* Only check mem with hmm range associated */
2698                 valid = amdgpu_ttm_tt_get_user_pages_done(
2699                                         mem->bo->tbo.ttm, mem->range);
2700
2701                 mem->range = NULL;
2702                 if (!valid) {
2703                         WARN(!mem->invalid, "Invalid BO not marked invalid");
2704                         ret = -EAGAIN;
2705                         continue;
2706                 }
2707
2708                 if (mem->invalid) {
2709                         WARN(1, "Valid BO is marked invalid");
2710                         ret = -EAGAIN;
2711                         continue;
2712                 }
2713
2714                 list_move_tail(&mem->validate_list,
2715                                &process_info->userptr_valid_list);
2716         }
2717
2718         return ret;
2719 }
2720
2721 /* Worker callback to restore evicted userptr BOs
2722  *
2723  * Tries to update and validate all userptr BOs. If successful and no
2724  * concurrent evictions happened, the queues are restarted. Otherwise,
2725  * reschedule for another attempt later.
2726  */
2727 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work)
2728 {
2729         struct delayed_work *dwork = to_delayed_work(work);
2730         struct amdkfd_process_info *process_info =
2731                 container_of(dwork, struct amdkfd_process_info,
2732                              restore_userptr_work);
2733         struct task_struct *usertask;
2734         struct mm_struct *mm;
2735         uint32_t evicted_bos;
2736
2737         mutex_lock(&process_info->notifier_lock);
2738         evicted_bos = process_info->evicted_bos;
2739         mutex_unlock(&process_info->notifier_lock);
2740         if (!evicted_bos)
2741                 return;
2742
2743         /* Reference task and mm in case of concurrent process termination */
2744         usertask = get_pid_task(process_info->pid, PIDTYPE_PID);
2745         if (!usertask)
2746                 return;
2747         mm = get_task_mm(usertask);
2748         if (!mm) {
2749                 put_task_struct(usertask);
2750                 return;
2751         }
2752
2753         mutex_lock(&process_info->lock);
2754
2755         if (update_invalid_user_pages(process_info, mm))
2756                 goto unlock_out;
2757         /* userptr_inval_list can be empty if all evicted userptr BOs
2758          * have been freed. In that case there is nothing to validate
2759          * and we can just restart the queues.
2760          */
2761         if (!list_empty(&process_info->userptr_inval_list)) {
2762                 if (validate_invalid_user_pages(process_info))
2763                         goto unlock_out;
2764         }
2765         /* Final check for concurrent evicton and atomic update. If
2766          * another eviction happens after successful update, it will
2767          * be a first eviction that calls quiesce_mm. The eviction
2768          * reference counting inside KFD will handle this case.
2769          */
2770         mutex_lock(&process_info->notifier_lock);
2771         if (process_info->evicted_bos != evicted_bos)
2772                 goto unlock_notifier_out;
2773
2774         if (confirm_valid_user_pages_locked(process_info)) {
2775                 WARN(1, "User pages unexpectedly invalid");
2776                 goto unlock_notifier_out;
2777         }
2778
2779         process_info->evicted_bos = evicted_bos = 0;
2780
2781         if (kgd2kfd_resume_mm(mm)) {
2782                 pr_err("%s: Failed to resume KFD\n", __func__);
2783                 /* No recovery from this failure. Probably the CP is
2784                  * hanging. No point trying again.
2785                  */
2786         }
2787
2788 unlock_notifier_out:
2789         mutex_unlock(&process_info->notifier_lock);
2790 unlock_out:
2791         mutex_unlock(&process_info->lock);
2792
2793         /* If validation failed, reschedule another attempt */
2794         if (evicted_bos) {
2795                 queue_delayed_work(system_freezable_wq,
2796                         &process_info->restore_userptr_work,
2797                         msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS));
2798
2799                 kfd_smi_event_queue_restore_rescheduled(mm);
2800         }
2801         mmput(mm);
2802         put_task_struct(usertask);
2803 }
2804
2805 static void replace_eviction_fence(struct dma_fence **ef,
2806                                    struct dma_fence *new_ef)
2807 {
2808         struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true
2809                 /* protected by process_info->lock */);
2810
2811         /* If we're replacing an unsignaled eviction fence, that fence will
2812          * never be signaled, and if anyone is still waiting on that fence,
2813          * they will hang forever. This should never happen. We should only
2814          * replace the fence in restore_work that only gets scheduled after
2815          * eviction work signaled the fence.
2816          */
2817         WARN_ONCE(!dma_fence_is_signaled(old_ef),
2818                   "Replacing unsignaled eviction fence");
2819         dma_fence_put(old_ef);
2820 }
2821
2822 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given
2823  *   KFD process identified by process_info
2824  *
2825  * @process_info: amdkfd_process_info of the KFD process
2826  *
2827  * After memory eviction, restore thread calls this function. The function
2828  * should be called when the Process is still valid. BO restore involves -
2829  *
2830  * 1.  Release old eviction fence and create new one
2831  * 2.  Get two copies of PD BO list from all the VMs. Keep one copy as pd_list.
2832  * 3   Use the second PD list and kfd_bo_list to create a list (ctx.list) of
2833  *     BOs that need to be reserved.
2834  * 4.  Reserve all the BOs
2835  * 5.  Validate of PD and PT BOs.
2836  * 6.  Validate all KFD BOs using kfd_bo_list and Map them and add new fence
2837  * 7.  Add fence to all PD and PT BOs.
2838  * 8.  Unreserve all BOs
2839  */
2840 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
2841 {
2842         struct amdkfd_process_info *process_info = info;
2843         struct amdgpu_vm *peer_vm;
2844         struct kgd_mem *mem;
2845         struct list_head duplicate_save;
2846         struct amdgpu_sync sync_obj;
2847         unsigned long failed_size = 0;
2848         unsigned long total_size = 0;
2849         struct drm_exec exec;
2850         int ret;
2851
2852         INIT_LIST_HEAD(&duplicate_save);
2853
2854         mutex_lock(&process_info->lock);
2855
2856         drm_exec_init(&exec, 0, 0);
2857         drm_exec_until_all_locked(&exec) {
2858                 list_for_each_entry(peer_vm, &process_info->vm_list_head,
2859                                     vm_list_node) {
2860                         ret = amdgpu_vm_lock_pd(peer_vm, &exec, 2);
2861                         drm_exec_retry_on_contention(&exec);
2862                         if (unlikely(ret))
2863                                 goto ttm_reserve_fail;
2864                 }
2865
2866                 /* Reserve all BOs and page tables/directory. Add all BOs from
2867                  * kfd_bo_list to ctx.list
2868                  */
2869                 list_for_each_entry(mem, &process_info->kfd_bo_list,
2870                                     validate_list) {
2871                         struct drm_gem_object *gobj;
2872
2873                         gobj = &mem->bo->tbo.base;
2874                         ret = drm_exec_prepare_obj(&exec, gobj, 1);
2875                         drm_exec_retry_on_contention(&exec);
2876                         if (unlikely(ret))
2877                                 goto ttm_reserve_fail;
2878                 }
2879         }
2880
2881         amdgpu_sync_create(&sync_obj);
2882
2883         /* Validate PDs and PTs */
2884         ret = process_validate_vms(process_info);
2885         if (ret)
2886                 goto validate_map_fail;
2887
2888         /* Validate BOs and map them to GPUVM (update VM page tables). */
2889         list_for_each_entry(mem, &process_info->kfd_bo_list,
2890                             validate_list) {
2891
2892                 struct amdgpu_bo *bo = mem->bo;
2893                 uint32_t domain = mem->domain;
2894                 struct kfd_mem_attachment *attachment;
2895                 struct dma_resv_iter cursor;
2896                 struct dma_fence *fence;
2897
2898                 total_size += amdgpu_bo_size(bo);
2899
2900                 ret = amdgpu_amdkfd_bo_validate(bo, domain, false);
2901                 if (ret) {
2902                         pr_debug("Memory eviction: Validate BOs failed\n");
2903                         failed_size += amdgpu_bo_size(bo);
2904                         ret = amdgpu_amdkfd_bo_validate(bo,
2905                                                 AMDGPU_GEM_DOMAIN_GTT, false);
2906                         if (ret) {
2907                                 pr_debug("Memory eviction: Try again\n");
2908                                 goto validate_map_fail;
2909                         }
2910                 }
2911                 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv,
2912                                         DMA_RESV_USAGE_KERNEL, fence) {
2913                         ret = amdgpu_sync_fence(&sync_obj, fence);
2914                         if (ret) {
2915                                 pr_debug("Memory eviction: Sync BO fence failed. Try again\n");
2916                                 goto validate_map_fail;
2917                         }
2918                 }
2919                 list_for_each_entry(attachment, &mem->attachments, list) {
2920                         if (!attachment->is_mapped)
2921                                 continue;
2922
2923                         if (attachment->bo_va->base.bo->tbo.pin_count)
2924                                 continue;
2925
2926                         kfd_mem_dmaunmap_attachment(mem, attachment);
2927                         ret = update_gpuvm_pte(mem, attachment, &sync_obj);
2928                         if (ret) {
2929                                 pr_debug("Memory eviction: update PTE failed. Try again\n");
2930                                 goto validate_map_fail;
2931                         }
2932                 }
2933         }
2934
2935         if (failed_size)
2936                 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size);
2937
2938         /* Update mappings not managed by KFD */
2939         list_for_each_entry(peer_vm, &process_info->vm_list_head,
2940                         vm_list_node) {
2941                 struct amdgpu_device *adev = amdgpu_ttm_adev(
2942                         peer_vm->root.bo->tbo.bdev);
2943
2944                 ret = amdgpu_vm_handle_moved(adev, peer_vm, &exec.ticket);
2945                 if (ret) {
2946                         pr_debug("Memory eviction: handle moved failed. Try again\n");
2947                         goto validate_map_fail;
2948                 }
2949         }
2950
2951         /* Update page directories */
2952         ret = process_update_pds(process_info, &sync_obj);
2953         if (ret) {
2954                 pr_debug("Memory eviction: update PDs failed. Try again\n");
2955                 goto validate_map_fail;
2956         }
2957
2958         /* Sync with fences on all the page tables. They implicitly depend on any
2959          * move fences from amdgpu_vm_handle_moved above.
2960          */
2961         ret = process_sync_pds_resv(process_info, &sync_obj);
2962         if (ret) {
2963                 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n");
2964                 goto validate_map_fail;
2965         }
2966
2967         /* Wait for validate and PT updates to finish */
2968         amdgpu_sync_wait(&sync_obj, false);
2969
2970         /* The old eviction fence may be unsignaled if restore happens
2971          * after a GPU reset or suspend/resume. Keep the old fence in that
2972          * case. Otherwise release the old eviction fence and create new
2973          * one, because fence only goes from unsignaled to signaled once
2974          * and cannot be reused. Use context and mm from the old fence.
2975          *
2976          * If an old eviction fence signals after this check, that's OK.
2977          * Anyone signaling an eviction fence must stop the queues first
2978          * and schedule another restore worker.
2979          */
2980         if (dma_fence_is_signaled(&process_info->eviction_fence->base)) {
2981                 struct amdgpu_amdkfd_fence *new_fence =
2982                         amdgpu_amdkfd_fence_create(
2983                                 process_info->eviction_fence->base.context,
2984                                 process_info->eviction_fence->mm,
2985                                 NULL);
2986
2987                 if (!new_fence) {
2988                         pr_err("Failed to create eviction fence\n");
2989                         ret = -ENOMEM;
2990                         goto validate_map_fail;
2991                 }
2992                 dma_fence_put(&process_info->eviction_fence->base);
2993                 process_info->eviction_fence = new_fence;
2994                 replace_eviction_fence(ef, dma_fence_get(&new_fence->base));
2995         } else {
2996                 WARN_ONCE(*ef != &process_info->eviction_fence->base,
2997                           "KFD eviction fence doesn't match KGD process_info");
2998         }
2999
3000         /* Attach new eviction fence to all BOs except pinned ones */
3001         list_for_each_entry(mem, &process_info->kfd_bo_list, validate_list) {
3002                 if (mem->bo->tbo.pin_count)
3003                         continue;
3004
3005                 dma_resv_add_fence(mem->bo->tbo.base.resv,
3006                                    &process_info->eviction_fence->base,
3007                                    DMA_RESV_USAGE_BOOKKEEP);
3008         }
3009         /* Attach eviction fence to PD / PT BOs */
3010         list_for_each_entry(peer_vm, &process_info->vm_list_head,
3011                             vm_list_node) {
3012                 struct amdgpu_bo *bo = peer_vm->root.bo;
3013
3014                 dma_resv_add_fence(bo->tbo.base.resv,
3015                                    &process_info->eviction_fence->base,
3016                                    DMA_RESV_USAGE_BOOKKEEP);
3017         }
3018
3019 validate_map_fail:
3020         amdgpu_sync_free(&sync_obj);
3021 ttm_reserve_fail:
3022         drm_exec_fini(&exec);
3023         mutex_unlock(&process_info->lock);
3024         return ret;
3025 }
3026
3027 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem)
3028 {
3029         struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3030         struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws;
3031         int ret;
3032
3033         if (!info || !gws)
3034                 return -EINVAL;
3035
3036         *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL);
3037         if (!*mem)
3038                 return -ENOMEM;
3039
3040         mutex_init(&(*mem)->lock);
3041         INIT_LIST_HEAD(&(*mem)->attachments);
3042         (*mem)->bo = amdgpu_bo_ref(gws_bo);
3043         (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS;
3044         (*mem)->process_info = process_info;
3045         add_kgd_mem_to_kfd_bo_list(*mem, process_info, false);
3046         amdgpu_sync_create(&(*mem)->sync);
3047
3048
3049         /* Validate gws bo the first time it is added to process */
3050         mutex_lock(&(*mem)->process_info->lock);
3051         ret = amdgpu_bo_reserve(gws_bo, false);
3052         if (unlikely(ret)) {
3053                 pr_err("Reserve gws bo failed %d\n", ret);
3054                 goto bo_reservation_failure;
3055         }
3056
3057         ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true);
3058         if (ret) {
3059                 pr_err("GWS BO validate failed %d\n", ret);
3060                 goto bo_validation_failure;
3061         }
3062         /* GWS resource is shared b/t amdgpu and amdkfd
3063          * Add process eviction fence to bo so they can
3064          * evict each other.
3065          */
3066         ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1);
3067         if (ret)
3068                 goto reserve_shared_fail;
3069         dma_resv_add_fence(gws_bo->tbo.base.resv,
3070                            &process_info->eviction_fence->base,
3071                            DMA_RESV_USAGE_BOOKKEEP);
3072         amdgpu_bo_unreserve(gws_bo);
3073         mutex_unlock(&(*mem)->process_info->lock);
3074
3075         return ret;
3076
3077 reserve_shared_fail:
3078 bo_validation_failure:
3079         amdgpu_bo_unreserve(gws_bo);
3080 bo_reservation_failure:
3081         mutex_unlock(&(*mem)->process_info->lock);
3082         amdgpu_sync_free(&(*mem)->sync);
3083         remove_kgd_mem_from_kfd_bo_list(*mem, process_info);
3084         amdgpu_bo_unref(&gws_bo);
3085         mutex_destroy(&(*mem)->lock);
3086         kfree(*mem);
3087         *mem = NULL;
3088         return ret;
3089 }
3090
3091 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem)
3092 {
3093         int ret;
3094         struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info;
3095         struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
3096         struct amdgpu_bo *gws_bo = kgd_mem->bo;
3097
3098         /* Remove BO from process's validate list so restore worker won't touch
3099          * it anymore
3100          */
3101         remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info);
3102
3103         ret = amdgpu_bo_reserve(gws_bo, false);
3104         if (unlikely(ret)) {
3105                 pr_err("Reserve gws bo failed %d\n", ret);
3106                 //TODO add BO back to validate_list?
3107                 return ret;
3108         }
3109         amdgpu_amdkfd_remove_eviction_fence(gws_bo,
3110                         process_info->eviction_fence);
3111         amdgpu_bo_unreserve(gws_bo);
3112         amdgpu_sync_free(&kgd_mem->sync);
3113         amdgpu_bo_unref(&gws_bo);
3114         mutex_destroy(&kgd_mem->lock);
3115         kfree(mem);
3116         return 0;
3117 }
3118
3119 /* Returns GPU-specific tiling mode information */
3120 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
3121                                 struct tile_config *config)
3122 {
3123         config->gb_addr_config = adev->gfx.config.gb_addr_config;
3124         config->tile_config_ptr = adev->gfx.config.tile_mode_array;
3125         config->num_tile_configs =
3126                         ARRAY_SIZE(adev->gfx.config.tile_mode_array);
3127         config->macro_tile_config_ptr =
3128                         adev->gfx.config.macrotile_mode_array;
3129         config->num_macro_tile_configs =
3130                         ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
3131
3132         /* Those values are not set from GFX9 onwards */
3133         config->num_banks = adev->gfx.config.num_banks;
3134         config->num_ranks = adev->gfx.config.num_ranks;
3135
3136         return 0;
3137 }
3138
3139 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem)
3140 {
3141         struct kfd_mem_attachment *entry;
3142
3143         list_for_each_entry(entry, &mem->attachments, list) {
3144                 if (entry->is_mapped && entry->adev == adev)
3145                         return true;
3146         }
3147         return false;
3148 }
3149
3150 #if defined(CONFIG_DEBUG_FS)
3151
3152 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data)
3153 {
3154
3155         spin_lock(&kfd_mem_limit.mem_limit_lock);
3156         seq_printf(m, "System mem used %lldM out of %lluM\n",
3157                   (kfd_mem_limit.system_mem_used >> 20),
3158                   (kfd_mem_limit.max_system_mem_limit >> 20));
3159         seq_printf(m, "TTM mem used %lldM out of %lluM\n",
3160                   (kfd_mem_limit.ttm_mem_used >> 20),
3161                   (kfd_mem_limit.max_ttm_mem_limit >> 20));
3162         spin_unlock(&kfd_mem_limit.mem_limit_lock);
3163
3164         return 0;
3165 }
3166
3167 #endif