drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/hmm.h>
  36 #include <linux/pagemap.h>
  37 #include <linux/sched/task.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42
  43 #include <drm/ttm/ttm_bo_api.h>
  44 #include <drm/ttm/ttm_bo_driver.h>
  45 #include <drm/ttm/ttm_placement.h>
  46 #include <drm/ttm/ttm_module.h>
  47 #include <drm/ttm/ttm_page_alloc.h>
  48
  49 #include <drm/drm_debugfs.h>
  50 #include <drm/amdgpu_drm.h>
  51
  52 #include "amdgpu.h"
  53 #include "amdgpu_object.h"
  54 #include "amdgpu_trace.h"
  55 #include "amdgpu_amdkfd.h"
  56 #include "amdgpu_sdma.h"
  57 #include "bif/bif_4_1_d.h"
  58
  59 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  60                              struct ttm_mem_reg *mem, unsigned num_pages,
  61                              uint64_t offset, unsigned window,
  62                              struct amdgpu_ring *ring,
  63                              uint64_t *addr);
  64
  65 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  66 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  67
  68 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  69 {
  70         return 0;
  71 }
  72
  73 /**
  74  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
  75  * memory request.
  76  *
  77  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
  78  * @type: The type of memory requested
  79  * @man: The memory type manager for each domain
  80  *
  81  * This is called by ttm_bo_init_mm() when a buffer object is being
  82  * initialized.
  83  */
  84 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  85                                 struct ttm_mem_type_manager *man)
  86 {
  87         struct amdgpu_device *adev;
  88
  89         adev = amdgpu_ttm_adev(bdev);
  90
  91         switch (type) {
  92         case TTM_PL_SYSTEM:
  93                 /* System memory */
  94                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  95                 man->available_caching = TTM_PL_MASK_CACHING;
  96                 man->default_caching = TTM_PL_FLAG_CACHED;
  97                 break;
  98         case TTM_PL_TT:
  99                 /* GTT memory  */
 100                 man->func = &amdgpu_gtt_mgr_func;
 101                 man->gpu_offset = adev->gmc.gart_start;
 102                 man->available_caching = TTM_PL_MASK_CACHING;
 103                 man->default_caching = TTM_PL_FLAG_CACHED;
 104                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 105                 break;
 106         case TTM_PL_VRAM:
 107                 /* "On-card" video ram */
 108                 man->func = &amdgpu_vram_mgr_func;
 109                 man->gpu_offset = adev->gmc.vram_start;
 110                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 111                              TTM_MEMTYPE_FLAG_MAPPABLE;
 112                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 113                 man->default_caching = TTM_PL_FLAG_WC;
 114                 break;
 115         case AMDGPU_PL_GDS:
 116         case AMDGPU_PL_GWS:
 117         case AMDGPU_PL_OA:
 118                 /* On-chip GDS memory*/
 119                 man->func = &ttm_bo_manager_func;
 120                 man->gpu_offset = 0;
 121                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 122                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 123                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 124                 break;
 125         default:
 126                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 127                 return -EINVAL;
 128         }
 129         return 0;
 130 }
 131
 132 /**
 133  * amdgpu_evict_flags - Compute placement flags
 134  *
 135  * @bo: The buffer object to evict
 136  * @placement: Possible destination(s) for evicted BO
 137  *
 138  * Fill in placement data when ttm_bo_evict() is called
 139  */
 140 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 141                                 struct ttm_placement *placement)
 142 {
 143         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 144         struct amdgpu_bo *abo;
 145         static const struct ttm_place placements = {
 146                 .fpfn = 0,
 147                 .lpfn = 0,
 148                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 149         };
 150
 151         /* Don't handle scatter gather BOs */
 152         if (bo->type == ttm_bo_type_sg) {
 153                 placement->num_placement = 0;
 154                 placement->num_busy_placement = 0;
 155                 return;
 156         }
 157
 158         /* Object isn't an AMDGPU object so ignore */
 159         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 160                 placement->placement = &placements;
 161                 placement->busy_placement = &placements;
 162                 placement->num_placement = 1;
 163                 placement->num_busy_placement = 1;
 164                 return;
 165         }
 166
 167         abo = ttm_to_amdgpu_bo(bo);
 168         switch (bo->mem.mem_type) {
 169         case AMDGPU_PL_GDS:
 170         case AMDGPU_PL_GWS:
 171         case AMDGPU_PL_OA:
 172                 placement->num_placement = 0;
 173                 placement->num_busy_placement = 0;
 174                 return;
 175
 176         case TTM_PL_VRAM:
 177                 if (!adev->mman.buffer_funcs_enabled) {
 178                         /* Move to system memory */
 179                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 180                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 181                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 182                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 183
 184                         /* Try evicting to the CPU inaccessible part of VRAM
 185                          * first, but only set GTT as busy placement, so this
 186                          * BO will be evicted to GTT rather than causing other
 187                          * BOs to be evicted from VRAM
 188                          */
 189                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 190                                                          AMDGPU_GEM_DOMAIN_GTT);
 191                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 192                         abo->placements[0].lpfn = 0;
 193                         abo->placement.busy_placement = &abo->placements[1];
 194                         abo->placement.num_busy_placement = 1;
 195                 } else {
 196                         /* Move to GTT memory */
 197                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 198                 }
 199                 break;
 200         case TTM_PL_TT:
 201         default:
 202                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 203                 break;
 204         }
 205         *placement = abo->placement;
 206 }
 207
 208 /**
 209  * amdgpu_verify_access - Verify access for a mmap call
 210  *
 211  * @bo: The buffer object to map
 212  * @filp: The file pointer from the process performing the mmap
 213  *
 214  * This is called by ttm_bo_mmap() to verify whether a process
 215  * has the right to mmap a BO to their process space.
 216  */
 217 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 218 {
 219         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 220
 221         /*
 222          * Don't verify access for KFD BOs. They don't have a GEM
 223          * object associated with them.
 224          */
 225         if (abo->kfd_bo)
 226                 return 0;
 227
 228         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 229                 return -EPERM;
 230         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 231                                           filp->private_data);
 232 }
 233
 234 /**
 235  * amdgpu_move_null - Register memory for a buffer object
 236  *
 237  * @bo: The bo to assign the memory to
 238  * @new_mem: The memory to be assigned.
 239  *
 240  * Assign the memory from new_mem to the memory of the buffer object bo.
 241  */
 242 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 243                              struct ttm_mem_reg *new_mem)
 244 {
 245         struct ttm_mem_reg *old_mem = &bo->mem;
 246
 247         BUG_ON(old_mem->mm_node != NULL);
 248         *old_mem = *new_mem;
 249         new_mem->mm_node = NULL;
 250 }
 251
 252 /**
 253  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 254  *
 255  * @bo: The bo to assign the memory to.
 256  * @mm_node: Memory manager node for drm allocator.
 257  * @mem: The region where the bo resides.
 258  *
 259  */
 260 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 261                                     struct drm_mm_node *mm_node,
 262                                     struct ttm_mem_reg *mem)
 263 {
 264         uint64_t addr = 0;
 265
 266         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 267                 addr = mm_node->start << PAGE_SHIFT;
 268                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 269         }
 270         return addr;
 271 }
 272
 273 /**
 274  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 275  * @offset. It also modifies the offset to be within the drm_mm_node returned
 276  *
 277  * @mem: The region where the bo resides.
 278  * @offset: The offset that drm_mm_node is used for finding.
 279  *
 280  */
 281 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 282                                                unsigned long *offset)
 283 {
 284         struct drm_mm_node *mm_node = mem->mm_node;
 285
 286         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 287                 *offset -= (mm_node->size << PAGE_SHIFT);
 288                 ++mm_node;
 289         }
 290         return mm_node;
 291 }
 292
 293 /**
 294  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 295  *
 296  * The function copies @size bytes from {src->mem + src->offset} to
 297  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 298  * move and different for a BO to BO copy.
 299  *
 300  * @f: Returns the last fence if multiple jobs are submitted.
 301  */
 302 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 303                                struct amdgpu_copy_mem *src,
 304                                struct amdgpu_copy_mem *dst,
 305                                uint64_t size,
 306                                struct reservation_object *resv,
 307                                struct dma_fence **f)
 308 {
 309         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 310         struct drm_mm_node *src_mm, *dst_mm;
 311         uint64_t src_node_start, dst_node_start, src_node_size,
 312                  dst_node_size, src_page_offset, dst_page_offset;
 313         struct dma_fence *fence = NULL;
 314         int r = 0;
 315         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 316                                         AMDGPU_GPU_PAGE_SIZE);
 317
 318         if (!adev->mman.buffer_funcs_enabled) {
 319                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 320                 return -EINVAL;
 321         }
 322
 323         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 324         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 325                                              src->offset;
 326         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 327         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 328
 329         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 330         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 331                                              dst->offset;
 332         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 333         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 334
 335         mutex_lock(&adev->mman.gtt_window_lock);
 336
 337         while (size) {
 338                 unsigned long cur_size;
 339                 uint64_t from = src_node_start, to = dst_node_start;
 340                 struct dma_fence *next;
 341
 342                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 343                  * begins at an offset, then adjust the size accordingly
 344                  */
 345                 cur_size = min3(min(src_node_size, dst_node_size), size,
 346                                 GTT_MAX_BYTES);
 347                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 348                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 349                         cur_size -= max(src_page_offset, dst_page_offset);
 350
 351                 /* Map only what needs to be accessed. Map src to window 0 and
 352                  * dst to window 1
 353                  */
 354                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 355                         r = amdgpu_map_buffer(src->bo, src->mem,
 356                                         PFN_UP(cur_size + src_page_offset),
 357                                         src_node_start, 0, ring,
 358                                         &from);
 359                         if (r)
 360                                 goto error;
 361                         /* Adjust the offset because amdgpu_map_buffer returns
 362                          * start of mapped page
 363                          */
 364                         from += src_page_offset;
 365                 }
 366
 367                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 368                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 369                                         PFN_UP(cur_size + dst_page_offset),
 370                                         dst_node_start, 1, ring,
 371                                         &to);
 372                         if (r)
 373                                 goto error;
 374                         to += dst_page_offset;
 375                 }
 376
 377                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 378                                        resv, &next, false, true);
 379                 if (r)
 380                         goto error;
 381
 382                 dma_fence_put(fence);
 383                 fence = next;
 384
 385                 size -= cur_size;
 386                 if (!size)
 387                         break;
 388
 389                 src_node_size -= cur_size;
 390                 if (!src_node_size) {
 391                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 392                                                              src->mem);
 393                         src_node_size = (src_mm->size << PAGE_SHIFT);
 394                 } else {
 395                         src_node_start += cur_size;
 396                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 397                 }
 398                 dst_node_size -= cur_size;
 399                 if (!dst_node_size) {
 400                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 401                                                              dst->mem);
 402                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 403                 } else {
 404                         dst_node_start += cur_size;
 405                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 406                 }
 407         }
 408 error:
 409         mutex_unlock(&adev->mman.gtt_window_lock);
 410         if (f)
 411                 *f = dma_fence_get(fence);
 412         dma_fence_put(fence);
 413         return r;
 414 }
 415
 416 /**
 417  * amdgpu_move_blit - Copy an entire buffer to another buffer
 418  *
 419  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 420  * help move buffers to and from VRAM.
 421  */
 422 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 423                             bool evict, bool no_wait_gpu,
 424                             struct ttm_mem_reg *new_mem,
 425                             struct ttm_mem_reg *old_mem)
 426 {
 427         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 428         struct amdgpu_copy_mem src, dst;
 429         struct dma_fence *fence = NULL;
 430         int r;
 431
 432         src.bo = bo;
 433         dst.bo = bo;
 434         src.mem = old_mem;
 435         dst.mem = new_mem;
 436         src.offset = 0;
 437         dst.offset = 0;
 438
 439         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 440                                        new_mem->num_pages << PAGE_SHIFT,
 441                                        bo->resv, &fence);
 442         if (r)
 443                 goto error;
 444
 445         /* Always block for VM page tables before committing the new location */
 446         if (bo->type == ttm_bo_type_kernel)
 447                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 448         else
 449                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 450         dma_fence_put(fence);
 451         return r;
 452
 453 error:
 454         if (fence)
 455                 dma_fence_wait(fence, false);
 456         dma_fence_put(fence);
 457         return r;
 458 }
 459
 460 /**
 461  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 462  *
 463  * Called by amdgpu_bo_move().
 464  */
 465 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 466                                 struct ttm_operation_ctx *ctx,
 467                                 struct ttm_mem_reg *new_mem)
 468 {
 469         struct amdgpu_device *adev;
 470         struct ttm_mem_reg *old_mem = &bo->mem;
 471         struct ttm_mem_reg tmp_mem;
 472         struct ttm_place placements;
 473         struct ttm_placement placement;
 474         int r;
 475
 476         adev = amdgpu_ttm_adev(bo->bdev);
 477
 478         /* create space/pages for new_mem in GTT space */
 479         tmp_mem = *new_mem;
 480         tmp_mem.mm_node = NULL;
 481         placement.num_placement = 1;
 482         placement.placement = &placements;
 483         placement.num_busy_placement = 1;
 484         placement.busy_placement = &placements;
 485         placements.fpfn = 0;
 486         placements.lpfn = 0;
 487         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 488         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 489         if (unlikely(r)) {
 490                 return r;
 491         }
 492
 493         /* set caching flags */
 494         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 495         if (unlikely(r)) {
 496                 goto out_cleanup;
 497         }
 498
 499         /* Bind the memory to the GTT space */
 500         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 501         if (unlikely(r)) {
 502                 goto out_cleanup;
 503         }
 504
 505         /* blit VRAM to GTT */
 506         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 507         if (unlikely(r)) {
 508                 goto out_cleanup;
 509         }
 510
 511         /* move BO (in tmp_mem) to new_mem */
 512         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 513 out_cleanup:
 514         ttm_bo_mem_put(bo, &tmp_mem);
 515         return r;
 516 }
 517
 518 /**
 519  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 520  *
 521  * Called by amdgpu_bo_move().
 522  */
 523 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 524                                 struct ttm_operation_ctx *ctx,
 525                                 struct ttm_mem_reg *new_mem)
 526 {
 527         struct amdgpu_device *adev;
 528         struct ttm_mem_reg *old_mem = &bo->mem;
 529         struct ttm_mem_reg tmp_mem;
 530         struct ttm_placement placement;
 531         struct ttm_place placements;
 532         int r;
 533
 534         adev = amdgpu_ttm_adev(bo->bdev);
 535
 536         /* make space in GTT for old_mem buffer */
 537         tmp_mem = *new_mem;
 538         tmp_mem.mm_node = NULL;
 539         placement.num_placement = 1;
 540         placement.placement = &placements;
 541         placement.num_busy_placement = 1;
 542         placement.busy_placement = &placements;
 543         placements.fpfn = 0;
 544         placements.lpfn = 0;
 545         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 546         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 547         if (unlikely(r)) {
 548                 return r;
 549         }
 550
 551         /* move/bind old memory to GTT space */
 552         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 553         if (unlikely(r)) {
 554                 goto out_cleanup;
 555         }
 556
 557         /* copy to VRAM */
 558         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 559         if (unlikely(r)) {
 560                 goto out_cleanup;
 561         }
 562 out_cleanup:
 563         ttm_bo_mem_put(bo, &tmp_mem);
 564         return r;
 565 }
 566
 567 /**
 568  * amdgpu_bo_move - Move a buffer object to a new memory location
 569  *
 570  * Called by ttm_bo_handle_move_mem()
 571  */
 572 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 573                           struct ttm_operation_ctx *ctx,
 574                           struct ttm_mem_reg *new_mem)
 575 {
 576         struct amdgpu_device *adev;
 577         struct amdgpu_bo *abo;
 578         struct ttm_mem_reg *old_mem = &bo->mem;
 579         int r;
 580
 581         /* Can't move a pinned BO */
 582         abo = ttm_to_amdgpu_bo(bo);
 583         if (WARN_ON_ONCE(abo->pin_count > 0))
 584                 return -EINVAL;
 585
 586         adev = amdgpu_ttm_adev(bo->bdev);
 587
 588         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 589                 amdgpu_move_null(bo, new_mem);
 590                 return 0;
 591         }
 592         if ((old_mem->mem_type == TTM_PL_TT &&
 593              new_mem->mem_type == TTM_PL_SYSTEM) ||
 594             (old_mem->mem_type == TTM_PL_SYSTEM &&
 595              new_mem->mem_type == TTM_PL_TT)) {
 596                 /* bind is enough */
 597                 amdgpu_move_null(bo, new_mem);
 598                 return 0;
 599         }
 600         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 601             old_mem->mem_type == AMDGPU_PL_GWS ||
 602             old_mem->mem_type == AMDGPU_PL_OA ||
 603             new_mem->mem_type == AMDGPU_PL_GDS ||
 604             new_mem->mem_type == AMDGPU_PL_GWS ||
 605             new_mem->mem_type == AMDGPU_PL_OA) {
 606                 /* Nothing to save here */
 607                 amdgpu_move_null(bo, new_mem);
 608                 return 0;
 609         }
 610
 611         if (!adev->mman.buffer_funcs_enabled)
 612                 goto memcpy;
 613
 614         if (old_mem->mem_type == TTM_PL_VRAM &&
 615             new_mem->mem_type == TTM_PL_SYSTEM) {
 616                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 617         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 618                    new_mem->mem_type == TTM_PL_VRAM) {
 619                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 620         } else {
 621                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 622                                      new_mem, old_mem);
 623         }
 624
 625         if (r) {
 626 memcpy:
 627                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 628                 if (r) {
 629                         return r;
 630                 }
 631         }
 632
 633         if (bo->type == ttm_bo_type_device &&
 634             new_mem->mem_type == TTM_PL_VRAM &&
 635             old_mem->mem_type != TTM_PL_VRAM) {
 636                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 637                  * accesses the BO after it's moved.
 638                  */
 639                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 640         }
 641
 642         /* update statistics */
 643         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 644         return 0;
 645 }
 646
 647 /**
 648  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 649  *
 650  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 651  */
 652 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 653 {
 654         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 655         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 656         struct drm_mm_node *mm_node = mem->mm_node;
 657
 658         mem->bus.addr = NULL;
 659         mem->bus.offset = 0;
 660         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 661         mem->bus.base = 0;
 662         mem->bus.is_iomem = false;
 663         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 664                 return -EINVAL;
 665         switch (mem->mem_type) {
 666         case TTM_PL_SYSTEM:
 667                 /* system memory */
 668                 return 0;
 669         case TTM_PL_TT:
 670                 break;
 671         case TTM_PL_VRAM:
 672                 mem->bus.offset = mem->start << PAGE_SHIFT;
 673                 /* check if it's visible */
 674                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 675                         return -EINVAL;
 676                 /* Only physically contiguous buffers apply. In a contiguous
 677                  * buffer, size of the first mm_node would match the number of
 678                  * pages in ttm_mem_reg.
 679                  */
 680                 if (adev->mman.aper_base_kaddr &&
 681                     (mm_node->size == mem->num_pages))
 682                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 683                                         mem->bus.offset;
 684
 685                 mem->bus.base = adev->gmc.aper_base;
 686                 mem->bus.is_iomem = true;
 687                 break;
 688         default:
 689                 return -EINVAL;
 690         }
 691         return 0;
 692 }
 693
 694 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 695 {
 696 }
 697
 698 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 699                                            unsigned long page_offset)
 700 {
 701         struct drm_mm_node *mm;
 702         unsigned long offset = (page_offset << PAGE_SHIFT);
 703
 704         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 705         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 706                 (offset >> PAGE_SHIFT);
 707 }
 708
 709 /*
 710  * TTM backend functions.
 711  */
 712 struct amdgpu_ttm_tt {
 713         struct ttm_dma_tt       ttm;
 714         u64                     offset;
 715         uint64_t                userptr;
 716         struct task_struct      *usertask;
 717         uint32_t                userflags;
 718 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 719         struct hmm_range        *ranges;
 720         int                     nr_ranges;
 721 #endif
 722 };
 723
 724 /**
 725  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 726  * memory and start HMM tracking CPU page table update
 727  *
 728  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 729  * once afterwards to stop HMM tracking
 730  */
 731 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 732
 733 /* Support Userptr pages cross max 16 vmas */
 734 #define MAX_NR_VMAS     (16)
 735
 736 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 737 {
 738         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 739         struct mm_struct *mm = gtt->usertask->mm;
 740         unsigned long start = gtt->userptr;
 741         unsigned long end = start + ttm->num_pages * PAGE_SIZE;
 742         struct vm_area_struct *vma = NULL, *vmas[MAX_NR_VMAS];
 743         struct hmm_range *ranges;
 744         unsigned long nr_pages, i;
 745         uint64_t *pfns, f;
 746         int r = 0;
 747
 748         if (!mm) /* Happens during process shutdown */
 749                 return -ESRCH;
 750
 751         down_read(&mm->mmap_sem);
 752
 753         /* user pages may cross multiple VMAs */
 754         gtt->nr_ranges = 0;
 755         do {
 756                 unsigned long vm_start;
 757
 758                 if (gtt->nr_ranges >= MAX_NR_VMAS) {
 759                         DRM_ERROR("Too many VMAs in userptr range\n");
 760                         r = -EFAULT;
 761                         goto out;
 762                 }
 763
 764                 vm_start = vma ? vma->vm_end : start;
 765                 vma = find_vma(mm, vm_start);
 766                 if (unlikely(!vma || vm_start < vma->vm_start)) {
 767                         r = -EFAULT;
 768                         goto out;
 769                 }
 770                 vmas[gtt->nr_ranges++] = vma;
 771         } while (end > vma->vm_end);
 772
 773         DRM_DEBUG_DRIVER("0x%lx nr_ranges %d pages 0x%lx\n",
 774                 start, gtt->nr_ranges, ttm->num_pages);
 775
 776         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 777                 vmas[0]->vm_file)) {
 778                 r = -EPERM;
 779                 goto out;
 780         }
 781
 782         ranges = kvmalloc_array(gtt->nr_ranges, sizeof(*ranges), GFP_KERNEL);
 783         if (unlikely(!ranges)) {
 784                 r = -ENOMEM;
 785                 goto out;
 786         }
 787
 788         pfns = kvmalloc_array(ttm->num_pages, sizeof(*pfns), GFP_KERNEL);
 789         if (unlikely(!pfns)) {
 790                 r = -ENOMEM;
 791                 goto out_free_ranges;
 792         }
 793
 794         for (i = 0; i < gtt->nr_ranges; i++)
 795                 amdgpu_hmm_init_range(&ranges[i]);
 796
 797         f = ranges[0].flags[HMM_PFN_VALID];
 798         f |= amdgpu_ttm_tt_is_readonly(ttm) ?
 799                                 0 : ranges[0].flags[HMM_PFN_WRITE];
 800         memset64(pfns, f, ttm->num_pages);
 801
 802         for (nr_pages = 0, i = 0; i < gtt->nr_ranges; i++) {
 803                 ranges[i].vma = vmas[i];
 804                 ranges[i].start = max(start, vmas[i]->vm_start);
 805                 ranges[i].end = min(end, vmas[i]->vm_end);
 806                 ranges[i].pfns = pfns + nr_pages;
 807                 nr_pages += (ranges[i].end - ranges[i].start) / PAGE_SIZE;
 808
 809                 r = hmm_vma_fault(&ranges[i], true);
 810                 if (unlikely(r))
 811                         break;
 812         }
 813         if (unlikely(r)) {
 814                 while (i--)
 815                         hmm_vma_range_done(&ranges[i]);
 816
 817                 goto out_free_pfns;
 818         }
 819
 820         up_read(&mm->mmap_sem);
 821
 822         for (i = 0; i < ttm->num_pages; i++) {
 823                 pages[i] = hmm_pfn_to_page(&ranges[0], pfns[i]);
 824                 if (!pages[i]) {
 825                         pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
 826                                i, pfns[i]);
 827                         goto out_invalid_pfn;
 828                 }
 829         }
 830         gtt->ranges = ranges;
 831
 832         return 0;
 833
 834 out_free_pfns:
 835         kvfree(pfns);
 836 out_free_ranges:
 837         kvfree(ranges);
 838 out:
 839         up_read(&mm->mmap_sem);
 840
 841         return r;
 842
 843 out_invalid_pfn:
 844         for (i = 0; i < gtt->nr_ranges; i++)
 845                 hmm_vma_range_done(&ranges[i]);
 846         kvfree(pfns);
 847         kvfree(ranges);
 848         return -ENOMEM;
 849 }
 850
 851 /**
 852  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 853  * Check if the pages backing this ttm range have been invalidated
 854  *
 855  * Returns: true if pages are still valid
 856  */
 857 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 858 {
 859         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 860         bool r = false;
 861         int i;
 862
 863         if (!gtt || !gtt->userptr)
 864                 return false;
 865
 866         DRM_DEBUG_DRIVER("user_pages_done 0x%llx nr_ranges %d pages 0x%lx\n",
 867                 gtt->userptr, gtt->nr_ranges, ttm->num_pages);
 868
 869         WARN_ONCE(!gtt->ranges || !gtt->ranges[0].pfns,
 870                 "No user pages to check\n");
 871
 872         if (gtt->ranges) {
 873                 for (i = 0; i < gtt->nr_ranges; i++)
 874                         r |= hmm_vma_range_done(&gtt->ranges[i]);
 875                 kvfree(gtt->ranges[0].pfns);
 876                 kvfree(gtt->ranges);
 877                 gtt->ranges = NULL;
 878         }
 879
 880         return r;
 881 }
 882 #endif
 883
 884 /**
 885  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 886  *
 887  * Called by amdgpu_cs_list_validate(). This creates the page list
 888  * that backs user memory and will ultimately be mapped into the device
 889  * address space.
 890  */
 891 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 892 {
 893         unsigned long i;
 894
 895         for (i = 0; i < ttm->num_pages; ++i)
 896                 ttm->pages[i] = pages ? pages[i] : NULL;
 897 }
 898
 899 /**
 900  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 901  *
 902  * Called by amdgpu_ttm_backend_bind()
 903  **/
 904 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 905 {
 906         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 907         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 908         unsigned nents;
 909         int r;
 910
 911         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 912         enum dma_data_direction direction = write ?
 913                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 914
 915         /* Allocate an SG array and squash pages into it */
 916         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 917                                       ttm->num_pages << PAGE_SHIFT,
 918                                       GFP_KERNEL);
 919         if (r)
 920                 goto release_sg;
 921
 922         /* Map SG to device */
 923         r = -ENOMEM;
 924         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 925         if (nents != ttm->sg->nents)
 926                 goto release_sg;
 927
 928         /* convert SG to linear array of pages and dma addresses */
 929         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 930                                          gtt->ttm.dma_address, ttm->num_pages);
 931
 932         return 0;
 933
 934 release_sg:
 935         kfree(ttm->sg);
 936         return r;
 937 }
 938
 939 /**
 940  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 941  */
 942 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 943 {
 944         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 945         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 946
 947         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 948         enum dma_data_direction direction = write ?
 949                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 950
 951         /* double check that we don't free the table twice */
 952         if (!ttm->sg->sgl)
 953                 return;
 954
 955         /* unmap the pages mapped to the device */
 956         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 957
 958         sg_free_table(ttm->sg);
 959
 960 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 961         if (gtt->ranges &&
 962             ttm->pages[0] == hmm_pfn_to_page(&gtt->ranges[0],
 963                                              gtt->ranges[0].pfns[0]))
 964                 WARN_ONCE(1, "Missing get_user_page_done\n");
 965 #endif
 966 }
 967
 968 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 969                                 struct ttm_buffer_object *tbo,
 970                                 uint64_t flags)
 971 {
 972         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 973         struct ttm_tt *ttm = tbo->ttm;
 974         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 975         int r;
 976
 977         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 978                 uint64_t page_idx = 1;
 979
 980                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 981                                 ttm->pages, gtt->ttm.dma_address, flags);
 982                 if (r)
 983                         goto gart_bind_fail;
 984
 985                 /* Patch mtype of the second part BO */
 986                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
 987                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
 988
 989                 r = amdgpu_gart_bind(adev,
 990                                 gtt->offset + (page_idx << PAGE_SHIFT),
 991                                 ttm->num_pages - page_idx,
 992                                 &ttm->pages[page_idx],
 993                                 &(gtt->ttm.dma_address[page_idx]), flags);
 994         } else {
 995                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 996                                      ttm->pages, gtt->ttm.dma_address, flags);
 997         }
 998
 999 gart_bind_fail:
1000         if (r)
1001                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1002                           ttm->num_pages, gtt->offset);
1003
1004         return r;
1005 }
1006
1007 /**
1008  * amdgpu_ttm_backend_bind - Bind GTT memory
1009  *
1010  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1011  * This handles binding GTT memory to the device address space.
1012  */
1013 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1014                                    struct ttm_mem_reg *bo_mem)
1015 {
1016         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1017         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1018         uint64_t flags;
1019         int r = 0;
1020
1021         if (gtt->userptr) {
1022                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1023                 if (r) {
1024                         DRM_ERROR("failed to pin userptr\n");
1025                         return r;
1026                 }
1027         }
1028         if (!ttm->num_pages) {
1029                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1030                      ttm->num_pages, bo_mem, ttm);
1031         }
1032
1033         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1034             bo_mem->mem_type == AMDGPU_PL_GWS ||
1035             bo_mem->mem_type == AMDGPU_PL_OA)
1036                 return -EINVAL;
1037
1038         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1039                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1040                 return 0;
1041         }
1042
1043         /* compute PTE flags relevant to this BO memory */
1044         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1045
1046         /* bind pages into GART page tables */
1047         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1048         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1049                 ttm->pages, gtt->ttm.dma_address, flags);
1050
1051         if (r)
1052                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1053                           ttm->num_pages, gtt->offset);
1054         return r;
1055 }
1056
1057 /**
1058  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1059  */
1060 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1061 {
1062         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1063         struct ttm_operation_ctx ctx = { false, false };
1064         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1065         struct ttm_mem_reg tmp;
1066         struct ttm_placement placement;
1067         struct ttm_place placements;
1068         uint64_t addr, flags;
1069         int r;
1070
1071         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1072                 return 0;
1073
1074         addr = amdgpu_gmc_agp_addr(bo);
1075         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1076                 bo->mem.start = addr >> PAGE_SHIFT;
1077         } else {
1078
1079                 /* allocate GART space */
1080                 tmp = bo->mem;
1081                 tmp.mm_node = NULL;
1082                 placement.num_placement = 1;
1083                 placement.placement = &placements;
1084                 placement.num_busy_placement = 1;
1085                 placement.busy_placement = &placements;
1086                 placements.fpfn = 0;
1087                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1088                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1089                         TTM_PL_FLAG_TT;
1090
1091                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1092                 if (unlikely(r))
1093                         return r;
1094
1095                 /* compute PTE flags for this buffer object */
1096                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1097
1098                 /* Bind pages */
1099                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1100                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1101                 if (unlikely(r)) {
1102                         ttm_bo_mem_put(bo, &tmp);
1103                         return r;
1104                 }
1105
1106                 ttm_bo_mem_put(bo, &bo->mem);
1107                 bo->mem = tmp;
1108         }
1109
1110         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1111                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1112
1113         return 0;
1114 }
1115
1116 /**
1117  * amdgpu_ttm_recover_gart - Rebind GTT pages
1118  *
1119  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1120  * rebind GTT pages during a GPU reset.
1121  */
1122 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1123 {
1124         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1125         uint64_t flags;
1126         int r;
1127
1128         if (!tbo->ttm)
1129                 return 0;
1130
1131         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1132         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1133
1134         return r;
1135 }
1136
1137 /**
1138  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1139  *
1140  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1141  * ttm_tt_destroy().
1142  */
1143 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1144 {
1145         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1146         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1147         int r;
1148
1149         /* if the pages have userptr pinning then clear that first */
1150         if (gtt->userptr)
1151                 amdgpu_ttm_tt_unpin_userptr(ttm);
1152
1153         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1154                 return 0;
1155
1156         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1157         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1158         if (r)
1159                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1160                           gtt->ttm.ttm.num_pages, gtt->offset);
1161         return r;
1162 }
1163
1164 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1165 {
1166         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1167
1168         if (gtt->usertask)
1169                 put_task_struct(gtt->usertask);
1170
1171         ttm_dma_tt_fini(&gtt->ttm);
1172         kfree(gtt);
1173 }
1174
1175 static struct ttm_backend_func amdgpu_backend_func = {
1176         .bind = &amdgpu_ttm_backend_bind,
1177         .unbind = &amdgpu_ttm_backend_unbind,
1178         .destroy = &amdgpu_ttm_backend_destroy,
1179 };
1180
1181 /**
1182  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1183  *
1184  * @bo: The buffer object to create a GTT ttm_tt object around
1185  *
1186  * Called by ttm_tt_create().
1187  */
1188 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1189                                            uint32_t page_flags)
1190 {
1191         struct amdgpu_device *adev;
1192         struct amdgpu_ttm_tt *gtt;
1193
1194         adev = amdgpu_ttm_adev(bo->bdev);
1195
1196         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1197         if (gtt == NULL) {
1198                 return NULL;
1199         }
1200         gtt->ttm.ttm.func = &amdgpu_backend_func;
1201
1202         /* allocate space for the uninitialized page entries */
1203         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1204                 kfree(gtt);
1205                 return NULL;
1206         }
1207         return &gtt->ttm.ttm;
1208 }
1209
1210 /**
1211  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1212  *
1213  * Map the pages of a ttm_tt object to an address space visible
1214  * to the underlying device.
1215  */
1216 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1217                         struct ttm_operation_ctx *ctx)
1218 {
1219         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1220         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1221         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1222
1223         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1224         if (gtt && gtt->userptr) {
1225                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1226                 if (!ttm->sg)
1227                         return -ENOMEM;
1228
1229                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1230                 ttm->state = tt_unbound;
1231                 return 0;
1232         }
1233
1234         if (slave && ttm->sg) {
1235                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1236                                                  gtt->ttm.dma_address,
1237                                                  ttm->num_pages);
1238                 ttm->state = tt_unbound;
1239                 return 0;
1240         }
1241
1242 #ifdef CONFIG_SWIOTLB
1243         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1244                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1245         }
1246 #endif
1247
1248         /* fall back to generic helper to populate the page array
1249          * and map them to the device */
1250         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1251 }
1252
1253 /**
1254  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1255  *
1256  * Unmaps pages of a ttm_tt object from the device address space and
1257  * unpopulates the page array backing it.
1258  */
1259 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1260 {
1261         struct amdgpu_device *adev;
1262         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1263         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1264
1265         if (gtt && gtt->userptr) {
1266                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1267                 kfree(ttm->sg);
1268                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1269                 return;
1270         }
1271
1272         if (slave)
1273                 return;
1274
1275         adev = amdgpu_ttm_adev(ttm->bdev);
1276
1277 #ifdef CONFIG_SWIOTLB
1278         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1279                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1280                 return;
1281         }
1282 #endif
1283
1284         /* fall back to generic helper to unmap and unpopulate array */
1285         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1286 }
1287
1288 /**
1289  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1290  * task
1291  *
1292  * @ttm: The ttm_tt object to bind this userptr object to
1293  * @addr:  The address in the current tasks VM space to use
1294  * @flags: Requirements of userptr object.
1295  *
1296  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1297  * to current task
1298  */
1299 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1300                               uint32_t flags)
1301 {
1302         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1303
1304         if (gtt == NULL)
1305                 return -EINVAL;
1306
1307         gtt->userptr = addr;
1308         gtt->userflags = flags;
1309
1310         if (gtt->usertask)
1311                 put_task_struct(gtt->usertask);
1312         gtt->usertask = current->group_leader;
1313         get_task_struct(gtt->usertask);
1314
1315         return 0;
1316 }
1317
1318 /**
1319  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1320  */
1321 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1322 {
1323         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1324
1325         if (gtt == NULL)
1326                 return NULL;
1327
1328         if (gtt->usertask == NULL)
1329                 return NULL;
1330
1331         return gtt->usertask->mm;
1332 }
1333
1334 /**
1335  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1336  * address range for the current task.
1337  *
1338  */
1339 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1340                                   unsigned long end)
1341 {
1342         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1343         unsigned long size;
1344
1345         if (gtt == NULL || !gtt->userptr)
1346                 return false;
1347
1348         /* Return false if no part of the ttm_tt object lies within
1349          * the range
1350          */
1351         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1352         if (gtt->userptr > end || gtt->userptr + size <= start)
1353                 return false;
1354
1355         return true;
1356 }
1357
1358 /**
1359  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1360  */
1361 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1362 {
1363         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1364
1365         if (gtt == NULL || !gtt->userptr)
1366                 return false;
1367
1368         return true;
1369 }
1370
1371 /**
1372  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1373  */
1374 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1375 {
1376         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1377
1378         if (gtt == NULL)
1379                 return false;
1380
1381         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1382 }
1383
1384 /**
1385  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1386  *
1387  * @ttm: The ttm_tt object to compute the flags for
1388  * @mem: The memory registry backing this ttm_tt object
1389  *
1390  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1391  */
1392 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1393 {
1394         uint64_t flags = 0;
1395
1396         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1397                 flags |= AMDGPU_PTE_VALID;
1398
1399         if (mem && mem->mem_type == TTM_PL_TT) {
1400                 flags |= AMDGPU_PTE_SYSTEM;
1401
1402                 if (ttm->caching_state == tt_cached)
1403                         flags |= AMDGPU_PTE_SNOOPED;
1404         }
1405
1406         return flags;
1407 }
1408
1409 /**
1410  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1411  *
1412  * @ttm: The ttm_tt object to compute the flags for
1413  * @mem: The memory registry backing this ttm_tt object
1414
1415  * Figure out the flags to use for a VM PTE (Page Table Entry).
1416  */
1417 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1418                                  struct ttm_mem_reg *mem)
1419 {
1420         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1421
1422         flags |= adev->gart.gart_pte_flags;
1423         flags |= AMDGPU_PTE_READABLE;
1424
1425         if (!amdgpu_ttm_tt_is_readonly(ttm))
1426                 flags |= AMDGPU_PTE_WRITEABLE;
1427
1428         return flags;
1429 }
1430
1431 /**
1432  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1433  * object.
1434  *
1435  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1436  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1437  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1438  * used to clean out a memory space.
1439  */
1440 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1441                                             const struct ttm_place *place)
1442 {
1443         unsigned long num_pages = bo->mem.num_pages;
1444         struct drm_mm_node *node = bo->mem.mm_node;
1445         struct reservation_object_list *flist;
1446         struct dma_fence *f;
1447         int i;
1448
1449         /* Don't evict VM page tables while they are busy, otherwise we can't
1450          * cleanly handle page faults.
1451          */
1452         if (bo->type == ttm_bo_type_kernel &&
1453             !reservation_object_test_signaled_rcu(bo->resv, true))
1454                 return false;
1455
1456         /* If bo is a KFD BO, check if the bo belongs to the current process.
1457          * If true, then return false as any KFD process needs all its BOs to
1458          * be resident to run successfully
1459          */
1460         flist = reservation_object_get_list(bo->resv);
1461         if (flist) {
1462                 for (i = 0; i < flist->shared_count; ++i) {
1463                         f = rcu_dereference_protected(flist->shared[i],
1464                                 reservation_object_held(bo->resv));
1465                         if (amdkfd_fence_check_mm(f, current->mm))
1466                                 return false;
1467                 }
1468         }
1469
1470         switch (bo->mem.mem_type) {
1471         case TTM_PL_TT:
1472                 return true;
1473
1474         case TTM_PL_VRAM:
1475                 /* Check each drm MM node individually */
1476                 while (num_pages) {
1477                         if (place->fpfn < (node->start + node->size) &&
1478                             !(place->lpfn && place->lpfn <= node->start))
1479                                 return true;
1480
1481                         num_pages -= node->size;
1482                         ++node;
1483                 }
1484                 return false;
1485
1486         default:
1487                 break;
1488         }
1489
1490         return ttm_bo_eviction_valuable(bo, place);
1491 }
1492
1493 /**
1494  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1495  *
1496  * @bo:  The buffer object to read/write
1497  * @offset:  Offset into buffer object
1498  * @buf:  Secondary buffer to write/read from
1499  * @len: Length in bytes of access
1500  * @write:  true if writing
1501  *
1502  * This is used to access VRAM that backs a buffer object via MMIO
1503  * access for debugging purposes.
1504  */
1505 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1506                                     unsigned long offset,
1507                                     void *buf, int len, int write)
1508 {
1509         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1510         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1511         struct drm_mm_node *nodes;
1512         uint32_t value = 0;
1513         int ret = 0;
1514         uint64_t pos;
1515         unsigned long flags;
1516
1517         if (bo->mem.mem_type != TTM_PL_VRAM)
1518                 return -EIO;
1519
1520         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1521         pos = (nodes->start << PAGE_SHIFT) + offset;
1522
1523         while (len && pos < adev->gmc.mc_vram_size) {
1524                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1525                 uint32_t bytes = 4 - (pos & 3);
1526                 uint32_t shift = (pos & 3) * 8;
1527                 uint32_t mask = 0xffffffff << shift;
1528
1529                 if (len < bytes) {
1530                         mask &= 0xffffffff >> (bytes - len) * 8;
1531                         bytes = len;
1532                 }
1533
1534                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1535                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1536                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1537                 if (!write || mask != 0xffffffff)
1538                         value = RREG32_NO_KIQ(mmMM_DATA);
1539                 if (write) {
1540                         value &= ~mask;
1541                         value |= (*(uint32_t *)buf << shift) & mask;
1542                         WREG32_NO_KIQ(mmMM_DATA, value);
1543                 }
1544                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1545                 if (!write) {
1546                         value = (value & mask) >> shift;
1547                         memcpy(buf, &value, bytes);
1548                 }
1549
1550                 ret += bytes;
1551                 buf = (uint8_t *)buf + bytes;
1552                 pos += bytes;
1553                 len -= bytes;
1554                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1555                         ++nodes;
1556                         pos = (nodes->start << PAGE_SHIFT);
1557                 }
1558         }
1559
1560         return ret;
1561 }
1562
1563 static struct ttm_bo_driver amdgpu_bo_driver = {
1564         .ttm_tt_create = &amdgpu_ttm_tt_create,
1565         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1566         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1567         .invalidate_caches = &amdgpu_invalidate_caches,
1568         .init_mem_type = &amdgpu_init_mem_type,
1569         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1570         .evict_flags = &amdgpu_evict_flags,
1571         .move = &amdgpu_bo_move,
1572         .verify_access = &amdgpu_verify_access,
1573         .move_notify = &amdgpu_bo_move_notify,
1574         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1575         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1576         .io_mem_free = &amdgpu_ttm_io_mem_free,
1577         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1578         .access_memory = &amdgpu_ttm_access_memory,
1579         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1580 };
1581
1582 /*
1583  * Firmware Reservation functions
1584  */
1585 /**
1586  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1587  *
1588  * @adev: amdgpu_device pointer
1589  *
1590  * free fw reserved vram if it has been reserved.
1591  */
1592 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1593 {
1594         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1595                 NULL, &adev->fw_vram_usage.va);
1596 }
1597
1598 /**
1599  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1600  *
1601  * @adev: amdgpu_device pointer
1602  *
1603  * create bo vram reservation from fw.
1604  */
1605 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1606 {
1607         struct ttm_operation_ctx ctx = { false, false };
1608         struct amdgpu_bo_param bp;
1609         int r = 0;
1610         int i;
1611         u64 vram_size = adev->gmc.visible_vram_size;
1612         u64 offset = adev->fw_vram_usage.start_offset;
1613         u64 size = adev->fw_vram_usage.size;
1614         struct amdgpu_bo *bo;
1615
1616         memset(&bp, 0, sizeof(bp));
1617         bp.size = adev->fw_vram_usage.size;
1618         bp.byte_align = PAGE_SIZE;
1619         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1620         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1621                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1622         bp.type = ttm_bo_type_kernel;
1623         bp.resv = NULL;
1624         adev->fw_vram_usage.va = NULL;
1625         adev->fw_vram_usage.reserved_bo = NULL;
1626
1627         if (adev->fw_vram_usage.size > 0 &&
1628                 adev->fw_vram_usage.size <= vram_size) {
1629
1630                 r = amdgpu_bo_create(adev, &bp,
1631                                      &adev->fw_vram_usage.reserved_bo);
1632                 if (r)
1633                         goto error_create;
1634
1635                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1636                 if (r)
1637                         goto error_reserve;
1638
1639                 /* remove the original mem node and create a new one at the
1640                  * request position
1641                  */
1642                 bo = adev->fw_vram_usage.reserved_bo;
1643                 offset = ALIGN(offset, PAGE_SIZE);
1644                 for (i = 0; i < bo->placement.num_placement; ++i) {
1645                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1646                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1647                 }
1648
1649                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1650                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1651                                      &bo->tbo.mem, &ctx);
1652                 if (r)
1653                         goto error_pin;
1654
1655                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1656                         AMDGPU_GEM_DOMAIN_VRAM,
1657                         adev->fw_vram_usage.start_offset,
1658                         (adev->fw_vram_usage.start_offset +
1659                         adev->fw_vram_usage.size));
1660                 if (r)
1661                         goto error_pin;
1662                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1663                         &adev->fw_vram_usage.va);
1664                 if (r)
1665                         goto error_kmap;
1666
1667                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1668         }
1669         return r;
1670
1671 error_kmap:
1672         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1673 error_pin:
1674         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1675 error_reserve:
1676         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1677 error_create:
1678         adev->fw_vram_usage.va = NULL;
1679         adev->fw_vram_usage.reserved_bo = NULL;
1680         return r;
1681 }
1682 /**
1683  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1684  * gtt/vram related fields.
1685  *
1686  * This initializes all of the memory space pools that the TTM layer
1687  * will need such as the GTT space (system memory mapped to the device),
1688  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1689  * can be mapped per VMID.
1690  */
1691 int amdgpu_ttm_init(struct amdgpu_device *adev)
1692 {
1693         uint64_t gtt_size;
1694         int r;
1695         u64 vis_vram_limit;
1696
1697         mutex_init(&adev->mman.gtt_window_lock);
1698
1699         /* No others user of address space so set it to 0 */
1700         r = ttm_bo_device_init(&adev->mman.bdev,
1701                                &amdgpu_bo_driver,
1702                                adev->ddev->anon_inode->i_mapping,
1703                                adev->need_dma32);
1704         if (r) {
1705                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1706                 return r;
1707         }
1708         adev->mman.initialized = true;
1709
1710         /* We opt to avoid OOM on system pages allocations */
1711         adev->mman.bdev.no_retry = true;
1712
1713         /* Initialize VRAM pool with all of VRAM divided into pages */
1714         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1715                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1716         if (r) {
1717                 DRM_ERROR("Failed initializing VRAM heap.\n");
1718                 return r;
1719         }
1720
1721         /* Reduce size of CPU-visible VRAM if requested */
1722         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1723         if (amdgpu_vis_vram_limit > 0 &&
1724             vis_vram_limit <= adev->gmc.visible_vram_size)
1725                 adev->gmc.visible_vram_size = vis_vram_limit;
1726
1727         /* Change the size here instead of the init above so only lpfn is affected */
1728         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1729 #ifdef CONFIG_64BIT
1730         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1731                                                 adev->gmc.visible_vram_size);
1732 #endif
1733
1734         /*
1735          *The reserved vram for firmware must be pinned to the specified
1736          *place on the VRAM, so reserve it early.
1737          */
1738         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1739         if (r) {
1740                 return r;
1741         }
1742
1743         /* allocate memory as required for VGA
1744          * This is used for VGA emulation and pre-OS scanout buffers to
1745          * avoid display artifacts while transitioning between pre-OS
1746          * and driver.  */
1747         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1748                                     AMDGPU_GEM_DOMAIN_VRAM,
1749                                     &adev->stolen_vga_memory,
1750                                     NULL, NULL);
1751         if (r)
1752                 return r;
1753         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1754                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1755
1756         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1757          * or whatever the user passed on module init */
1758         if (amdgpu_gtt_size == -1) {
1759                 struct sysinfo si;
1760
1761                 si_meminfo(&si);
1762                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1763                                adev->gmc.mc_vram_size),
1764                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1765         }
1766         else
1767                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1768
1769         /* Initialize GTT memory pool */
1770         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1771         if (r) {
1772                 DRM_ERROR("Failed initializing GTT heap.\n");
1773                 return r;
1774         }
1775         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1776                  (unsigned)(gtt_size / (1024 * 1024)));
1777
1778         /* Initialize various on-chip memory pools */
1779         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1780                            adev->gds.gds_size);
1781         if (r) {
1782                 DRM_ERROR("Failed initializing GDS heap.\n");
1783                 return r;
1784         }
1785
1786         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1787                            adev->gds.gws_size);
1788         if (r) {
1789                 DRM_ERROR("Failed initializing gws heap.\n");
1790                 return r;
1791         }
1792
1793         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1794                            adev->gds.oa_size);
1795         if (r) {
1796                 DRM_ERROR("Failed initializing oa heap.\n");
1797                 return r;
1798         }
1799
1800         /* Register debugfs entries for amdgpu_ttm */
1801         r = amdgpu_ttm_debugfs_init(adev);
1802         if (r) {
1803                 DRM_ERROR("Failed to init debugfs\n");
1804                 return r;
1805         }
1806         return 0;
1807 }
1808
1809 /**
1810  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1811  */
1812 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1813 {
1814         /* return the VGA stolen memory (if any) back to VRAM */
1815         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1816 }
1817
1818 /**
1819  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1820  */
1821 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1822 {
1823         if (!adev->mman.initialized)
1824                 return;
1825
1826         amdgpu_ttm_debugfs_fini(adev);
1827         amdgpu_ttm_fw_reserve_vram_fini(adev);
1828         if (adev->mman.aper_base_kaddr)
1829                 iounmap(adev->mman.aper_base_kaddr);
1830         adev->mman.aper_base_kaddr = NULL;
1831
1832         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1833         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1834         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1835         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1836         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1837         ttm_bo_device_release(&adev->mman.bdev);
1838         adev->mman.initialized = false;
1839         DRM_INFO("amdgpu: ttm finalized\n");
1840 }
1841
1842 /**
1843  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1844  *
1845  * @adev: amdgpu_device pointer
1846  * @enable: true when we can use buffer functions.
1847  *
1848  * Enable/disable use of buffer functions during suspend/resume. This should
1849  * only be called at bootup or when userspace isn't running.
1850  */
1851 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1852 {
1853         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1854         uint64_t size;
1855         int r;
1856
1857         if (!adev->mman.initialized || adev->in_gpu_reset ||
1858             adev->mman.buffer_funcs_enabled == enable)
1859                 return;
1860
1861         if (enable) {
1862                 struct amdgpu_ring *ring;
1863                 struct drm_sched_rq *rq;
1864
1865                 ring = adev->mman.buffer_funcs_ring;
1866                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1867                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1868                 if (r) {
1869                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1870                                   r);
1871                         return;
1872                 }
1873         } else {
1874                 drm_sched_entity_destroy(&adev->mman.entity);
1875                 dma_fence_put(man->move);
1876                 man->move = NULL;
1877         }
1878
1879         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1880         if (enable)
1881                 size = adev->gmc.real_vram_size;
1882         else
1883                 size = adev->gmc.visible_vram_size;
1884         man->size = size >> PAGE_SHIFT;
1885         adev->mman.buffer_funcs_enabled = enable;
1886 }
1887
1888 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1889 {
1890         struct drm_file *file_priv = filp->private_data;
1891         struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
1892
1893         if (adev == NULL)
1894                 return -EINVAL;
1895
1896         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1897 }
1898
1899 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1900                              struct ttm_mem_reg *mem, unsigned num_pages,
1901                              uint64_t offset, unsigned window,
1902                              struct amdgpu_ring *ring,
1903                              uint64_t *addr)
1904 {
1905         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1906         struct amdgpu_device *adev = ring->adev;
1907         struct ttm_tt *ttm = bo->ttm;
1908         struct amdgpu_job *job;
1909         unsigned num_dw, num_bytes;
1910         dma_addr_t *dma_address;
1911         struct dma_fence *fence;
1912         uint64_t src_addr, dst_addr;
1913         uint64_t flags;
1914         int r;
1915
1916         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1917                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1918
1919         *addr = adev->gmc.gart_start;
1920         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1921                 AMDGPU_GPU_PAGE_SIZE;
1922
1923         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1924         while (num_dw & 0x7)
1925                 num_dw++;
1926
1927         num_bytes = num_pages * 8;
1928
1929         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1930         if (r)
1931                 return r;
1932
1933         src_addr = num_dw * 4;
1934         src_addr += job->ibs[0].gpu_addr;
1935
1936         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
1937         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1938         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1939                                 dst_addr, num_bytes);
1940
1941         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1942         WARN_ON(job->ibs[0].length_dw > num_dw);
1943
1944         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1945         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
1946         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
1947                             &job->ibs[0].ptr[num_dw]);
1948         if (r)
1949                 goto error_free;
1950
1951         r = amdgpu_job_submit(job, &adev->mman.entity,
1952                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
1953         if (r)
1954                 goto error_free;
1955
1956         dma_fence_put(fence);
1957
1958         return r;
1959
1960 error_free:
1961         amdgpu_job_free(job);
1962         return r;
1963 }
1964
1965 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1966                        uint64_t dst_offset, uint32_t byte_count,
1967                        struct reservation_object *resv,
1968                        struct dma_fence **fence, bool direct_submit,
1969                        bool vm_needs_flush)
1970 {
1971         struct amdgpu_device *adev = ring->adev;
1972         struct amdgpu_job *job;
1973
1974         uint32_t max_bytes;
1975         unsigned num_loops, num_dw;
1976         unsigned i;
1977         int r;
1978
1979         if (direct_submit && !ring->sched.ready) {
1980                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1981                 return -EINVAL;
1982         }
1983
1984         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1985         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1986         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
1987
1988         /* for IB padding */
1989         while (num_dw & 0x7)
1990                 num_dw++;
1991
1992         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
1993         if (r)
1994                 return r;
1995
1996         if (vm_needs_flush) {
1997                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
1998                 job->vm_needs_flush = true;
1999         }
2000         if (resv) {
2001                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2002                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2003                                      false);
2004                 if (r) {
2005                         DRM_ERROR("sync failed (%d).\n", r);
2006                         goto error_free;
2007                 }
2008         }
2009
2010         for (i = 0; i < num_loops; i++) {
2011                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2012
2013                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2014                                         dst_offset, cur_size_in_bytes);
2015
2016                 src_offset += cur_size_in_bytes;
2017                 dst_offset += cur_size_in_bytes;
2018                 byte_count -= cur_size_in_bytes;
2019         }
2020
2021         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2022         WARN_ON(job->ibs[0].length_dw > num_dw);
2023         if (direct_submit)
2024                 r = amdgpu_job_submit_direct(job, ring, fence);
2025         else
2026                 r = amdgpu_job_submit(job, &adev->mman.entity,
2027                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2028         if (r)
2029                 goto error_free;
2030
2031         return r;
2032
2033 error_free:
2034         amdgpu_job_free(job);
2035         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2036         return r;
2037 }
2038
2039 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2040                        uint32_t src_data,
2041                        struct reservation_object *resv,
2042                        struct dma_fence **fence)
2043 {
2044         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2045         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2046         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2047
2048         struct drm_mm_node *mm_node;
2049         unsigned long num_pages;
2050         unsigned int num_loops, num_dw;
2051
2052         struct amdgpu_job *job;
2053         int r;
2054
2055         if (!adev->mman.buffer_funcs_enabled) {
2056                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2057                 return -EINVAL;
2058         }
2059
2060         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2061                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2062                 if (r)
2063                         return r;
2064         }
2065
2066         num_pages = bo->tbo.num_pages;
2067         mm_node = bo->tbo.mem.mm_node;
2068         num_loops = 0;
2069         while (num_pages) {
2070                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2071
2072                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2073                 num_pages -= mm_node->size;
2074                 ++mm_node;
2075         }
2076         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2077
2078         /* for IB padding */
2079         num_dw += 64;
2080
2081         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2082         if (r)
2083                 return r;
2084
2085         if (resv) {
2086                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2087                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2088                 if (r) {
2089                         DRM_ERROR("sync failed (%d).\n", r);
2090                         goto error_free;
2091                 }
2092         }
2093
2094         num_pages = bo->tbo.num_pages;
2095         mm_node = bo->tbo.mem.mm_node;
2096
2097         while (num_pages) {
2098                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2099                 uint64_t dst_addr;
2100
2101                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2102                 while (byte_count) {
2103                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2104
2105                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2106                                                 dst_addr, cur_size_in_bytes);
2107
2108                         dst_addr += cur_size_in_bytes;
2109                         byte_count -= cur_size_in_bytes;
2110                 }
2111
2112                 num_pages -= mm_node->size;
2113                 ++mm_node;
2114         }
2115
2116         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2117         WARN_ON(job->ibs[0].length_dw > num_dw);
2118         r = amdgpu_job_submit(job, &adev->mman.entity,
2119                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2120         if (r)
2121                 goto error_free;
2122
2123         return 0;
2124
2125 error_free:
2126         amdgpu_job_free(job);
2127         return r;
2128 }
2129
2130 #if defined(CONFIG_DEBUG_FS)
2131
2132 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2133 {
2134         struct drm_info_node *node = (struct drm_info_node *)m->private;
2135         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2136         struct drm_device *dev = node->minor->dev;
2137         struct amdgpu_device *adev = dev->dev_private;
2138         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2139         struct drm_printer p = drm_seq_file_printer(m);
2140
2141         man->func->debug(man, &p);
2142         return 0;
2143 }
2144
2145 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2146         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2147         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2148         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2149         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2150         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2151         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2152 #ifdef CONFIG_SWIOTLB
2153         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2154 #endif
2155 };
2156
2157 /**
2158  * amdgpu_ttm_vram_read - Linear read access to VRAM
2159  *
2160  * Accesses VRAM via MMIO for debugging purposes.
2161  */
2162 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2163                                     size_t size, loff_t *pos)
2164 {
2165         struct amdgpu_device *adev = file_inode(f)->i_private;
2166         ssize_t result = 0;
2167         int r;
2168
2169         if (size & 0x3 || *pos & 0x3)
2170                 return -EINVAL;
2171
2172         if (*pos >= adev->gmc.mc_vram_size)
2173                 return -ENXIO;
2174
2175         while (size) {
2176                 unsigned long flags;
2177                 uint32_t value;
2178
2179                 if (*pos >= adev->gmc.mc_vram_size)
2180                         return result;
2181
2182                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2183                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2184                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2185                 value = RREG32_NO_KIQ(mmMM_DATA);
2186                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2187
2188                 r = put_user(value, (uint32_t *)buf);
2189                 if (r)
2190                         return r;
2191
2192                 result += 4;
2193                 buf += 4;
2194                 *pos += 4;
2195                 size -= 4;
2196         }
2197
2198         return result;
2199 }
2200
2201 /**
2202  * amdgpu_ttm_vram_write - Linear write access to VRAM
2203  *
2204  * Accesses VRAM via MMIO for debugging purposes.
2205  */
2206 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2207                                     size_t size, loff_t *pos)
2208 {
2209         struct amdgpu_device *adev = file_inode(f)->i_private;
2210         ssize_t result = 0;
2211         int r;
2212
2213         if (size & 0x3 || *pos & 0x3)
2214                 return -EINVAL;
2215
2216         if (*pos >= adev->gmc.mc_vram_size)
2217                 return -ENXIO;
2218
2219         while (size) {
2220                 unsigned long flags;
2221                 uint32_t value;
2222
2223                 if (*pos >= adev->gmc.mc_vram_size)
2224                         return result;
2225
2226                 r = get_user(value, (uint32_t *)buf);
2227                 if (r)
2228                         return r;
2229
2230                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2231                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2232                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2233                 WREG32_NO_KIQ(mmMM_DATA, value);
2234                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2235
2236                 result += 4;
2237                 buf += 4;
2238                 *pos += 4;
2239                 size -= 4;
2240         }
2241
2242         return result;
2243 }
2244
2245 static const struct file_operations amdgpu_ttm_vram_fops = {
2246         .owner = THIS_MODULE,
2247         .read = amdgpu_ttm_vram_read,
2248         .write = amdgpu_ttm_vram_write,
2249         .llseek = default_llseek,
2250 };
2251
2252 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2253
2254 /**
2255  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2256  */
2257 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2258                                    size_t size, loff_t *pos)
2259 {
2260         struct amdgpu_device *adev = file_inode(f)->i_private;
2261         ssize_t result = 0;
2262         int r;
2263
2264         while (size) {
2265                 loff_t p = *pos / PAGE_SIZE;
2266                 unsigned off = *pos & ~PAGE_MASK;
2267                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2268                 struct page *page;
2269                 void *ptr;
2270
2271                 if (p >= adev->gart.num_cpu_pages)
2272                         return result;
2273
2274                 page = adev->gart.pages[p];
2275                 if (page) {
2276                         ptr = kmap(page);
2277                         ptr += off;
2278
2279                         r = copy_to_user(buf, ptr, cur_size);
2280                         kunmap(adev->gart.pages[p]);
2281                 } else
2282                         r = clear_user(buf, cur_size);
2283
2284                 if (r)
2285                         return -EFAULT;
2286
2287                 result += cur_size;
2288                 buf += cur_size;
2289                 *pos += cur_size;
2290                 size -= cur_size;
2291         }
2292
2293         return result;
2294 }
2295
2296 static const struct file_operations amdgpu_ttm_gtt_fops = {
2297         .owner = THIS_MODULE,
2298         .read = amdgpu_ttm_gtt_read,
2299         .llseek = default_llseek
2300 };
2301
2302 #endif
2303
2304 /**
2305  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2306  *
2307  * This function is used to read memory that has been mapped to the
2308  * GPU and the known addresses are not physical addresses but instead
2309  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2310  */
2311 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2312                                  size_t size, loff_t *pos)
2313 {
2314         struct amdgpu_device *adev = file_inode(f)->i_private;
2315         struct iommu_domain *dom;
2316         ssize_t result = 0;
2317         int r;
2318
2319         /* retrieve the IOMMU domain if any for this device */
2320         dom = iommu_get_domain_for_dev(adev->dev);
2321
2322         while (size) {
2323                 phys_addr_t addr = *pos & PAGE_MASK;
2324                 loff_t off = *pos & ~PAGE_MASK;
2325                 size_t bytes = PAGE_SIZE - off;
2326                 unsigned long pfn;
2327                 struct page *p;
2328                 void *ptr;
2329
2330                 bytes = bytes < size ? bytes : size;
2331
2332                 /* Translate the bus address to a physical address.  If
2333                  * the domain is NULL it means there is no IOMMU active
2334                  * and the address translation is the identity
2335                  */
2336                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2337
2338                 pfn = addr >> PAGE_SHIFT;
2339                 if (!pfn_valid(pfn))
2340                         return -EPERM;
2341
2342                 p = pfn_to_page(pfn);
2343                 if (p->mapping != adev->mman.bdev.dev_mapping)
2344                         return -EPERM;
2345
2346                 ptr = kmap(p);
2347                 r = copy_to_user(buf, ptr + off, bytes);
2348                 kunmap(p);
2349                 if (r)
2350                         return -EFAULT;
2351
2352                 size -= bytes;
2353                 *pos += bytes;
2354                 result += bytes;
2355         }
2356
2357         return result;
2358 }
2359
2360 /**
2361  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2362  *
2363  * This function is used to write memory that has been mapped to the
2364  * GPU and the known addresses are not physical addresses but instead
2365  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2366  */
2367 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2368                                  size_t size, loff_t *pos)
2369 {
2370         struct amdgpu_device *adev = file_inode(f)->i_private;
2371         struct iommu_domain *dom;
2372         ssize_t result = 0;
2373         int r;
2374
2375         dom = iommu_get_domain_for_dev(adev->dev);
2376
2377         while (size) {
2378                 phys_addr_t addr = *pos & PAGE_MASK;
2379                 loff_t off = *pos & ~PAGE_MASK;
2380                 size_t bytes = PAGE_SIZE - off;
2381                 unsigned long pfn;
2382                 struct page *p;
2383                 void *ptr;
2384
2385                 bytes = bytes < size ? bytes : size;
2386
2387                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2388
2389                 pfn = addr >> PAGE_SHIFT;
2390                 if (!pfn_valid(pfn))
2391                         return -EPERM;
2392
2393                 p = pfn_to_page(pfn);
2394                 if (p->mapping != adev->mman.bdev.dev_mapping)
2395                         return -EPERM;
2396
2397                 ptr = kmap(p);
2398                 r = copy_from_user(ptr + off, buf, bytes);
2399                 kunmap(p);
2400                 if (r)
2401                         return -EFAULT;
2402
2403                 size -= bytes;
2404                 *pos += bytes;
2405                 result += bytes;
2406         }
2407
2408         return result;
2409 }
2410
2411 static const struct file_operations amdgpu_ttm_iomem_fops = {
2412         .owner = THIS_MODULE,
2413         .read = amdgpu_iomem_read,
2414         .write = amdgpu_iomem_write,
2415         .llseek = default_llseek
2416 };
2417
2418 static const struct {
2419         char *name;
2420         const struct file_operations *fops;
2421         int domain;
2422 } ttm_debugfs_entries[] = {
2423         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2424 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2425         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2426 #endif
2427         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2428 };
2429
2430 #endif
2431
2432 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2433 {
2434 #if defined(CONFIG_DEBUG_FS)
2435         unsigned count;
2436
2437         struct drm_minor *minor = adev->ddev->primary;
2438         struct dentry *ent, *root = minor->debugfs_root;
2439
2440         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2441                 ent = debugfs_create_file(
2442                                 ttm_debugfs_entries[count].name,
2443                                 S_IFREG | S_IRUGO, root,
2444                                 adev,
2445                                 ttm_debugfs_entries[count].fops);
2446                 if (IS_ERR(ent))
2447                         return PTR_ERR(ent);
2448                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2449                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2450                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2451                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2452                 adev->mman.debugfs_entries[count] = ent;
2453         }
2454
2455         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2456
2457 #ifdef CONFIG_SWIOTLB
2458         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2459                 --count;
2460 #endif
2461
2462         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2463 #else
2464         return 0;
2465 #endif
2466 }
2467
2468 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2469 {
2470 #if defined(CONFIG_DEBUG_FS)
2471         unsigned i;
2472
2473         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2474                 debugfs_remove(adev->mman.debugfs_entries[i]);
2475 #endif
2476 }