1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
5 // Copyright (c) 2019, 2020, 2021 Pengutronix,
10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
15 #include <linux/bitfield.h>
17 #include "mcp251xfd.h"
20 mcp251xfd_rx_head_get_from_chip(const struct mcp251xfd_priv *priv,
21 const struct mcp251xfd_rx_ring *ring,
22 u8 *rx_head, bool *fifo_empty)
27 err = regmap_read(priv->map_reg, MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
32 *rx_head = FIELD_GET(MCP251XFD_REG_FIFOSTA_FIFOCI_MASK, fifo_sta);
33 *fifo_empty = !(fifo_sta & MCP251XFD_REG_FIFOSTA_TFNRFNIF);
39 mcp251xfd_rx_tail_get_from_chip(const struct mcp251xfd_priv *priv,
40 const struct mcp251xfd_rx_ring *ring,
46 err = regmap_read(priv->map_reg, MCP251XFD_REG_FIFOUA(ring->fifo_nr),
51 fifo_ua -= ring->base - MCP251XFD_RAM_START;
52 *rx_tail = fifo_ua / ring->obj_size;
58 mcp251xfd_check_rx_tail(const struct mcp251xfd_priv *priv,
59 const struct mcp251xfd_rx_ring *ring)
61 u8 rx_tail_chip, rx_tail;
64 if (!IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY))
67 err = mcp251xfd_rx_tail_get_from_chip(priv, ring, &rx_tail_chip);
71 rx_tail = mcp251xfd_get_rx_tail(ring);
72 if (rx_tail_chip != rx_tail) {
73 netdev_err(priv->ndev,
74 "RX tail of chip (%d) and ours (%d) inconsistent.\n",
75 rx_tail_chip, rx_tail);
83 mcp251xfd_rx_ring_update(const struct mcp251xfd_priv *priv,
84 struct mcp251xfd_rx_ring *ring)
91 err = mcp251xfd_rx_head_get_from_chip(priv, ring, &chip_rx_head,
93 if (err || fifo_empty)
96 /* chip_rx_head, is the next RX-Object filled by the HW.
97 * The new RX head must be >= the old head.
99 new_head = round_down(ring->head, ring->obj_num) + chip_rx_head;
100 if (new_head <= ring->head)
101 new_head += ring->obj_num;
103 ring->head = new_head;
105 return mcp251xfd_check_rx_tail(priv, ring);
109 mcp251xfd_hw_rx_obj_to_skb(const struct mcp251xfd_priv *priv,
110 const struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj,
113 struct canfd_frame *cfd = (struct canfd_frame *)skb->data;
116 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_IDE) {
119 eid = FIELD_GET(MCP251XFD_OBJ_ID_EID_MASK, hw_rx_obj->id);
120 sid = FIELD_GET(MCP251XFD_OBJ_ID_SID_MASK, hw_rx_obj->id);
122 cfd->can_id = CAN_EFF_FLAG |
123 FIELD_PREP(MCP251XFD_REG_FRAME_EFF_EID_MASK, eid) |
124 FIELD_PREP(MCP251XFD_REG_FRAME_EFF_SID_MASK, sid);
126 cfd->can_id = FIELD_GET(MCP251XFD_OBJ_ID_SID_MASK,
130 dlc = FIELD_GET(MCP251XFD_OBJ_FLAGS_DLC_MASK, hw_rx_obj->flags);
133 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_FDF) {
134 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_ESI)
135 cfd->flags |= CANFD_ESI;
137 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_BRS)
138 cfd->flags |= CANFD_BRS;
140 cfd->len = can_fd_dlc2len(dlc);
142 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_RTR)
143 cfd->can_id |= CAN_RTR_FLAG;
145 can_frame_set_cc_len((struct can_frame *)cfd, dlc,
149 if (!(hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_RTR))
150 memcpy(cfd->data, hw_rx_obj->data, cfd->len);
152 mcp251xfd_skb_set_timestamp(priv, skb, hw_rx_obj->ts);
156 mcp251xfd_handle_rxif_one(struct mcp251xfd_priv *priv,
157 struct mcp251xfd_rx_ring *ring,
158 const struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj)
160 struct net_device_stats *stats = &priv->ndev->stats;
162 struct canfd_frame *cfd;
165 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_FDF)
166 skb = alloc_canfd_skb(priv->ndev, &cfd);
168 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cfd);
175 mcp251xfd_hw_rx_obj_to_skb(priv, hw_rx_obj, skb);
176 err = can_rx_offload_queue_timestamp(&priv->offload, skb, hw_rx_obj->ts);
178 stats->rx_fifo_errors++;
184 mcp251xfd_rx_obj_read(const struct mcp251xfd_priv *priv,
185 const struct mcp251xfd_rx_ring *ring,
186 struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj,
187 const u8 offset, const u8 len)
189 const int val_bytes = regmap_get_val_bytes(priv->map_rx);
192 err = regmap_bulk_read(priv->map_rx,
193 mcp251xfd_get_rx_obj_addr(ring, offset),
195 len * ring->obj_size / val_bytes);
201 mcp251xfd_handle_rxif_ring(struct mcp251xfd_priv *priv,
202 struct mcp251xfd_rx_ring *ring)
204 struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj = ring->obj;
208 err = mcp251xfd_rx_ring_update(priv, ring);
212 while ((len = mcp251xfd_get_rx_linear_len(ring))) {
215 rx_tail = mcp251xfd_get_rx_tail(ring);
217 err = mcp251xfd_rx_obj_read(priv, ring, hw_rx_obj,
222 for (i = 0; i < len; i++) {
223 err = mcp251xfd_handle_rxif_one(priv, ring,
230 /* Increment the RX FIFO tail pointer 'len' times in a
231 * single SPI message.
234 * Calculate offset, so that the SPI transfer ends on
235 * the last message of the uinc_xfer array, which has
236 * "cs_change == 0", to properly deactivate the chip
239 offset = ARRAY_SIZE(ring->uinc_xfer) - len;
240 err = spi_sync_transfer(priv->spi,
241 ring->uinc_xfer + offset, len);
251 int mcp251xfd_handle_rxif(struct mcp251xfd_priv *priv)
253 struct mcp251xfd_rx_ring *ring;
256 mcp251xfd_for_each_rx_ring(priv, ring, n) {
257 /* - if RX IRQ coalescing is active always handle ring 0
258 * - only handle rings if RX IRQ is active
260 if ((ring->nr > 0 || !priv->rx_obj_num_coalesce_irq) &&
261 !(priv->regs_status.rxif & BIT(ring->fifo_nr)))
264 err = mcp251xfd_handle_rxif_ring(priv, ring);
269 if (priv->rx_coalesce_usecs_irq)
270 hrtimer_start(&priv->rx_irq_timer,
271 ns_to_ktime(priv->rx_coalesce_usecs_irq *