1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Micron Technology, Inc.
10 #define pr_fmt(fmt) "spi-nand: " fmt
12 #include <linux/device.h>
13 #include <linux/jiffies.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/mtd/spinand.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi-mem.h>
23 static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
25 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(reg,
29 ret = spi_mem_exec_op(spinand->spimem, &op);
33 *val = *spinand->scratchbuf;
37 static int spinand_write_reg_op(struct spinand_device *spinand, u8 reg, u8 val)
39 struct spi_mem_op op = SPINAND_SET_FEATURE_OP(reg,
42 *spinand->scratchbuf = val;
43 return spi_mem_exec_op(spinand->spimem, &op);
46 static int spinand_read_status(struct spinand_device *spinand, u8 *status)
48 return spinand_read_reg_op(spinand, REG_STATUS, status);
51 static int spinand_get_cfg(struct spinand_device *spinand, u8 *cfg)
53 struct nand_device *nand = spinand_to_nand(spinand);
55 if (WARN_ON(spinand->cur_target < 0 ||
56 spinand->cur_target >= nand->memorg.ntargets))
59 *cfg = spinand->cfg_cache[spinand->cur_target];
63 static int spinand_set_cfg(struct spinand_device *spinand, u8 cfg)
65 struct nand_device *nand = spinand_to_nand(spinand);
68 if (WARN_ON(spinand->cur_target < 0 ||
69 spinand->cur_target >= nand->memorg.ntargets))
72 if (spinand->cfg_cache[spinand->cur_target] == cfg)
75 ret = spinand_write_reg_op(spinand, REG_CFG, cfg);
79 spinand->cfg_cache[spinand->cur_target] = cfg;
84 * spinand_upd_cfg() - Update the configuration register
85 * @spinand: the spinand device
86 * @mask: the mask encoding the bits to update in the config reg
87 * @val: the new value to apply
89 * Update the configuration register.
91 * Return: 0 on success, a negative error code otherwise.
93 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val)
98 ret = spinand_get_cfg(spinand, &cfg);
105 return spinand_set_cfg(spinand, cfg);
109 * spinand_select_target() - Select a specific NAND target/die
110 * @spinand: the spinand device
111 * @target: the target/die to select
113 * Select a new target/die. If chip only has one die, this function is a NOOP.
115 * Return: 0 on success, a negative error code otherwise.
117 int spinand_select_target(struct spinand_device *spinand, unsigned int target)
119 struct nand_device *nand = spinand_to_nand(spinand);
122 if (WARN_ON(target >= nand->memorg.ntargets))
125 if (spinand->cur_target == target)
128 if (nand->memorg.ntargets == 1) {
129 spinand->cur_target = target;
133 ret = spinand->select_target(spinand, target);
137 spinand->cur_target = target;
141 static int spinand_read_cfg(struct spinand_device *spinand)
143 struct nand_device *nand = spinand_to_nand(spinand);
147 for (target = 0; target < nand->memorg.ntargets; target++) {
148 ret = spinand_select_target(spinand, target);
153 * We use spinand_read_reg_op() instead of spinand_get_cfg()
154 * here to bypass the config cache.
156 ret = spinand_read_reg_op(spinand, REG_CFG,
157 &spinand->cfg_cache[target]);
165 static int spinand_init_cfg_cache(struct spinand_device *spinand)
167 struct nand_device *nand = spinand_to_nand(spinand);
168 struct device *dev = &spinand->spimem->spi->dev;
170 spinand->cfg_cache = devm_kcalloc(dev,
171 nand->memorg.ntargets,
172 sizeof(*spinand->cfg_cache),
174 if (!spinand->cfg_cache)
180 static int spinand_init_quad_enable(struct spinand_device *spinand)
184 if (!(spinand->flags & SPINAND_HAS_QE_BIT))
187 if (spinand->op_templates.read_cache->data.buswidth == 4 ||
188 spinand->op_templates.write_cache->data.buswidth == 4 ||
189 spinand->op_templates.update_cache->data.buswidth == 4)
192 return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
193 enable ? CFG_QUAD_ENABLE : 0);
196 static int spinand_ecc_enable(struct spinand_device *spinand,
199 return spinand_upd_cfg(spinand, CFG_ECC_ENABLE,
200 enable ? CFG_ECC_ENABLE : 0);
203 static int spinand_check_ecc_status(struct spinand_device *spinand, u8 status)
205 struct nand_device *nand = spinand_to_nand(spinand);
207 if (spinand->eccinfo.get_status)
208 return spinand->eccinfo.get_status(spinand, status);
210 switch (status & STATUS_ECC_MASK) {
211 case STATUS_ECC_NO_BITFLIPS:
214 case STATUS_ECC_HAS_BITFLIPS:
216 * We have no way to know exactly how many bitflips have been
217 * fixed, so let's return the maximum possible value so that
218 * wear-leveling layers move the data immediately.
220 return nanddev_get_ecc_conf(nand)->strength;
222 case STATUS_ECC_UNCOR_ERROR:
232 static int spinand_noecc_ooblayout_ecc(struct mtd_info *mtd, int section,
233 struct mtd_oob_region *region)
238 static int spinand_noecc_ooblayout_free(struct mtd_info *mtd, int section,
239 struct mtd_oob_region *region)
244 /* Reserve 2 bytes for the BBM. */
251 static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
252 .ecc = spinand_noecc_ooblayout_ecc,
253 .free = spinand_noecc_ooblayout_free,
256 static int spinand_ondie_ecc_init_ctx(struct nand_device *nand)
258 struct spinand_device *spinand = nand_to_spinand(nand);
259 struct mtd_info *mtd = nanddev_to_mtd(nand);
260 struct spinand_ondie_ecc_conf *engine_conf;
262 nand->ecc.ctx.conf.engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE;
263 nand->ecc.ctx.conf.step_size = nand->ecc.requirements.step_size;
264 nand->ecc.ctx.conf.strength = nand->ecc.requirements.strength;
266 engine_conf = kzalloc(sizeof(*engine_conf), GFP_KERNEL);
270 nand->ecc.ctx.priv = engine_conf;
272 if (spinand->eccinfo.ooblayout)
273 mtd_set_ooblayout(mtd, spinand->eccinfo.ooblayout);
275 mtd_set_ooblayout(mtd, &spinand_noecc_ooblayout);
280 static void spinand_ondie_ecc_cleanup_ctx(struct nand_device *nand)
282 kfree(nand->ecc.ctx.priv);
285 static int spinand_ondie_ecc_prepare_io_req(struct nand_device *nand,
286 struct nand_page_io_req *req)
288 struct spinand_device *spinand = nand_to_spinand(nand);
289 bool enable = (req->mode != MTD_OPS_RAW);
291 memset(spinand->oobbuf, 0xff, nanddev_per_page_oobsize(nand));
293 /* Only enable or disable the engine */
294 return spinand_ecc_enable(spinand, enable);
297 static int spinand_ondie_ecc_finish_io_req(struct nand_device *nand,
298 struct nand_page_io_req *req)
300 struct spinand_ondie_ecc_conf *engine_conf = nand->ecc.ctx.priv;
301 struct spinand_device *spinand = nand_to_spinand(nand);
302 struct mtd_info *mtd = spinand_to_mtd(spinand);
305 if (req->mode == MTD_OPS_RAW)
308 /* Nothing to do when finishing a page write */
309 if (req->type == NAND_PAGE_WRITE)
312 /* Finish a page read: check the status, report errors/bitflips */
313 ret = spinand_check_ecc_status(spinand, engine_conf->status);
315 mtd->ecc_stats.failed++;
317 mtd->ecc_stats.corrected += ret;
322 static struct nand_ecc_engine_ops spinand_ondie_ecc_engine_ops = {
323 .init_ctx = spinand_ondie_ecc_init_ctx,
324 .cleanup_ctx = spinand_ondie_ecc_cleanup_ctx,
325 .prepare_io_req = spinand_ondie_ecc_prepare_io_req,
326 .finish_io_req = spinand_ondie_ecc_finish_io_req,
329 static struct nand_ecc_engine spinand_ondie_ecc_engine = {
330 .ops = &spinand_ondie_ecc_engine_ops,
333 static void spinand_ondie_ecc_save_status(struct nand_device *nand, u8 status)
335 struct spinand_ondie_ecc_conf *engine_conf = nand->ecc.ctx.priv;
337 if (nand->ecc.ctx.conf.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE &&
339 engine_conf->status = status;
342 static int spinand_write_enable_op(struct spinand_device *spinand)
344 struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true);
346 return spi_mem_exec_op(spinand->spimem, &op);
349 static int spinand_load_page_op(struct spinand_device *spinand,
350 const struct nand_page_io_req *req)
352 struct nand_device *nand = spinand_to_nand(spinand);
353 unsigned int row = nanddev_pos_to_row(nand, &req->pos);
354 struct spi_mem_op op = SPINAND_PAGE_READ_OP(row);
356 return spi_mem_exec_op(spinand->spimem, &op);
359 static int spinand_read_from_cache_op(struct spinand_device *spinand,
360 const struct nand_page_io_req *req)
362 struct nand_device *nand = spinand_to_nand(spinand);
363 struct mtd_info *mtd = spinand_to_mtd(spinand);
364 struct spi_mem_dirmap_desc *rdesc;
365 unsigned int nbytes = 0;
371 buf = spinand->databuf;
372 nbytes = nanddev_page_size(nand);
377 nbytes += nanddev_per_page_oobsize(nand);
379 buf = spinand->oobbuf;
380 column = nanddev_page_size(nand);
384 if (req->mode == MTD_OPS_RAW)
385 rdesc = spinand->dirmaps[req->pos.plane].rdesc;
387 rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
390 ret = spi_mem_dirmap_read(rdesc, column, nbytes, buf);
394 if (!ret || ret > nbytes)
403 memcpy(req->databuf.in, spinand->databuf + req->dataoffs,
407 if (req->mode == MTD_OPS_AUTO_OOB)
408 mtd_ooblayout_get_databytes(mtd, req->oobbuf.in,
413 memcpy(req->oobbuf.in, spinand->oobbuf + req->ooboffs,
420 static int spinand_write_to_cache_op(struct spinand_device *spinand,
421 const struct nand_page_io_req *req)
423 struct nand_device *nand = spinand_to_nand(spinand);
424 struct mtd_info *mtd = spinand_to_mtd(spinand);
425 struct spi_mem_dirmap_desc *wdesc;
426 unsigned int nbytes, column = 0;
427 void *buf = spinand->databuf;
431 * Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
432 * the cache content to 0xFF (depends on vendor implementation), so we
433 * must fill the page cache entirely even if we only want to program
434 * the data portion of the page, otherwise we might corrupt the BBM or
435 * user data previously programmed in OOB area.
437 * Only reset the data buffer manually, the OOB buffer is prepared by
438 * ECC engines ->prepare_io_req() callback.
440 nbytes = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
441 memset(spinand->databuf, 0xff, nanddev_page_size(nand));
444 memcpy(spinand->databuf + req->dataoffs, req->databuf.out,
448 if (req->mode == MTD_OPS_AUTO_OOB)
449 mtd_ooblayout_set_databytes(mtd, req->oobbuf.out,
454 memcpy(spinand->oobbuf + req->ooboffs, req->oobbuf.out,
458 if (req->mode == MTD_OPS_RAW)
459 wdesc = spinand->dirmaps[req->pos.plane].wdesc;
461 wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
464 ret = spi_mem_dirmap_write(wdesc, column, nbytes, buf);
468 if (!ret || ret > nbytes)
479 static int spinand_program_op(struct spinand_device *spinand,
480 const struct nand_page_io_req *req)
482 struct nand_device *nand = spinand_to_nand(spinand);
483 unsigned int row = nanddev_pos_to_row(nand, &req->pos);
484 struct spi_mem_op op = SPINAND_PROG_EXEC_OP(row);
486 return spi_mem_exec_op(spinand->spimem, &op);
489 static int spinand_erase_op(struct spinand_device *spinand,
490 const struct nand_pos *pos)
492 struct nand_device *nand = spinand_to_nand(spinand);
493 unsigned int row = nanddev_pos_to_row(nand, pos);
494 struct spi_mem_op op = SPINAND_BLK_ERASE_OP(row);
496 return spi_mem_exec_op(spinand->spimem, &op);
499 static int spinand_wait(struct spinand_device *spinand,
500 unsigned long initial_delay_us,
501 unsigned long poll_delay_us,
504 struct spi_mem_op op = SPINAND_GET_FEATURE_OP(REG_STATUS,
505 spinand->scratchbuf);
509 ret = spi_mem_poll_status(spinand->spimem, &op, STATUS_BUSY, 0,
512 SPINAND_WAITRDY_TIMEOUT_MS);
516 status = *spinand->scratchbuf;
517 if (!(status & STATUS_BUSY))
521 * Extra read, just in case the STATUS_READY bit has changed
522 * since our last check
524 ret = spinand_read_status(spinand, &status);
532 return status & STATUS_BUSY ? -ETIMEDOUT : 0;
535 static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
538 struct spi_mem_op op = SPINAND_READID_OP(
539 naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
542 ret = spi_mem_exec_op(spinand->spimem, &op);
544 memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
549 static int spinand_reset_op(struct spinand_device *spinand)
551 struct spi_mem_op op = SPINAND_RESET_OP;
554 ret = spi_mem_exec_op(spinand->spimem, &op);
558 return spinand_wait(spinand,
559 SPINAND_RESET_INITIAL_DELAY_US,
560 SPINAND_RESET_POLL_DELAY_US,
564 static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
566 return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
569 static int spinand_read_page(struct spinand_device *spinand,
570 const struct nand_page_io_req *req)
572 struct nand_device *nand = spinand_to_nand(spinand);
576 ret = nand_ecc_prepare_io_req(nand, (struct nand_page_io_req *)req);
580 ret = spinand_load_page_op(spinand, req);
584 ret = spinand_wait(spinand,
585 SPINAND_READ_INITIAL_DELAY_US,
586 SPINAND_READ_POLL_DELAY_US,
591 spinand_ondie_ecc_save_status(nand, status);
593 ret = spinand_read_from_cache_op(spinand, req);
597 return nand_ecc_finish_io_req(nand, (struct nand_page_io_req *)req);
600 static int spinand_write_page(struct spinand_device *spinand,
601 const struct nand_page_io_req *req)
603 struct nand_device *nand = spinand_to_nand(spinand);
607 ret = nand_ecc_prepare_io_req(nand, (struct nand_page_io_req *)req);
611 ret = spinand_write_enable_op(spinand);
615 ret = spinand_write_to_cache_op(spinand, req);
619 ret = spinand_program_op(spinand, req);
623 ret = spinand_wait(spinand,
624 SPINAND_WRITE_INITIAL_DELAY_US,
625 SPINAND_WRITE_POLL_DELAY_US,
627 if (!ret && (status & STATUS_PROG_FAILED))
630 return nand_ecc_finish_io_req(nand, (struct nand_page_io_req *)req);
633 static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
634 struct mtd_oob_ops *ops)
636 struct spinand_device *spinand = mtd_to_spinand(mtd);
637 struct nand_device *nand = mtd_to_nanddev(mtd);
638 struct mtd_ecc_stats old_stats;
639 unsigned int max_bitflips = 0;
640 struct nand_io_iter iter;
641 bool disable_ecc = false;
642 bool ecc_failed = false;
645 if (ops->mode == MTD_OPS_RAW || !spinand->eccinfo.ooblayout)
648 mutex_lock(&spinand->lock);
650 old_stats = mtd->ecc_stats;
652 nanddev_io_for_each_page(nand, NAND_PAGE_READ, from, ops, &iter) {
654 iter.req.mode = MTD_OPS_RAW;
656 ret = spinand_select_target(spinand, iter.req.pos.target);
660 ret = spinand_read_page(spinand, &iter.req);
661 if (ret < 0 && ret != -EBADMSG)
667 max_bitflips = max_t(unsigned int, max_bitflips, ret);
670 ops->retlen += iter.req.datalen;
671 ops->oobretlen += iter.req.ooblen;
675 ops->stats->uncorrectable_errors +=
676 mtd->ecc_stats.failed - old_stats.failed;
677 ops->stats->corrected_bitflips +=
678 mtd->ecc_stats.corrected - old_stats.corrected;
681 mutex_unlock(&spinand->lock);
683 if (ecc_failed && !ret)
686 return ret ? ret : max_bitflips;
689 static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
690 struct mtd_oob_ops *ops)
692 struct spinand_device *spinand = mtd_to_spinand(mtd);
693 struct nand_device *nand = mtd_to_nanddev(mtd);
694 struct nand_io_iter iter;
695 bool disable_ecc = false;
698 if (ops->mode == MTD_OPS_RAW || !mtd->ooblayout)
701 mutex_lock(&spinand->lock);
703 nanddev_io_for_each_page(nand, NAND_PAGE_WRITE, to, ops, &iter) {
705 iter.req.mode = MTD_OPS_RAW;
707 ret = spinand_select_target(spinand, iter.req.pos.target);
711 ret = spinand_write_page(spinand, &iter.req);
715 ops->retlen += iter.req.datalen;
716 ops->oobretlen += iter.req.ooblen;
719 mutex_unlock(&spinand->lock);
724 static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
726 struct spinand_device *spinand = nand_to_spinand(nand);
728 struct nand_page_io_req req = {
730 .ooblen = sizeof(marker),
736 spinand_select_target(spinand, pos->target);
737 spinand_read_page(spinand, &req);
738 if (marker[0] != 0xff || marker[1] != 0xff)
744 static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
746 struct nand_device *nand = mtd_to_nanddev(mtd);
747 struct spinand_device *spinand = nand_to_spinand(nand);
751 nanddev_offs_to_pos(nand, offs, &pos);
752 mutex_lock(&spinand->lock);
753 ret = nanddev_isbad(nand, &pos);
754 mutex_unlock(&spinand->lock);
759 static int spinand_markbad(struct nand_device *nand, const struct nand_pos *pos)
761 struct spinand_device *spinand = nand_to_spinand(nand);
763 struct nand_page_io_req req = {
766 .ooblen = sizeof(marker),
767 .oobbuf.out = marker,
772 ret = spinand_select_target(spinand, pos->target);
776 ret = spinand_write_enable_op(spinand);
780 return spinand_write_page(spinand, &req);
783 static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
785 struct nand_device *nand = mtd_to_nanddev(mtd);
786 struct spinand_device *spinand = nand_to_spinand(nand);
790 nanddev_offs_to_pos(nand, offs, &pos);
791 mutex_lock(&spinand->lock);
792 ret = nanddev_markbad(nand, &pos);
793 mutex_unlock(&spinand->lock);
798 static int spinand_erase(struct nand_device *nand, const struct nand_pos *pos)
800 struct spinand_device *spinand = nand_to_spinand(nand);
804 ret = spinand_select_target(spinand, pos->target);
808 ret = spinand_write_enable_op(spinand);
812 ret = spinand_erase_op(spinand, pos);
816 ret = spinand_wait(spinand,
817 SPINAND_ERASE_INITIAL_DELAY_US,
818 SPINAND_ERASE_POLL_DELAY_US,
821 if (!ret && (status & STATUS_ERASE_FAILED))
827 static int spinand_mtd_erase(struct mtd_info *mtd,
828 struct erase_info *einfo)
830 struct spinand_device *spinand = mtd_to_spinand(mtd);
833 mutex_lock(&spinand->lock);
834 ret = nanddev_mtd_erase(mtd, einfo);
835 mutex_unlock(&spinand->lock);
840 static int spinand_mtd_block_isreserved(struct mtd_info *mtd, loff_t offs)
842 struct spinand_device *spinand = mtd_to_spinand(mtd);
843 struct nand_device *nand = mtd_to_nanddev(mtd);
847 nanddev_offs_to_pos(nand, offs, &pos);
848 mutex_lock(&spinand->lock);
849 ret = nanddev_isreserved(nand, &pos);
850 mutex_unlock(&spinand->lock);
855 static int spinand_create_dirmap(struct spinand_device *spinand,
858 struct nand_device *nand = spinand_to_nand(spinand);
859 struct spi_mem_dirmap_info info = {
860 .length = nanddev_page_size(nand) +
861 nanddev_per_page_oobsize(nand),
863 struct spi_mem_dirmap_desc *desc;
865 /* The plane number is passed in MSB just above the column address */
866 info.offset = plane << fls(nand->memorg.pagesize);
868 info.op_tmpl = *spinand->op_templates.update_cache;
869 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
870 spinand->spimem, &info);
872 return PTR_ERR(desc);
874 spinand->dirmaps[plane].wdesc = desc;
876 info.op_tmpl = *spinand->op_templates.read_cache;
877 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
878 spinand->spimem, &info);
880 return PTR_ERR(desc);
882 spinand->dirmaps[plane].rdesc = desc;
884 if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
885 spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
886 spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
891 info.op_tmpl = *spinand->op_templates.update_cache;
892 info.op_tmpl.data.ecc = true;
893 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
894 spinand->spimem, &info);
896 return PTR_ERR(desc);
898 spinand->dirmaps[plane].wdesc_ecc = desc;
900 info.op_tmpl = *spinand->op_templates.read_cache;
901 info.op_tmpl.data.ecc = true;
902 desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
903 spinand->spimem, &info);
905 return PTR_ERR(desc);
907 spinand->dirmaps[plane].rdesc_ecc = desc;
912 static int spinand_create_dirmaps(struct spinand_device *spinand)
914 struct nand_device *nand = spinand_to_nand(spinand);
917 spinand->dirmaps = devm_kzalloc(&spinand->spimem->spi->dev,
918 sizeof(*spinand->dirmaps) *
919 nand->memorg.planes_per_lun,
921 if (!spinand->dirmaps)
924 for (i = 0; i < nand->memorg.planes_per_lun; i++) {
925 ret = spinand_create_dirmap(spinand, i);
933 static const struct nand_ops spinand_ops = {
934 .erase = spinand_erase,
935 .markbad = spinand_markbad,
936 .isbad = spinand_isbad,
939 static const struct spinand_manufacturer *spinand_manufacturers[] = {
940 &alliancememory_spinand_manufacturer,
941 &ato_spinand_manufacturer,
942 &esmt_c8_spinand_manufacturer,
943 &gigadevice_spinand_manufacturer,
944 ¯onix_spinand_manufacturer,
945 µn_spinand_manufacturer,
946 ¶gon_spinand_manufacturer,
947 &toshiba_spinand_manufacturer,
948 &winbond_spinand_manufacturer,
949 &xtx_spinand_manufacturer,
952 static int spinand_manufacturer_match(struct spinand_device *spinand,
953 enum spinand_readid_method rdid_method)
955 u8 *id = spinand->id.data;
959 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
960 const struct spinand_manufacturer *manufacturer =
961 spinand_manufacturers[i];
963 if (id[0] != manufacturer->id)
966 ret = spinand_match_and_init(spinand,
968 manufacturer->nchips,
973 spinand->manufacturer = manufacturer;
979 static int spinand_id_detect(struct spinand_device *spinand)
981 u8 *id = spinand->id.data;
984 ret = spinand_read_id_op(spinand, 0, 0, id);
987 ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
991 ret = spinand_read_id_op(spinand, 1, 0, id);
994 ret = spinand_manufacturer_match(spinand,
995 SPINAND_READID_METHOD_OPCODE_ADDR);
999 ret = spinand_read_id_op(spinand, 0, 1, id);
1002 ret = spinand_manufacturer_match(spinand,
1003 SPINAND_READID_METHOD_OPCODE_DUMMY);
1008 static int spinand_manufacturer_init(struct spinand_device *spinand)
1010 if (spinand->manufacturer->ops->init)
1011 return spinand->manufacturer->ops->init(spinand);
1016 static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
1018 /* Release manufacturer private data */
1019 if (spinand->manufacturer->ops->cleanup)
1020 return spinand->manufacturer->ops->cleanup(spinand);
1023 static const struct spi_mem_op *
1024 spinand_select_op_variant(struct spinand_device *spinand,
1025 const struct spinand_op_variants *variants)
1027 struct nand_device *nand = spinand_to_nand(spinand);
1030 for (i = 0; i < variants->nops; i++) {
1031 struct spi_mem_op op = variants->ops[i];
1032 unsigned int nbytes;
1035 nbytes = nanddev_per_page_oobsize(nand) +
1036 nanddev_page_size(nand);
1039 op.data.nbytes = nbytes;
1040 ret = spi_mem_adjust_op_size(spinand->spimem, &op);
1044 if (!spi_mem_supports_op(spinand->spimem, &op))
1047 nbytes -= op.data.nbytes;
1051 return &variants->ops[i];
1058 * spinand_match_and_init() - Try to find a match between a device ID and an
1059 * entry in a spinand_info table
1060 * @spinand: SPI NAND object
1061 * @table: SPI NAND device description table
1062 * @table_size: size of the device description table
1063 * @rdid_method: read id method to match
1065 * Match between a device ID retrieved through the READ_ID command and an
1066 * entry in the SPI NAND description table. If a match is found, the spinand
1067 * object will be initialized with information provided by the matching
1068 * spinand_info entry.
1070 * Return: 0 on success, a negative error code otherwise.
1072 int spinand_match_and_init(struct spinand_device *spinand,
1073 const struct spinand_info *table,
1074 unsigned int table_size,
1075 enum spinand_readid_method rdid_method)
1077 u8 *id = spinand->id.data;
1078 struct nand_device *nand = spinand_to_nand(spinand);
1081 for (i = 0; i < table_size; i++) {
1082 const struct spinand_info *info = &table[i];
1083 const struct spi_mem_op *op;
1085 if (rdid_method != info->devid.method)
1088 if (memcmp(id + 1, info->devid.id, info->devid.len))
1091 nand->memorg = table[i].memorg;
1092 nanddev_set_ecc_requirements(nand, &table[i].eccreq);
1093 spinand->eccinfo = table[i].eccinfo;
1094 spinand->flags = table[i].flags;
1095 spinand->id.len = 1 + table[i].devid.len;
1096 spinand->select_target = table[i].select_target;
1098 op = spinand_select_op_variant(spinand,
1099 info->op_variants.read_cache);
1103 spinand->op_templates.read_cache = op;
1105 op = spinand_select_op_variant(spinand,
1106 info->op_variants.write_cache);
1110 spinand->op_templates.write_cache = op;
1112 op = spinand_select_op_variant(spinand,
1113 info->op_variants.update_cache);
1114 spinand->op_templates.update_cache = op;
1122 static int spinand_detect(struct spinand_device *spinand)
1124 struct device *dev = &spinand->spimem->spi->dev;
1125 struct nand_device *nand = spinand_to_nand(spinand);
1128 ret = spinand_reset_op(spinand);
1132 ret = spinand_id_detect(spinand);
1134 dev_err(dev, "unknown raw ID %*phN\n", SPINAND_MAX_ID_LEN,
1139 if (nand->memorg.ntargets > 1 && !spinand->select_target) {
1141 "SPI NANDs with more than one die must implement ->select_target()\n");
1145 dev_info(&spinand->spimem->spi->dev,
1146 "%s SPI NAND was found.\n", spinand->manufacturer->name);
1147 dev_info(&spinand->spimem->spi->dev,
1148 "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
1149 nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10,
1150 nanddev_page_size(nand), nanddev_per_page_oobsize(nand));
1155 static int spinand_init_flash(struct spinand_device *spinand)
1157 struct device *dev = &spinand->spimem->spi->dev;
1158 struct nand_device *nand = spinand_to_nand(spinand);
1161 ret = spinand_read_cfg(spinand);
1165 ret = spinand_init_quad_enable(spinand);
1169 ret = spinand_upd_cfg(spinand, CFG_OTP_ENABLE, 0);
1173 ret = spinand_manufacturer_init(spinand);
1176 "Failed to initialize the SPI NAND chip (err = %d)\n",
1181 /* After power up, all blocks are locked, so unlock them here. */
1182 for (i = 0; i < nand->memorg.ntargets; i++) {
1183 ret = spinand_select_target(spinand, i);
1187 ret = spinand_lock_block(spinand, BL_ALL_UNLOCKED);
1193 spinand_manufacturer_cleanup(spinand);
1198 static void spinand_mtd_resume(struct mtd_info *mtd)
1200 struct spinand_device *spinand = mtd_to_spinand(mtd);
1203 ret = spinand_reset_op(spinand);
1207 ret = spinand_init_flash(spinand);
1211 spinand_ecc_enable(spinand, false);
1214 static int spinand_init(struct spinand_device *spinand)
1216 struct device *dev = &spinand->spimem->spi->dev;
1217 struct mtd_info *mtd = spinand_to_mtd(spinand);
1218 struct nand_device *nand = mtd_to_nanddev(mtd);
1222 * We need a scratch buffer because the spi_mem interface requires that
1223 * buf passed in spi_mem_op->data.buf be DMA-able.
1225 spinand->scratchbuf = kzalloc(SPINAND_MAX_ID_LEN, GFP_KERNEL);
1226 if (!spinand->scratchbuf)
1229 ret = spinand_detect(spinand);
1234 * Use kzalloc() instead of devm_kzalloc() here, because some drivers
1235 * may use this buffer for DMA access.
1236 * Memory allocated by devm_ does not guarantee DMA-safe alignment.
1238 spinand->databuf = kzalloc(nanddev_page_size(nand) +
1239 nanddev_per_page_oobsize(nand),
1241 if (!spinand->databuf) {
1246 spinand->oobbuf = spinand->databuf + nanddev_page_size(nand);
1248 ret = spinand_init_cfg_cache(spinand);
1252 ret = spinand_init_flash(spinand);
1256 ret = nanddev_init(nand, &spinand_ops, THIS_MODULE);
1258 goto err_manuf_cleanup;
1260 /* SPI-NAND default ECC engine is on-die */
1261 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_DIE;
1262 nand->ecc.ondie_engine = &spinand_ondie_ecc_engine;
1264 spinand_ecc_enable(spinand, false);
1265 ret = nanddev_ecc_engine_init(nand);
1267 goto err_cleanup_nanddev;
1269 mtd->_read_oob = spinand_mtd_read;
1270 mtd->_write_oob = spinand_mtd_write;
1271 mtd->_block_isbad = spinand_mtd_block_isbad;
1272 mtd->_block_markbad = spinand_mtd_block_markbad;
1273 mtd->_block_isreserved = spinand_mtd_block_isreserved;
1274 mtd->_erase = spinand_mtd_erase;
1275 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks;
1276 mtd->_resume = spinand_mtd_resume;
1278 if (nand->ecc.engine) {
1279 ret = mtd_ooblayout_count_freebytes(mtd);
1281 goto err_cleanup_ecc_engine;
1284 mtd->oobavail = ret;
1286 /* Propagate ECC information to mtd_info */
1287 mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength;
1288 mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size;
1290 ret = spinand_create_dirmaps(spinand);
1293 "Failed to create direct mappings for read/write operations (err = %d)\n",
1295 goto err_cleanup_ecc_engine;
1300 err_cleanup_ecc_engine:
1301 nanddev_ecc_engine_cleanup(nand);
1303 err_cleanup_nanddev:
1304 nanddev_cleanup(nand);
1307 spinand_manufacturer_cleanup(spinand);
1310 kfree(spinand->databuf);
1311 kfree(spinand->scratchbuf);
1315 static void spinand_cleanup(struct spinand_device *spinand)
1317 struct nand_device *nand = spinand_to_nand(spinand);
1319 nanddev_cleanup(nand);
1320 spinand_manufacturer_cleanup(spinand);
1321 kfree(spinand->databuf);
1322 kfree(spinand->scratchbuf);
1325 static int spinand_probe(struct spi_mem *mem)
1327 struct spinand_device *spinand;
1328 struct mtd_info *mtd;
1331 spinand = devm_kzalloc(&mem->spi->dev, sizeof(*spinand),
1336 spinand->spimem = mem;
1337 spi_mem_set_drvdata(mem, spinand);
1338 spinand_set_of_node(spinand, mem->spi->dev.of_node);
1339 mutex_init(&spinand->lock);
1340 mtd = spinand_to_mtd(spinand);
1341 mtd->dev.parent = &mem->spi->dev;
1343 ret = spinand_init(spinand);
1347 ret = mtd_device_register(mtd, NULL, 0);
1349 goto err_spinand_cleanup;
1353 err_spinand_cleanup:
1354 spinand_cleanup(spinand);
1359 static int spinand_remove(struct spi_mem *mem)
1361 struct spinand_device *spinand;
1362 struct mtd_info *mtd;
1365 spinand = spi_mem_get_drvdata(mem);
1366 mtd = spinand_to_mtd(spinand);
1368 ret = mtd_device_unregister(mtd);
1372 spinand_cleanup(spinand);
1377 static const struct spi_device_id spinand_ids[] = {
1378 { .name = "spi-nand" },
1381 MODULE_DEVICE_TABLE(spi, spinand_ids);
1384 static const struct of_device_id spinand_of_ids[] = {
1385 { .compatible = "spi-nand" },
1388 MODULE_DEVICE_TABLE(of, spinand_of_ids);
1391 static struct spi_mem_driver spinand_drv = {
1393 .id_table = spinand_ids,
1396 .of_match_table = of_match_ptr(spinand_of_ids),
1399 .probe = spinand_probe,
1400 .remove = spinand_remove,
1402 module_spi_mem_driver(spinand_drv);
1404 MODULE_DESCRIPTION("SPI NAND framework");
1406 MODULE_LICENSE("GPL v2");