drivers/infiniband/hw/irdma/hw.c

   1 // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
   2 /* Copyright (c) 2015 - 2021 Intel Corporation */
   3 #include "main.h"
   4
   5 static struct irdma_rsrc_limits rsrc_limits_table[] = {
   6         [0] = {
   7                 .qplimit = SZ_128,
   8         },
   9         [1] = {
  10                 .qplimit = SZ_1K,
  11         },
  12         [2] = {
  13                 .qplimit = SZ_2K,
  14         },
  15         [3] = {
  16                 .qplimit = SZ_4K,
  17         },
  18         [4] = {
  19                 .qplimit = SZ_16K,
  20         },
  21         [5] = {
  22                 .qplimit = SZ_64K,
  23         },
  24         [6] = {
  25                 .qplimit = SZ_128K,
  26         },
  27         [7] = {
  28                 .qplimit = SZ_256K,
  29         },
  30 };
  31
  32 /* types of hmc objects */
  33 static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = {
  34         IRDMA_HMC_IW_QP,
  35         IRDMA_HMC_IW_CQ,
  36         IRDMA_HMC_IW_HTE,
  37         IRDMA_HMC_IW_ARP,
  38         IRDMA_HMC_IW_APBVT_ENTRY,
  39         IRDMA_HMC_IW_MR,
  40         IRDMA_HMC_IW_XF,
  41         IRDMA_HMC_IW_XFFL,
  42         IRDMA_HMC_IW_Q1,
  43         IRDMA_HMC_IW_Q1FL,
  44         IRDMA_HMC_IW_PBLE,
  45         IRDMA_HMC_IW_TIMER,
  46         IRDMA_HMC_IW_FSIMC,
  47         IRDMA_HMC_IW_FSIAV,
  48         IRDMA_HMC_IW_RRF,
  49         IRDMA_HMC_IW_RRFFL,
  50         IRDMA_HMC_IW_HDR,
  51         IRDMA_HMC_IW_MD,
  52         IRDMA_HMC_IW_OOISC,
  53         IRDMA_HMC_IW_OOISCFFL,
  54 };
  55
  56 /**
  57  * irdma_iwarp_ce_handler - handle iwarp completions
  58  * @iwcq: iwarp cq receiving event
  59  */
  60 static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq)
  61 {
  62         struct irdma_cq *cq = iwcq->back_cq;
  63
  64         if (!cq->user_mode)
  65                 atomic_set(&cq->armed, 0);
  66         if (cq->ibcq.comp_handler)
  67                 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
  68 }
  69
  70 /**
  71  * irdma_puda_ce_handler - handle puda completion events
  72  * @rf: RDMA PCI function
  73  * @cq: puda completion q for event
  74  */
  75 static void irdma_puda_ce_handler(struct irdma_pci_f *rf,
  76                                   struct irdma_sc_cq *cq)
  77 {
  78         struct irdma_sc_dev *dev = &rf->sc_dev;
  79         u32 compl_error;
  80         int status;
  81
  82         do {
  83                 status = irdma_puda_poll_cmpl(dev, cq, &compl_error);
  84                 if (status == -ENOENT)
  85                         break;
  86                 if (status) {
  87                         ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status);
  88                         break;
  89                 }
  90                 if (compl_error) {
  91                         ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err  =0x%x\n",
  92                                   compl_error);
  93                         break;
  94                 }
  95         } while (1);
  96
  97         irdma_sc_ccq_arm(cq);
  98 }
  99
 100 /**
 101  * irdma_process_ceq - handle ceq for completions
 102  * @rf: RDMA PCI function
 103  * @ceq: ceq having cq for completion
 104  */
 105 static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq)
 106 {
 107         struct irdma_sc_dev *dev = &rf->sc_dev;
 108         struct irdma_sc_ceq *sc_ceq;
 109         struct irdma_sc_cq *cq;
 110         unsigned long flags;
 111
 112         sc_ceq = &ceq->sc_ceq;
 113         do {
 114                 spin_lock_irqsave(&ceq->ce_lock, flags);
 115                 cq = irdma_sc_process_ceq(dev, sc_ceq);
 116                 if (!cq) {
 117                         spin_unlock_irqrestore(&ceq->ce_lock, flags);
 118                         break;
 119                 }
 120
 121                 if (cq->cq_type == IRDMA_CQ_TYPE_IWARP)
 122                         irdma_iwarp_ce_handler(cq);
 123
 124                 spin_unlock_irqrestore(&ceq->ce_lock, flags);
 125
 126                 if (cq->cq_type == IRDMA_CQ_TYPE_CQP)
 127                         queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work);
 128                 else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ ||
 129                          cq->cq_type == IRDMA_CQ_TYPE_IEQ)
 130                         irdma_puda_ce_handler(rf, cq);
 131         } while (1);
 132 }
 133
 134 static void irdma_set_flush_fields(struct irdma_sc_qp *qp,
 135                                    struct irdma_aeqe_info *info)
 136 {
 137         qp->sq_flush_code = info->sq;
 138         qp->rq_flush_code = info->rq;
 139         qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 140
 141         switch (info->ae_id) {
 142         case IRDMA_AE_AMP_BOUNDS_VIOLATION:
 143         case IRDMA_AE_AMP_INVALID_STAG:
 144         case IRDMA_AE_AMP_RIGHTS_VIOLATION:
 145         case IRDMA_AE_AMP_UNALLOCATED_STAG:
 146         case IRDMA_AE_AMP_BAD_PD:
 147         case IRDMA_AE_AMP_BAD_QP:
 148         case IRDMA_AE_AMP_BAD_STAG_KEY:
 149         case IRDMA_AE_AMP_BAD_STAG_INDEX:
 150         case IRDMA_AE_AMP_TO_WRAP:
 151         case IRDMA_AE_PRIV_OPERATION_DENIED:
 152                 qp->flush_code = FLUSH_PROT_ERR;
 153                 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
 154                 break;
 155         case IRDMA_AE_UDA_XMIT_BAD_PD:
 156         case IRDMA_AE_WQE_UNEXPECTED_OPCODE:
 157                 qp->flush_code = FLUSH_LOC_QP_OP_ERR;
 158                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 159                 break;
 160         case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
 161         case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT:
 162         case IRDMA_AE_UDA_L4LEN_INVALID:
 163         case IRDMA_AE_DDP_UBE_INVALID_MO:
 164         case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER:
 165                 qp->flush_code = FLUSH_LOC_LEN_ERR;
 166                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 167                 break;
 168         case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS:
 169         case IRDMA_AE_IB_REMOTE_ACCESS_ERROR:
 170                 qp->flush_code = FLUSH_REM_ACCESS_ERR;
 171                 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
 172                 break;
 173         case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
 174         case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
 175         case IRDMA_AE_ROCE_RSP_LENGTH_ERROR:
 176         case IRDMA_AE_IB_REMOTE_OP_ERROR:
 177                 qp->flush_code = FLUSH_REM_OP_ERR;
 178                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 179                 break;
 180         case IRDMA_AE_LCE_QP_CATASTROPHIC:
 181                 qp->flush_code = FLUSH_FATAL_ERR;
 182                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 183                 break;
 184         case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
 185                 qp->flush_code = FLUSH_GENERAL_ERR;
 186                 break;
 187         case IRDMA_AE_LLP_TOO_MANY_RETRIES:
 188                 qp->flush_code = FLUSH_RETRY_EXC_ERR;
 189                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 190                 break;
 191         case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS:
 192         case IRDMA_AE_AMP_MWBIND_BIND_DISABLED:
 193         case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS:
 194         case IRDMA_AE_AMP_MWBIND_VALID_STAG:
 195                 qp->flush_code = FLUSH_MW_BIND_ERR;
 196                 qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR;
 197                 break;
 198         case IRDMA_AE_IB_INVALID_REQUEST:
 199                 qp->flush_code = FLUSH_REM_INV_REQ_ERR;
 200                 qp->event_type = IRDMA_QP_EVENT_REQ_ERR;
 201                 break;
 202         default:
 203                 qp->flush_code = FLUSH_GENERAL_ERR;
 204                 qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC;
 205                 break;
 206         }
 207 }
 208
 209 /**
 210  * irdma_process_aeq - handle aeq events
 211  * @rf: RDMA PCI function
 212  */
 213 static void irdma_process_aeq(struct irdma_pci_f *rf)
 214 {
 215         struct irdma_sc_dev *dev = &rf->sc_dev;
 216         struct irdma_aeq *aeq = &rf->aeq;
 217         struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq;
 218         struct irdma_aeqe_info aeinfo;
 219         struct irdma_aeqe_info *info = &aeinfo;
 220         int ret;
 221         struct irdma_qp *iwqp = NULL;
 222         struct irdma_sc_cq *cq = NULL;
 223         struct irdma_cq *iwcq = NULL;
 224         struct irdma_sc_qp *qp = NULL;
 225         struct irdma_qp_host_ctx_info *ctx_info = NULL;
 226         struct irdma_device *iwdev = rf->iwdev;
 227         unsigned long flags;
 228
 229         u32 aeqcnt = 0;
 230
 231         if (!sc_aeq->size)
 232                 return;
 233
 234         do {
 235                 memset(info, 0, sizeof(*info));
 236                 ret = irdma_sc_get_next_aeqe(sc_aeq, info);
 237                 if (ret)
 238                         break;
 239
 240                 aeqcnt++;
 241                 ibdev_dbg(&iwdev->ibdev,
 242                           "AEQ: ae_id = 0x%x bool qp=%d qp_id = %d tcp_state=%d iwarp_state=%d ae_src=%d\n",
 243                           info->ae_id, info->qp, info->qp_cq_id, info->tcp_state,
 244                           info->iwarp_state, info->ae_src);
 245
 246                 if (info->qp) {
 247                         spin_lock_irqsave(&rf->qptable_lock, flags);
 248                         iwqp = rf->qp_table[info->qp_cq_id];
 249                         if (!iwqp) {
 250                                 spin_unlock_irqrestore(&rf->qptable_lock,
 251                                                        flags);
 252                                 if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) {
 253                                         atomic_dec(&iwdev->vsi.qp_suspend_reqs);
 254                                         wake_up(&iwdev->suspend_wq);
 255                                         continue;
 256                                 }
 257                                 ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n",
 258                                           info->qp_cq_id);
 259                                 continue;
 260                         }
 261                         irdma_qp_add_ref(&iwqp->ibqp);
 262                         spin_unlock_irqrestore(&rf->qptable_lock, flags);
 263                         qp = &iwqp->sc_qp;
 264                         spin_lock_irqsave(&iwqp->lock, flags);
 265                         iwqp->hw_tcp_state = info->tcp_state;
 266                         iwqp->hw_iwarp_state = info->iwarp_state;
 267                         if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE)
 268                                 iwqp->last_aeq = info->ae_id;
 269                         spin_unlock_irqrestore(&iwqp->lock, flags);
 270                         ctx_info = &iwqp->ctx_info;
 271                 } else {
 272                         if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR)
 273                                 continue;
 274                 }
 275
 276                 switch (info->ae_id) {
 277                         struct irdma_cm_node *cm_node;
 278                 case IRDMA_AE_LLP_CONNECTION_ESTABLISHED:
 279                         cm_node = iwqp->cm_node;
 280                         if (cm_node->accept_pend) {
 281                                 atomic_dec(&cm_node->listener->pend_accepts_cnt);
 282                                 cm_node->accept_pend = 0;
 283                         }
 284                         iwqp->rts_ae_rcvd = 1;
 285                         wake_up_interruptible(&iwqp->waitq);
 286                         break;
 287                 case IRDMA_AE_LLP_FIN_RECEIVED:
 288                 case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE:
 289                         if (qp->term_flags)
 290                                 break;
 291                         if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
 292                                 iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT;
 293                                 if (iwqp->hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT &&
 294                                     iwqp->ibqp_state == IB_QPS_RTS) {
 295                                         irdma_next_iw_state(iwqp,
 296                                                             IRDMA_QP_STATE_CLOSING,
 297                                                             0, 0, 0);
 298                                         irdma_cm_disconn(iwqp);
 299                                 }
 300                                 irdma_schedule_cm_timer(iwqp->cm_node,
 301                                                         (struct irdma_puda_buf *)iwqp,
 302                                                         IRDMA_TIMER_TYPE_CLOSE,
 303                                                         1, 0);
 304                         }
 305                         break;
 306                 case IRDMA_AE_LLP_CLOSE_COMPLETE:
 307                         if (qp->term_flags)
 308                                 irdma_terminate_done(qp, 0);
 309                         else
 310                                 irdma_cm_disconn(iwqp);
 311                         break;
 312                 case IRDMA_AE_BAD_CLOSE:
 313                 case IRDMA_AE_RESET_SENT:
 314                         irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0,
 315                                             0);
 316                         irdma_cm_disconn(iwqp);
 317                         break;
 318                 case IRDMA_AE_LLP_CONNECTION_RESET:
 319                         if (atomic_read(&iwqp->close_timer_started))
 320                                 break;
 321                         irdma_cm_disconn(iwqp);
 322                         break;
 323                 case IRDMA_AE_QP_SUSPEND_COMPLETE:
 324                         if (iwqp->iwdev->vsi.tc_change_pending) {
 325                                 atomic_dec(&iwqp->sc_qp.vsi->qp_suspend_reqs);
 326                                 wake_up(&iwqp->iwdev->suspend_wq);
 327                         }
 328                         break;
 329                 case IRDMA_AE_TERMINATE_SENT:
 330                         irdma_terminate_send_fin(qp);
 331                         break;
 332                 case IRDMA_AE_LLP_TERMINATE_RECEIVED:
 333                         irdma_terminate_received(qp, info);
 334                         break;
 335                 case IRDMA_AE_CQ_OPERATION_ERROR:
 336                         ibdev_err(&iwdev->ibdev,
 337                                   "Processing an iWARP related AE for CQ misc = 0x%04X\n",
 338                                   info->ae_id);
 339                         cq = (struct irdma_sc_cq *)(unsigned long)
 340                              info->compl_ctx;
 341
 342                         iwcq = cq->back_cq;
 343
 344                         if (iwcq->ibcq.event_handler) {
 345                                 struct ib_event ibevent;
 346
 347                                 ibevent.device = iwcq->ibcq.device;
 348                                 ibevent.event = IB_EVENT_CQ_ERR;
 349                                 ibevent.element.cq = &iwcq->ibcq;
 350                                 iwcq->ibcq.event_handler(&ibevent,
 351                                                          iwcq->ibcq.cq_context);
 352                         }
 353                         break;
 354                 case IRDMA_AE_RESET_NOT_SENT:
 355                 case IRDMA_AE_LLP_DOUBT_REACHABILITY:
 356                 case IRDMA_AE_RESOURCE_EXHAUSTION:
 357                         break;
 358                 case IRDMA_AE_PRIV_OPERATION_DENIED:
 359                 case IRDMA_AE_STAG_ZERO_INVALID:
 360                 case IRDMA_AE_IB_RREQ_AND_Q1_FULL:
 361                 case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION:
 362                 case IRDMA_AE_DDP_UBE_INVALID_MO:
 363                 case IRDMA_AE_DDP_UBE_INVALID_QN:
 364                 case IRDMA_AE_DDP_NO_L_BIT:
 365                 case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
 366                 case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
 367                 case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST:
 368                 case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
 369                 case IRDMA_AE_INVALID_ARP_ENTRY:
 370                 case IRDMA_AE_INVALID_TCP_OPTION_RCVD:
 371                 case IRDMA_AE_STALE_ARP_ENTRY:
 372                 case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR:
 373                 case IRDMA_AE_LLP_SEGMENT_TOO_SMALL:
 374                 case IRDMA_AE_LLP_SYN_RECEIVED:
 375                 case IRDMA_AE_LLP_TOO_MANY_RETRIES:
 376                 case IRDMA_AE_LCE_QP_CATASTROPHIC:
 377                 case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC:
 378                 case IRDMA_AE_LCE_CQ_CATASTROPHIC:
 379                 case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG:
 380                 default:
 381                         ibdev_err(&iwdev->ibdev, "abnormal ae_id = 0x%x bool qp=%d qp_id = %d, ae_src=%d\n",
 382                                   info->ae_id, info->qp, info->qp_cq_id, info->ae_src);
 383                         if (rdma_protocol_roce(&iwdev->ibdev, 1)) {
 384                                 ctx_info->roce_info->err_rq_idx_valid = info->rq;
 385                                 if (info->rq) {
 386                                         ctx_info->roce_info->err_rq_idx = info->wqe_idx;
 387                                         irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va,
 388                                                                 ctx_info);
 389                                 }
 390                                 irdma_set_flush_fields(qp, info);
 391                                 irdma_cm_disconn(iwqp);
 392                                 break;
 393                         }
 394                         ctx_info->iwarp_info->err_rq_idx_valid = info->rq;
 395                         if (info->rq) {
 396                                 ctx_info->iwarp_info->err_rq_idx = info->wqe_idx;
 397                                 ctx_info->tcp_info_valid = false;
 398                                 ctx_info->iwarp_info_valid = true;
 399                                 irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va,
 400                                                    ctx_info);
 401                         }
 402                         if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS &&
 403                             iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) {
 404                                 irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0);
 405                                 irdma_cm_disconn(iwqp);
 406                         } else {
 407                                 irdma_terminate_connection(qp, info);
 408                         }
 409                         break;
 410                 }
 411                 if (info->qp)
 412                         irdma_qp_rem_ref(&iwqp->ibqp);
 413         } while (1);
 414
 415         if (aeqcnt)
 416                 irdma_sc_repost_aeq_entries(dev, aeqcnt);
 417 }
 418
 419 /**
 420  * irdma_ena_intr - set up device interrupts
 421  * @dev: hardware control device structure
 422  * @msix_id: id of the interrupt to be enabled
 423  */
 424 static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id)
 425 {
 426         dev->irq_ops->irdma_en_irq(dev, msix_id);
 427 }
 428
 429 /**
 430  * irdma_dpc - tasklet for aeq and ceq 0
 431  * @t: tasklet_struct ptr
 432  */
 433 static void irdma_dpc(struct tasklet_struct *t)
 434 {
 435         struct irdma_pci_f *rf = from_tasklet(rf, t, dpc_tasklet);
 436
 437         if (rf->msix_shared)
 438                 irdma_process_ceq(rf, rf->ceqlist);
 439         irdma_process_aeq(rf);
 440         irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx);
 441 }
 442
 443 /**
 444  * irdma_ceq_dpc - dpc handler for CEQ
 445  * @t: tasklet_struct ptr
 446  */
 447 static void irdma_ceq_dpc(struct tasklet_struct *t)
 448 {
 449         struct irdma_ceq *iwceq = from_tasklet(iwceq, t, dpc_tasklet);
 450         struct irdma_pci_f *rf = iwceq->rf;
 451
 452         irdma_process_ceq(rf, iwceq);
 453         irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx);
 454 }
 455
 456 /**
 457  * irdma_save_msix_info - copy msix vector information to iwarp device
 458  * @rf: RDMA PCI function
 459  *
 460  * Allocate iwdev msix table and copy the msix info to the table
 461  * Return 0 if successful, otherwise return error
 462  */
 463 static int irdma_save_msix_info(struct irdma_pci_f *rf)
 464 {
 465         struct irdma_qvlist_info *iw_qvlist;
 466         struct irdma_qv_info *iw_qvinfo;
 467         struct msix_entry *pmsix;
 468         u32 ceq_idx;
 469         u32 i;
 470         size_t size;
 471
 472         if (!rf->msix_count)
 473                 return -EINVAL;
 474
 475         size = sizeof(struct irdma_msix_vector) * rf->msix_count;
 476         size += struct_size(iw_qvlist, qv_info, rf->msix_count);
 477         rf->iw_msixtbl = kzalloc(size, GFP_KERNEL);
 478         if (!rf->iw_msixtbl)
 479                 return -ENOMEM;
 480
 481         rf->iw_qvlist = (struct irdma_qvlist_info *)
 482                         (&rf->iw_msixtbl[rf->msix_count]);
 483         iw_qvlist = rf->iw_qvlist;
 484         iw_qvinfo = iw_qvlist->qv_info;
 485         iw_qvlist->num_vectors = rf->msix_count;
 486         if (rf->msix_count <= num_online_cpus())
 487                 rf->msix_shared = true;
 488         else if (rf->msix_count > num_online_cpus() + 1)
 489                 rf->msix_count = num_online_cpus() + 1;
 490
 491         pmsix = rf->msix_entries;
 492         for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) {
 493                 rf->iw_msixtbl[i].idx = pmsix->entry;
 494                 rf->iw_msixtbl[i].irq = pmsix->vector;
 495                 rf->iw_msixtbl[i].cpu_affinity = ceq_idx;
 496                 if (!i) {
 497                         iw_qvinfo->aeq_idx = 0;
 498                         if (rf->msix_shared)
 499                                 iw_qvinfo->ceq_idx = ceq_idx++;
 500                         else
 501                                 iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX;
 502                 } else {
 503                         iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX;
 504                         iw_qvinfo->ceq_idx = ceq_idx++;
 505                 }
 506                 iw_qvinfo->itr_idx = 3;
 507                 iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx;
 508                 pmsix++;
 509         }
 510
 511         return 0;
 512 }
 513
 514 /**
 515  * irdma_irq_handler - interrupt handler for aeq and ceq0
 516  * @irq: Interrupt request number
 517  * @data: RDMA PCI function
 518  */
 519 static irqreturn_t irdma_irq_handler(int irq, void *data)
 520 {
 521         struct irdma_pci_f *rf = data;
 522
 523         tasklet_schedule(&rf->dpc_tasklet);
 524
 525         return IRQ_HANDLED;
 526 }
 527
 528 /**
 529  * irdma_ceq_handler - interrupt handler for ceq
 530  * @irq: interrupt request number
 531  * @data: ceq pointer
 532  */
 533 static irqreturn_t irdma_ceq_handler(int irq, void *data)
 534 {
 535         struct irdma_ceq *iwceq = data;
 536
 537         if (iwceq->irq != irq)
 538                 ibdev_err(to_ibdev(&iwceq->rf->sc_dev), "expected irq = %d received irq = %d\n",
 539                           iwceq->irq, irq);
 540         tasklet_schedule(&iwceq->dpc_tasklet);
 541
 542         return IRQ_HANDLED;
 543 }
 544
 545 /**
 546  * irdma_destroy_irq - destroy device interrupts
 547  * @rf: RDMA PCI function
 548  * @msix_vec: msix vector to disable irq
 549  * @dev_id: parameter to pass to free_irq (used during irq setup)
 550  *
 551  * The function is called when destroying aeq/ceq
 552  */
 553 static void irdma_destroy_irq(struct irdma_pci_f *rf,
 554                               struct irdma_msix_vector *msix_vec, void *dev_id)
 555 {
 556         struct irdma_sc_dev *dev = &rf->sc_dev;
 557
 558         dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx);
 559         irq_update_affinity_hint(msix_vec->irq, NULL);
 560         free_irq(msix_vec->irq, dev_id);
 561 }
 562
 563 /**
 564  * irdma_destroy_cqp  - destroy control qp
 565  * @rf: RDMA PCI function
 566  * @free_hwcqp: 1 if hw cqp should be freed
 567  *
 568  * Issue destroy cqp request and
 569  * free the resources associated with the cqp
 570  */
 571 static void irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp)
 572 {
 573         struct irdma_sc_dev *dev = &rf->sc_dev;
 574         struct irdma_cqp *cqp = &rf->cqp;
 575         int status = 0;
 576
 577         if (rf->cqp_cmpl_wq)
 578                 destroy_workqueue(rf->cqp_cmpl_wq);
 579         if (free_hwcqp)
 580                 status = irdma_sc_cqp_destroy(dev->cqp);
 581         if (status)
 582                 ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status);
 583
 584         irdma_cleanup_pending_cqp_op(rf);
 585         dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va,
 586                           cqp->sq.pa);
 587         cqp->sq.va = NULL;
 588         kfree(cqp->scratch_array);
 589         cqp->scratch_array = NULL;
 590         kfree(cqp->cqp_requests);
 591         cqp->cqp_requests = NULL;
 592 }
 593
 594 static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf)
 595 {
 596         struct irdma_aeq *aeq = &rf->aeq;
 597         u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
 598         dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
 599
 600         irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt);
 601         irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
 602         vfree(aeq->mem.va);
 603 }
 604
 605 /**
 606  * irdma_destroy_aeq - destroy aeq
 607  * @rf: RDMA PCI function
 608  *
 609  * Issue a destroy aeq request and
 610  * free the resources associated with the aeq
 611  * The function is called during driver unload
 612  */
 613 static void irdma_destroy_aeq(struct irdma_pci_f *rf)
 614 {
 615         struct irdma_sc_dev *dev = &rf->sc_dev;
 616         struct irdma_aeq *aeq = &rf->aeq;
 617         int status = -EBUSY;
 618
 619         if (!rf->msix_shared) {
 620                 rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, rf->iw_msixtbl->idx, false);
 621                 irdma_destroy_irq(rf, rf->iw_msixtbl, rf);
 622         }
 623         if (rf->reset)
 624                 goto exit;
 625
 626         aeq->sc_aeq.size = 0;
 627         status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY);
 628         if (status)
 629                 ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status);
 630
 631 exit:
 632         if (aeq->virtual_map) {
 633                 irdma_destroy_virt_aeq(rf);
 634         } else {
 635                 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
 636                                   aeq->mem.pa);
 637                 aeq->mem.va = NULL;
 638         }
 639 }
 640
 641 /**
 642  * irdma_destroy_ceq - destroy ceq
 643  * @rf: RDMA PCI function
 644  * @iwceq: ceq to be destroyed
 645  *
 646  * Issue a destroy ceq request and
 647  * free the resources associated with the ceq
 648  */
 649 static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq)
 650 {
 651         struct irdma_sc_dev *dev = &rf->sc_dev;
 652         int status;
 653
 654         if (rf->reset)
 655                 goto exit;
 656
 657         status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1);
 658         if (status) {
 659                 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status);
 660                 goto exit;
 661         }
 662
 663         status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq);
 664         if (status)
 665                 ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n",
 666                           status);
 667 exit:
 668         dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va,
 669                           iwceq->mem.pa);
 670         iwceq->mem.va = NULL;
 671 }
 672
 673 /**
 674  * irdma_del_ceq_0 - destroy ceq 0
 675  * @rf: RDMA PCI function
 676  *
 677  * Disable the ceq 0 interrupt and destroy the ceq 0
 678  */
 679 static void irdma_del_ceq_0(struct irdma_pci_f *rf)
 680 {
 681         struct irdma_ceq *iwceq = rf->ceqlist;
 682         struct irdma_msix_vector *msix_vec;
 683
 684         if (rf->msix_shared) {
 685                 msix_vec = &rf->iw_msixtbl[0];
 686                 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev,
 687                                                   msix_vec->ceq_id,
 688                                                   msix_vec->idx, false);
 689                 irdma_destroy_irq(rf, msix_vec, rf);
 690         } else {
 691                 msix_vec = &rf->iw_msixtbl[1];
 692                 irdma_destroy_irq(rf, msix_vec, iwceq);
 693         }
 694
 695         irdma_destroy_ceq(rf, iwceq);
 696         rf->sc_dev.ceq_valid = false;
 697         rf->ceqs_count = 0;
 698 }
 699
 700 /**
 701  * irdma_del_ceqs - destroy all ceq's except CEQ 0
 702  * @rf: RDMA PCI function
 703  *
 704  * Go through all of the device ceq's, except 0, and for each
 705  * ceq disable the ceq interrupt and destroy the ceq
 706  */
 707 static void irdma_del_ceqs(struct irdma_pci_f *rf)
 708 {
 709         struct irdma_ceq *iwceq = &rf->ceqlist[1];
 710         struct irdma_msix_vector *msix_vec;
 711         u32 i = 0;
 712
 713         if (rf->msix_shared)
 714                 msix_vec = &rf->iw_msixtbl[1];
 715         else
 716                 msix_vec = &rf->iw_msixtbl[2];
 717
 718         for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) {
 719                 rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, msix_vec->ceq_id,
 720                                                   msix_vec->idx, false);
 721                 irdma_destroy_irq(rf, msix_vec, iwceq);
 722                 irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
 723                                   IRDMA_OP_CEQ_DESTROY);
 724                 dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size,
 725                                   iwceq->mem.va, iwceq->mem.pa);
 726                 iwceq->mem.va = NULL;
 727         }
 728         rf->ceqs_count = 1;
 729 }
 730
 731 /**
 732  * irdma_destroy_ccq - destroy control cq
 733  * @rf: RDMA PCI function
 734  *
 735  * Issue destroy ccq request and
 736  * free the resources associated with the ccq
 737  */
 738 static void irdma_destroy_ccq(struct irdma_pci_f *rf)
 739 {
 740         struct irdma_sc_dev *dev = &rf->sc_dev;
 741         struct irdma_ccq *ccq = &rf->ccq;
 742         int status = 0;
 743
 744         if (!rf->reset)
 745                 status = irdma_sc_ccq_destroy(dev->ccq, 0, true);
 746         if (status)
 747                 ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status);
 748         dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va,
 749                           ccq->mem_cq.pa);
 750         ccq->mem_cq.va = NULL;
 751 }
 752
 753 /**
 754  * irdma_close_hmc_objects_type - delete hmc objects of a given type
 755  * @dev: iwarp device
 756  * @obj_type: the hmc object type to be deleted
 757  * @hmc_info: host memory info struct
 758  * @privileged: permission to close HMC objects
 759  * @reset: true if called before reset
 760  */
 761 static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev,
 762                                          enum irdma_hmc_rsrc_type obj_type,
 763                                          struct irdma_hmc_info *hmc_info,
 764                                          bool privileged, bool reset)
 765 {
 766         struct irdma_hmc_del_obj_info info = {};
 767
 768         info.hmc_info = hmc_info;
 769         info.rsrc_type = obj_type;
 770         info.count = hmc_info->hmc_obj[obj_type].cnt;
 771         info.privileged = privileged;
 772         if (irdma_sc_del_hmc_obj(dev, &info, reset))
 773                 ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n",
 774                           obj_type);
 775 }
 776
 777 /**
 778  * irdma_del_hmc_objects - remove all device hmc objects
 779  * @dev: iwarp device
 780  * @hmc_info: hmc_info to free
 781  * @privileged: permission to delete HMC objects
 782  * @reset: true if called before reset
 783  * @vers: hardware version
 784  */
 785 static void irdma_del_hmc_objects(struct irdma_sc_dev *dev,
 786                                   struct irdma_hmc_info *hmc_info, bool privileged,
 787                                   bool reset, enum irdma_vers vers)
 788 {
 789         unsigned int i;
 790
 791         for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
 792                 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
 793                         irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
 794                                                      hmc_info, privileged, reset);
 795                 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
 796                         break;
 797         }
 798 }
 799
 800 /**
 801  * irdma_create_hmc_obj_type - create hmc object of a given type
 802  * @dev: hardware control device structure
 803  * @info: information for the hmc object to create
 804  */
 805 static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev,
 806                                      struct irdma_hmc_create_obj_info *info)
 807 {
 808         return irdma_sc_create_hmc_obj(dev, info);
 809 }
 810
 811 /**
 812  * irdma_create_hmc_objs - create all hmc objects for the device
 813  * @rf: RDMA PCI function
 814  * @privileged: permission to create HMC objects
 815  * @vers: HW version
 816  *
 817  * Create the device hmc objects and allocate hmc pages
 818  * Return 0 if successful, otherwise clean up and return error
 819  */
 820 static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged,
 821                                  enum irdma_vers vers)
 822 {
 823         struct irdma_sc_dev *dev = &rf->sc_dev;
 824         struct irdma_hmc_create_obj_info info = {};
 825         int i, status = 0;
 826
 827         info.hmc_info = dev->hmc_info;
 828         info.privileged = privileged;
 829         info.entry_type = rf->sd_type;
 830
 831         for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
 832                 if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE)
 833                         continue;
 834                 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) {
 835                         info.rsrc_type = iw_hmc_obj_types[i];
 836                         info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt;
 837                         info.add_sd_cnt = 0;
 838                         status = irdma_create_hmc_obj_type(dev, &info);
 839                         if (status) {
 840                                 ibdev_dbg(to_ibdev(dev),
 841                                           "ERR: create obj type %d status = %d\n",
 842                                           iw_hmc_obj_types[i], status);
 843                                 break;
 844                         }
 845                 }
 846                 if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER)
 847                         break;
 848         }
 849
 850         if (!status)
 851                 return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id,
 852                                                            true, true);
 853
 854         while (i) {
 855                 i--;
 856                 /* destroy the hmc objects of a given type */
 857                 if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt)
 858                         irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i],
 859                                                      dev->hmc_info, privileged,
 860                                                      false);
 861         }
 862
 863         return status;
 864 }
 865
 866 /**
 867  * irdma_obj_aligned_mem - get aligned memory from device allocated memory
 868  * @rf: RDMA PCI function
 869  * @memptr: points to the memory addresses
 870  * @size: size of memory needed
 871  * @mask: mask for the aligned memory
 872  *
 873  * Get aligned memory of the requested size and
 874  * update the memptr to point to the new aligned memory
 875  * Return 0 if successful, otherwise return no memory error
 876  */
 877 static int irdma_obj_aligned_mem(struct irdma_pci_f *rf,
 878                                  struct irdma_dma_mem *memptr, u32 size,
 879                                  u32 mask)
 880 {
 881         unsigned long va, newva;
 882         unsigned long extra;
 883
 884         va = (unsigned long)rf->obj_next.va;
 885         newva = va;
 886         if (mask)
 887                 newva = ALIGN(va, (unsigned long)mask + 1ULL);
 888         extra = newva - va;
 889         memptr->va = (u8 *)va + extra;
 890         memptr->pa = rf->obj_next.pa + extra;
 891         memptr->size = size;
 892         if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size))
 893                 return -ENOMEM;
 894
 895         rf->obj_next.va = (u8 *)memptr->va + size;
 896         rf->obj_next.pa = memptr->pa + size;
 897
 898         return 0;
 899 }
 900
 901 /**
 902  * irdma_create_cqp - create control qp
 903  * @rf: RDMA PCI function
 904  *
 905  * Return 0, if the cqp and all the resources associated with it
 906  * are successfully created, otherwise return error
 907  */
 908 static int irdma_create_cqp(struct irdma_pci_f *rf)
 909 {
 910         u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048;
 911         struct irdma_dma_mem mem;
 912         struct irdma_sc_dev *dev = &rf->sc_dev;
 913         struct irdma_cqp_init_info cqp_init_info = {};
 914         struct irdma_cqp *cqp = &rf->cqp;
 915         u16 maj_err, min_err;
 916         int i, status;
 917
 918         cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL);
 919         if (!cqp->cqp_requests)
 920                 return -ENOMEM;
 921
 922         cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL);
 923         if (!cqp->scratch_array) {
 924                 kfree(cqp->cqp_requests);
 925                 return -ENOMEM;
 926         }
 927
 928         dev->cqp = &cqp->sc_cqp;
 929         dev->cqp->dev = dev;
 930         cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize,
 931                              IRDMA_CQP_ALIGNMENT);
 932         cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size,
 933                                         &cqp->sq.pa, GFP_KERNEL);
 934         if (!cqp->sq.va) {
 935                 kfree(cqp->scratch_array);
 936                 kfree(cqp->cqp_requests);
 937                 return -ENOMEM;
 938         }
 939
 940         status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx),
 941                                        IRDMA_HOST_CTX_ALIGNMENT_M);
 942         if (status)
 943                 goto exit;
 944
 945         dev->cqp->host_ctx_pa = mem.pa;
 946         dev->cqp->host_ctx = mem.va;
 947         /* populate the cqp init info */
 948         cqp_init_info.dev = dev;
 949         cqp_init_info.sq_size = sqsize;
 950         cqp_init_info.sq = cqp->sq.va;
 951         cqp_init_info.sq_pa = cqp->sq.pa;
 952         cqp_init_info.host_ctx_pa = mem.pa;
 953         cqp_init_info.host_ctx = mem.va;
 954         cqp_init_info.hmc_profile = rf->rsrc_profile;
 955         cqp_init_info.scratch_array = cqp->scratch_array;
 956         cqp_init_info.protocol_used = rf->protocol_used;
 957
 958         switch (rf->rdma_ver) {
 959         case IRDMA_GEN_1:
 960                 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1;
 961                 break;
 962         case IRDMA_GEN_2:
 963                 cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2;
 964                 break;
 965         }
 966         status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info);
 967         if (status) {
 968                 ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status);
 969                 goto exit;
 970         }
 971
 972         spin_lock_init(&cqp->req_lock);
 973         spin_lock_init(&cqp->compl_lock);
 974
 975         status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err);
 976         if (status) {
 977                 ibdev_dbg(to_ibdev(dev),
 978                           "ERR: cqp create failed - status %d maj_err %d min_err %d\n",
 979                           status, maj_err, min_err);
 980                 goto exit;
 981         }
 982
 983         INIT_LIST_HEAD(&cqp->cqp_avail_reqs);
 984         INIT_LIST_HEAD(&cqp->cqp_pending_reqs);
 985
 986         /* init the waitqueue of the cqp_requests and add them to the list */
 987         for (i = 0; i < sqsize; i++) {
 988                 init_waitqueue_head(&cqp->cqp_requests[i].waitq);
 989                 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs);
 990         }
 991         init_waitqueue_head(&cqp->remove_wq);
 992         return 0;
 993
 994 exit:
 995         irdma_destroy_cqp(rf, false);
 996
 997         return status;
 998 }
 999
1000 /**
1001  * irdma_create_ccq - create control cq
1002  * @rf: RDMA PCI function
1003  *
1004  * Return 0, if the ccq and the resources associated with it
1005  * are successfully created, otherwise return error
1006  */
1007 static int irdma_create_ccq(struct irdma_pci_f *rf)
1008 {
1009         struct irdma_sc_dev *dev = &rf->sc_dev;
1010         struct irdma_ccq_init_info info = {};
1011         struct irdma_ccq *ccq = &rf->ccq;
1012         int status;
1013
1014         dev->ccq = &ccq->sc_cq;
1015         dev->ccq->dev = dev;
1016         info.dev = dev;
1017         ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area);
1018         ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE,
1019                                  IRDMA_CQ0_ALIGNMENT);
1020         ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size,
1021                                             &ccq->mem_cq.pa, GFP_KERNEL);
1022         if (!ccq->mem_cq.va)
1023                 return -ENOMEM;
1024
1025         status = irdma_obj_aligned_mem(rf, &ccq->shadow_area,
1026                                        ccq->shadow_area.size,
1027                                        IRDMA_SHADOWAREA_M);
1028         if (status)
1029                 goto exit;
1030
1031         ccq->sc_cq.back_cq = ccq;
1032         /* populate the ccq init info */
1033         info.cq_base = ccq->mem_cq.va;
1034         info.cq_pa = ccq->mem_cq.pa;
1035         info.num_elem = IW_CCQ_SIZE;
1036         info.shadow_area = ccq->shadow_area.va;
1037         info.shadow_area_pa = ccq->shadow_area.pa;
1038         info.ceqe_mask = false;
1039         info.ceq_id_valid = true;
1040         info.shadow_read_threshold = 16;
1041         info.vsi = &rf->default_vsi;
1042         status = irdma_sc_ccq_init(dev->ccq, &info);
1043         if (!status)
1044                 status = irdma_sc_ccq_create(dev->ccq, 0, true, true);
1045 exit:
1046         if (status) {
1047                 dma_free_coherent(dev->hw->device, ccq->mem_cq.size,
1048                                   ccq->mem_cq.va, ccq->mem_cq.pa);
1049                 ccq->mem_cq.va = NULL;
1050         }
1051
1052         return status;
1053 }
1054
1055 /**
1056  * irdma_alloc_set_mac - set up a mac address table entry
1057  * @iwdev: irdma device
1058  *
1059  * Allocate a mac ip entry and add it to the hw table Return 0
1060  * if successful, otherwise return error
1061  */
1062 static int irdma_alloc_set_mac(struct irdma_device *iwdev)
1063 {
1064         int status;
1065
1066         status = irdma_alloc_local_mac_entry(iwdev->rf,
1067                                              &iwdev->mac_ip_table_idx);
1068         if (!status) {
1069                 status = irdma_add_local_mac_entry(iwdev->rf,
1070                                                    (const u8 *)iwdev->netdev->dev_addr,
1071                                                    (u8)iwdev->mac_ip_table_idx);
1072                 if (status)
1073                         irdma_del_local_mac_entry(iwdev->rf,
1074                                                   (u8)iwdev->mac_ip_table_idx);
1075         }
1076         return status;
1077 }
1078
1079 /**
1080  * irdma_cfg_ceq_vector - set up the msix interrupt vector for
1081  * ceq
1082  * @rf: RDMA PCI function
1083  * @iwceq: ceq associated with the vector
1084  * @ceq_id: the id number of the iwceq
1085  * @msix_vec: interrupt vector information
1086  *
1087  * Allocate interrupt resources and enable irq handling
1088  * Return 0 if successful, otherwise return error
1089  */
1090 static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1091                                 u32 ceq_id, struct irdma_msix_vector *msix_vec)
1092 {
1093         int status;
1094
1095         if (rf->msix_shared && !ceq_id) {
1096                 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1097                          "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev));
1098                 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1099                 status = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1100                                      msix_vec->name, rf);
1101         } else {
1102                 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1103                          "irdma-%s-CEQ-%d",
1104                          dev_name(&rf->pcidev->dev), ceq_id);
1105                 tasklet_setup(&iwceq->dpc_tasklet, irdma_ceq_dpc);
1106
1107                 status = request_irq(msix_vec->irq, irdma_ceq_handler, 0,
1108                                      msix_vec->name, iwceq);
1109         }
1110         cpumask_clear(&msix_vec->mask);
1111         cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask);
1112         irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask);
1113         if (status) {
1114                 ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n");
1115                 return status;
1116         }
1117
1118         msix_vec->ceq_id = ceq_id;
1119         rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, msix_vec->idx, true);
1120
1121         return 0;
1122 }
1123
1124 /**
1125  * irdma_cfg_aeq_vector - set up the msix vector for aeq
1126  * @rf: RDMA PCI function
1127  *
1128  * Allocate interrupt resources and enable irq handling
1129  * Return 0 if successful, otherwise return error
1130  */
1131 static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf)
1132 {
1133         struct irdma_msix_vector *msix_vec = rf->iw_msixtbl;
1134         u32 ret = 0;
1135
1136         if (!rf->msix_shared) {
1137                 snprintf(msix_vec->name, sizeof(msix_vec->name) - 1,
1138                          "irdma-%s-AEQ", dev_name(&rf->pcidev->dev));
1139                 tasklet_setup(&rf->dpc_tasklet, irdma_dpc);
1140                 ret = request_irq(msix_vec->irq, irdma_irq_handler, 0,
1141                                   msix_vec->name, rf);
1142         }
1143         if (ret) {
1144                 ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n");
1145                 return -EINVAL;
1146         }
1147
1148         rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, true);
1149
1150         return 0;
1151 }
1152
1153 /**
1154  * irdma_create_ceq - create completion event queue
1155  * @rf: RDMA PCI function
1156  * @iwceq: pointer to the ceq resources to be created
1157  * @ceq_id: the id number of the iwceq
1158  * @vsi: SC vsi struct
1159  *
1160  * Return 0, if the ceq and the resources associated with it
1161  * are successfully created, otherwise return error
1162  */
1163 static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq,
1164                             u32 ceq_id, struct irdma_sc_vsi *vsi)
1165 {
1166         int status;
1167         struct irdma_ceq_init_info info = {};
1168         struct irdma_sc_dev *dev = &rf->sc_dev;
1169         u64 scratch;
1170         u32 ceq_size;
1171
1172         info.ceq_id = ceq_id;
1173         iwceq->rf = rf;
1174         ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt,
1175                        dev->hw_attrs.max_hw_ceq_size);
1176         iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size,
1177                                 IRDMA_CEQ_ALIGNMENT);
1178         iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size,
1179                                            &iwceq->mem.pa, GFP_KERNEL);
1180         if (!iwceq->mem.va)
1181                 return -ENOMEM;
1182
1183         info.ceq_id = ceq_id;
1184         info.ceqe_base = iwceq->mem.va;
1185         info.ceqe_pa = iwceq->mem.pa;
1186         info.elem_cnt = ceq_size;
1187         iwceq->sc_ceq.ceq_id = ceq_id;
1188         info.dev = dev;
1189         info.vsi = vsi;
1190         scratch = (uintptr_t)&rf->cqp.sc_cqp;
1191         status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info);
1192         if (!status) {
1193                 if (dev->ceq_valid)
1194                         status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq,
1195                                                    IRDMA_OP_CEQ_CREATE);
1196                 else
1197                         status = irdma_sc_cceq_create(&iwceq->sc_ceq, scratch);
1198         }
1199
1200         if (status) {
1201                 dma_free_coherent(dev->hw->device, iwceq->mem.size,
1202                                   iwceq->mem.va, iwceq->mem.pa);
1203                 iwceq->mem.va = NULL;
1204         }
1205
1206         return status;
1207 }
1208
1209 /**
1210  * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource
1211  * @rf: RDMA PCI function
1212  *
1213  * Allocate a list for all device completion event queues
1214  * Create the ceq 0 and configure it's msix interrupt vector
1215  * Return 0, if successfully set up, otherwise return error
1216  */
1217 static int irdma_setup_ceq_0(struct irdma_pci_f *rf)
1218 {
1219         struct irdma_ceq *iwceq;
1220         struct irdma_msix_vector *msix_vec;
1221         u32 i;
1222         int status = 0;
1223         u32 num_ceqs;
1224
1225         num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1226         rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL);
1227         if (!rf->ceqlist) {
1228                 status = -ENOMEM;
1229                 goto exit;
1230         }
1231
1232         iwceq = &rf->ceqlist[0];
1233         status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi);
1234         if (status) {
1235                 ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n",
1236                           status);
1237                 goto exit;
1238         }
1239
1240         spin_lock_init(&iwceq->ce_lock);
1241         i = rf->msix_shared ? 0 : 1;
1242         msix_vec = &rf->iw_msixtbl[i];
1243         iwceq->irq = msix_vec->irq;
1244         iwceq->msix_idx = msix_vec->idx;
1245         status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec);
1246         if (status) {
1247                 irdma_destroy_ceq(rf, iwceq);
1248                 goto exit;
1249         }
1250
1251         irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1252         rf->ceqs_count++;
1253
1254 exit:
1255         if (status && !rf->ceqs_count) {
1256                 kfree(rf->ceqlist);
1257                 rf->ceqlist = NULL;
1258                 return status;
1259         }
1260         rf->sc_dev.ceq_valid = true;
1261
1262         return 0;
1263 }
1264
1265 /**
1266  * irdma_setup_ceqs - manage the device ceq's and their interrupt resources
1267  * @rf: RDMA PCI function
1268  * @vsi: VSI structure for this CEQ
1269  *
1270  * Allocate a list for all device completion event queues
1271  * Create the ceq's and configure their msix interrupt vectors
1272  * Return 0, if ceqs are successfully set up, otherwise return error
1273  */
1274 static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi)
1275 {
1276         u32 i;
1277         u32 ceq_id;
1278         struct irdma_ceq *iwceq;
1279         struct irdma_msix_vector *msix_vec;
1280         int status;
1281         u32 num_ceqs;
1282
1283         num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs);
1284         i = (rf->msix_shared) ? 1 : 2;
1285         for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) {
1286                 iwceq = &rf->ceqlist[ceq_id];
1287                 status = irdma_create_ceq(rf, iwceq, ceq_id, vsi);
1288                 if (status) {
1289                         ibdev_dbg(&rf->iwdev->ibdev,
1290                                   "ERR: create ceq status = %d\n", status);
1291                         goto del_ceqs;
1292                 }
1293                 spin_lock_init(&iwceq->ce_lock);
1294                 msix_vec = &rf->iw_msixtbl[i];
1295                 iwceq->irq = msix_vec->irq;
1296                 iwceq->msix_idx = msix_vec->idx;
1297                 status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec);
1298                 if (status) {
1299                         irdma_destroy_ceq(rf, iwceq);
1300                         goto del_ceqs;
1301                 }
1302                 irdma_ena_intr(&rf->sc_dev, msix_vec->idx);
1303                 rf->ceqs_count++;
1304         }
1305
1306         return 0;
1307
1308 del_ceqs:
1309         irdma_del_ceqs(rf);
1310
1311         return status;
1312 }
1313
1314 static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size)
1315 {
1316         struct irdma_aeq *aeq = &rf->aeq;
1317         dma_addr_t *pg_arr;
1318         u32 pg_cnt;
1319         int status;
1320
1321         if (rf->rdma_ver < IRDMA_GEN_2)
1322                 return -EOPNOTSUPP;
1323
1324         aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size;
1325         aeq->mem.va = vzalloc(aeq->mem.size);
1326
1327         if (!aeq->mem.va)
1328                 return -ENOMEM;
1329
1330         pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE);
1331         status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true);
1332         if (status) {
1333                 vfree(aeq->mem.va);
1334                 return status;
1335         }
1336
1337         pg_arr = (dma_addr_t *)aeq->palloc.level1.addr;
1338         status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt);
1339         if (status) {
1340                 irdma_free_pble(rf->pble_rsrc, &aeq->palloc);
1341                 vfree(aeq->mem.va);
1342                 return status;
1343         }
1344
1345         return 0;
1346 }
1347
1348 /**
1349  * irdma_create_aeq - create async event queue
1350  * @rf: RDMA PCI function
1351  *
1352  * Return 0, if the aeq and the resources associated with it
1353  * are successfully created, otherwise return error
1354  */
1355 static int irdma_create_aeq(struct irdma_pci_f *rf)
1356 {
1357         struct irdma_aeq_init_info info = {};
1358         struct irdma_sc_dev *dev = &rf->sc_dev;
1359         struct irdma_aeq *aeq = &rf->aeq;
1360         struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info;
1361         u32 aeq_size;
1362         u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1;
1363         int status;
1364
1365         aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt +
1366                    hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
1367         aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size);
1368
1369         aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size,
1370                               IRDMA_AEQ_ALIGNMENT);
1371         aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size,
1372                                          &aeq->mem.pa,
1373                                          GFP_KERNEL | __GFP_NOWARN);
1374         if (aeq->mem.va)
1375                 goto skip_virt_aeq;
1376
1377         /* physically mapped aeq failed. setup virtual aeq */
1378         status = irdma_create_virt_aeq(rf, aeq_size);
1379         if (status)
1380                 return status;
1381
1382         info.virtual_map = true;
1383         aeq->virtual_map = info.virtual_map;
1384         info.pbl_chunk_size = 1;
1385         info.first_pm_pbl_idx = aeq->palloc.level1.idx;
1386
1387 skip_virt_aeq:
1388         info.aeqe_base = aeq->mem.va;
1389         info.aeq_elem_pa = aeq->mem.pa;
1390         info.elem_cnt = aeq_size;
1391         info.dev = dev;
1392         info.msix_idx = rf->iw_msixtbl->idx;
1393         status = irdma_sc_aeq_init(&aeq->sc_aeq, &info);
1394         if (status)
1395                 goto err;
1396
1397         status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE);
1398         if (status)
1399                 goto err;
1400
1401         return 0;
1402
1403 err:
1404         if (aeq->virtual_map) {
1405                 irdma_destroy_virt_aeq(rf);
1406         } else {
1407                 dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va,
1408                                   aeq->mem.pa);
1409                 aeq->mem.va = NULL;
1410         }
1411
1412         return status;
1413 }
1414
1415 /**
1416  * irdma_setup_aeq - set up the device aeq
1417  * @rf: RDMA PCI function
1418  *
1419  * Create the aeq and configure its msix interrupt vector
1420  * Return 0 if successful, otherwise return error
1421  */
1422 static int irdma_setup_aeq(struct irdma_pci_f *rf)
1423 {
1424         struct irdma_sc_dev *dev = &rf->sc_dev;
1425         int status;
1426
1427         status = irdma_create_aeq(rf);
1428         if (status)
1429                 return status;
1430
1431         status = irdma_cfg_aeq_vector(rf);
1432         if (status) {
1433                 irdma_destroy_aeq(rf);
1434                 return status;
1435         }
1436
1437         if (!rf->msix_shared)
1438                 irdma_ena_intr(dev, rf->iw_msixtbl[0].idx);
1439
1440         return 0;
1441 }
1442
1443 /**
1444  * irdma_initialize_ilq - create iwarp local queue for cm
1445  * @iwdev: irdma device
1446  *
1447  * Return 0 if successful, otherwise return error
1448  */
1449 static int irdma_initialize_ilq(struct irdma_device *iwdev)
1450 {
1451         struct irdma_puda_rsrc_info info = {};
1452         int status;
1453
1454         info.type = IRDMA_PUDA_RSRC_TYPE_ILQ;
1455         info.cq_id = 1;
1456         info.qp_id = 1;
1457         info.count = 1;
1458         info.pd_id = 1;
1459         info.abi_ver = IRDMA_ABI_VER;
1460         info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1461         info.rq_size = info.sq_size;
1462         info.buf_size = 1024;
1463         info.tx_buf_cnt = 2 * info.sq_size;
1464         info.receive = irdma_receive_ilq;
1465         info.xmit_complete = irdma_free_sqbuf;
1466         status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1467         if (status)
1468                 ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n");
1469
1470         return status;
1471 }
1472
1473 /**
1474  * irdma_initialize_ieq - create iwarp exception queue
1475  * @iwdev: irdma device
1476  *
1477  * Return 0 if successful, otherwise return error
1478  */
1479 static int irdma_initialize_ieq(struct irdma_device *iwdev)
1480 {
1481         struct irdma_puda_rsrc_info info = {};
1482         int status;
1483
1484         info.type = IRDMA_PUDA_RSRC_TYPE_IEQ;
1485         info.cq_id = 2;
1486         info.qp_id = iwdev->vsi.exception_lan_q;
1487         info.count = 1;
1488         info.pd_id = 2;
1489         info.abi_ver = IRDMA_ABI_VER;
1490         info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768);
1491         info.rq_size = info.sq_size;
1492         info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD;
1493         info.tx_buf_cnt = 4096;
1494         status = irdma_puda_create_rsrc(&iwdev->vsi, &info);
1495         if (status)
1496                 ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n");
1497
1498         return status;
1499 }
1500
1501 /**
1502  * irdma_reinitialize_ieq - destroy and re-create ieq
1503  * @vsi: VSI structure
1504  */
1505 void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi)
1506 {
1507         struct irdma_device *iwdev = vsi->back_vsi;
1508         struct irdma_pci_f *rf = iwdev->rf;
1509
1510         irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false);
1511         if (irdma_initialize_ieq(iwdev)) {
1512                 iwdev->rf->reset = true;
1513                 rf->gen_ops.request_reset(rf);
1514         }
1515 }
1516
1517 /**
1518  * irdma_hmc_setup - create hmc objects for the device
1519  * @rf: RDMA PCI function
1520  *
1521  * Set up the device private memory space for the number and size of
1522  * the hmc objects and create the objects
1523  * Return 0 if successful, otherwise return error
1524  */
1525 static int irdma_hmc_setup(struct irdma_pci_f *rf)
1526 {
1527         int status;
1528         u32 qpcnt;
1529
1530         qpcnt = rsrc_limits_table[rf->limits_sel].qplimit;
1531
1532         rf->sd_type = IRDMA_SD_TYPE_DIRECT;
1533         status = irdma_cfg_fpm_val(&rf->sc_dev, qpcnt);
1534         if (status)
1535                 return status;
1536
1537         status = irdma_create_hmc_objs(rf, true, rf->rdma_ver);
1538
1539         return status;
1540 }
1541
1542 /**
1543  * irdma_del_init_mem - deallocate memory resources
1544  * @rf: RDMA PCI function
1545  */
1546 static void irdma_del_init_mem(struct irdma_pci_f *rf)
1547 {
1548         struct irdma_sc_dev *dev = &rf->sc_dev;
1549
1550         kfree(dev->hmc_info->sd_table.sd_entry);
1551         dev->hmc_info->sd_table.sd_entry = NULL;
1552         kfree(rf->mem_rsrc);
1553         rf->mem_rsrc = NULL;
1554         dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1555                           rf->obj_mem.pa);
1556         rf->obj_mem.va = NULL;
1557         if (rf->rdma_ver != IRDMA_GEN_1) {
1558                 bitmap_free(rf->allocated_ws_nodes);
1559                 rf->allocated_ws_nodes = NULL;
1560         }
1561         kfree(rf->ceqlist);
1562         rf->ceqlist = NULL;
1563         kfree(rf->iw_msixtbl);
1564         rf->iw_msixtbl = NULL;
1565         kfree(rf->hmc_info_mem);
1566         rf->hmc_info_mem = NULL;
1567 }
1568
1569 /**
1570  * irdma_initialize_dev - initialize device
1571  * @rf: RDMA PCI function
1572  *
1573  * Allocate memory for the hmc objects and initialize iwdev
1574  * Return 0 if successful, otherwise clean up the resources
1575  * and return error
1576  */
1577 static int irdma_initialize_dev(struct irdma_pci_f *rf)
1578 {
1579         int status;
1580         struct irdma_sc_dev *dev = &rf->sc_dev;
1581         struct irdma_device_init_info info = {};
1582         struct irdma_dma_mem mem;
1583         u32 size;
1584
1585         size = sizeof(struct irdma_hmc_pble_rsrc) +
1586                sizeof(struct irdma_hmc_info) +
1587                (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX);
1588
1589         rf->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1590         if (!rf->hmc_info_mem)
1591                 return -ENOMEM;
1592
1593         rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem;
1594         dev->hmc_info = &rf->hw.hmc;
1595         dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *)
1596                                  (rf->pble_rsrc + 1);
1597
1598         status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE,
1599                                        IRDMA_FPM_QUERY_BUF_ALIGNMENT_M);
1600         if (status)
1601                 goto error;
1602
1603         info.fpm_query_buf_pa = mem.pa;
1604         info.fpm_query_buf = mem.va;
1605
1606         status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE,
1607                                        IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M);
1608         if (status)
1609                 goto error;
1610
1611         info.fpm_commit_buf_pa = mem.pa;
1612         info.fpm_commit_buf = mem.va;
1613
1614         info.bar0 = rf->hw.hw_addr;
1615         info.hmc_fn_id = rf->pf_id;
1616         info.hw = &rf->hw;
1617         status = irdma_sc_dev_init(rf->rdma_ver, &rf->sc_dev, &info);
1618         if (status)
1619                 goto error;
1620
1621         return status;
1622 error:
1623         kfree(rf->hmc_info_mem);
1624         rf->hmc_info_mem = NULL;
1625
1626         return status;
1627 }
1628
1629 /**
1630  * irdma_rt_deinit_hw - clean up the irdma device resources
1631  * @iwdev: irdma device
1632  *
1633  * remove the mac ip entry and ipv4/ipv6 addresses, destroy the
1634  * device queues and free the pble and the hmc objects
1635  */
1636 void irdma_rt_deinit_hw(struct irdma_device *iwdev)
1637 {
1638         ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state);
1639
1640         switch (iwdev->init_state) {
1641         case IP_ADDR_REGISTERED:
1642                 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1643                         irdma_del_local_mac_entry(iwdev->rf,
1644                                                   (u8)iwdev->mac_ip_table_idx);
1645                 fallthrough;
1646         case AEQ_CREATED:
1647         case PBLE_CHUNK_MEM:
1648         case CEQS_CREATED:
1649         case IEQ_CREATED:
1650                 if (!iwdev->roce_mode)
1651                         irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ,
1652                                              iwdev->rf->reset);
1653                 fallthrough;
1654         case ILQ_CREATED:
1655                 if (!iwdev->roce_mode)
1656                         irdma_puda_dele_rsrc(&iwdev->vsi,
1657                                              IRDMA_PUDA_RSRC_TYPE_ILQ,
1658                                              iwdev->rf->reset);
1659                 break;
1660         default:
1661                 ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state);
1662                 break;
1663         }
1664
1665         irdma_cleanup_cm_core(&iwdev->cm_core);
1666         if (iwdev->vsi.pestat) {
1667                 irdma_vsi_stats_free(&iwdev->vsi);
1668                 kfree(iwdev->vsi.pestat);
1669         }
1670         if (iwdev->cleanup_wq)
1671                 destroy_workqueue(iwdev->cleanup_wq);
1672 }
1673
1674 static int irdma_setup_init_state(struct irdma_pci_f *rf)
1675 {
1676         int status;
1677
1678         status = irdma_save_msix_info(rf);
1679         if (status)
1680                 return status;
1681
1682         rf->hw.device = &rf->pcidev->dev;
1683         rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE);
1684         rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size,
1685                                             &rf->obj_mem.pa, GFP_KERNEL);
1686         if (!rf->obj_mem.va) {
1687                 status = -ENOMEM;
1688                 goto clean_msixtbl;
1689         }
1690
1691         rf->obj_next = rf->obj_mem;
1692         status = irdma_initialize_dev(rf);
1693         if (status)
1694                 goto clean_obj_mem;
1695
1696         return 0;
1697
1698 clean_obj_mem:
1699         dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va,
1700                           rf->obj_mem.pa);
1701         rf->obj_mem.va = NULL;
1702 clean_msixtbl:
1703         kfree(rf->iw_msixtbl);
1704         rf->iw_msixtbl = NULL;
1705         return status;
1706 }
1707
1708 /**
1709  * irdma_get_used_rsrc - determine resources used internally
1710  * @iwdev: irdma device
1711  *
1712  * Called at the end of open to get all internal allocations
1713  */
1714 static void irdma_get_used_rsrc(struct irdma_device *iwdev)
1715 {
1716         iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds,
1717                                                  iwdev->rf->max_pd);
1718         iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps,
1719                                                  iwdev->rf->max_qp);
1720         iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs,
1721                                                  iwdev->rf->max_cq);
1722         iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs,
1723                                                  iwdev->rf->max_mr);
1724 }
1725
1726 void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf)
1727 {
1728         enum init_completion_state state = rf->init_state;
1729
1730         rf->init_state = INVALID_STATE;
1731         if (rf->rsrc_created) {
1732                 irdma_destroy_aeq(rf);
1733                 irdma_destroy_pble_prm(rf->pble_rsrc);
1734                 irdma_del_ceqs(rf);
1735                 rf->rsrc_created = false;
1736         }
1737         switch (state) {
1738         case CEQ0_CREATED:
1739                 irdma_del_ceq_0(rf);
1740                 fallthrough;
1741         case CCQ_CREATED:
1742                 irdma_destroy_ccq(rf);
1743                 fallthrough;
1744         case HW_RSRC_INITIALIZED:
1745         case HMC_OBJS_CREATED:
1746                 irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true,
1747                                       rf->reset, rf->rdma_ver);
1748                 fallthrough;
1749         case CQP_CREATED:
1750                 irdma_destroy_cqp(rf, true);
1751                 fallthrough;
1752         case INITIAL_STATE:
1753                 irdma_del_init_mem(rf);
1754                 break;
1755         case INVALID_STATE:
1756         default:
1757                 ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state);
1758                 break;
1759         }
1760 }
1761
1762 /**
1763  * irdma_rt_init_hw - Initializes runtime portion of HW
1764  * @iwdev: irdma device
1765  * @l2params: qos, tc, mtu info from netdev driver
1766  *
1767  * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma
1768  * device resource objects.
1769  */
1770 int irdma_rt_init_hw(struct irdma_device *iwdev,
1771                      struct irdma_l2params *l2params)
1772 {
1773         struct irdma_pci_f *rf = iwdev->rf;
1774         struct irdma_sc_dev *dev = &rf->sc_dev;
1775         struct irdma_vsi_init_info vsi_info = {};
1776         struct irdma_vsi_stats_info stats_info = {};
1777         int status;
1778
1779         vsi_info.dev = dev;
1780         vsi_info.back_vsi = iwdev;
1781         vsi_info.params = l2params;
1782         vsi_info.pf_data_vsi_num = iwdev->vsi_num;
1783         vsi_info.register_qset = rf->gen_ops.register_qset;
1784         vsi_info.unregister_qset = rf->gen_ops.unregister_qset;
1785         vsi_info.exception_lan_q = 2;
1786         irdma_sc_vsi_init(&iwdev->vsi, &vsi_info);
1787
1788         status = irdma_setup_cm_core(iwdev, rf->rdma_ver);
1789         if (status)
1790                 return status;
1791
1792         stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1793         if (!stats_info.pestat) {
1794                 irdma_cleanup_cm_core(&iwdev->cm_core);
1795                 return -ENOMEM;
1796         }
1797         stats_info.fcn_id = dev->hmc_fn_id;
1798         status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info);
1799         if (status) {
1800                 irdma_cleanup_cm_core(&iwdev->cm_core);
1801                 kfree(stats_info.pestat);
1802                 return status;
1803         }
1804
1805         do {
1806                 if (!iwdev->roce_mode) {
1807                         status = irdma_initialize_ilq(iwdev);
1808                         if (status)
1809                                 break;
1810                         iwdev->init_state = ILQ_CREATED;
1811                         status = irdma_initialize_ieq(iwdev);
1812                         if (status)
1813                                 break;
1814                         iwdev->init_state = IEQ_CREATED;
1815                 }
1816                 if (!rf->rsrc_created) {
1817                         status = irdma_setup_ceqs(rf, &iwdev->vsi);
1818                         if (status)
1819                                 break;
1820
1821                         iwdev->init_state = CEQS_CREATED;
1822
1823                         status = irdma_hmc_init_pble(&rf->sc_dev,
1824                                                      rf->pble_rsrc);
1825                         if (status) {
1826                                 irdma_del_ceqs(rf);
1827                                 break;
1828                         }
1829
1830                         iwdev->init_state = PBLE_CHUNK_MEM;
1831
1832                         status = irdma_setup_aeq(rf);
1833                         if (status) {
1834                                 irdma_destroy_pble_prm(rf->pble_rsrc);
1835                                 irdma_del_ceqs(rf);
1836                                 break;
1837                         }
1838                         iwdev->init_state = AEQ_CREATED;
1839                         rf->rsrc_created = true;
1840                 }
1841
1842                 if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)
1843                         irdma_alloc_set_mac(iwdev);
1844                 irdma_add_ip(iwdev);
1845                 iwdev->init_state = IP_ADDR_REGISTERED;
1846
1847                 /* handles asynch cleanup tasks - disconnect CM , free qp,
1848                  * free cq bufs
1849                  */
1850                 iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq",
1851                                         WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
1852                 if (!iwdev->cleanup_wq)
1853                         return -ENOMEM;
1854                 irdma_get_used_rsrc(iwdev);
1855                 init_waitqueue_head(&iwdev->suspend_wq);
1856
1857                 return 0;
1858         } while (0);
1859
1860         dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n",
1861                 status, iwdev->init_state);
1862         irdma_rt_deinit_hw(iwdev);
1863
1864         return status;
1865 }
1866
1867 /**
1868  * irdma_ctrl_init_hw - Initializes control portion of HW
1869  * @rf: RDMA PCI function
1870  *
1871  * Create admin queues, HMC obejcts and RF resource objects
1872  */
1873 int irdma_ctrl_init_hw(struct irdma_pci_f *rf)
1874 {
1875         struct irdma_sc_dev *dev = &rf->sc_dev;
1876         int status;
1877         do {
1878                 status = irdma_setup_init_state(rf);
1879                 if (status)
1880                         break;
1881                 rf->init_state = INITIAL_STATE;
1882
1883                 status = irdma_create_cqp(rf);
1884                 if (status)
1885                         break;
1886                 rf->init_state = CQP_CREATED;
1887
1888                 status = irdma_hmc_setup(rf);
1889                 if (status)
1890                         break;
1891                 rf->init_state = HMC_OBJS_CREATED;
1892
1893                 status = irdma_initialize_hw_rsrc(rf);
1894                 if (status)
1895                         break;
1896                 rf->init_state = HW_RSRC_INITIALIZED;
1897
1898                 status = irdma_create_ccq(rf);
1899                 if (status)
1900                         break;
1901                 rf->init_state = CCQ_CREATED;
1902
1903                 dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT;
1904                 if (rf->rdma_ver != IRDMA_GEN_1) {
1905                         status = irdma_get_rdma_features(dev);
1906                         if (status)
1907                                 break;
1908                 }
1909
1910                 status = irdma_setup_ceq_0(rf);
1911                 if (status)
1912                         break;
1913                 rf->init_state = CEQ0_CREATED;
1914                 /* Handles processing of CQP completions */
1915                 rf->cqp_cmpl_wq =
1916                         alloc_ordered_workqueue("cqp_cmpl_wq", WQ_HIGHPRI);
1917                 if (!rf->cqp_cmpl_wq) {
1918                         status = -ENOMEM;
1919                         break;
1920                 }
1921                 INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker);
1922                 irdma_sc_ccq_arm(dev->ccq);
1923                 return 0;
1924         } while (0);
1925
1926         dev_err(&rf->pcidev->dev, "IRDMA hardware initialization FAILED init_state=%d status=%d\n",
1927                 rf->init_state, status);
1928         irdma_ctrl_deinit_hw(rf);
1929         return status;
1930 }
1931
1932 /**
1933  * irdma_set_hw_rsrc - set hw memory resources.
1934  * @rf: RDMA PCI function
1935  */
1936 static void irdma_set_hw_rsrc(struct irdma_pci_f *rf)
1937 {
1938         rf->allocated_qps = (void *)(rf->mem_rsrc +
1939                    (sizeof(struct irdma_arp_entry) * rf->arp_table_size));
1940         rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)];
1941         rf->allocated_mrs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)];
1942         rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)];
1943         rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)];
1944         rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)];
1945         rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)];
1946         rf->qp_table = (struct irdma_qp **)
1947                 (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]);
1948
1949         spin_lock_init(&rf->rsrc_lock);
1950         spin_lock_init(&rf->arp_lock);
1951         spin_lock_init(&rf->qptable_lock);
1952         spin_lock_init(&rf->qh_list_lock);
1953 }
1954
1955 /**
1956  * irdma_calc_mem_rsrc_size - calculate memory resources size.
1957  * @rf: RDMA PCI function
1958  */
1959 static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf)
1960 {
1961         u32 rsrc_size;
1962
1963         rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size;
1964         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp);
1965         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr);
1966         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq);
1967         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd);
1968         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size);
1969         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah);
1970         rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg);
1971         rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp;
1972
1973         return rsrc_size;
1974 }
1975
1976 /**
1977  * irdma_initialize_hw_rsrc - initialize hw resource tracking array
1978  * @rf: RDMA PCI function
1979  */
1980 u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf)
1981 {
1982         u32 rsrc_size;
1983         u32 mrdrvbits;
1984         u32 ret;
1985
1986         if (rf->rdma_ver != IRDMA_GEN_1) {
1987                 rf->allocated_ws_nodes = bitmap_zalloc(IRDMA_MAX_WS_NODES,
1988                                                        GFP_KERNEL);
1989                 if (!rf->allocated_ws_nodes)
1990                         return -ENOMEM;
1991
1992                 set_bit(0, rf->allocated_ws_nodes);
1993                 rf->max_ws_node_id = IRDMA_MAX_WS_NODES;
1994         }
1995         rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size;
1996         rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt;
1997         rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt;
1998         rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt;
1999         rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds;
2000         rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt;
2001         rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt;
2002         rf->max_mcg = rf->max_qp;
2003
2004         rsrc_size = irdma_calc_mem_rsrc_size(rf);
2005         rf->mem_rsrc = kzalloc(rsrc_size, GFP_KERNEL);
2006         if (!rf->mem_rsrc) {
2007                 ret = -ENOMEM;
2008                 goto mem_rsrc_kzalloc_fail;
2009         }
2010
2011         rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc;
2012
2013         irdma_set_hw_rsrc(rf);
2014
2015         set_bit(0, rf->allocated_mrs);
2016         set_bit(0, rf->allocated_qps);
2017         set_bit(0, rf->allocated_cqs);
2018         set_bit(0, rf->allocated_pds);
2019         set_bit(0, rf->allocated_arps);
2020         set_bit(0, rf->allocated_ahs);
2021         set_bit(0, rf->allocated_mcgs);
2022         set_bit(2, rf->allocated_qps); /* qp 2 IEQ */
2023         set_bit(1, rf->allocated_qps); /* qp 1 ILQ */
2024         set_bit(1, rf->allocated_cqs);
2025         set_bit(1, rf->allocated_pds);
2026         set_bit(2, rf->allocated_cqs);
2027         set_bit(2, rf->allocated_pds);
2028
2029         INIT_LIST_HEAD(&rf->mc_qht_list.list);
2030         /* stag index mask has a minimum of 14 bits */
2031         mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14);
2032         rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
2033
2034         return 0;
2035
2036 mem_rsrc_kzalloc_fail:
2037         bitmap_free(rf->allocated_ws_nodes);
2038         rf->allocated_ws_nodes = NULL;
2039
2040         return ret;
2041 }
2042
2043 /**
2044  * irdma_cqp_ce_handler - handle cqp completions
2045  * @rf: RDMA PCI function
2046  * @cq: cq for cqp completions
2047  */
2048 void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)
2049 {
2050         struct irdma_cqp_request *cqp_request;
2051         struct irdma_sc_dev *dev = &rf->sc_dev;
2052         u32 cqe_count = 0;
2053         struct irdma_ccq_cqe_info info;
2054         unsigned long flags;
2055         int ret;
2056
2057         do {
2058                 memset(&info, 0, sizeof(info));
2059                 spin_lock_irqsave(&rf->cqp.compl_lock, flags);
2060                 ret = irdma_sc_ccq_get_cqe_info(cq, &info);
2061                 spin_unlock_irqrestore(&rf->cqp.compl_lock, flags);
2062                 if (ret)
2063                         break;
2064
2065                 cqp_request = (struct irdma_cqp_request *)
2066                               (unsigned long)info.scratch;
2067                 if (info.error && irdma_cqp_crit_err(dev, cqp_request->info.cqp_cmd,
2068                                                      info.maj_err_code,
2069                                                      info.min_err_code))
2070                         ibdev_err(&rf->iwdev->ibdev, "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
2071                                   info.op_code, info.maj_err_code, info.min_err_code);
2072                 if (cqp_request) {
2073                         cqp_request->compl_info.maj_err_code = info.maj_err_code;
2074                         cqp_request->compl_info.min_err_code = info.min_err_code;
2075                         cqp_request->compl_info.op_ret_val = info.op_ret_val;
2076                         cqp_request->compl_info.error = info.error;
2077
2078                         if (cqp_request->waiting) {
2079                                 WRITE_ONCE(cqp_request->request_done, true);
2080                                 wake_up(&cqp_request->waitq);
2081                                 irdma_put_cqp_request(&rf->cqp, cqp_request);
2082                         } else {
2083                                 if (cqp_request->callback_fcn)
2084                                         cqp_request->callback_fcn(cqp_request);
2085                                 irdma_put_cqp_request(&rf->cqp, cqp_request);
2086                         }
2087                 }
2088
2089                 cqe_count++;
2090         } while (1);
2091
2092         if (cqe_count) {
2093                 irdma_process_bh(dev);
2094                 irdma_sc_ccq_arm(cq);
2095         }
2096 }
2097
2098 /**
2099  * cqp_compl_worker - Handle cqp completions
2100  * @work: Pointer to work structure
2101  */
2102 void cqp_compl_worker(struct work_struct *work)
2103 {
2104         struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f,
2105                                               cqp_cmpl_work);
2106         struct irdma_sc_cq *cq = &rf->ccq.sc_cq;
2107
2108         irdma_cqp_ce_handler(rf, cq);
2109 }
2110
2111 /**
2112  * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port
2113  * @cm_core: cm's core
2114  * @port: port to identify apbvt entry
2115  */
2116 static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core,
2117                                                           u16 port)
2118 {
2119         struct irdma_apbvt_entry *entry;
2120
2121         hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) {
2122                 if (entry->port == port) {
2123                         entry->use_cnt++;
2124                         return entry;
2125                 }
2126         }
2127
2128         return NULL;
2129 }
2130
2131 /**
2132  * irdma_next_iw_state - modify qp state
2133  * @iwqp: iwarp qp to modify
2134  * @state: next state for qp
2135  * @del_hash: del hash
2136  * @term: term message
2137  * @termlen: length of term message
2138  */
2139 void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
2140                          u8 termlen)
2141 {
2142         struct irdma_modify_qp_info info = {};
2143
2144         info.next_iwarp_state = state;
2145         info.remove_hash_idx = del_hash;
2146         info.cq_num_valid = true;
2147         info.arp_cache_idx_valid = true;
2148         info.dont_send_term = true;
2149         info.dont_send_fin = true;
2150         info.termlen = termlen;
2151
2152         if (term & IRDMAQP_TERM_SEND_TERM_ONLY)
2153                 info.dont_send_term = false;
2154         if (term & IRDMAQP_TERM_SEND_FIN_ONLY)
2155                 info.dont_send_fin = false;
2156         if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR)
2157                 info.reset_tcp_conn = true;
2158         iwqp->hw_iwarp_state = state;
2159         irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
2160         iwqp->iwarp_state = info.next_iwarp_state;
2161 }
2162
2163 /**
2164  * irdma_del_local_mac_entry - remove a mac entry from the hw
2165  * table
2166  * @rf: RDMA PCI function
2167  * @idx: the index of the mac ip address to delete
2168  */
2169 void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx)
2170 {
2171         struct irdma_cqp *iwcqp = &rf->cqp;
2172         struct irdma_cqp_request *cqp_request;
2173         struct cqp_cmds_info *cqp_info;
2174
2175         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2176         if (!cqp_request)
2177                 return;
2178
2179         cqp_info = &cqp_request->info;
2180         cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY;
2181         cqp_info->post_sq = 1;
2182         cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp;
2183         cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request;
2184         cqp_info->in.u.del_local_mac_entry.entry_idx = idx;
2185         cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0;
2186
2187         irdma_handle_cqp_op(rf, cqp_request);
2188         irdma_put_cqp_request(iwcqp, cqp_request);
2189 }
2190
2191 /**
2192  * irdma_add_local_mac_entry - add a mac ip address entry to the
2193  * hw table
2194  * @rf: RDMA PCI function
2195  * @mac_addr: pointer to mac address
2196  * @idx: the index of the mac ip address to add
2197  */
2198 int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx)
2199 {
2200         struct irdma_local_mac_entry_info *info;
2201         struct irdma_cqp *iwcqp = &rf->cqp;
2202         struct irdma_cqp_request *cqp_request;
2203         struct cqp_cmds_info *cqp_info;
2204         int status;
2205
2206         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2207         if (!cqp_request)
2208                 return -ENOMEM;
2209
2210         cqp_info = &cqp_request->info;
2211         cqp_info->post_sq = 1;
2212         info = &cqp_info->in.u.add_local_mac_entry.info;
2213         ether_addr_copy(info->mac_addr, mac_addr);
2214         info->entry_idx = idx;
2215         cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2216         cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY;
2217         cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp;
2218         cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request;
2219
2220         status = irdma_handle_cqp_op(rf, cqp_request);
2221         irdma_put_cqp_request(iwcqp, cqp_request);
2222
2223         return status;
2224 }
2225
2226 /**
2227  * irdma_alloc_local_mac_entry - allocate a mac entry
2228  * @rf: RDMA PCI function
2229  * @mac_tbl_idx: the index of the new mac address
2230  *
2231  * Allocate a mac address entry and update the mac_tbl_idx
2232  * to hold the index of the newly created mac address
2233  * Return 0 if successful, otherwise return error
2234  */
2235 int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx)
2236 {
2237         struct irdma_cqp *iwcqp = &rf->cqp;
2238         struct irdma_cqp_request *cqp_request;
2239         struct cqp_cmds_info *cqp_info;
2240         int status = 0;
2241
2242         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true);
2243         if (!cqp_request)
2244                 return -ENOMEM;
2245
2246         cqp_info = &cqp_request->info;
2247         cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY;
2248         cqp_info->post_sq = 1;
2249         cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp;
2250         cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request;
2251         status = irdma_handle_cqp_op(rf, cqp_request);
2252         if (!status)
2253                 *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val;
2254
2255         irdma_put_cqp_request(iwcqp, cqp_request);
2256
2257         return status;
2258 }
2259
2260 /**
2261  * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt
2262  * @iwdev: irdma device
2263  * @accel_local_port: port for apbvt
2264  * @add_port: add ordelete port
2265  */
2266 static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev,
2267                                       u16 accel_local_port, bool add_port)
2268 {
2269         struct irdma_apbvt_info *info;
2270         struct irdma_cqp_request *cqp_request;
2271         struct cqp_cmds_info *cqp_info;
2272         int status;
2273
2274         cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port);
2275         if (!cqp_request)
2276                 return -ENOMEM;
2277
2278         cqp_info = &cqp_request->info;
2279         info = &cqp_info->in.u.manage_apbvt_entry.info;
2280         memset(info, 0, sizeof(*info));
2281         info->add = add_port;
2282         info->port = accel_local_port;
2283         cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY;
2284         cqp_info->post_sq = 1;
2285         cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2286         cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
2287         ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n",
2288                   (!add_port) ? "DELETE" : "ADD", accel_local_port);
2289
2290         status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2291         irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request);
2292
2293         return status;
2294 }
2295
2296 /**
2297  * irdma_add_apbvt - add tcp port to HW apbvt table
2298  * @iwdev: irdma device
2299  * @port: port for apbvt
2300  */
2301 struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port)
2302 {
2303         struct irdma_cm_core *cm_core = &iwdev->cm_core;
2304         struct irdma_apbvt_entry *entry;
2305         unsigned long flags;
2306
2307         spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2308         entry = irdma_lookup_apbvt_entry(cm_core, port);
2309         if (entry) {
2310                 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2311                 return entry;
2312         }
2313
2314         entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
2315         if (!entry) {
2316                 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2317                 return NULL;
2318         }
2319
2320         entry->port = port;
2321         entry->use_cnt = 1;
2322         hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port);
2323         spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2324
2325         if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) {
2326                 kfree(entry);
2327                 return NULL;
2328         }
2329
2330         return entry;
2331 }
2332
2333 /**
2334  * irdma_del_apbvt - delete tcp port from HW apbvt table
2335  * @iwdev: irdma device
2336  * @entry: apbvt entry object
2337  */
2338 void irdma_del_apbvt(struct irdma_device *iwdev,
2339                      struct irdma_apbvt_entry *entry)
2340 {
2341         struct irdma_cm_core *cm_core = &iwdev->cm_core;
2342         unsigned long flags;
2343
2344         spin_lock_irqsave(&cm_core->apbvt_lock, flags);
2345         if (--entry->use_cnt) {
2346                 spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2347                 return;
2348         }
2349
2350         hash_del(&entry->hlist);
2351         /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to
2352          * protect against race where add APBVT CQP can race ahead of the delete
2353          * APBVT for same port.
2354          */
2355         irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false);
2356         kfree(entry);
2357         spin_unlock_irqrestore(&cm_core->apbvt_lock, flags);
2358 }
2359
2360 /**
2361  * irdma_manage_arp_cache - manage hw arp cache
2362  * @rf: RDMA PCI function
2363  * @mac_addr: mac address ptr
2364  * @ip_addr: ip addr for arp cache
2365  * @ipv4: flag inicating IPv4
2366  * @action: add, delete or modify
2367  */
2368 void irdma_manage_arp_cache(struct irdma_pci_f *rf,
2369                             const unsigned char *mac_addr,
2370                             u32 *ip_addr, bool ipv4, u32 action)
2371 {
2372         struct irdma_add_arp_cache_entry_info *info;
2373         struct irdma_cqp_request *cqp_request;
2374         struct cqp_cmds_info *cqp_info;
2375         int arp_index;
2376
2377         arp_index = irdma_arp_table(rf, ip_addr, ipv4, mac_addr, action);
2378         if (arp_index == -1)
2379                 return;
2380
2381         cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false);
2382         if (!cqp_request)
2383                 return;
2384
2385         cqp_info = &cqp_request->info;
2386         if (action == IRDMA_ARP_ADD) {
2387                 cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY;
2388                 info = &cqp_info->in.u.add_arp_cache_entry.info;
2389                 memset(info, 0, sizeof(*info));
2390                 info->arp_index = (u16)arp_index;
2391                 info->permanent = true;
2392                 ether_addr_copy(info->mac_addr, mac_addr);
2393                 cqp_info->in.u.add_arp_cache_entry.scratch =
2394                         (uintptr_t)cqp_request;
2395                 cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2396         } else {
2397                 cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY;
2398                 cqp_info->in.u.del_arp_cache_entry.scratch =
2399                         (uintptr_t)cqp_request;
2400                 cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp;
2401                 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
2402         }
2403
2404         cqp_info->post_sq = 1;
2405         irdma_handle_cqp_op(rf, cqp_request);
2406         irdma_put_cqp_request(&rf->cqp, cqp_request);
2407 }
2408
2409 /**
2410  * irdma_send_syn_cqp_callback - do syn/ack after qhash
2411  * @cqp_request: qhash cqp completion
2412  */
2413 static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request)
2414 {
2415         struct irdma_cm_node *cm_node = cqp_request->param;
2416
2417         irdma_send_syn(cm_node, 1);
2418         irdma_rem_ref_cm_node(cm_node);
2419 }
2420
2421 /**
2422  * irdma_manage_qhash - add or modify qhash
2423  * @iwdev: irdma device
2424  * @cminfo: cm info for qhash
2425  * @etype: type (syn or quad)
2426  * @mtype: type of qhash
2427  * @cmnode: cmnode associated with connection
2428  * @wait: wait for completion
2429  */
2430 int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
2431                        enum irdma_quad_entry_type etype,
2432                        enum irdma_quad_hash_manage_type mtype, void *cmnode,
2433                        bool wait)
2434 {
2435         struct irdma_qhash_table_info *info;
2436         struct irdma_cqp *iwcqp = &iwdev->rf->cqp;
2437         struct irdma_cqp_request *cqp_request;
2438         struct cqp_cmds_info *cqp_info;
2439         struct irdma_cm_node *cm_node = cmnode;
2440         int status;
2441
2442         cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait);
2443         if (!cqp_request)
2444                 return -ENOMEM;
2445
2446         cqp_info = &cqp_request->info;
2447         info = &cqp_info->in.u.manage_qhash_table_entry.info;
2448         memset(info, 0, sizeof(*info));
2449         info->vsi = &iwdev->vsi;
2450         info->manage = mtype;
2451         info->entry_type = etype;
2452         if (cminfo->vlan_id < VLAN_N_VID) {
2453                 info->vlan_valid = true;
2454                 info->vlan_id = cminfo->vlan_id;
2455         } else {
2456                 info->vlan_valid = false;
2457         }
2458         info->ipv4_valid = cminfo->ipv4;
2459         info->user_pri = cminfo->user_pri;
2460         ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
2461         info->qp_num = cminfo->qh_qpid;
2462         info->dest_port = cminfo->loc_port;
2463         info->dest_ip[0] = cminfo->loc_addr[0];
2464         info->dest_ip[1] = cminfo->loc_addr[1];
2465         info->dest_ip[2] = cminfo->loc_addr[2];
2466         info->dest_ip[3] = cminfo->loc_addr[3];
2467         if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED ||
2468             etype == IRDMA_QHASH_TYPE_UDP_UNICAST ||
2469             etype == IRDMA_QHASH_TYPE_UDP_MCAST ||
2470             etype == IRDMA_QHASH_TYPE_ROCE_MCAST ||
2471             etype == IRDMA_QHASH_TYPE_ROCEV2_HW) {
2472                 info->src_port = cminfo->rem_port;
2473                 info->src_ip[0] = cminfo->rem_addr[0];
2474                 info->src_ip[1] = cminfo->rem_addr[1];
2475                 info->src_ip[2] = cminfo->rem_addr[2];
2476                 info->src_ip[3] = cminfo->rem_addr[3];
2477         }
2478         if (cmnode) {
2479                 cqp_request->callback_fcn = irdma_send_syn_cqp_callback;
2480                 cqp_request->param = cmnode;
2481                 if (!wait)
2482                         refcount_inc(&cm_node->refcnt);
2483         }
2484         if (info->ipv4_valid)
2485                 ibdev_dbg(&iwdev->ibdev,
2486                           "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n",
2487                           (!mtype) ? "DELETE" : "ADD",
2488                           __builtin_return_address(0), info->dest_port,
2489                           info->src_port, info->dest_ip, info->src_ip,
2490                           info->mac_addr, cminfo->vlan_id,
2491                           cmnode ? cmnode : NULL);
2492         else
2493                 ibdev_dbg(&iwdev->ibdev,
2494                           "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n",
2495                           (!mtype) ? "DELETE" : "ADD",
2496                           __builtin_return_address(0), info->dest_port,
2497                           info->src_port, info->dest_ip, info->src_ip,
2498                           info->mac_addr, cminfo->vlan_id,
2499                           cmnode ? cmnode : NULL);
2500
2501         cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp;
2502         cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
2503         cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY;
2504         cqp_info->post_sq = 1;
2505         status = irdma_handle_cqp_op(iwdev->rf, cqp_request);
2506         if (status && cm_node && !wait)
2507                 irdma_rem_ref_cm_node(cm_node);
2508
2509         irdma_put_cqp_request(iwcqp, cqp_request);
2510
2511         return status;
2512 }
2513
2514 /**
2515  * irdma_hw_flush_wqes_callback - Check return code after flush
2516  * @cqp_request: qhash cqp completion
2517  */
2518 static void irdma_hw_flush_wqes_callback(struct irdma_cqp_request *cqp_request)
2519 {
2520         struct irdma_qp_flush_info *hw_info;
2521         struct irdma_sc_qp *qp;
2522         struct irdma_qp *iwqp;
2523         struct cqp_cmds_info *cqp_info;
2524
2525         cqp_info = &cqp_request->info;
2526         hw_info = &cqp_info->in.u.qp_flush_wqes.info;
2527         qp = cqp_info->in.u.qp_flush_wqes.qp;
2528         iwqp = qp->qp_uk.back_qp;
2529
2530         if (cqp_request->compl_info.maj_err_code)
2531                 return;
2532
2533         if (hw_info->rq &&
2534             (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2535              cqp_request->compl_info.min_err_code == 0)) {
2536                 /* RQ WQE flush was requested but did not happen */
2537                 qp->qp_uk.rq_flush_complete = true;
2538         }
2539         if (hw_info->sq &&
2540             (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2541              cqp_request->compl_info.min_err_code == 0)) {
2542                 if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2543                         ibdev_err(&iwqp->iwdev->ibdev, "Flush QP[%d] failed, SQ has more work",
2544                                   qp->qp_uk.qp_id);
2545                         irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2546                 }
2547                 qp->qp_uk.sq_flush_complete = true;
2548         }
2549 }
2550
2551 /**
2552  * irdma_hw_flush_wqes - flush qp's wqe
2553  * @rf: RDMA PCI function
2554  * @qp: hardware control qp
2555  * @info: info for flush
2556  * @wait: flag wait for completion
2557  */
2558 int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2559                         struct irdma_qp_flush_info *info, bool wait)
2560 {
2561         int status;
2562         struct irdma_qp_flush_info *hw_info;
2563         struct irdma_cqp_request *cqp_request;
2564         struct cqp_cmds_info *cqp_info;
2565         struct irdma_qp *iwqp = qp->qp_uk.back_qp;
2566
2567         cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2568         if (!cqp_request)
2569                 return -ENOMEM;
2570
2571         cqp_info = &cqp_request->info;
2572         if (!wait)
2573                 cqp_request->callback_fcn = irdma_hw_flush_wqes_callback;
2574         hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
2575         memcpy(hw_info, info, sizeof(*hw_info));
2576         cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2577         cqp_info->post_sq = 1;
2578         cqp_info->in.u.qp_flush_wqes.qp = qp;
2579         cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
2580         status = irdma_handle_cqp_op(rf, cqp_request);
2581         if (status) {
2582                 qp->qp_uk.sq_flush_complete = true;
2583                 qp->qp_uk.rq_flush_complete = true;
2584                 irdma_put_cqp_request(&rf->cqp, cqp_request);
2585                 return status;
2586         }
2587
2588         if (!wait || cqp_request->compl_info.maj_err_code)
2589                 goto put_cqp;
2590
2591         if (info->rq) {
2592                 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2593                     cqp_request->compl_info.min_err_code == 0) {
2594                         /* RQ WQE flush was requested but did not happen */
2595                         qp->qp_uk.rq_flush_complete = true;
2596                 }
2597         }
2598         if (info->sq) {
2599                 if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED ||
2600                     cqp_request->compl_info.min_err_code == 0) {
2601                         /*
2602                          * Handling case where WQE is posted to empty SQ when
2603                          * flush has not completed
2604                          */
2605                         if (IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring)) {
2606                                 struct irdma_cqp_request *new_req;
2607
2608                                 if (!qp->qp_uk.sq_flush_complete)
2609                                         goto put_cqp;
2610                                 qp->qp_uk.sq_flush_complete = false;
2611                                 qp->flush_sq = false;
2612
2613                                 info->rq = false;
2614                                 info->sq = true;
2615                                 new_req = irdma_alloc_and_get_cqp_request(&rf->cqp, true);
2616                                 if (!new_req) {
2617                                         status = -ENOMEM;
2618                                         goto put_cqp;
2619                                 }
2620                                 cqp_info = &new_req->info;
2621                                 hw_info = &new_req->info.in.u.qp_flush_wqes.info;
2622                                 memcpy(hw_info, info, sizeof(*hw_info));
2623                                 cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES;
2624                                 cqp_info->post_sq = 1;
2625                                 cqp_info->in.u.qp_flush_wqes.qp = qp;
2626                                 cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)new_req;
2627
2628                                 status = irdma_handle_cqp_op(rf, new_req);
2629                                 if (new_req->compl_info.maj_err_code ||
2630                                     new_req->compl_info.min_err_code != IRDMA_CQP_COMPL_SQ_WQE_FLUSHED ||
2631                                     status) {
2632                                         ibdev_err(&iwqp->iwdev->ibdev, "fatal QP event: SQ in error but not flushed, qp: %d",
2633                                                   iwqp->ibqp.qp_num);
2634                                         qp->qp_uk.sq_flush_complete = false;
2635                                         irdma_ib_qp_event(iwqp, IRDMA_QP_EVENT_CATASTROPHIC);
2636                                 }
2637                                 irdma_put_cqp_request(&rf->cqp, new_req);
2638                         } else {
2639                                 /* SQ WQE flush was requested but did not happen */
2640                                 qp->qp_uk.sq_flush_complete = true;
2641                         }
2642                 } else {
2643                         if (!IRDMA_RING_MORE_WORK(qp->qp_uk.sq_ring))
2644                                 qp->qp_uk.sq_flush_complete = true;
2645                 }
2646         }
2647
2648         ibdev_dbg(&rf->iwdev->ibdev,
2649                   "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n",
2650                   iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state,
2651                   iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state,
2652                   cqp_request->compl_info.maj_err_code,
2653                   cqp_request->compl_info.min_err_code);
2654 put_cqp:
2655         irdma_put_cqp_request(&rf->cqp, cqp_request);
2656
2657         return status;
2658 }
2659
2660 /**
2661  * irdma_gen_ae - generate AE
2662  * @rf: RDMA PCI function
2663  * @qp: qp associated with AE
2664  * @info: info for ae
2665  * @wait: wait for completion
2666  */
2667 void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
2668                   struct irdma_gen_ae_info *info, bool wait)
2669 {
2670         struct irdma_gen_ae_info *ae_info;
2671         struct irdma_cqp_request *cqp_request;
2672         struct cqp_cmds_info *cqp_info;
2673
2674         cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait);
2675         if (!cqp_request)
2676                 return;
2677
2678         cqp_info = &cqp_request->info;
2679         ae_info = &cqp_request->info.in.u.gen_ae.info;
2680         memcpy(ae_info, info, sizeof(*ae_info));
2681         cqp_info->cqp_cmd = IRDMA_OP_GEN_AE;
2682         cqp_info->post_sq = 1;
2683         cqp_info->in.u.gen_ae.qp = qp;
2684         cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request;
2685
2686         irdma_handle_cqp_op(rf, cqp_request);
2687         irdma_put_cqp_request(&rf->cqp, cqp_request);
2688 }
2689
2690 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask)
2691 {
2692         struct irdma_qp_flush_info info = {};
2693         struct irdma_pci_f *rf = iwqp->iwdev->rf;
2694         u8 flush_code = iwqp->sc_qp.flush_code;
2695
2696         if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ))
2697                 return;
2698
2699         /* Set flush info fields*/
2700         info.sq = flush_mask & IRDMA_FLUSH_SQ;
2701         info.rq = flush_mask & IRDMA_FLUSH_RQ;
2702
2703         /* Generate userflush errors in CQE */
2704         info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2705         info.sq_minor_code = FLUSH_GENERAL_ERR;
2706         info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR;
2707         info.rq_minor_code = FLUSH_GENERAL_ERR;
2708         info.userflushcode = true;
2709
2710         if (flush_mask & IRDMA_REFLUSH) {
2711                 if (info.sq)
2712                         iwqp->sc_qp.flush_sq = false;
2713                 if (info.rq)
2714                         iwqp->sc_qp.flush_rq = false;
2715         } else {
2716                 if (flush_code) {
2717                         if (info.sq && iwqp->sc_qp.sq_flush_code)
2718                                 info.sq_minor_code = flush_code;
2719                         if (info.rq && iwqp->sc_qp.rq_flush_code)
2720                                 info.rq_minor_code = flush_code;
2721                 }
2722                 if (!iwqp->user_mode)
2723                         queue_delayed_work(iwqp->iwdev->cleanup_wq,
2724                                            &iwqp->dwork_flush,
2725                                            msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS));
2726         }
2727
2728         /* Issue flush */
2729         (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info,
2730                                   flush_mask & IRDMA_FLUSH_WAIT);
2731         iwqp->flush_issued = true;
2732 }