drivers/gpu/drm/tidss/tidss_plane.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
   4  * Author: Tomi Valkeinen <[email protected]>
   5  */
   6
   7 #include <drm/drm_atomic.h>
   8 #include <drm/drm_atomic_helper.h>
   9 #include <drm/drm_blend.h>
  10 #include <drm/drm_crtc.h>
  11 #include <drm/drm_fourcc.h>
  12 #include <drm/drm_framebuffer.h>
  13 #include <drm/drm_gem_atomic_helper.h>
  14
  15 #include "tidss_crtc.h"
  16 #include "tidss_dispc.h"
  17 #include "tidss_drv.h"
  18 #include "tidss_plane.h"
  19
  20 /* drm_plane_helper_funcs */
  21
  22 static int tidss_plane_atomic_check(struct drm_plane *plane,
  23                                     struct drm_atomic_state *state)
  24 {
  25         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
  26                                                                                  plane);
  27         struct drm_device *ddev = plane->dev;
  28         struct tidss_device *tidss = to_tidss(ddev);
  29         struct tidss_plane *tplane = to_tidss_plane(plane);
  30         const struct drm_format_info *finfo;
  31         struct drm_crtc_state *crtc_state;
  32         u32 hw_plane = tplane->hw_plane_id;
  33         u32 hw_videoport;
  34         int ret;
  35
  36         dev_dbg(ddev->dev, "%s\n", __func__);
  37
  38         if (!new_plane_state->crtc) {
  39                 /*
  40                  * The visible field is not reset by the DRM core but only
  41                  * updated by drm_plane_helper_check_state(), set it manually.
  42                  */
  43                 new_plane_state->visible = false;
  44                 return 0;
  45         }
  46
  47         crtc_state = drm_atomic_get_crtc_state(state,
  48                                                new_plane_state->crtc);
  49         if (IS_ERR(crtc_state))
  50                 return PTR_ERR(crtc_state);
  51
  52         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
  53                                                   0,
  54                                                   INT_MAX, true, true);
  55         if (ret < 0)
  56                 return ret;
  57
  58         /*
  59          * The HW is only able to start drawing at subpixel boundary
  60          * (the two first checks bellow). At the end of a row the HW
  61          * can only jump integer number of subpixels forward to the
  62          * beginning of the next row. So we can only show picture with
  63          * integer subpixel width (the third check). However, after
  64          * reaching the end of the drawn picture the drawing starts
  65          * again at the absolute memory address where top left corner
  66          * position of the drawn picture is (so there is no need to
  67          * check for odd height).
  68          */
  69
  70         finfo = drm_format_info(new_plane_state->fb->format->format);
  71
  72         if ((new_plane_state->src_x >> 16) % finfo->hsub != 0) {
  73                 dev_dbg(ddev->dev,
  74                         "%s: x-position %u not divisible subpixel size %u\n",
  75                         __func__, (new_plane_state->src_x >> 16), finfo->hsub);
  76                 return -EINVAL;
  77         }
  78
  79         if ((new_plane_state->src_y >> 16) % finfo->vsub != 0) {
  80                 dev_dbg(ddev->dev,
  81                         "%s: y-position %u not divisible subpixel size %u\n",
  82                         __func__, (new_plane_state->src_y >> 16), finfo->vsub);
  83                 return -EINVAL;
  84         }
  85
  86         if ((new_plane_state->src_w >> 16) % finfo->hsub != 0) {
  87                 dev_dbg(ddev->dev,
  88                         "%s: src width %u not divisible by subpixel size %u\n",
  89                          __func__, (new_plane_state->src_w >> 16),
  90                          finfo->hsub);
  91                 return -EINVAL;
  92         }
  93
  94         if (!new_plane_state->visible)
  95                 return 0;
  96
  97         hw_videoport = to_tidss_crtc(new_plane_state->crtc)->hw_videoport;
  98
  99         ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state,
 100                                 hw_videoport);
 101         if (ret)
 102                 return ret;
 103
 104         return 0;
 105 }
 106
 107 static void tidss_plane_atomic_update(struct drm_plane *plane,
 108                                       struct drm_atomic_state *state)
 109 {
 110         struct drm_device *ddev = plane->dev;
 111         struct tidss_device *tidss = to_tidss(ddev);
 112         struct tidss_plane *tplane = to_tidss_plane(plane);
 113         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 114                                                                            plane);
 115         u32 hw_videoport;
 116
 117         dev_dbg(ddev->dev, "%s\n", __func__);
 118
 119         if (!new_state->visible) {
 120                 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
 121                 return;
 122         }
 123
 124         hw_videoport = to_tidss_crtc(new_state->crtc)->hw_videoport;
 125
 126         dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, new_state, hw_videoport);
 127 }
 128
 129 static void tidss_plane_atomic_enable(struct drm_plane *plane,
 130                                       struct drm_atomic_state *state)
 131 {
 132         struct drm_device *ddev = plane->dev;
 133         struct tidss_device *tidss = to_tidss(ddev);
 134         struct tidss_plane *tplane = to_tidss_plane(plane);
 135
 136         dev_dbg(ddev->dev, "%s\n", __func__);
 137
 138         dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true);
 139 }
 140
 141 static void tidss_plane_atomic_disable(struct drm_plane *plane,
 142                                        struct drm_atomic_state *state)
 143 {
 144         struct drm_device *ddev = plane->dev;
 145         struct tidss_device *tidss = to_tidss(ddev);
 146         struct tidss_plane *tplane = to_tidss_plane(plane);
 147
 148         dev_dbg(ddev->dev, "%s\n", __func__);
 149
 150         dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
 151 }
 152
 153 static void drm_plane_destroy(struct drm_plane *plane)
 154 {
 155         struct tidss_plane *tplane = to_tidss_plane(plane);
 156
 157         drm_plane_cleanup(plane);
 158         kfree(tplane);
 159 }
 160
 161 static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
 162         .atomic_check = tidss_plane_atomic_check,
 163         .atomic_update = tidss_plane_atomic_update,
 164         .atomic_enable = tidss_plane_atomic_enable,
 165         .atomic_disable = tidss_plane_atomic_disable,
 166 };
 167
 168 static const struct drm_plane_funcs tidss_plane_funcs = {
 169         .update_plane = drm_atomic_helper_update_plane,
 170         .disable_plane = drm_atomic_helper_disable_plane,
 171         .reset = drm_atomic_helper_plane_reset,
 172         .destroy = drm_plane_destroy,
 173         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 174         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 175 };
 176
 177 struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
 178                                        u32 hw_plane_id, u32 plane_type,
 179                                        u32 crtc_mask, const u32 *formats,
 180                                        u32 num_formats)
 181 {
 182         struct tidss_plane *tplane;
 183         enum drm_plane_type type;
 184         u32 possible_crtcs;
 185         u32 num_planes = tidss->feat->num_planes;
 186         u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
 187                                BIT(DRM_COLOR_YCBCR_BT709));
 188         u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
 189                             BIT(DRM_COLOR_YCBCR_LIMITED_RANGE));
 190         u32 default_encoding = DRM_COLOR_YCBCR_BT601;
 191         u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE;
 192         u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) |
 193                            BIT(DRM_MODE_BLEND_COVERAGE));
 194         int ret;
 195
 196         tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
 197         if (!tplane)
 198                 return ERR_PTR(-ENOMEM);
 199
 200         tplane->hw_plane_id = hw_plane_id;
 201
 202         possible_crtcs = crtc_mask;
 203         type = plane_type;
 204
 205         ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane,
 206                                        possible_crtcs,
 207                                        &tidss_plane_funcs,
 208                                        formats, num_formats,
 209                                        NULL, type, NULL);
 210         if (ret < 0)
 211                 goto err;
 212
 213         drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
 214
 215         drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0,
 216                                        num_planes - 1);
 217
 218         ret = drm_plane_create_color_properties(&tplane->plane,
 219                                                 color_encodings,
 220                                                 color_ranges,
 221                                                 default_encoding,
 222                                                 default_range);
 223         if (ret)
 224                 goto err;
 225
 226         ret = drm_plane_create_alpha_property(&tplane->plane);
 227         if (ret)
 228                 goto err;
 229
 230         ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
 231         if (ret)
 232                 goto err;
 233
 234         return tplane;
 235
 236 err:
 237         kfree(tplane);
 238         return ERR_PTR(ret);
 239 }