drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "../dmub_srv.h"
  27 #include "dmub_reg.h"
  28 #include "dmub_dcn20.h"
  29
  30 #include "dcn/dcn_2_0_0_offset.h"
  31 #include "dcn/dcn_2_0_0_sh_mask.h"
  32 #include "soc15_hw_ip.h"
  33 #include "vega10_ip_offset.h"
  34
  35 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
  36 #define CTX dmub
  37 #define REGS dmub->regs
  38
  39 /* Registers. */
  40
  41 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
  42 #define DMUB_SR(reg) REG_OFFSET(reg),
  43         {
  44                 DMUB_COMMON_REGS()
  45                 DMCUB_INTERNAL_REGS()
  46         },
  47 #undef DMUB_SR
  48
  49 #define DMUB_SF(reg, field) FD_MASK(reg, field),
  50         { DMUB_COMMON_FIELDS() },
  51 #undef DMUB_SF
  52
  53 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
  54         { DMUB_COMMON_FIELDS() },
  55 #undef DMUB_SF
  56 };
  57
  58 /* Shared functions. */
  59
  60 static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
  61                                           uint64_t *fb_base,
  62                                           uint64_t *fb_offset)
  63 {
  64         uint32_t tmp;
  65
  66         if (dmub->fb_base || dmub->fb_offset) {
  67                 *fb_base = dmub->fb_base;
  68                 *fb_offset = dmub->fb_offset;
  69                 return;
  70         }
  71
  72         REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
  73         *fb_base = (uint64_t)tmp << 24;
  74
  75         REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
  76         *fb_offset = (uint64_t)tmp << 24;
  77 }
  78
  79 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
  80                                              uint64_t fb_base,
  81                                              uint64_t fb_offset,
  82                                              union dmub_addr *addr_out)
  83 {
  84         addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
  85 }
  86
  87 bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)
  88 {
  89         /* Cached inbox is not supported in this fw version range */
  90         return !(dmub->fw_version >= DMUB_FW_VERSION(1, 0, 0) &&
  91                  dmub->fw_version <= DMUB_FW_VERSION(1, 10, 0));
  92 }
  93
  94 void dmub_dcn20_reset(struct dmub_srv *dmub)
  95 {
  96         union dmub_gpint_data_register cmd;
  97         const uint32_t timeout = 30;
  98         uint32_t in_reset, scratch, i;
  99
 100         REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset);
 101
 102         if (in_reset == 0) {
 103                 cmd.bits.status = 1;
 104                 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
 105                 cmd.bits.param = 0;
 106
 107                 dmub->hw_funcs.set_gpint(dmub, cmd);
 108
 109                 /**
 110                  * Timeout covers both the ACK and the wait
 111                  * for remaining work to finish.
 112                  *
 113                  * This is mostly bound by the PHY disable sequence.
 114                  * Each register check will be greater than 1us, so
 115                  * don't bother using udelay.
 116                  */
 117
 118                 for (i = 0; i < timeout; ++i) {
 119                         if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
 120                                 break;
 121                 }
 122
 123                 for (i = 0; i < timeout; ++i) {
 124                         scratch = dmub->hw_funcs.get_gpint_response(dmub);
 125                         if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
 126                                 break;
 127                 }
 128
 129                 /* Clear the GPINT command manually so we don't reset again. */
 130                 cmd.all = 0;
 131                 dmub->hw_funcs.set_gpint(dmub, cmd);
 132
 133                 /* Force reset in case we timed out, DMCUB is likely hung. */
 134         }
 135
 136         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
 137         REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
 138         REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
 139         REG_WRITE(DMCUB_INBOX1_RPTR, 0);
 140         REG_WRITE(DMCUB_INBOX1_WPTR, 0);
 141         REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
 142         REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
 143         REG_WRITE(DMCUB_SCRATCH0, 0);
 144 }
 145
 146 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
 147 {
 148         REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
 149         REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
 150         REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
 151         REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
 152 }
 153
 154 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
 155                               const struct dmub_window *cw0,
 156                               const struct dmub_window *cw1)
 157 {
 158         union dmub_addr offset;
 159         uint64_t fb_base, fb_offset;
 160
 161         dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
 162
 163         REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
 164         REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
 165                      DMCUB_MEM_WRITE_SPACE, 0x3);
 166
 167         dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
 168
 169         REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
 170         REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
 171         REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
 172         REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
 173                   DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
 174                   DMCUB_REGION3_CW0_ENABLE, 1);
 175
 176         dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
 177
 178         REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
 179         REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
 180         REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
 181         REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
 182                   DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
 183                   DMCUB_REGION3_CW1_ENABLE, 1);
 184
 185         REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
 186                      0x20);
 187 }
 188
 189 void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
 190                               const struct dmub_window *cw2,
 191                               const struct dmub_window *cw3,
 192                               const struct dmub_window *cw4,
 193                               const struct dmub_window *cw5,
 194                               const struct dmub_window *cw6)
 195 {
 196         union dmub_addr offset;
 197         uint64_t fb_base, fb_offset;
 198
 199         dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
 200
 201         if (cw2->region.base != cw2->region.top) {
 202                 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset,
 203                                           &offset);
 204
 205                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
 206                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
 207                 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
 208                 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
 209                           DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
 210                           DMCUB_REGION3_CW2_ENABLE, 1);
 211         } else {
 212                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, 0);
 213                 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, 0);
 214                 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, 0);
 215                 REG_WRITE(DMCUB_REGION3_CW2_TOP_ADDRESS, 0);
 216         }
 217
 218         dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
 219
 220         REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
 221         REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
 222         REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
 223         REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
 224                   DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
 225                   DMCUB_REGION3_CW3_ENABLE, 1);
 226
 227         /* TODO: Move this to CW4. */
 228         dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
 229
 230         /* New firmware can support CW4. */
 231         if (dmub_dcn20_use_cached_inbox(dmub)) {
 232                 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
 233                 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
 234                 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
 235                 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
 236                           DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
 237                           DMCUB_REGION3_CW4_ENABLE, 1);
 238         } else {
 239                 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
 240                 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
 241                 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0,
 242                           DMCUB_REGION4_TOP_ADDRESS,
 243                           cw4->region.top - cw4->region.base - 1,
 244                           DMCUB_REGION4_ENABLE, 1);
 245         }
 246
 247         dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
 248
 249         REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
 250         REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
 251         REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
 252         REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
 253                   DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
 254                   DMCUB_REGION3_CW5_ENABLE, 1);
 255
 256         REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
 257         REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
 258         REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
 259                   DMCUB_REGION5_TOP_ADDRESS,
 260                   cw5->region.top - cw5->region.base - 1,
 261                   DMCUB_REGION5_ENABLE, 1);
 262
 263         dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
 264
 265         REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
 266         REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
 267         REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
 268         REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
 269                   DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
 270                   DMCUB_REGION3_CW6_ENABLE, 1);
 271 }
 272
 273 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
 274                               const struct dmub_region *inbox1)
 275 {
 276         /* New firmware can support CW4 for the inbox. */
 277         if (dmub_dcn20_use_cached_inbox(dmub))
 278                 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
 279         else
 280                 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
 281
 282         REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
 283 }
 284
 285 uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub)
 286 {
 287         return REG_READ(DMCUB_INBOX1_WPTR);
 288 }
 289
 290 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
 291 {
 292         return REG_READ(DMCUB_INBOX1_RPTR);
 293 }
 294
 295 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
 296 {
 297         REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
 298 }
 299
 300 void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,
 301                               const struct dmub_region *outbox1)
 302 {
 303         /* New firmware can support CW4 for the outbox. */
 304         if (dmub_dcn20_use_cached_inbox(dmub))
 305                 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
 306         else
 307                 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, 0x80002000);
 308
 309         REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
 310 }
 311
 312 uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)
 313 {
 314         /**
 315          * outbox1 wptr register is accessed without locks (dal & dc)
 316          * and to be called only by dmub_srv_stat_get_notification()
 317          */
 318         return REG_READ(DMCUB_OUTBOX1_WPTR);
 319 }
 320
 321 void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
 322 {
 323         /**
 324          * outbox1 rptr register is accessed without locks (dal & dc)
 325          * and to be called only by dmub_srv_stat_get_notification()
 326          */
 327         REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
 328 }
 329
 330 void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,
 331                               const struct dmub_region *outbox0)
 332 {
 333         REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
 334
 335         REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
 336 }
 337
 338 uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)
 339 {
 340         return REG_READ(DMCUB_OUTBOX0_WPTR);
 341 }
 342
 343 void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
 344 {
 345         REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
 346 }
 347
 348 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
 349 {
 350         uint32_t is_hw_init;
 351
 352         REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
 353
 354         return is_hw_init != 0;
 355 }
 356
 357 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
 358 {
 359         uint32_t supported = 0;
 360
 361         REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
 362
 363         return supported;
 364 }
 365
 366 void dmub_dcn20_set_gpint(struct dmub_srv *dmub,
 367                           union dmub_gpint_data_register reg)
 368 {
 369         REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
 370 }
 371
 372 bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
 373                                union dmub_gpint_data_register reg)
 374 {
 375         union dmub_gpint_data_register test;
 376
 377         reg.bits.status = 0;
 378         test.all = REG_READ(DMCUB_GPINT_DATAIN1);
 379
 380         return test.all == reg.all;
 381 }
 382
 383 uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
 384 {
 385         return REG_READ(DMCUB_SCRATCH7);
 386 }
 387
 388 union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
 389 {
 390         union dmub_fw_boot_status status;
 391
 392         status.all = REG_READ(DMCUB_SCRATCH0);
 393         return status;
 394 }
 395
 396 void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
 397 {
 398         union dmub_fw_boot_options boot_options = {0};
 399
 400         REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
 401 }
 402
 403 void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
 404 {
 405         union dmub_fw_boot_options boot_options;
 406         boot_options.all = REG_READ(DMCUB_SCRATCH14);
 407         boot_options.bits.skip_phy_init_panel_sequence = skip;
 408         REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
 409 }
 410
 411 uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)
 412 {
 413         return REG_READ(DMCUB_TIMER_CURRENT);
 414 }
 415
 416 void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
 417 {
 418         uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
 419         uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
 420
 421         if (!dmub || !diag_data)
 422                 return;
 423
 424         memset(diag_data, 0, sizeof(*diag_data));
 425
 426         diag_data->dmcub_version = dmub->fw_version;
 427
 428         diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
 429         diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
 430         diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
 431         diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
 432         diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
 433         diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
 434         diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
 435         diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
 436         diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
 437         diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
 438         diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
 439         diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
 440         diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
 441         diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
 442         diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
 443         diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
 444
 445         diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
 446         diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
 447         diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
 448
 449         diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
 450         diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
 451         diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
 452
 453         diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
 454         diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
 455         diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
 456
 457         REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
 458         diag_data->is_dmcub_enabled = is_dmub_enabled;
 459
 460         REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset);
 461         diag_data->is_dmcub_soft_reset = is_soft_reset;
 462
 463         REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
 464         diag_data->is_dmcub_secure_reset = is_sec_reset;
 465
 466         REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
 467         diag_data->is_traceport_en  = is_traceport_enabled;
 468
 469         REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
 470         diag_data->is_cw0_enabled = is_cw0_enabled;
 471
 472         REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
 473         diag_data->is_cw6_enabled = is_cw6_enabled;
 474 }