drivers/dma/qcom/hidma_mgmt.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm Technologies HIDMA DMA engine Management interface
   4  *
   5  * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <linux/dmaengine.h>
   9 #include <linux/acpi.h>
  10 #include <linux/of.h>
  11 #include <linux/property.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_irq.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include <linux/uaccess.h>
  19 #include <linux/slab.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/bitops.h>
  22 #include <linux/dma-mapping.h>
  23
  24 #include "hidma_mgmt.h"
  25
  26 #define HIDMA_QOS_N_OFFSET              0x700
  27 #define HIDMA_CFG_OFFSET                0x400
  28 #define HIDMA_MAX_BUS_REQ_LEN_OFFSET    0x41C
  29 #define HIDMA_MAX_XACTIONS_OFFSET       0x420
  30 #define HIDMA_HW_VERSION_OFFSET 0x424
  31 #define HIDMA_CHRESET_TIMEOUT_OFFSET    0x418
  32
  33 #define HIDMA_MAX_WR_XACTIONS_MASK      GENMASK(4, 0)
  34 #define HIDMA_MAX_RD_XACTIONS_MASK      GENMASK(4, 0)
  35 #define HIDMA_WEIGHT_MASK               GENMASK(6, 0)
  36 #define HIDMA_MAX_BUS_REQ_LEN_MASK      GENMASK(15, 0)
  37 #define HIDMA_CHRESET_TIMEOUT_MASK      GENMASK(19, 0)
  38
  39 #define HIDMA_MAX_WR_XACTIONS_BIT_POS   16
  40 #define HIDMA_MAX_BUS_WR_REQ_BIT_POS    16
  41 #define HIDMA_WRR_BIT_POS               8
  42 #define HIDMA_PRIORITY_BIT_POS          15
  43
  44 #define HIDMA_AUTOSUSPEND_TIMEOUT       2000
  45 #define HIDMA_MAX_CHANNEL_WEIGHT        15
  46
  47 static unsigned int max_write_request;
  48 module_param(max_write_request, uint, 0644);
  49 MODULE_PARM_DESC(max_write_request,
  50                 "maximum write burst (default: ACPI/DT value)");
  51
  52 static unsigned int max_read_request;
  53 module_param(max_read_request, uint, 0644);
  54 MODULE_PARM_DESC(max_read_request,
  55                 "maximum read burst (default: ACPI/DT value)");
  56
  57 static unsigned int max_wr_xactions;
  58 module_param(max_wr_xactions, uint, 0644);
  59 MODULE_PARM_DESC(max_wr_xactions,
  60         "maximum number of write transactions (default: ACPI/DT value)");
  61
  62 static unsigned int max_rd_xactions;
  63 module_param(max_rd_xactions, uint, 0644);
  64 MODULE_PARM_DESC(max_rd_xactions,
  65         "maximum number of read transactions (default: ACPI/DT value)");
  66
  67 int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
  68 {
  69         unsigned int i;
  70         u32 val;
  71
  72         if (!is_power_of_2(mgmtdev->max_write_request) ||
  73             (mgmtdev->max_write_request < 128) ||
  74             (mgmtdev->max_write_request > 1024)) {
  75                 dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
  76                         mgmtdev->max_write_request);
  77                 return -EINVAL;
  78         }
  79
  80         if (!is_power_of_2(mgmtdev->max_read_request) ||
  81             (mgmtdev->max_read_request < 128) ||
  82             (mgmtdev->max_read_request > 1024)) {
  83                 dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
  84                         mgmtdev->max_read_request);
  85                 return -EINVAL;
  86         }
  87
  88         if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
  89                 dev_err(&mgmtdev->pdev->dev,
  90                         "max_wr_xactions cannot be bigger than %ld\n",
  91                         HIDMA_MAX_WR_XACTIONS_MASK);
  92                 return -EINVAL;
  93         }
  94
  95         if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
  96                 dev_err(&mgmtdev->pdev->dev,
  97                         "max_rd_xactions cannot be bigger than %ld\n",
  98                         HIDMA_MAX_RD_XACTIONS_MASK);
  99                 return -EINVAL;
 100         }
 101
 102         for (i = 0; i < mgmtdev->dma_channels; i++) {
 103                 if (mgmtdev->priority[i] > 1) {
 104                         dev_err(&mgmtdev->pdev->dev,
 105                                 "priority can be 0 or 1\n");
 106                         return -EINVAL;
 107                 }
 108
 109                 if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
 110                         dev_err(&mgmtdev->pdev->dev,
 111                                 "max value of weight can be %d.\n",
 112                                 HIDMA_MAX_CHANNEL_WEIGHT);
 113                         return -EINVAL;
 114                 }
 115
 116                 /* weight needs to be at least one */
 117                 if (mgmtdev->weight[i] == 0)
 118                         mgmtdev->weight[i] = 1;
 119         }
 120
 121         pm_runtime_get_sync(&mgmtdev->pdev->dev);
 122         val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
 123         val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
 124         val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
 125         val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
 126         val |= mgmtdev->max_read_request;
 127         writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
 128
 129         val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
 130         val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
 131         val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
 132         val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
 133         val |= mgmtdev->max_rd_xactions;
 134         writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
 135
 136         mgmtdev->hw_version =
 137             readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
 138         mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
 139         mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
 140
 141         for (i = 0; i < mgmtdev->dma_channels; i++) {
 142                 u32 weight = mgmtdev->weight[i];
 143                 u32 priority = mgmtdev->priority[i];
 144
 145                 val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
 146                 val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
 147                 val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
 148                 val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
 149                 val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
 150                 writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
 151         }
 152
 153         val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
 154         val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
 155         val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
 156         writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
 157
 158         pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
 159         pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
 160         return 0;
 161 }
 162 EXPORT_SYMBOL_GPL(hidma_mgmt_setup);
 163
 164 static int hidma_mgmt_probe(struct platform_device *pdev)
 165 {
 166         struct hidma_mgmt_dev *mgmtdev;
 167         struct resource *res;
 168         void __iomem *virtaddr;
 169         int irq;
 170         int rc;
 171         u32 val;
 172
 173         pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
 174         pm_runtime_use_autosuspend(&pdev->dev);
 175         pm_runtime_set_active(&pdev->dev);
 176         pm_runtime_enable(&pdev->dev);
 177         pm_runtime_get_sync(&pdev->dev);
 178
 179         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 180         virtaddr = devm_ioremap_resource(&pdev->dev, res);
 181         if (IS_ERR(virtaddr)) {
 182                 rc = -ENOMEM;
 183                 goto out;
 184         }
 185
 186         irq = platform_get_irq(pdev, 0);
 187         if (irq < 0) {
 188                 rc = irq;
 189                 goto out;
 190         }
 191
 192         mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
 193         if (!mgmtdev) {
 194                 rc = -ENOMEM;
 195                 goto out;
 196         }
 197
 198         mgmtdev->pdev = pdev;
 199         mgmtdev->addrsize = resource_size(res);
 200         mgmtdev->virtaddr = virtaddr;
 201
 202         rc = device_property_read_u32(&pdev->dev, "dma-channels",
 203                                       &mgmtdev->dma_channels);
 204         if (rc) {
 205                 dev_err(&pdev->dev, "number of channels missing\n");
 206                 goto out;
 207         }
 208
 209         rc = device_property_read_u32(&pdev->dev,
 210                                       "channel-reset-timeout-cycles",
 211                                       &mgmtdev->chreset_timeout_cycles);
 212         if (rc) {
 213                 dev_err(&pdev->dev, "channel reset timeout missing\n");
 214                 goto out;
 215         }
 216
 217         rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",
 218                                       &mgmtdev->max_write_request);
 219         if (rc) {
 220                 dev_err(&pdev->dev, "max-write-burst-bytes missing\n");
 221                 goto out;
 222         }
 223
 224         if (max_write_request &&
 225                         (max_write_request != mgmtdev->max_write_request)) {
 226                 dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n",
 227                         max_write_request);
 228                 mgmtdev->max_write_request = max_write_request;
 229         } else
 230                 max_write_request = mgmtdev->max_write_request;
 231
 232         rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",
 233                                       &mgmtdev->max_read_request);
 234         if (rc) {
 235                 dev_err(&pdev->dev, "max-read-burst-bytes missing\n");
 236                 goto out;
 237         }
 238         if (max_read_request &&
 239                         (max_read_request != mgmtdev->max_read_request)) {
 240                 dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n",
 241                         max_read_request);
 242                 mgmtdev->max_read_request = max_read_request;
 243         } else
 244                 max_read_request = mgmtdev->max_read_request;
 245
 246         rc = device_property_read_u32(&pdev->dev, "max-write-transactions",
 247                                       &mgmtdev->max_wr_xactions);
 248         if (rc) {
 249                 dev_err(&pdev->dev, "max-write-transactions missing\n");
 250                 goto out;
 251         }
 252         if (max_wr_xactions &&
 253                         (max_wr_xactions != mgmtdev->max_wr_xactions)) {
 254                 dev_info(&pdev->dev, "overriding max-write-transactions: %d\n",
 255                         max_wr_xactions);
 256                 mgmtdev->max_wr_xactions = max_wr_xactions;
 257         } else
 258                 max_wr_xactions = mgmtdev->max_wr_xactions;
 259
 260         rc = device_property_read_u32(&pdev->dev, "max-read-transactions",
 261                                       &mgmtdev->max_rd_xactions);
 262         if (rc) {
 263                 dev_err(&pdev->dev, "max-read-transactions missing\n");
 264                 goto out;
 265         }
 266         if (max_rd_xactions &&
 267                         (max_rd_xactions != mgmtdev->max_rd_xactions)) {
 268                 dev_info(&pdev->dev, "overriding max-read-transactions: %d\n",
 269                         max_rd_xactions);
 270                 mgmtdev->max_rd_xactions = max_rd_xactions;
 271         } else
 272                 max_rd_xactions = mgmtdev->max_rd_xactions;
 273
 274         mgmtdev->priority = devm_kcalloc(&pdev->dev,
 275                                          mgmtdev->dma_channels,
 276                                          sizeof(*mgmtdev->priority),
 277                                          GFP_KERNEL);
 278         if (!mgmtdev->priority) {
 279                 rc = -ENOMEM;
 280                 goto out;
 281         }
 282
 283         mgmtdev->weight = devm_kcalloc(&pdev->dev,
 284                                        mgmtdev->dma_channels,
 285                                        sizeof(*mgmtdev->weight), GFP_KERNEL);
 286         if (!mgmtdev->weight) {
 287                 rc = -ENOMEM;
 288                 goto out;
 289         }
 290
 291         rc = hidma_mgmt_setup(mgmtdev);
 292         if (rc) {
 293                 dev_err(&pdev->dev, "setup failed\n");
 294                 goto out;
 295         }
 296
 297         /* start the HW */
 298         val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
 299         val |= 1;
 300         writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
 301
 302         rc = hidma_mgmt_init_sys(mgmtdev);
 303         if (rc) {
 304                 dev_err(&pdev->dev, "sysfs setup failed\n");
 305                 goto out;
 306         }
 307
 308         dev_info(&pdev->dev,
 309                  "HW rev: %d.%d @ %pa with %d physical channels\n",
 310                  mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
 311                  &res->start, mgmtdev->dma_channels);
 312
 313         platform_set_drvdata(pdev, mgmtdev);
 314         pm_runtime_mark_last_busy(&pdev->dev);
 315         pm_runtime_put_autosuspend(&pdev->dev);
 316         return 0;
 317 out:
 318         pm_runtime_put_sync_suspend(&pdev->dev);
 319         pm_runtime_disable(&pdev->dev);
 320         return rc;
 321 }
 322
 323 #if IS_ENABLED(CONFIG_ACPI)
 324 static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {
 325         {"QCOM8060"},
 326         {},
 327 };
 328 MODULE_DEVICE_TABLE(acpi, hidma_mgmt_acpi_ids);
 329 #endif
 330
 331 static const struct of_device_id hidma_mgmt_match[] = {
 332         {.compatible = "qcom,hidma-mgmt-1.0",},
 333         {},
 334 };
 335 MODULE_DEVICE_TABLE(of, hidma_mgmt_match);
 336
 337 static struct platform_driver hidma_mgmt_driver = {
 338         .probe = hidma_mgmt_probe,
 339         .driver = {
 340                    .name = "hidma-mgmt",
 341                    .of_match_table = hidma_mgmt_match,
 342                    .acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),
 343         },
 344 };
 345
 346 #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
 347 static int object_counter;
 348
 349 static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
 350 {
 351         struct platform_device *pdev_parent = of_find_device_by_node(np);
 352         struct platform_device_info pdevinfo;
 353         struct device_node *child;
 354         struct resource *res;
 355         int ret = 0;
 356
 357         /* allocate a resource array */
 358         res = kcalloc(3, sizeof(*res), GFP_KERNEL);
 359         if (!res)
 360                 return -ENOMEM;
 361
 362         for_each_available_child_of_node(np, child) {
 363                 struct platform_device *new_pdev;
 364
 365                 ret = of_address_to_resource(child, 0, &res[0]);
 366                 if (!ret)
 367                         goto out;
 368
 369                 ret = of_address_to_resource(child, 1, &res[1]);
 370                 if (!ret)
 371                         goto out;
 372
 373                 ret = of_irq_to_resource(child, 0, &res[2]);
 374                 if (ret <= 0)
 375                         goto out;
 376
 377                 memset(&pdevinfo, 0, sizeof(pdevinfo));
 378                 pdevinfo.fwnode = &child->fwnode;
 379                 pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL;
 380                 pdevinfo.name = child->name;
 381                 pdevinfo.id = object_counter++;
 382                 pdevinfo.res = res;
 383                 pdevinfo.num_res = 3;
 384                 pdevinfo.data = NULL;
 385                 pdevinfo.size_data = 0;
 386                 pdevinfo.dma_mask = DMA_BIT_MASK(64);
 387                 new_pdev = platform_device_register_full(&pdevinfo);
 388                 if (IS_ERR(new_pdev)) {
 389                         ret = PTR_ERR(new_pdev);
 390                         goto out;
 391                 }
 392                 new_pdev->dev.of_node = child;
 393                 of_dma_configure(&new_pdev->dev, child, true);
 394                 /*
 395                  * It is assumed that calling of_msi_configure is safe on
 396                  * platforms with or without MSI support.
 397                  */
 398                 of_msi_configure(&new_pdev->dev, child);
 399         }
 400
 401         kfree(res);
 402
 403         return ret;
 404
 405 out:
 406         of_node_put(child);
 407         kfree(res);
 408
 409         return ret;
 410 }
 411 #endif
 412
 413 static int __init hidma_mgmt_init(void)
 414 {
 415 #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
 416         struct device_node *child;
 417
 418         for_each_matching_node(child, hidma_mgmt_match) {
 419                 /* device tree based firmware here */
 420                 hidma_mgmt_of_populate_channels(child);
 421         }
 422 #endif
 423         /*
 424          * We do not check for return value here, as it is assumed that
 425          * platform_driver_register must not fail. The reason for this is that
 426          * the (potential) hidma_mgmt_of_populate_channels calls above are not
 427          * cleaned up if it does fail, and to do this work is quite
 428          * complicated. In particular, various calls of of_address_to_resource,
 429          * of_irq_to_resource, platform_device_register_full, of_dma_configure,
 430          * and of_msi_configure which then call other functions and so on, must
 431          * be cleaned up - this is not a trivial exercise.
 432          *
 433          * Currently, this module is not intended to be unloaded, and there is
 434          * no module_exit function defined which does the needed cleanup. For
 435          * this reason, we have to assume success here.
 436          */
 437         platform_driver_register(&hidma_mgmt_driver);
 438
 439         return 0;
 440 }
 441 module_init(hidma_mgmt_init);
 442 MODULE_LICENSE("GPL v2");