1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #include <linux/init.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/slab.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/workqueue.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <linux/device.h>
15 #include <linux/idr.h>
16 #include <linux/iommu.h>
17 #include <uapi/linux/idxd.h>
18 #include <linux/dmaengine.h>
19 #include "../dmaengine.h"
20 #include "registers.h"
24 MODULE_VERSION(IDXD_DRIVER_VERSION);
25 MODULE_LICENSE("GPL v2");
26 MODULE_AUTHOR("Intel Corporation");
27 MODULE_IMPORT_NS(IDXD);
29 static bool sva = true;
30 module_param(sva, bool, 0644);
31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off");
34 module_param(tc_override, bool, 0644);
35 MODULE_PARM_DESC(tc_override, "Override traffic class defaults");
37 #define DRV_NAME "idxd"
42 static struct idxd_driver_data idxd_driver_data[] = {
45 .type = IDXD_TYPE_DSA,
46 .compl_size = sizeof(struct dsa_completion_record),
48 .dev_type = &dsa_device_type,
49 .evl_cr_off = offsetof(struct dsa_evl_entry, cr),
50 .cr_status_off = offsetof(struct dsa_completion_record, status),
51 .cr_result_off = offsetof(struct dsa_completion_record, result),
55 .type = IDXD_TYPE_IAX,
56 .compl_size = sizeof(struct iax_completion_record),
58 .dev_type = &iax_device_type,
59 .evl_cr_off = offsetof(struct iax_evl_entry, cr),
60 .cr_status_off = offsetof(struct iax_completion_record, status),
61 .cr_result_off = offsetof(struct iax_completion_record, error_code),
65 static struct pci_device_id idxd_pci_tbl[] = {
66 /* DSA ver 1.0 platforms */
67 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) },
69 /* IAX ver 1.0 platforms */
70 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) },
73 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl);
75 static int idxd_setup_interrupts(struct idxd_device *idxd)
77 struct pci_dev *pdev = idxd->pdev;
78 struct device *dev = &pdev->dev;
79 struct idxd_irq_entry *ie;
83 msixcnt = pci_msix_vec_count(pdev);
85 dev_err(dev, "Not MSI-X interrupt capable.\n");
88 idxd->irq_cnt = msixcnt;
90 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX);
92 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc);
95 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt);
98 ie = idxd_get_ie(idxd, 0);
99 ie->vector = pci_irq_vector(pdev, 0);
100 rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie);
102 dev_err(dev, "Failed to allocate misc interrupt.\n");
105 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector);
107 for (i = 0; i < idxd->max_wqs; i++) {
108 int msix_idx = i + 1;
110 ie = idxd_get_ie(idxd, msix_idx);
112 ie->int_handle = INVALID_INT_HANDLE;
113 ie->pasid = IOMMU_PASID_INVALID;
115 spin_lock_init(&ie->list_lock);
116 init_llist_head(&ie->pending_llist);
117 INIT_LIST_HEAD(&ie->work_list);
120 idxd_unmask_error_interrupts(idxd);
124 idxd_mask_error_interrupts(idxd);
125 pci_free_irq_vectors(pdev);
126 dev_err(dev, "No usable interrupts\n");
130 static void idxd_cleanup_interrupts(struct idxd_device *idxd)
132 struct pci_dev *pdev = idxd->pdev;
133 struct idxd_irq_entry *ie;
136 msixcnt = pci_msix_vec_count(pdev);
140 ie = idxd_get_ie(idxd, 0);
141 idxd_mask_error_interrupts(idxd);
142 free_irq(ie->vector, ie);
143 pci_free_irq_vectors(pdev);
146 static int idxd_setup_wqs(struct idxd_device *idxd)
148 struct device *dev = &idxd->pdev->dev;
150 struct device *conf_dev;
153 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *),
154 GFP_KERNEL, dev_to_node(dev));
158 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev));
159 if (!idxd->wq_enable_map) {
164 for (i = 0; i < idxd->max_wqs; i++) {
165 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev));
171 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ);
172 conf_dev = wq_confdev(wq);
175 device_initialize(wq_confdev(wq));
176 conf_dev->parent = idxd_confdev(idxd);
177 conf_dev->bus = &dsa_bus_type;
178 conf_dev->type = &idxd_wq_device_type;
179 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id);
181 put_device(conf_dev);
185 mutex_init(&wq->wq_lock);
186 init_waitqueue_head(&wq->err_queue);
187 init_completion(&wq->wq_dead);
188 init_completion(&wq->wq_resurrect);
189 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER;
190 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH);
191 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
192 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev));
194 put_device(conf_dev);
199 if (idxd->hw.wq_cap.op_config) {
200 wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL);
201 if (!wq->opcap_bmap) {
202 put_device(conf_dev);
206 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS);
208 mutex_init(&wq->uc_lock);
209 xa_init(&wq->upasid_xa);
218 conf_dev = wq_confdev(wq);
219 put_device(conf_dev);
224 static int idxd_setup_engines(struct idxd_device *idxd)
226 struct idxd_engine *engine;
227 struct device *dev = &idxd->pdev->dev;
228 struct device *conf_dev;
231 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *),
232 GFP_KERNEL, dev_to_node(dev));
236 for (i = 0; i < idxd->max_engines; i++) {
237 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev));
243 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE);
244 conf_dev = engine_confdev(engine);
247 device_initialize(conf_dev);
248 conf_dev->parent = idxd_confdev(idxd);
249 conf_dev->bus = &dsa_bus_type;
250 conf_dev->type = &idxd_engine_device_type;
251 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id);
253 put_device(conf_dev);
257 idxd->engines[i] = engine;
264 engine = idxd->engines[i];
265 conf_dev = engine_confdev(engine);
266 put_device(conf_dev);
271 static int idxd_setup_groups(struct idxd_device *idxd)
273 struct device *dev = &idxd->pdev->dev;
274 struct device *conf_dev;
275 struct idxd_group *group;
278 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *),
279 GFP_KERNEL, dev_to_node(dev));
283 for (i = 0; i < idxd->max_groups; i++) {
284 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev));
290 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP);
291 conf_dev = group_confdev(group);
294 device_initialize(conf_dev);
295 conf_dev->parent = idxd_confdev(idxd);
296 conf_dev->bus = &dsa_bus_type;
297 conf_dev->type = &idxd_group_device_type;
298 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id);
300 put_device(conf_dev);
304 idxd->groups[i] = group;
305 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
313 * The default value is the same as the value of
314 * total read buffers in GRPCAP.
316 group->rdbufs_allowed = idxd->max_rdbufs;
323 group = idxd->groups[i];
324 put_device(group_confdev(group));
329 static void idxd_cleanup_internals(struct idxd_device *idxd)
333 for (i = 0; i < idxd->max_groups; i++)
334 put_device(group_confdev(idxd->groups[i]));
335 for (i = 0; i < idxd->max_engines; i++)
336 put_device(engine_confdev(idxd->engines[i]));
337 for (i = 0; i < idxd->max_wqs; i++)
338 put_device(wq_confdev(idxd->wqs[i]));
339 destroy_workqueue(idxd->wq);
342 static int idxd_init_evl(struct idxd_device *idxd)
344 struct device *dev = &idxd->pdev->dev;
345 struct idxd_evl *evl;
347 if (idxd->hw.gen_cap.evl_support == 0)
350 evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev));
354 spin_lock_init(&evl->lock);
355 evl->size = IDXD_EVL_SIZE_MIN;
357 idxd->evl_cache = kmem_cache_create(dev_name(idxd_confdev(idxd)),
358 sizeof(struct idxd_evl_fault) + evl_ent_size(idxd),
360 if (!idxd->evl_cache) {
369 static int idxd_setup_internals(struct idxd_device *idxd)
371 struct device *dev = &idxd->pdev->dev;
374 init_waitqueue_head(&idxd->cmd_waitq);
376 rc = idxd_setup_wqs(idxd);
380 rc = idxd_setup_engines(idxd);
384 rc = idxd_setup_groups(idxd);
388 idxd->wq = create_workqueue(dev_name(dev));
394 rc = idxd_init_evl(idxd);
401 destroy_workqueue(idxd->wq);
403 for (i = 0; i < idxd->max_groups; i++)
404 put_device(group_confdev(idxd->groups[i]));
406 for (i = 0; i < idxd->max_engines; i++)
407 put_device(engine_confdev(idxd->engines[i]));
409 for (i = 0; i < idxd->max_wqs; i++)
410 put_device(wq_confdev(idxd->wqs[i]));
415 static void idxd_read_table_offsets(struct idxd_device *idxd)
417 union offsets_reg offsets;
418 struct device *dev = &idxd->pdev->dev;
420 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET);
421 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64));
422 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT;
423 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset);
424 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT;
425 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset);
426 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT;
427 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset);
428 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT;
429 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset);
432 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count)
436 for (i = 0, nr = 0; i < count; i++) {
437 for (j = 0; j < BITS_PER_LONG_LONG; j++) {
445 static void idxd_read_caps(struct idxd_device *idxd)
447 struct device *dev = &idxd->pdev->dev;
450 /* reading generic capabilities */
451 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET);
452 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits);
454 if (idxd->hw.gen_cap.cmd_cap) {
455 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET);
456 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap);
459 /* reading command capabilities */
460 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))
461 idxd->request_int_handles = true;
463 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift;
464 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes);
465 idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift);
466 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size);
467 if (idxd->hw.gen_cap.config_en)
468 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags);
470 /* reading group capabilities */
471 idxd->hw.group_cap.bits =
472 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET);
473 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits);
474 idxd->max_groups = idxd->hw.group_cap.num_groups;
475 dev_dbg(dev, "max groups: %u\n", idxd->max_groups);
476 idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs;
477 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs);
478 idxd->nr_rdbufs = idxd->max_rdbufs;
480 /* read engine capabilities */
481 idxd->hw.engine_cap.bits =
482 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET);
483 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits);
484 idxd->max_engines = idxd->hw.engine_cap.num_engines;
485 dev_dbg(dev, "max engines: %u\n", idxd->max_engines);
487 /* read workqueue capabilities */
488 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET);
489 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits);
490 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size;
491 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size);
492 idxd->max_wqs = idxd->hw.wq_cap.num_wqs;
493 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs);
494 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN);
495 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size);
497 /* reading operation capabilities */
498 for (i = 0; i < 4; i++) {
499 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base +
500 IDXD_OPCAP_OFFSET + i * sizeof(u64));
501 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]);
503 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4);
506 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2)
507 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET);
510 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data)
512 struct device *dev = &pdev->dev;
513 struct device *conf_dev;
514 struct idxd_device *idxd;
517 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev));
521 conf_dev = idxd_confdev(idxd);
524 idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type);
525 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL);
529 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev));
530 if (!idxd->opcap_bmap) {
531 ida_free(&idxd_ida, idxd->id);
535 device_initialize(conf_dev);
536 conf_dev->parent = dev;
537 conf_dev->bus = &dsa_bus_type;
538 conf_dev->type = idxd->data->dev_type;
539 rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id);
541 put_device(conf_dev);
545 spin_lock_init(&idxd->dev_lock);
546 spin_lock_init(&idxd->cmd_lock);
551 static int idxd_enable_system_pasid(struct idxd_device *idxd)
556 static void idxd_disable_system_pasid(struct idxd_device *idxd)
559 iommu_sva_unbind_device(idxd->sva);
563 static int idxd_enable_sva(struct pci_dev *pdev)
567 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
571 ret = iommu_dev_enable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
573 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
578 static void idxd_disable_sva(struct pci_dev *pdev)
580 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);
581 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);
584 static int idxd_probe(struct idxd_device *idxd)
586 struct pci_dev *pdev = idxd->pdev;
587 struct device *dev = &pdev->dev;
590 dev_dbg(dev, "%s entered and resetting device\n", __func__);
591 rc = idxd_device_init_reset(idxd);
595 dev_dbg(dev, "IDXD reset complete\n");
597 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) {
598 if (idxd_enable_sva(pdev)) {
599 dev_warn(dev, "Unable to turn on user SVA feature.\n");
601 set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags);
603 if (idxd_enable_system_pasid(idxd))
604 dev_warn(dev, "No in-kernel DMA with PASID.\n");
606 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags);
609 dev_warn(dev, "User forced SVA off via module param.\n");
612 idxd_read_caps(idxd);
613 idxd_read_table_offsets(idxd);
615 rc = idxd_setup_internals(idxd);
619 /* If the configs are readonly, then load them from device */
620 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
621 dev_dbg(dev, "Loading RO device config\n");
622 rc = idxd_device_load_config(idxd);
627 rc = idxd_setup_interrupts(idxd);
631 idxd->major = idxd_cdev_get_major(idxd);
633 rc = perfmon_pmu_init(idxd);
635 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc);
637 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id);
641 idxd_cleanup_internals(idxd);
643 if (device_pasid_enabled(idxd))
644 idxd_disable_system_pasid(idxd);
645 if (device_user_pasid_enabled(idxd))
646 idxd_disable_sva(pdev);
650 static void idxd_cleanup(struct idxd_device *idxd)
652 perfmon_pmu_remove(idxd);
653 idxd_cleanup_interrupts(idxd);
654 idxd_cleanup_internals(idxd);
655 if (device_pasid_enabled(idxd))
656 idxd_disable_system_pasid(idxd);
657 if (device_user_pasid_enabled(idxd))
658 idxd_disable_sva(idxd->pdev);
661 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
663 struct device *dev = &pdev->dev;
664 struct idxd_device *idxd;
665 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data;
668 rc = pci_enable_device(pdev);
672 dev_dbg(dev, "Alloc IDXD context\n");
673 idxd = idxd_alloc(pdev, data);
679 dev_dbg(dev, "Mapping BARs\n");
680 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0);
681 if (!idxd->reg_base) {
686 dev_dbg(dev, "Set DMA masks\n");
687 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
691 dev_dbg(dev, "Set PCI master\n");
692 pci_set_master(pdev);
693 pci_set_drvdata(pdev, idxd);
695 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET);
696 rc = idxd_probe(idxd);
698 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n");
702 rc = idxd_register_devices(idxd);
704 dev_err(dev, "IDXD sysfs setup failed\n");
705 goto err_dev_register;
708 rc = idxd_device_init_debugfs(idxd);
710 dev_warn(dev, "IDXD debugfs failed to setup\n");
712 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n",
720 pci_iounmap(pdev, idxd->reg_base);
722 put_device(idxd_confdev(idxd));
724 pci_disable_device(pdev);
728 void idxd_wqs_quiesce(struct idxd_device *idxd)
733 for (i = 0; i < idxd->max_wqs; i++) {
735 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL)
740 static void idxd_shutdown(struct pci_dev *pdev)
742 struct idxd_device *idxd = pci_get_drvdata(pdev);
743 struct idxd_irq_entry *irq_entry;
746 rc = idxd_device_disable(idxd);
748 dev_err(&pdev->dev, "Disabling device failed\n");
750 irq_entry = &idxd->ie;
751 synchronize_irq(irq_entry->vector);
752 idxd_mask_error_interrupts(idxd);
753 flush_workqueue(idxd->wq);
756 static void idxd_remove(struct pci_dev *pdev)
758 struct idxd_device *idxd = pci_get_drvdata(pdev);
759 struct idxd_irq_entry *irq_entry;
761 idxd_unregister_devices(idxd);
763 * When ->release() is called for the idxd->conf_dev, it frees all the memory related
764 * to the idxd context. The driver still needs those bits in order to do the rest of
765 * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref
766 * on the device here to hold off the freeing while allowing the idxd sub-driver
769 get_device(idxd_confdev(idxd));
770 device_unregister(idxd_confdev(idxd));
772 if (device_pasid_enabled(idxd))
773 idxd_disable_system_pasid(idxd);
774 idxd_device_remove_debugfs(idxd);
776 irq_entry = idxd_get_ie(idxd, 0);
777 free_irq(irq_entry->vector, irq_entry);
778 pci_free_irq_vectors(pdev);
779 pci_iounmap(pdev, idxd->reg_base);
780 if (device_user_pasid_enabled(idxd))
781 idxd_disable_sva(pdev);
782 pci_disable_device(pdev);
783 destroy_workqueue(idxd->wq);
784 perfmon_pmu_remove(idxd);
785 put_device(idxd_confdev(idxd));
788 static struct pci_driver idxd_pci_driver = {
790 .id_table = idxd_pci_tbl,
791 .probe = idxd_pci_probe,
792 .remove = idxd_remove,
793 .shutdown = idxd_shutdown,
796 static int __init idxd_init_module(void)
801 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in
802 * enumerating the device. We can not utilize it.
804 if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) {
805 pr_warn("idxd driver failed to load without MOVDIR64B.\n");
809 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD))
810 pr_warn("Platform does not have ENQCMD(S) support.\n");
812 support_enqcmd = true;
816 err = idxd_driver_register(&idxd_drv);
818 goto err_idxd_driver_register;
820 err = idxd_driver_register(&idxd_dmaengine_drv);
822 goto err_idxd_dmaengine_driver_register;
824 err = idxd_driver_register(&idxd_user_drv);
826 goto err_idxd_user_driver_register;
828 err = idxd_cdev_register();
830 goto err_cdev_register;
832 err = idxd_init_debugfs();
836 err = pci_register_driver(&idxd_pci_driver);
838 goto err_pci_register;
843 idxd_remove_debugfs();
847 idxd_driver_unregister(&idxd_user_drv);
848 err_idxd_user_driver_register:
849 idxd_driver_unregister(&idxd_dmaengine_drv);
850 err_idxd_dmaengine_driver_register:
851 idxd_driver_unregister(&idxd_drv);
852 err_idxd_driver_register:
855 module_init(idxd_init_module);
857 static void __exit idxd_exit_module(void)
859 idxd_driver_unregister(&idxd_user_drv);
860 idxd_driver_unregister(&idxd_dmaengine_drv);
861 idxd_driver_unregister(&idxd_drv);
862 pci_unregister_driver(&idxd_pci_driver);
865 idxd_remove_debugfs();
867 module_exit(idxd_exit_module);