drivers/nvmem/imx-ocotp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * i.MX6 OCOTP fusebox driver
   4  *
   5  * Copyright (c) 2015 Pengutronix, Philipp Zabel <[email protected]>
   6  *
   7  * Based on the barebox ocotp driver,
   8  * Copyright (c) 2010 Baruch Siach <[email protected]>,
   9  *      Orex Computed Radiography
  10  *
  11  * Write support based on the fsl_otp driver,
  12  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/device.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/nvmem-provider.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/slab.h>
  24 #include <linux/delay.h>
  25
  26 #define IMX_OCOTP_OFFSET_B0W0           0x400 /* Offset from base address of the
  27                                                * OTP Bank0 Word0
  28                                                */
  29 #define IMX_OCOTP_OFFSET_PER_WORD       0x10  /* Offset between the start addr
  30                                                * of two consecutive OTP words.
  31                                                */
  32
  33 #define IMX_OCOTP_ADDR_CTRL             0x0000
  34 #define IMX_OCOTP_ADDR_CTRL_SET         0x0004
  35 #define IMX_OCOTP_ADDR_CTRL_CLR         0x0008
  36 #define IMX_OCOTP_ADDR_TIMING           0x0010
  37 #define IMX_OCOTP_ADDR_DATA0            0x0020
  38 #define IMX_OCOTP_ADDR_DATA1            0x0030
  39 #define IMX_OCOTP_ADDR_DATA2            0x0040
  40 #define IMX_OCOTP_ADDR_DATA3            0x0050
  41
  42 #define IMX_OCOTP_BM_CTRL_ADDR          0x000000FF
  43 #define IMX_OCOTP_BM_CTRL_BUSY          0x00000100
  44 #define IMX_OCOTP_BM_CTRL_ERROR         0x00000200
  45 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS   0x00000400
  46
  47 #define IMX_OCOTP_BM_CTRL_DEFAULT                               \
  48         {                                                       \
  49                 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR,              \
  50                 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY,              \
  51                 .bm_error = IMX_OCOTP_BM_CTRL_ERROR,            \
  52                 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
  53         }
  54
  55 #define TIMING_STROBE_PROG_US           10      /* Min time to blow a fuse */
  56 #define TIMING_STROBE_READ_NS           37      /* Min time before read */
  57 #define TIMING_RELAX_NS                 17
  58 #define DEF_FSOURCE                     1001    /* > 1000 ns */
  59 #define DEF_STROBE_PROG                 10000   /* IPG clocks */
  60 #define IMX_OCOTP_WR_UNLOCK             0x3E770000
  61 #define IMX_OCOTP_READ_LOCKED_VAL       0xBADABADA
  62
  63 static DEFINE_MUTEX(ocotp_mutex);
  64
  65 struct ocotp_priv {
  66         struct device *dev;
  67         struct clk *clk;
  68         void __iomem *base;
  69         const struct ocotp_params *params;
  70         struct nvmem_config *config;
  71 };
  72
  73 struct ocotp_ctrl_reg {
  74         u32 bm_addr;
  75         u32 bm_busy;
  76         u32 bm_error;
  77         u32 bm_rel_shadows;
  78 };
  79
  80 struct ocotp_params {
  81         unsigned int nregs;
  82         unsigned int bank_address_words;
  83         void (*set_timing)(struct ocotp_priv *priv);
  84         struct ocotp_ctrl_reg ctrl;
  85 };
  86
  87 static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
  88 {
  89         int count;
  90         u32 c, mask;
  91         u32 bm_ctrl_busy, bm_ctrl_error;
  92         void __iomem *base = priv->base;
  93
  94         bm_ctrl_busy = priv->params->ctrl.bm_busy;
  95         bm_ctrl_error = priv->params->ctrl.bm_error;
  96
  97         mask = bm_ctrl_busy | bm_ctrl_error | flags;
  98
  99         for (count = 10000; count >= 0; count--) {
 100                 c = readl(base + IMX_OCOTP_ADDR_CTRL);
 101                 if (!(c & mask))
 102                         break;
 103                 cpu_relax();
 104         }
 105
 106         if (count < 0) {
 107                 /* HW_OCOTP_CTRL[ERROR] will be set under the following
 108                  * conditions:
 109                  * - A write is performed to a shadow register during a shadow
 110                  *   reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
 111                  *   set. In addition, the contents of the shadow register shall
 112                  *   not be updated.
 113                  * - A write is performed to a shadow register which has been
 114                  *   locked.
 115                  * - A read is performed to from a shadow register which has
 116                  *   been read locked.
 117                  * - A program is performed to a fuse word which has been locked
 118                  * - A read is performed to from a fuse word which has been read
 119                  *   locked.
 120                  */
 121                 if (c & bm_ctrl_error)
 122                         return -EPERM;
 123                 return -ETIMEDOUT;
 124         }
 125
 126         return 0;
 127 }
 128
 129 static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
 130 {
 131         u32 c, bm_ctrl_error;
 132         void __iomem *base = priv->base;
 133
 134         bm_ctrl_error = priv->params->ctrl.bm_error;
 135
 136         c = readl(base + IMX_OCOTP_ADDR_CTRL);
 137         if (!(c & bm_ctrl_error))
 138                 return;
 139
 140         writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
 141 }
 142
 143 static int imx_ocotp_read(void *context, unsigned int offset,
 144                           void *val, size_t bytes)
 145 {
 146         struct ocotp_priv *priv = context;
 147         unsigned int count;
 148         u32 *buf = val;
 149         int i, ret;
 150         u32 index;
 151
 152         index = offset >> 2;
 153         count = bytes >> 2;
 154
 155         if (count > (priv->params->nregs - index))
 156                 count = priv->params->nregs - index;
 157
 158         mutex_lock(&ocotp_mutex);
 159
 160         ret = clk_prepare_enable(priv->clk);
 161         if (ret < 0) {
 162                 mutex_unlock(&ocotp_mutex);
 163                 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
 164                 return ret;
 165         }
 166
 167         ret = imx_ocotp_wait_for_busy(priv, 0);
 168         if (ret < 0) {
 169                 dev_err(priv->dev, "timeout during read setup\n");
 170                 goto read_end;
 171         }
 172
 173         for (i = index; i < (index + count); i++) {
 174                 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
 175                                i * IMX_OCOTP_OFFSET_PER_WORD);
 176
 177                 /* 47.3.1.2
 178                  * For "read locked" registers 0xBADABADA will be returned and
 179                  * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
 180                  * software before any new write, read or reload access can be
 181                  * issued
 182                  */
 183                 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
 184                         imx_ocotp_clr_err_if_set(priv);
 185         }
 186         ret = 0;
 187
 188 read_end:
 189         clk_disable_unprepare(priv->clk);
 190         mutex_unlock(&ocotp_mutex);
 191         return ret;
 192 }
 193
 194 static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
 195 {
 196         unsigned long clk_rate = 0;
 197         unsigned long strobe_read, relax, strobe_prog;
 198         u32 timing = 0;
 199
 200         /* 47.3.1.3.1
 201          * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
 202          * fields with timing values to match the current frequency of the
 203          * ipg_clk. OTP writes will work at maximum bus frequencies as long
 204          * as the HW_OCOTP_TIMING parameters are set correctly.
 205          *
 206          * Note: there are minimum timings required to ensure an OTP fuse burns
 207          * correctly that are independent of the ipg_clk. Those values are not
 208          * formally documented anywhere however, working from the minimum
 209          * timings given in u-boot we can say:
 210          *
 211          * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
 212          *   microseconds feels about right as representative of a minimum time
 213          *   to physically burn out a fuse.
 214          *
 215          * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
 216          *   performing another read is 37 nanoseconds
 217          *
 218          * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
 219          *   timing is not entirely clear the documentation says "This
 220          *   count value specifies the time to add to all default timing
 221          *   parameters other than the Tpgm and Trd. It is given in number
 222          *   of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
 223          *   and STROBE_READ respectively. What the other timing parameters
 224          *   are though, is not specified. Experience shows a zero RELAX
 225          *   value will mess up a re-load of the shadow registers post OTP
 226          *   burn.
 227          */
 228         clk_rate = clk_get_rate(priv->clk);
 229
 230         relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
 231         strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
 232                                    1000000000);
 233         strobe_read += 2 * (relax + 1) - 1;
 234         strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
 235                                         1000000);
 236         strobe_prog += 2 * (relax + 1) - 1;
 237
 238         timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
 239         timing |= strobe_prog & 0x00000FFF;
 240         timing |= (relax       << 12) & 0x0000F000;
 241         timing |= (strobe_read << 16) & 0x003F0000;
 242
 243         writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
 244 }
 245
 246 static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
 247 {
 248         unsigned long clk_rate = 0;
 249         u64 fsource, strobe_prog;
 250         u32 timing = 0;
 251
 252         /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
 253          * 6.4.3.3
 254          */
 255         clk_rate = clk_get_rate(priv->clk);
 256         fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
 257                                    NSEC_PER_SEC) + 1;
 258         strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
 259                                             NSEC_PER_SEC) + 1;
 260
 261         timing = strobe_prog & 0x00000FFF;
 262         timing |= (fsource << 12) & 0x000FF000;
 263
 264         writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
 265 }
 266
 267 static int imx_ocotp_write(void *context, unsigned int offset, void *val,
 268                            size_t bytes)
 269 {
 270         struct ocotp_priv *priv = context;
 271         u32 *buf = val;
 272         int ret;
 273
 274         u32 ctrl;
 275         u8 waddr;
 276         u8 word = 0;
 277
 278         /* allow only writing one complete OTP word at a time */
 279         if ((bytes != priv->config->word_size) ||
 280             (offset % priv->config->word_size))
 281                 return -EINVAL;
 282
 283         mutex_lock(&ocotp_mutex);
 284
 285         ret = clk_prepare_enable(priv->clk);
 286         if (ret < 0) {
 287                 mutex_unlock(&ocotp_mutex);
 288                 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
 289                 return ret;
 290         }
 291
 292         /* Setup the write timing values */
 293         priv->params->set_timing(priv);
 294
 295         /* 47.3.1.3.2
 296          * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
 297          * Overlapped accesses are not supported by the controller. Any pending
 298          * write or reload must be completed before a write access can be
 299          * requested.
 300          */
 301         ret = imx_ocotp_wait_for_busy(priv, 0);
 302         if (ret < 0) {
 303                 dev_err(priv->dev, "timeout during timing setup\n");
 304                 goto write_end;
 305         }
 306
 307         /* 47.3.1.3.3
 308          * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
 309          * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
 310          * for each write access. The lock code is documented in the register
 311          * description. Both the unlock code and address can be written in the
 312          * same operation.
 313          */
 314         if (priv->params->bank_address_words != 0) {
 315                 /*
 316                  * In banked/i.MX7 mode the OTP register bank goes into waddr
 317                  * see i.MX 7Solo Applications Processor Reference Manual, Rev.
 318                  * 0.1 section 6.4.3.1
 319                  */
 320                 offset = offset / priv->config->word_size;
 321                 waddr = offset / priv->params->bank_address_words;
 322                 word  = offset & (priv->params->bank_address_words - 1);
 323         } else {
 324                 /*
 325                  * Non-banked i.MX6 mode.
 326                  * OTP write/read address specifies one of 128 word address
 327                  * locations
 328                  */
 329                 waddr = offset / 4;
 330         }
 331
 332         ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
 333         ctrl &= ~priv->params->ctrl.bm_addr;
 334         ctrl |= waddr & priv->params->ctrl.bm_addr;
 335         ctrl |= IMX_OCOTP_WR_UNLOCK;
 336
 337         writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
 338
 339         /* 47.3.1.3.4
 340          * Write the data to the HW_OCOTP_DATA register. This will automatically
 341          * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
 342          * protect programming same OTP bit twice, before program OCOTP will
 343          * automatically read fuse value in OTP and use read value to mask
 344          * program data. The controller will use masked program data to program
 345          * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
 346          * fields with 1's will result in that OTP bit being programmed. Bit
 347          * fields with 0's will be ignored. At the same time that the write is
 348          * accepted, the controller makes an internal copy of
 349          * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
 350          * sequence is initiated. This copy guarantees that erroneous writes to
 351          * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
 352          * should also be noted that during the programming HW_OCOTP_DATA will
 353          * shift right (with zero fill). This shifting is required to program
 354          * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
 355          * modified.
 356          * Note: on i.MX7 there are four data fields to write for banked write
 357          *       with the fuse blowing operation only taking place after data0
 358          *       has been written. This is why data0 must always be the last
 359          *       register written.
 360          */
 361         if (priv->params->bank_address_words != 0) {
 362                 /* Banked/i.MX7 mode */
 363                 switch (word) {
 364                 case 0:
 365                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
 366                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
 367                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
 368                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
 369                         break;
 370                 case 1:
 371                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
 372                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
 373                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
 374                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
 375                         break;
 376                 case 2:
 377                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
 378                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
 379                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
 380                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
 381                         break;
 382                 case 3:
 383                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
 384                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
 385                         writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
 386                         writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
 387                         break;
 388                 }
 389         } else {
 390                 /* Non-banked i.MX6 mode */
 391                 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
 392         }
 393
 394         /* 47.4.1.4.5
 395          * Once complete, the controller will clear BUSY. A write request to a
 396          * protected or locked region will result in no OTP access and no
 397          * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
 398          * be set. It must be cleared by software before any new write access
 399          * can be issued.
 400          */
 401         ret = imx_ocotp_wait_for_busy(priv, 0);
 402         if (ret < 0) {
 403                 if (ret == -EPERM) {
 404                         dev_err(priv->dev, "failed write to locked region");
 405                         imx_ocotp_clr_err_if_set(priv);
 406                 } else {
 407                         dev_err(priv->dev, "timeout during data write\n");
 408                 }
 409                 goto write_end;
 410         }
 411
 412         /* 47.3.1.4
 413          * Write Postamble: Due to internal electrical characteristics of the
 414          * OTP during writes, all OTP operations following a write must be
 415          * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
 416          * the write.
 417          */
 418         udelay(2);
 419
 420         /* reload all shadow registers */
 421         writel(priv->params->ctrl.bm_rel_shadows,
 422                priv->base + IMX_OCOTP_ADDR_CTRL_SET);
 423         ret = imx_ocotp_wait_for_busy(priv,
 424                                       priv->params->ctrl.bm_rel_shadows);
 425         if (ret < 0) {
 426                 dev_err(priv->dev, "timeout during shadow register reload\n");
 427                 goto write_end;
 428         }
 429
 430 write_end:
 431         clk_disable_unprepare(priv->clk);
 432         mutex_unlock(&ocotp_mutex);
 433         if (ret < 0)
 434                 return ret;
 435         return bytes;
 436 }
 437
 438 static struct nvmem_config imx_ocotp_nvmem_config = {
 439         .name = "imx-ocotp",
 440         .read_only = false,
 441         .word_size = 4,
 442         .stride = 4,
 443         .reg_read = imx_ocotp_read,
 444         .reg_write = imx_ocotp_write,
 445 };
 446
 447 static const struct ocotp_params imx6q_params = {
 448         .nregs = 128,
 449         .bank_address_words = 0,
 450         .set_timing = imx_ocotp_set_imx6_timing,
 451         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 452 };
 453
 454 static const struct ocotp_params imx6sl_params = {
 455         .nregs = 64,
 456         .bank_address_words = 0,
 457         .set_timing = imx_ocotp_set_imx6_timing,
 458         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 459 };
 460
 461 static const struct ocotp_params imx6sll_params = {
 462         .nregs = 128,
 463         .bank_address_words = 0,
 464         .set_timing = imx_ocotp_set_imx6_timing,
 465         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 466 };
 467
 468 static const struct ocotp_params imx6sx_params = {
 469         .nregs = 128,
 470         .bank_address_words = 0,
 471         .set_timing = imx_ocotp_set_imx6_timing,
 472         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 473 };
 474
 475 static const struct ocotp_params imx6ul_params = {
 476         .nregs = 128,
 477         .bank_address_words = 0,
 478         .set_timing = imx_ocotp_set_imx6_timing,
 479         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 480 };
 481
 482 static const struct ocotp_params imx6ull_params = {
 483         .nregs = 64,
 484         .bank_address_words = 0,
 485         .set_timing = imx_ocotp_set_imx6_timing,
 486         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 487 };
 488
 489 static const struct ocotp_params imx7d_params = {
 490         .nregs = 64,
 491         .bank_address_words = 4,
 492         .set_timing = imx_ocotp_set_imx7_timing,
 493         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 494 };
 495
 496 static const struct ocotp_params imx7ulp_params = {
 497         .nregs = 256,
 498         .bank_address_words = 0,
 499         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 500 };
 501
 502 static const struct ocotp_params imx8mq_params = {
 503         .nregs = 256,
 504         .bank_address_words = 0,
 505         .set_timing = imx_ocotp_set_imx6_timing,
 506         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 507 };
 508
 509 static const struct ocotp_params imx8mm_params = {
 510         .nregs = 256,
 511         .bank_address_words = 0,
 512         .set_timing = imx_ocotp_set_imx6_timing,
 513         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 514 };
 515
 516 static const struct ocotp_params imx8mn_params = {
 517         .nregs = 256,
 518         .bank_address_words = 0,
 519         .set_timing = imx_ocotp_set_imx6_timing,
 520         .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
 521 };
 522
 523 static const struct of_device_id imx_ocotp_dt_ids[] = {
 524         { .compatible = "fsl,imx6q-ocotp",  .data = &imx6q_params },
 525         { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
 526         { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
 527         { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
 528         { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
 529         { .compatible = "fsl,imx7d-ocotp",  .data = &imx7d_params },
 530         { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
 531         { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
 532         { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
 533         { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
 534         { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
 535         { },
 536 };
 537 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
 538
 539 static int imx_ocotp_probe(struct platform_device *pdev)
 540 {
 541         struct device *dev = &pdev->dev;
 542         struct ocotp_priv *priv;
 543         struct nvmem_device *nvmem;
 544
 545         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 546         if (!priv)
 547                 return -ENOMEM;
 548
 549         priv->dev = dev;
 550
 551         priv->base = devm_platform_ioremap_resource(pdev, 0);
 552         if (IS_ERR(priv->base))
 553                 return PTR_ERR(priv->base);
 554
 555         priv->clk = devm_clk_get(dev, NULL);
 556         if (IS_ERR(priv->clk))
 557                 return PTR_ERR(priv->clk);
 558
 559         priv->params = of_device_get_match_data(&pdev->dev);
 560         imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
 561         imx_ocotp_nvmem_config.dev = dev;
 562         imx_ocotp_nvmem_config.priv = priv;
 563         priv->config = &imx_ocotp_nvmem_config;
 564
 565         clk_prepare_enable(priv->clk);
 566         imx_ocotp_clr_err_if_set(priv);
 567         clk_disable_unprepare(priv->clk);
 568
 569         nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
 570
 571         return PTR_ERR_OR_ZERO(nvmem);
 572 }
 573
 574 static struct platform_driver imx_ocotp_driver = {
 575         .probe  = imx_ocotp_probe,
 576         .driver = {
 577                 .name   = "imx_ocotp",
 578                 .of_match_table = imx_ocotp_dt_ids,
 579         },
 580 };
 581 module_platform_driver(imx_ocotp_driver);
 582
 583 MODULE_AUTHOR("Philipp Zabel <[email protected]>");
 584 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
 585 MODULE_LICENSE("GPL v2");