drivers/net/ethernet/qlogic/qed/qed_init_fw_funcs.c

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/crc8.h>
  35 #include <linux/delay.h>
  36 #include <linux/kernel.h>
  37 #include <linux/slab.h>
  38 #include <linux/string.h>
  39 #include "qed_hsi.h"
  40 #include "qed_hw.h"
  41 #include "qed_init_ops.h"
  42 #include "qed_reg_addr.h"
  43
  44 #define CDU_VALIDATION_DEFAULT_CFG      61
  45
  46 static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {
  47         {400, 336, 352, 368, 304, 384, 416, 352},       /* region 3 offsets */
  48         {528, 496, 416, 512, 448, 512, 544, 480},       /* region 4 offsets */
  49         {608, 544, 496, 576, 576, 592, 624, 560}        /* region 5 offsets */
  50 };
  51
  52 static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
  53         {240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
  54 };
  55
  56 /* General constants */
  57 #define QM_PQ_MEM_4KB(pq_size)  (pq_size ? DIV_ROUND_UP((pq_size + 1) * \
  58                                                         QM_PQ_ELEMENT_SIZE, \
  59                                                         0x1000) : 0)
  60 #define QM_PQ_SIZE_256B(pq_size)        (pq_size ? DIV_ROUND_UP(pq_size, \
  61                                                                 0x100) - 1 : 0)
  62 #define QM_INVALID_PQ_ID                0xffff
  63
  64 /* Max link speed (in Mbps) */
  65 #define QM_MAX_LINK_SPEED               100000
  66
  67 /* Feature enable */
  68 #define QM_BYPASS_EN    1
  69 #define QM_BYTE_CRD_EN  1
  70
  71 /* Other PQ constants */
  72 #define QM_OTHER_PQS_PER_PF     4
  73
  74 /* WFQ constants */
  75
  76 /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
  77 #define QM_WFQ_UPPER_BOUND      62500000
  78
  79 /* Bit  of VOQ in WFQ VP PQ map */
  80 #define QM_WFQ_VP_PQ_VOQ_SHIFT  0
  81
  82 /* Bit  of PF in WFQ VP PQ map */
  83 #define QM_WFQ_VP_PQ_PF_E4_SHIFT        5
  84
  85 /* 0x9000 = 4*9*1024 */
  86 #define QM_WFQ_INC_VAL(weight)  ((weight) * 0x9000)
  87
  88 /* Max WFQ increment value is 0.7 * upper bound */
  89 #define QM_WFQ_MAX_INC_VAL      ((QM_WFQ_UPPER_BOUND * 7) / 10)
  90
  91 /* RL constants */
  92
  93 /* Period in us */
  94 #define QM_RL_PERIOD    5
  95
  96 /* Period in 25MHz cycles */
  97 #define QM_RL_PERIOD_CLK_25M    (25 * QM_RL_PERIOD)
  98
  99 /* RL increment value - rate is specified in mbps */
 100 #define QM_RL_INC_VAL(rate) ({ \
 101         typeof(rate) __rate = (rate); \
 102         max_t(u32, \
 103               (u32)(((__rate ? __rate : 1000000) * QM_RL_PERIOD * 101) / \
 104                     (8 * 100)), \
 105               1); })
 106
 107 /* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
 108 #define QM_PF_RL_UPPER_BOUND    62500000
 109
 110 /* Max PF RL increment value is 0.7 * upper bound */
 111 #define QM_PF_RL_MAX_INC_VAL    ((QM_PF_RL_UPPER_BOUND * 7) / 10)
 112
 113 /* Vport RL Upper bound, link speed is in Mpbs */
 114 #define QM_VP_RL_UPPER_BOUND(speed)     ((u32)max_t(u32, \
 115                                                     QM_RL_INC_VAL(speed), \
 116                                                     9700 + 1000))
 117
 118 /* Max Vport RL increment value is the Vport RL upper bound */
 119 #define QM_VP_RL_MAX_INC_VAL(speed)     QM_VP_RL_UPPER_BOUND(speed)
 120
 121 /* Vport RL credit threshold in case of QM bypass */
 122 #define QM_VP_RL_BYPASS_THRESH_SPEED    (QM_VP_RL_UPPER_BOUND(10000) - 1)
 123
 124 /* AFullOprtnstcCrdMask constants */
 125 #define QM_OPPOR_LINE_VOQ_DEF   1
 126 #define QM_OPPOR_FW_STOP_DEF    0
 127 #define QM_OPPOR_PQ_EMPTY_DEF   1
 128
 129 /* Command Queue constants */
 130
 131 /* Pure LB CmdQ lines (+spare) */
 132 #define PBF_CMDQ_PURE_LB_LINES  150
 133
 134 #define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
 135         (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
 136          (ext_voq) * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
 137                 PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
 138
 139 #define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
 140         (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
 141          (ext_voq) * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
 142                 PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
 143
 144 /* Returns the VOQ line credit for the specified number of PBF command lines.
 145  * PBF lines are specified in 256b units.
 146  */
 147 #define QM_VOQ_LINE_CRD(pbf_cmd_lines) \
 148         ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
 149
 150 /* BTB: blocks constants (block size = 256B) */
 151
 152 /* 256B blocks in 9700B packet */
 153 #define BTB_JUMBO_PKT_BLOCKS    38
 154
 155 /* Headroom per-port */
 156 #define BTB_HEADROOM_BLOCKS     BTB_JUMBO_PKT_BLOCKS
 157 #define BTB_PURE_LB_FACTOR      10
 158
 159 /* Factored (hence really 0.7) */
 160 #define BTB_PURE_LB_RATIO       7
 161
 162 /* QM stop command constants */
 163 #define QM_STOP_PQ_MASK_WIDTH           32
 164 #define QM_STOP_CMD_ADDR                2
 165 #define QM_STOP_CMD_STRUCT_SIZE         2
 166 #define QM_STOP_CMD_PAUSE_MASK_OFFSET   0
 167 #define QM_STOP_CMD_PAUSE_MASK_SHIFT    0
 168 #define QM_STOP_CMD_PAUSE_MASK_MASK     -1
 169 #define QM_STOP_CMD_GROUP_ID_OFFSET     1
 170 #define QM_STOP_CMD_GROUP_ID_SHIFT      16
 171 #define QM_STOP_CMD_GROUP_ID_MASK       15
 172 #define QM_STOP_CMD_PQ_TYPE_OFFSET      1
 173 #define QM_STOP_CMD_PQ_TYPE_SHIFT       24
 174 #define QM_STOP_CMD_PQ_TYPE_MASK        1
 175 #define QM_STOP_CMD_MAX_POLL_COUNT      100
 176 #define QM_STOP_CMD_POLL_PERIOD_US      500
 177
 178 /* QM command macros */
 179 #define QM_CMD_STRUCT_SIZE(cmd) cmd ## _STRUCT_SIZE
 180 #define QM_CMD_SET_FIELD(var, cmd, field, value) \
 181         SET_FIELD(var[cmd ## _ ## field ## _OFFSET], \
 182                   cmd ## _ ## field, \
 183                   value)
 184
 185 #define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, vp_pq_id, rl_valid, rl_id, \
 186                           ext_voq, wrr) \
 187         do { \
 188                 typeof(map) __map; \
 189                 memset(&__map, 0, sizeof(__map)); \
 190                 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _PQ_VALID, 1); \
 191                 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_VALID, \
 192                           rl_valid ? 1 : 0);\
 193                 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VP_PQ_ID, \
 194                           vp_pq_id); \
 195                 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _RL_ID, rl_id); \
 196                 SET_FIELD(__map.reg, QM_RF_PQ_MAP_ ## chip ## _VOQ, ext_voq); \
 197                 SET_FIELD(__map.reg, \
 198                           QM_RF_PQ_MAP_ ## chip ## _WRR_WEIGHT_GROUP, wrr); \
 199                 STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \
 200                              *((u32 *)&__map)); \
 201                 (map) = __map; \
 202         } while (0)
 203
 204 #define WRITE_PQ_INFO_TO_RAM    1
 205 #define PQ_INFO_ELEMENT(vp, pf, tc, port, rl_valid, rl) \
 206         (((vp) << 0) | ((pf) << 12) | ((tc) << 16) | ((port) << 20) | \
 207         ((rl_valid ? 1 : 0) << 22) | (((rl) & 255) << 24) | \
 208         (((rl) >> 8) << 9))
 209
 210 #define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \
 211         XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + \
 212         XSTORM_PQ_INFO_OFFSET(pq_id)
 213
 214 /******************** INTERNAL IMPLEMENTATION *********************/
 215
 216 /* Returns the external VOQ number */
 217 static u8 qed_get_ext_voq(struct qed_hwfn *p_hwfn,
 218                           u8 port_id, u8 tc, u8 max_phys_tcs_per_port)
 219 {
 220         if (tc == PURE_LB_TC)
 221                 return NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + port_id;
 222         else
 223                 return port_id * max_phys_tcs_per_port + tc;
 224 }
 225
 226 /* Prepare PF RL enable/disable runtime init values */
 227 static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en)
 228 {
 229         STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
 230         if (pf_rl_en) {
 231                 u8 num_ext_voqs = MAX_NUM_VOQS_E4;
 232                 u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1;
 233
 234                 /* Enable RLs for all VOQs */
 235                 STORE_RT_REG(p_hwfn,
 236                              QM_REG_RLPFVOQENABLE_RT_OFFSET,
 237                              (u32)voq_bit_mask);
 238
 239                 /* Write RL period */
 240                 STORE_RT_REG(p_hwfn,
 241                              QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
 242                 STORE_RT_REG(p_hwfn,
 243                              QM_REG_RLPFPERIODTIMER_RT_OFFSET,
 244                              QM_RL_PERIOD_CLK_25M);
 245
 246                 /* Set credit threshold for QM bypass flow */
 247                 if (QM_BYPASS_EN)
 248                         STORE_RT_REG(p_hwfn,
 249                                      QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
 250                                      QM_PF_RL_UPPER_BOUND);
 251         }
 252 }
 253
 254 /* Prepare PF WFQ enable/disable runtime init values */
 255 static void qed_enable_pf_wfq(struct qed_hwfn *p_hwfn, bool pf_wfq_en)
 256 {
 257         STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
 258
 259         /* Set credit threshold for QM bypass flow */
 260         if (pf_wfq_en && QM_BYPASS_EN)
 261                 STORE_RT_REG(p_hwfn,
 262                              QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET,
 263                              QM_WFQ_UPPER_BOUND);
 264 }
 265
 266 /* Prepare global RL enable/disable runtime init values */
 267 static void qed_enable_global_rl(struct qed_hwfn *p_hwfn, bool global_rl_en)
 268 {
 269         STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET,
 270                      global_rl_en ? 1 : 0);
 271         if (global_rl_en) {
 272                 /* Write RL period (use timer 0 only) */
 273                 STORE_RT_REG(p_hwfn,
 274                              QM_REG_RLGLBLPERIOD_0_RT_OFFSET,
 275                              QM_RL_PERIOD_CLK_25M);
 276                 STORE_RT_REG(p_hwfn,
 277                              QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET,
 278                              QM_RL_PERIOD_CLK_25M);
 279
 280                 /* Set credit threshold for QM bypass flow */
 281                 if (QM_BYPASS_EN)
 282                         STORE_RT_REG(p_hwfn,
 283                                      QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
 284                                      QM_VP_RL_BYPASS_THRESH_SPEED);
 285         }
 286 }
 287
 288 /* Prepare VPORT WFQ enable/disable runtime init values */
 289 static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en)
 290 {
 291         STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET,
 292                      vport_wfq_en ? 1 : 0);
 293
 294         /* Set credit threshold for QM bypass flow */
 295         if (vport_wfq_en && QM_BYPASS_EN)
 296                 STORE_RT_REG(p_hwfn,
 297                              QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET,
 298                              QM_WFQ_UPPER_BOUND);
 299 }
 300
 301 /* Prepare runtime init values to allocate PBF command queue lines for
 302  * the specified VOQ.
 303  */
 304 static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn,
 305                                        u8 ext_voq, u16 cmdq_lines)
 306 {
 307         u32 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
 308
 309         OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq),
 310                          (u32)cmdq_lines);
 311         STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + ext_voq,
 312                      qm_line_crd);
 313         STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + ext_voq,
 314                      qm_line_crd);
 315 }
 316
 317 /* Prepare runtime init values to allocate PBF command queue lines. */
 318 static void qed_cmdq_lines_rt_init(
 319         struct qed_hwfn *p_hwfn,
 320         u8 max_ports_per_engine,
 321         u8 max_phys_tcs_per_port,
 322         struct init_qm_port_params port_params[MAX_NUM_PORTS])
 323 {
 324         u8 tc, ext_voq, port_id, num_tcs_in_port;
 325         u8 num_ext_voqs = MAX_NUM_VOQS_E4;
 326
 327         /* Clear PBF lines of all VOQs */
 328         for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++)
 329                 STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 0);
 330
 331         for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
 332                 u16 phys_lines, phys_lines_per_tc;
 333
 334                 if (!port_params[port_id].active)
 335                         continue;
 336
 337                 /* Find number of command queue lines to divide between the
 338                  * active physical TCs.
 339                  */
 340                 phys_lines = port_params[port_id].num_pbf_cmd_lines;
 341                 phys_lines -= PBF_CMDQ_PURE_LB_LINES;
 342
 343                 /* Find #lines per active physical TC */
 344                 num_tcs_in_port = 0;
 345                 for (tc = 0; tc < max_phys_tcs_per_port; tc++)
 346                         if (((port_params[port_id].active_phys_tcs >>
 347                               tc) & 0x1) == 1)
 348                                 num_tcs_in_port++;
 349                 phys_lines_per_tc = phys_lines / num_tcs_in_port;
 350
 351                 /* Init registers per active TC */
 352                 for (tc = 0; tc < max_phys_tcs_per_port; tc++) {
 353                         ext_voq = qed_get_ext_voq(p_hwfn,
 354                                                   port_id,
 355                                                   tc, max_phys_tcs_per_port);
 356                         if (((port_params[port_id].active_phys_tcs >>
 357                               tc) & 0x1) == 1)
 358                                 qed_cmdq_lines_voq_rt_init(p_hwfn,
 359                                                            ext_voq,
 360                                                            phys_lines_per_tc);
 361                 }
 362
 363                 /* Init registers for pure LB TC */
 364                 ext_voq = qed_get_ext_voq(p_hwfn,
 365                                           port_id,
 366                                           PURE_LB_TC, max_phys_tcs_per_port);
 367                 qed_cmdq_lines_voq_rt_init(p_hwfn, ext_voq,
 368                                            PBF_CMDQ_PURE_LB_LINES);
 369         }
 370 }
 371
 372 /* Prepare runtime init values to allocate guaranteed BTB blocks for the
 373  * specified port. The guaranteed BTB space is divided between the TCs as
 374  * follows (shared space Is currently not used):
 375  * 1. Parameters:
 376  *    B - BTB blocks for this port
 377  *    C - Number of physical TCs for this port
 378  * 2. Calculation:
 379  *    a. 38 blocks (9700B jumbo frame) are allocated for global per port
 380  *       headroom.
 381  *    b. B = B - 38 (remainder after global headroom allocation).
 382  *    c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ.
 383  *    d. B = B - MAX(38, B/(C+0.7)) (remainder after pure LB allocation).
 384  *    e. B/C blocks are allocated for each physical TC.
 385  * Assumptions:
 386  * - MTU is up to 9700 bytes (38 blocks)
 387  * - All TCs are considered symmetrical (same rate and packet size)
 388  * - No optimization for lossy TC (all are considered lossless). Shared space
 389  *   is not enabled and allocated for each TC.
 390  */
 391 static void qed_btb_blocks_rt_init(
 392         struct qed_hwfn *p_hwfn,
 393         u8 max_ports_per_engine,
 394         u8 max_phys_tcs_per_port,
 395         struct init_qm_port_params port_params[MAX_NUM_PORTS])
 396 {
 397         u32 usable_blocks, pure_lb_blocks, phys_blocks;
 398         u8 tc, ext_voq, port_id, num_tcs_in_port;
 399
 400         for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
 401                 if (!port_params[port_id].active)
 402                         continue;
 403
 404                 /* Subtract headroom blocks */
 405                 usable_blocks = port_params[port_id].num_btb_blocks -
 406                                 BTB_HEADROOM_BLOCKS;
 407
 408                 /* Find blocks per physical TC. Use factor to avoid floating
 409                  * arithmethic.
 410                  */
 411                 num_tcs_in_port = 0;
 412                 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
 413                         if (((port_params[port_id].active_phys_tcs >>
 414                               tc) & 0x1) == 1)
 415                                 num_tcs_in_port++;
 416
 417                 pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) /
 418                                  (num_tcs_in_port * BTB_PURE_LB_FACTOR +
 419                                   BTB_PURE_LB_RATIO);
 420                 pure_lb_blocks = max_t(u32, BTB_JUMBO_PKT_BLOCKS,
 421                                        pure_lb_blocks / BTB_PURE_LB_FACTOR);
 422                 phys_blocks = (usable_blocks - pure_lb_blocks) /
 423                               num_tcs_in_port;
 424
 425                 /* Init physical TCs */
 426                 for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
 427                         if (((port_params[port_id].active_phys_tcs >>
 428                               tc) & 0x1) == 1) {
 429                                 ext_voq =
 430                                         qed_get_ext_voq(p_hwfn,
 431                                                         port_id,
 432                                                         tc,
 433                                                         max_phys_tcs_per_port);
 434                                 STORE_RT_REG(p_hwfn,
 435                                              PBF_BTB_GUARANTEED_RT_OFFSET
 436                                              (ext_voq), phys_blocks);
 437                         }
 438                 }
 439
 440                 /* Init pure LB TC */
 441                 ext_voq = qed_get_ext_voq(p_hwfn,
 442                                           port_id,
 443                                           PURE_LB_TC, max_phys_tcs_per_port);
 444                 STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq),
 445                              pure_lb_blocks);
 446         }
 447 }
 448
 449 /* Prepare runtime init values for the specified RL.
 450  * Set max link speed (100Gbps) per rate limiter.
 451  * Return -1 on error.
 452  */
 453 static int qed_global_rl_rt_init(struct qed_hwfn *p_hwfn)
 454 {
 455         u32 upper_bound = QM_VP_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) |
 456                           (u32)QM_RL_CRD_REG_SIGN_BIT;
 457         u32 inc_val;
 458         u16 rl_id;
 459
 460         /* Go over all global RLs */
 461         for (rl_id = 0; rl_id < MAX_QM_GLOBAL_RLS; rl_id++) {
 462                 inc_val = QM_RL_INC_VAL(QM_MAX_LINK_SPEED);
 463
 464                 STORE_RT_REG(p_hwfn,
 465                              QM_REG_RLGLBLCRD_RT_OFFSET + rl_id,
 466                              (u32)QM_RL_CRD_REG_SIGN_BIT);
 467                 STORE_RT_REG(p_hwfn,
 468                              QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + rl_id,
 469                              upper_bound);
 470                 STORE_RT_REG(p_hwfn,
 471                              QM_REG_RLGLBLINCVAL_RT_OFFSET + rl_id, inc_val);
 472         }
 473
 474         return 0;
 475 }
 476
 477 /* Prepare Tx PQ mapping runtime init values for the specified PF */
 478 static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn,
 479                                   struct qed_ptt *p_ptt,
 480                                   struct qed_qm_pf_rt_init_params *p_params,
 481                                   u32 base_mem_addr_4kb)
 482 {
 483         u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
 484         struct init_qm_vport_params *vport_params = p_params->vport_params;
 485         u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
 486         u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group;
 487         struct init_qm_pq_params *pq_params = p_params->pq_params;
 488         u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
 489
 490         num_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
 491
 492         first_pq_group = p_params->start_pq / QM_PF_QUEUE_GROUP_SIZE;
 493         last_pq_group = (p_params->start_pq + num_pqs - 1) /
 494                         QM_PF_QUEUE_GROUP_SIZE;
 495
 496         pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids);
 497         vport_pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_vf_cids);
 498         mem_addr_4kb = base_mem_addr_4kb;
 499
 500         /* Set mapping from PQ group to PF */
 501         for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
 502                 STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group,
 503                              (u32)(p_params->pf_id));
 504
 505         /* Set PQ sizes */
 506         STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET,
 507                      QM_PQ_SIZE_256B(p_params->num_pf_cids));
 508         STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET,
 509                      QM_PQ_SIZE_256B(p_params->num_vf_cids));
 510
 511         /* Go over all Tx PQs */
 512         for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) {
 513                 u16 *p_first_tx_pq_id, vport_id_in_pf;
 514                 struct qm_rf_pq_map_e4 tx_pq_map;
 515                 u8 tc_id = pq_params[i].tc_id;
 516                 bool is_vf_pq;
 517                 u8 ext_voq;
 518
 519                 ext_voq = qed_get_ext_voq(p_hwfn,
 520                                           pq_params[i].port_id,
 521                                           tc_id,
 522                                           p_params->max_phys_tcs_per_port);
 523                 is_vf_pq = (i >= p_params->num_pf_pqs);
 524
 525                 /* Update first Tx PQ of VPORT/TC */
 526                 vport_id_in_pf = pq_params[i].vport_id - p_params->start_vport;
 527                 p_first_tx_pq_id =
 528                     &vport_params[vport_id_in_pf].first_tx_pq_id[tc_id];
 529                 if (*p_first_tx_pq_id == QM_INVALID_PQ_ID) {
 530                         u32 map_val =
 531                                 (ext_voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
 532                                 (p_params->pf_id << QM_WFQ_VP_PQ_PF_E4_SHIFT);
 533
 534                         /* Create new VP PQ */
 535                         *p_first_tx_pq_id = pq_id;
 536
 537                         /* Map VP PQ to VOQ and PF */
 538                         STORE_RT_REG(p_hwfn,
 539                                      QM_REG_WFQVPMAP_RT_OFFSET +
 540                                      *p_first_tx_pq_id,
 541                                      map_val);
 542                 }
 543
 544                 /* Prepare PQ map entry */
 545                 QM_INIT_TX_PQ_MAP(p_hwfn,
 546                                   tx_pq_map,
 547                                   E4,
 548                                   pq_id,
 549                                   *p_first_tx_pq_id,
 550                                   pq_params[i].rl_valid,
 551                                   pq_params[i].rl_id,
 552                                   ext_voq, pq_params[i].wrr_group);
 553
 554                 /* Set PQ base address */
 555                 STORE_RT_REG(p_hwfn,
 556                              QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
 557                              mem_addr_4kb);
 558
 559                 /* Clear PQ pointer table entry (64 bit) */
 560                 if (p_params->is_pf_loading)
 561                         for (j = 0; j < 2; j++)
 562                                 STORE_RT_REG(p_hwfn,
 563                                              QM_REG_PTRTBLTX_RT_OFFSET +
 564                                              (pq_id * 2) + j, 0);
 565
 566                 /* Write PQ info to RAM */
 567                 if (WRITE_PQ_INFO_TO_RAM != 0) {
 568                         u32 pq_info = 0;
 569
 570                         pq_info = PQ_INFO_ELEMENT(*p_first_tx_pq_id,
 571                                                   p_params->pf_id,
 572                                                   tc_id,
 573                                                   pq_params[i].port_id,
 574                                                   pq_params[i].rl_valid,
 575                                                   pq_params[i].rl_id);
 576                         qed_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id),
 577                                pq_info);
 578                 }
 579
 580                 /* If VF PQ, add indication to PQ VF mask */
 581                 if (is_vf_pq) {
 582                         tx_pq_vf_mask[pq_id /
 583                                       QM_PF_QUEUE_GROUP_SIZE] |=
 584                             BIT((pq_id % QM_PF_QUEUE_GROUP_SIZE));
 585                         mem_addr_4kb += vport_pq_mem_4kb;
 586                 } else {
 587                         mem_addr_4kb += pq_mem_4kb;
 588                 }
 589         }
 590
 591         /* Store Tx PQ VF mask to size select register */
 592         for (i = 0; i < num_tx_pq_vf_masks; i++)
 593                 if (tx_pq_vf_mask[i])
 594                         STORE_RT_REG(p_hwfn,
 595                                      QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i,
 596                                      tx_pq_vf_mask[i]);
 597 }
 598
 599 /* Prepare Other PQ mapping runtime init values for the specified PF */
 600 static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn,
 601                                      u8 pf_id,
 602                                      bool is_pf_loading,
 603                                      u32 num_pf_cids,
 604                                      u32 num_tids, u32 base_mem_addr_4kb)
 605 {
 606         u32 pq_size, pq_mem_4kb, mem_addr_4kb;
 607         u16 i, j, pq_id, pq_group;
 608
 609         /* A single other PQ group is used in each PF, where PQ group i is used
 610          * in PF i.
 611          */
 612         pq_group = pf_id;
 613         pq_size = num_pf_cids + num_tids;
 614         pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
 615         mem_addr_4kb = base_mem_addr_4kb;
 616
 617         /* Map PQ group to PF */
 618         STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group,
 619                      (u32)(pf_id));
 620
 621         /* Set PQ sizes */
 622         STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET,
 623                      QM_PQ_SIZE_256B(pq_size));
 624
 625         for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE;
 626              i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
 627                 /* Set PQ base address */
 628                 STORE_RT_REG(p_hwfn,
 629                              QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id,
 630                              mem_addr_4kb);
 631
 632                 /* Clear PQ pointer table entry */
 633                 if (is_pf_loading)
 634                         for (j = 0; j < 2; j++)
 635                                 STORE_RT_REG(p_hwfn,
 636                                              QM_REG_PTRTBLOTHER_RT_OFFSET +
 637                                              (pq_id * 2) + j, 0);
 638
 639                 mem_addr_4kb += pq_mem_4kb;
 640         }
 641 }
 642
 643 /* Prepare PF WFQ runtime init values for the specified PF.
 644  * Return -1 on error.
 645  */
 646 static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn,
 647
 648                               struct qed_qm_pf_rt_init_params *p_params)
 649 {
 650         u16 num_tx_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs;
 651         struct init_qm_pq_params *pq_params = p_params->pq_params;
 652         u32 inc_val, crd_reg_offset;
 653         u8 ext_voq;
 654         u16 i;
 655
 656         inc_val = QM_WFQ_INC_VAL(p_params->pf_wfq);
 657         if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
 658                 DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
 659                 return -1;
 660         }
 661
 662         for (i = 0; i < num_tx_pqs; i++) {
 663                 ext_voq = qed_get_ext_voq(p_hwfn,
 664                                           pq_params[i].port_id,
 665                                           pq_params[i].tc_id,
 666                                           p_params->max_phys_tcs_per_port);
 667                 crd_reg_offset =
 668                         (p_params->pf_id < MAX_NUM_PFS_BB ?
 669                          QM_REG_WFQPFCRD_RT_OFFSET :
 670                          QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
 671                         ext_voq * MAX_NUM_PFS_BB +
 672                         (p_params->pf_id % MAX_NUM_PFS_BB);
 673                 OVERWRITE_RT_REG(p_hwfn,
 674                                  crd_reg_offset, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
 675         }
 676
 677         STORE_RT_REG(p_hwfn,
 678                      QM_REG_WFQPFUPPERBOUND_RT_OFFSET + p_params->pf_id,
 679                      QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
 680         STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + p_params->pf_id,
 681                      inc_val);
 682
 683         return 0;
 684 }
 685
 686 /* Prepare PF RL runtime init values for the specified PF.
 687  * Return -1 on error.
 688  */
 689 static int qed_pf_rl_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
 690 {
 691         u32 inc_val = QM_RL_INC_VAL(pf_rl);
 692
 693         if (inc_val > QM_PF_RL_MAX_INC_VAL) {
 694                 DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
 695                 return -1;
 696         }
 697
 698         STORE_RT_REG(p_hwfn,
 699                      QM_REG_RLPFCRD_RT_OFFSET + pf_id,
 700                      (u32)QM_RL_CRD_REG_SIGN_BIT);
 701         STORE_RT_REG(p_hwfn,
 702                      QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
 703                      QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
 704         STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
 705
 706         return 0;
 707 }
 708
 709 /* Prepare VPORT WFQ runtime init values for the specified VPORTs.
 710  * Return -1 on error.
 711  */
 712 static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn,
 713                               u16 num_vports,
 714                               struct init_qm_vport_params *vport_params)
 715 {
 716         u16 vport_pq_id, i;
 717         u32 inc_val;
 718         u8 tc;
 719
 720         /* Go over all PF VPORTs */
 721         for (i = 0; i < num_vports; i++) {
 722                 if (!vport_params[i].wfq)
 723                         continue;
 724
 725                 inc_val = QM_WFQ_INC_VAL(vport_params[i].wfq);
 726                 if (inc_val > QM_WFQ_MAX_INC_VAL) {
 727                         DP_NOTICE(p_hwfn,
 728                                   "Invalid VPORT WFQ weight configuration\n");
 729                         return -1;
 730                 }
 731
 732                 /* Each VPORT can have several VPORT PQ IDs for various TCs */
 733                 for (tc = 0; tc < NUM_OF_TCS; tc++) {
 734                         vport_pq_id = vport_params[i].first_tx_pq_id[tc];
 735                         if (vport_pq_id != QM_INVALID_PQ_ID) {
 736                                 STORE_RT_REG(p_hwfn,
 737                                              QM_REG_WFQVPCRD_RT_OFFSET +
 738                                              vport_pq_id,
 739                                              (u32)QM_WFQ_CRD_REG_SIGN_BIT);
 740                                 STORE_RT_REG(p_hwfn,
 741                                              QM_REG_WFQVPWEIGHT_RT_OFFSET +
 742                                              vport_pq_id, inc_val);
 743                         }
 744                 }
 745         }
 746
 747         return 0;
 748 }
 749
 750 static bool qed_poll_on_qm_cmd_ready(struct qed_hwfn *p_hwfn,
 751                                      struct qed_ptt *p_ptt)
 752 {
 753         u32 reg_val, i;
 754
 755         for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
 756              i++) {
 757                 udelay(QM_STOP_CMD_POLL_PERIOD_US);
 758                 reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
 759         }
 760
 761         /* Check if timeout while waiting for SDM command ready */
 762         if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
 763                 DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
 764                            "Timeout when waiting for QM SDM command ready signal\n");
 765                 return false;
 766         }
 767
 768         return true;
 769 }
 770
 771 static bool qed_send_qm_cmd(struct qed_hwfn *p_hwfn,
 772                             struct qed_ptt *p_ptt,
 773                             u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb)
 774 {
 775         if (!qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
 776                 return false;
 777
 778         qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr);
 779         qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb);
 780         qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb);
 781         qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1);
 782         qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0);
 783
 784         return qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt);
 785 }
 786
 787 /******************** INTERFACE IMPLEMENTATION *********************/
 788
 789 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
 790                        u32 num_vf_cids,
 791                        u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs)
 792 {
 793         return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
 794                QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
 795                QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
 796 }
 797
 798 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
 799                           struct qed_qm_common_rt_init_params *p_params)
 800 {
 801         u32 mask = 0;
 802
 803         /* Init AFullOprtnstcCrdMask */
 804         SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_LINEVOQ,
 805                   QM_OPPOR_LINE_VOQ_DEF);
 806         SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ, QM_BYTE_CRD_EN);
 807         SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFWFQ, p_params->pf_wfq_en);
 808         SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPWFQ, p_params->vport_wfq_en);
 809         SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFRL, p_params->pf_rl_en);
 810         SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPQCNRL,
 811                   p_params->global_rl_en);
 812         SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_FWPAUSE, QM_OPPOR_FW_STOP_DEF);
 813         SET_FIELD(mask,
 814                   QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY, QM_OPPOR_PQ_EMPTY_DEF);
 815         STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
 816
 817         /* Enable/disable PF RL */
 818         qed_enable_pf_rl(p_hwfn, p_params->pf_rl_en);
 819
 820         /* Enable/disable PF WFQ */
 821         qed_enable_pf_wfq(p_hwfn, p_params->pf_wfq_en);
 822
 823         /* Enable/disable global RL */
 824         qed_enable_global_rl(p_hwfn, p_params->global_rl_en);
 825
 826         /* Enable/disable VPORT WFQ */
 827         qed_enable_vport_wfq(p_hwfn, p_params->vport_wfq_en);
 828
 829         /* Init PBF CMDQ line credit */
 830         qed_cmdq_lines_rt_init(p_hwfn,
 831                                p_params->max_ports_per_engine,
 832                                p_params->max_phys_tcs_per_port,
 833                                p_params->port_params);
 834
 835         /* Init BTB blocks in PBF */
 836         qed_btb_blocks_rt_init(p_hwfn,
 837                                p_params->max_ports_per_engine,
 838                                p_params->max_phys_tcs_per_port,
 839                                p_params->port_params);
 840
 841         qed_global_rl_rt_init(p_hwfn);
 842
 843         return 0;
 844 }
 845
 846 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
 847                       struct qed_ptt *p_ptt,
 848                       struct qed_qm_pf_rt_init_params *p_params)
 849 {
 850         struct init_qm_vport_params *vport_params = p_params->vport_params;
 851         u32 other_mem_size_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids +
 852                                                p_params->num_tids) *
 853                                  QM_OTHER_PQS_PER_PF;
 854         u16 i;
 855         u8 tc;
 856
 857
 858         /* Clear first Tx PQ ID array for each VPORT */
 859         for (i = 0; i < p_params->num_vports; i++)
 860                 for (tc = 0; tc < NUM_OF_TCS; tc++)
 861                         vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
 862
 863         /* Map Other PQs (if any) */
 864         qed_other_pq_map_rt_init(p_hwfn,
 865                                  p_params->pf_id,
 866                                  p_params->is_pf_loading, p_params->num_pf_cids,
 867                                  p_params->num_tids, 0);
 868
 869         /* Map Tx PQs */
 870         qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb);
 871
 872         /* Init PF WFQ */
 873         if (p_params->pf_wfq)
 874                 if (qed_pf_wfq_rt_init(p_hwfn, p_params))
 875                         return -1;
 876
 877         /* Init PF RL */
 878         if (qed_pf_rl_rt_init(p_hwfn, p_params->pf_id, p_params->pf_rl))
 879                 return -1;
 880
 881         /* Init VPORT WFQ */
 882         if (qed_vp_wfq_rt_init(p_hwfn, p_params->num_vports, vport_params))
 883                 return -1;
 884
 885         return 0;
 886 }
 887
 888 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
 889                     struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq)
 890 {
 891         u32 inc_val = QM_WFQ_INC_VAL(pf_wfq);
 892
 893         if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
 894                 DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n");
 895                 return -1;
 896         }
 897
 898         qed_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
 899
 900         return 0;
 901 }
 902
 903 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
 904                    struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl)
 905 {
 906         u32 inc_val = QM_RL_INC_VAL(pf_rl);
 907
 908         if (inc_val > QM_PF_RL_MAX_INC_VAL) {
 909                 DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n");
 910                 return -1;
 911         }
 912
 913         qed_wr(p_hwfn,
 914                p_ptt, QM_REG_RLPFCRD + pf_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
 915         qed_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
 916
 917         return 0;
 918 }
 919
 920 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
 921                        struct qed_ptt *p_ptt,
 922                        u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq)
 923 {
 924         u16 vport_pq_id;
 925         u32 inc_val;
 926         u8 tc;
 927
 928         inc_val = QM_WFQ_INC_VAL(wfq);
 929         if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
 930                 DP_NOTICE(p_hwfn, "Invalid VPORT WFQ configuration.\n");
 931                 return -1;
 932         }
 933
 934         /* A VPORT can have several VPORT PQ IDs for various TCs */
 935         for (tc = 0; tc < NUM_OF_TCS; tc++) {
 936                 vport_pq_id = first_tx_pq_id[tc];
 937                 if (vport_pq_id != QM_INVALID_PQ_ID)
 938                         qed_wr(p_hwfn,
 939                                p_ptt,
 940                                QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val);
 941         }
 942
 943         return 0;
 944 }
 945
 946 int qed_init_global_rl(struct qed_hwfn *p_hwfn,
 947                        struct qed_ptt *p_ptt, u16 rl_id, u32 rate_limit)
 948 {
 949         u32 inc_val;
 950
 951         inc_val = QM_RL_INC_VAL(rate_limit);
 952         if (inc_val > QM_VP_RL_MAX_INC_VAL(rate_limit)) {
 953                 DP_NOTICE(p_hwfn, "Invalid rate limit configuration.\n");
 954                 return -1;
 955         }
 956
 957         qed_wr(p_hwfn, p_ptt,
 958                QM_REG_RLGLBLCRD + rl_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
 959         qed_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + rl_id * 4, inc_val);
 960
 961         return 0;
 962 }
 963
 964 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
 965                           struct qed_ptt *p_ptt,
 966                           bool is_release_cmd,
 967                           bool is_tx_pq, u16 start_pq, u16 num_pqs)
 968 {
 969         u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 };
 970         u32 pq_mask = 0, last_pq, pq_id;
 971
 972         last_pq = start_pq + num_pqs - 1;
 973
 974         /* Set command's PQ type */
 975         QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
 976
 977         /* Go over requested PQs */
 978         for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
 979                 /* Set PQ bit in mask (stop command only) */
 980                 if (!is_release_cmd)
 981                         pq_mask |= BIT((pq_id % QM_STOP_PQ_MASK_WIDTH));
 982
 983                 /* If last PQ or end of PQ mask, write command */
 984                 if ((pq_id == last_pq) ||
 985                     (pq_id % QM_STOP_PQ_MASK_WIDTH ==
 986                      (QM_STOP_PQ_MASK_WIDTH - 1))) {
 987                         QM_CMD_SET_FIELD(cmd_arr,
 988                                          QM_STOP_CMD, PAUSE_MASK, pq_mask);
 989                         QM_CMD_SET_FIELD(cmd_arr,
 990                                          QM_STOP_CMD,
 991                                          GROUP_ID,
 992                                          pq_id / QM_STOP_PQ_MASK_WIDTH);
 993                         if (!qed_send_qm_cmd(p_hwfn, p_ptt, QM_STOP_CMD_ADDR,
 994                                              cmd_arr[0], cmd_arr[1]))
 995                                 return false;
 996                         pq_mask = 0;
 997                 }
 998         }
 999
1000         return true;
1001 }
1002
1003 #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \
1004         do { \
1005                 typeof(var) *__p_var = &(var); \
1006                 typeof(offset) __offset = offset; \
1007                 *__p_var = (*__p_var & ~BIT(__offset)) | \
1008                            ((enable) ? BIT(__offset) : 0); \
1009         } while (0)
1010
1011 #define PRS_ETH_TUNN_OUTPUT_FORMAT     0xF4DAB910
1012 #define PRS_ETH_OUTPUT_FORMAT          0xFFFF4910
1013
1014 #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \
1015         do { \
1016                 u32 i; \
1017                 \
1018                 for (i = 0; i < (arr_size); i++) \
1019                         qed_wr(dev, ptt, \
1020                                ((addr) + (4 * i)), \
1021                                ((u32 *)&(arr))[i]); \
1022         } while (0)
1023
1024 /**
1025  * @brief qed_dmae_to_grc - is an internal function - writes from host to
1026  * wide-bus registers (split registers are not supported yet)
1027  *
1028  * @param p_hwfn - HW device data
1029  * @param p_ptt - ptt window used for writing the registers.
1030  * @param p_data - pointer to source data.
1031  * @param addr - Destination register address.
1032  * @param len_in_dwords - data length in DWARDS (u32)
1033  */
1034 static int qed_dmae_to_grc(struct qed_hwfn *p_hwfn,
1035                            struct qed_ptt *p_ptt,
1036                            u32 *p_data, u32 addr, u32 len_in_dwords)
1037 {
1038         struct qed_dmae_params params = {};
1039         int rc;
1040
1041         if (!p_data)
1042                 return -1;
1043
1044         /* Set DMAE params */
1045         SET_FIELD(params.flags, QED_DMAE_PARAMS_COMPLETION_DST, 1);
1046
1047         /* Execute DMAE command */
1048         rc = qed_dmae_host2grc(p_hwfn, p_ptt,
1049                                (u64)(uintptr_t)(p_data),
1050                                addr, len_in_dwords, &params);
1051
1052         /* If not read using DMAE, read using GRC */
1053         if (rc) {
1054                 DP_VERBOSE(p_hwfn,
1055                            QED_MSG_DEBUG,
1056                            "Failed writing to chip using DMAE, using GRC instead\n");
1057                 /* write to registers using GRC */
1058                 ARR_REG_WR(p_hwfn, p_ptt, addr, p_data, len_in_dwords);
1059         }
1060
1061         return len_in_dwords;
1062 }
1063
1064 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
1065                              struct qed_ptt *p_ptt, u16 dest_port)
1066 {
1067         /* Update PRS register */
1068         qed_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
1069
1070         /* Update NIG register */
1071         qed_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
1072
1073         /* Update PBF register */
1074         qed_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
1075 }
1076
1077 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
1078                           struct qed_ptt *p_ptt, bool vxlan_enable)
1079 {
1080         u32 reg_val;
1081         u8 shift;
1082
1083         /* Update PRS register */
1084         reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1085         shift = PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT;
1086         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
1087         qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1088         if (reg_val) {
1089                 reg_val =
1090                     qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
1091
1092                 /* Update output  only if tunnel blocks not included. */
1093                 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1094                         qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1095                                (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1096         }
1097
1098         /* Update NIG register */
1099         reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1100         shift = NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT;
1101         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
1102         qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1103
1104         /* Update DORQ register */
1105         qed_wr(p_hwfn,
1106                p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN, vxlan_enable ? 1 : 0);
1107 }
1108
1109 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
1110                         struct qed_ptt *p_ptt,
1111                         bool eth_gre_enable, bool ip_gre_enable)
1112 {
1113         u32 reg_val;
1114         u8 shift;
1115
1116         /* Update PRS register */
1117         reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1118         shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT;
1119         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
1120         shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT;
1121         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
1122         qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1123         if (reg_val) {
1124                 reg_val =
1125                     qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
1126
1127                 /* Update output  only if tunnel blocks not included. */
1128                 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1129                         qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1130                                (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1131         }
1132
1133         /* Update NIG register */
1134         reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1135         shift = NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT;
1136         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
1137         shift = NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT;
1138         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
1139         qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1140
1141         /* Update DORQ registers */
1142         qed_wr(p_hwfn,
1143                p_ptt,
1144                DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN, eth_gre_enable ? 1 : 0);
1145         qed_wr(p_hwfn,
1146                p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN, ip_gre_enable ? 1 : 0);
1147 }
1148
1149 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
1150                               struct qed_ptt *p_ptt, u16 dest_port)
1151 {
1152         /* Update PRS register */
1153         qed_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port);
1154
1155         /* Update NIG register */
1156         qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port);
1157
1158         /* Update PBF register */
1159         qed_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port);
1160 }
1161
1162 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
1163                            struct qed_ptt *p_ptt,
1164                            bool eth_geneve_enable, bool ip_geneve_enable)
1165 {
1166         u32 reg_val;
1167         u8 shift;
1168
1169         /* Update PRS register */
1170         reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1171         shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT;
1172         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_geneve_enable);
1173         shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT;
1174         SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_geneve_enable);
1175         qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1176         if (reg_val) {
1177                 reg_val =
1178                     qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2);
1179
1180                 /* Update output  only if tunnel blocks not included. */
1181                 if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1182                         qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1183                                (u32)PRS_ETH_TUNN_OUTPUT_FORMAT);
1184         }
1185
1186         /* Update NIG register */
1187         qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
1188                eth_geneve_enable ? 1 : 0);
1189         qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE, ip_geneve_enable ? 1 : 0);
1190
1191         /* EDPM with geneve tunnel not supported in BB */
1192         if (QED_IS_BB_B0(p_hwfn->cdev))
1193                 return;
1194
1195         /* Update DORQ registers */
1196         qed_wr(p_hwfn,
1197                p_ptt,
1198                DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5,
1199                eth_geneve_enable ? 1 : 0);
1200         qed_wr(p_hwfn,
1201                p_ptt,
1202                DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5,
1203                ip_geneve_enable ? 1 : 0);
1204 }
1205
1206 #define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET      3
1207 #define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT   -925189872
1208
1209 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
1210                                 struct qed_ptt *p_ptt, bool enable)
1211 {
1212         u32 reg_val, cfg_mask;
1213
1214         /* read PRS config register */
1215         reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO);
1216
1217         /* set VXLAN_NO_L2_ENABLE mask */
1218         cfg_mask = BIT(PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET);
1219
1220         if (enable) {
1221                 /* set VXLAN_NO_L2_ENABLE flag */
1222                 reg_val |= cfg_mask;
1223
1224                 /* update PRS FIC  register */
1225                 qed_wr(p_hwfn,
1226                        p_ptt,
1227                        PRS_REG_OUTPUT_FORMAT_4_0_BB_K2,
1228                        (u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT);
1229         } else {
1230                 /* clear VXLAN_NO_L2_ENABLE flag */
1231                 reg_val &= ~cfg_mask;
1232         }
1233
1234         /* write PRS config register */
1235         qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val);
1236 }
1237
1238 #define T_ETH_PACKET_ACTION_GFT_EVENTID  23
1239 #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR  272
1240 #define T_ETH_PACKET_MATCH_RFS_EVENTID 25
1241 #define PARSER_ETH_CONN_CM_HDR 0
1242 #define CAM_LINE_SIZE sizeof(u32)
1243 #define RAM_LINE_SIZE sizeof(u64)
1244 #define REG_SIZE sizeof(u32)
1245
1246 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id)
1247 {
1248         struct regpair ram_line = { };
1249
1250         /* Disable gft search for PF */
1251         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
1252
1253         /* Clean ram & cam for next gft session */
1254
1255         /* Zero camline */
1256         qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0);
1257
1258         /* Zero ramline */
1259         qed_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line,
1260                         PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
1261                         sizeof(ram_line) / REG_SIZE);
1262 }
1263
1264 void qed_gft_config(struct qed_hwfn *p_hwfn,
1265                     struct qed_ptt *p_ptt,
1266                     u16 pf_id,
1267                     bool tcp,
1268                     bool udp,
1269                     bool ipv4, bool ipv6, enum gft_profile_type profile_type)
1270 {
1271         u32 reg_val, cam_line, search_non_ip_as_gft;
1272         struct regpair ram_line = { };
1273
1274         if (!ipv6 && !ipv4)
1275                 DP_NOTICE(p_hwfn,
1276                           "gft_config: must accept at least on of - ipv4 or ipv6'\n");
1277         if (!tcp && !udp)
1278                 DP_NOTICE(p_hwfn,
1279                           "gft_config: must accept at least on of - udp or tcp\n");
1280         if (profile_type >= MAX_GFT_PROFILE_TYPE)
1281                 DP_NOTICE(p_hwfn, "gft_config: unsupported gft_profile_type\n");
1282
1283         /* Set RFS event ID to be awakened i Tstorm By Prs */
1284         reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<
1285                   PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
1286         reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1287         qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);
1288
1289         /* Do not load context only cid in PRS on match. */
1290         qed_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
1291
1292         /* Do not use tenant ID exist bit for gft search */
1293         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0);
1294
1295         /* Set Cam */
1296         cam_line = 0;
1297         SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1);
1298
1299         /* Filters are per PF!! */
1300         SET_FIELD(cam_line,
1301                   GFT_CAM_LINE_MAPPED_PF_ID_MASK,
1302                   GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
1303         SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
1304
1305         if (!(tcp && udp)) {
1306                 SET_FIELD(cam_line,
1307                           GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
1308                           GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
1309                 if (tcp)
1310                         SET_FIELD(cam_line,
1311                                   GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1312                                   GFT_PROFILE_TCP_PROTOCOL);
1313                 else
1314                         SET_FIELD(cam_line,
1315                                   GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
1316                                   GFT_PROFILE_UDP_PROTOCOL);
1317         }
1318
1319         if (!(ipv4 && ipv6)) {
1320                 SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
1321                 if (ipv4)
1322                         SET_FIELD(cam_line,
1323                                   GFT_CAM_LINE_MAPPED_IP_VERSION,
1324                                   GFT_PROFILE_IPV4);
1325                 else
1326                         SET_FIELD(cam_line,
1327                                   GFT_CAM_LINE_MAPPED_IP_VERSION,
1328                                   GFT_PROFILE_IPV6);
1329         }
1330
1331         /* Write characteristics to cam */
1332         qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
1333                cam_line);
1334         cam_line =
1335             qed_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
1336
1337         /* Write line to RAM - compare to filter 4 tuple */
1338
1339         /* Search no IP as GFT */
1340         search_non_ip_as_gft = 0;
1341
1342         /* Tunnel type */
1343         SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1);
1344         SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1);
1345
1346         if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) {
1347                 SET_FIELD(ram_line.hi, GFT_RAM_LINE_DST_IP, 1);
1348                 SET_FIELD(ram_line.hi, GFT_RAM_LINE_SRC_IP, 1);
1349                 SET_FIELD(ram_line.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1350                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1351                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_SRC_PORT, 1);
1352                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_DST_PORT, 1);
1353         } else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) {
1354                 SET_FIELD(ram_line.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
1355                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1356                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_DST_PORT, 1);
1357         } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_ADDR) {
1358                 SET_FIELD(ram_line.hi, GFT_RAM_LINE_DST_IP, 1);
1359                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1360         } else if (profile_type == GFT_PROFILE_TYPE_IP_SRC_ADDR) {
1361                 SET_FIELD(ram_line.hi, GFT_RAM_LINE_SRC_IP, 1);
1362                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
1363         } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) {
1364                 SET_FIELD(ram_line.lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1);
1365
1366                 /* Allow tunneled traffic without inner IP */
1367                 search_non_ip_as_gft = 1;
1368         }
1369
1370         qed_wr(p_hwfn,
1371                p_ptt, PRS_REG_SEARCH_NON_IP_AS_GFT, search_non_ip_as_gft);
1372         qed_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line,
1373                         PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
1374                         sizeof(ram_line) / REG_SIZE);
1375
1376         /* Set default profile so that no filter match will happen */
1377         ram_line.lo = 0xffffffff;
1378         ram_line.hi = 0x3ff;
1379         qed_dmae_to_grc(p_hwfn, p_ptt, (u32 *)&ram_line,
1380                         PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
1381                         PRS_GFT_CAM_LINES_NO_MATCH,
1382                         sizeof(ram_line) / REG_SIZE);
1383
1384         /* Enable gft search */
1385         qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
1386 }
1387
1388 DECLARE_CRC8_TABLE(cdu_crc8_table);
1389
1390 /* Calculate and return CDU validation byte per connection type/region/cid */
1391 static u8 qed_calc_cdu_validation_byte(u8 conn_type, u8 region, u32 cid)
1392 {
1393         const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG;
1394         u8 crc, validation_byte = 0;
1395         static u8 crc8_table_valid; /* automatically initialized to 0 */
1396         u32 validation_string = 0;
1397         u32 data_to_crc;
1398
1399         if (!crc8_table_valid) {
1400                 crc8_populate_msb(cdu_crc8_table, 0x07);
1401                 crc8_table_valid = 1;
1402         }
1403
1404         /* The CRC is calculated on the String-to-compress:
1405          * [31:8]  = {CID[31:20],CID[11:0]}
1406          * [7:4]   = Region
1407          * [3:0]   = Type
1408          */
1409         if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1)
1410                 validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8);
1411
1412         if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1)
1413                 validation_string |= ((region & 0xF) << 4);
1414
1415         if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1)
1416                 validation_string |= (conn_type & 0xF);
1417
1418         /* Convert to big-endian and calculate CRC8 */
1419         data_to_crc = be32_to_cpu(validation_string);
1420
1421         crc = crc8(cdu_crc8_table,
1422                    (u8 *)&data_to_crc, sizeof(data_to_crc), CRC8_INIT_VALUE);
1423
1424         /* The validation byte [7:0] is composed:
1425          * for type A validation
1426          * [7]          = active configuration bit
1427          * [6:0]        = crc[6:0]
1428          *
1429          * for type B validation
1430          * [7]          = active configuration bit
1431          * [6:3]        = connection_type[3:0]
1432          * [2:0]        = crc[2:0]
1433          */
1434         validation_byte |=
1435             ((validation_cfg >>
1436               CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7;
1437
1438         if ((validation_cfg >>
1439              CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1)
1440                 validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7);
1441         else
1442                 validation_byte |= crc & 0x7F;
1443
1444         return validation_byte;
1445 }
1446
1447 /* Calcualte and set validation bytes for session context */
1448 void qed_calc_session_ctx_validation(void *p_ctx_mem,
1449                                      u16 ctx_size, u8 ctx_type, u32 cid)
1450 {
1451         u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1452
1453         p_ctx = (u8 * const)p_ctx_mem;
1454         x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1455         t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1456         u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1457
1458         memset(p_ctx, 0, ctx_size);
1459
1460         *x_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 3, cid);
1461         *t_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 4, cid);
1462         *u_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 5, cid);
1463 }
1464
1465 /* Calcualte and set validation bytes for task context */
1466 void qed_calc_task_ctx_validation(void *p_ctx_mem,
1467                                   u16 ctx_size, u8 ctx_type, u32 tid)
1468 {
1469         u8 *p_ctx, *region1_val_ptr;
1470
1471         p_ctx = (u8 * const)p_ctx_mem;
1472         region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1473
1474         memset(p_ctx, 0, ctx_size);
1475
1476         *region1_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 1, tid);
1477 }
1478
1479 /* Memset session context to 0 while preserving validation bytes */
1480 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
1481 {
1482         u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
1483         u8 x_val, t_val, u_val;
1484
1485         p_ctx = (u8 * const)p_ctx_mem;
1486         x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
1487         t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
1488         u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
1489
1490         x_val = *x_val_ptr;
1491         t_val = *t_val_ptr;
1492         u_val = *u_val_ptr;
1493
1494         memset(p_ctx, 0, ctx_size);
1495
1496         *x_val_ptr = x_val;
1497         *t_val_ptr = t_val;
1498         *u_val_ptr = u_val;
1499 }
1500
1501 /* Memset task context to 0 while preserving validation bytes */
1502 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
1503 {
1504         u8 *p_ctx, *region1_val_ptr;
1505         u8 region1_val;
1506
1507         p_ctx = (u8 * const)p_ctx_mem;
1508         region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
1509
1510         region1_val = *region1_val_ptr;
1511
1512         memset(p_ctx, 0, ctx_size);
1513
1514         *region1_val_ptr = region1_val;
1515 }
1516
1517 /* Enable and configure context validation */
1518 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
1519                                    struct qed_ptt *p_ptt)
1520 {
1521         u32 ctx_validation;
1522
1523         /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */
1524         ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24;
1525         qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation);
1526
1527         /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */
1528         ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1529         qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation);
1530
1531         /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */
1532         ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
1533         qed_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);
1534 }
1535
1536 static u32 qed_get_rdma_assert_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id)
1537 {
1538         switch (storm_id) {
1539         case 0:
1540                 return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1541                     TSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1542         case 1:
1543                 return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1544                     MSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1545         case 2:
1546                 return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1547                     USTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1548         case 3:
1549                 return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1550                     XSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1551         case 4:
1552                 return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1553                     YSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1554         case 5:
1555                 return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1556                     PSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id);
1557
1558         default:
1559                 return 0;
1560         }
1561 }
1562
1563 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
1564                               struct qed_ptt *p_ptt,
1565                               u8 assert_level[NUM_STORMS])
1566 {
1567         u8 storm_id;
1568
1569         for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
1570                 u32 ram_addr = qed_get_rdma_assert_ram_addr(p_hwfn, storm_id);
1571
1572                 qed_wr(p_hwfn, p_ptt, ram_addr, assert_level[storm_id]);
1573         }
1574 }
1575
1576 #define PHYS_ADDR_DWORDS        DIV_ROUND_UP(sizeof(dma_addr_t), 4)
1577 #define OVERLAY_HDR_SIZE_DWORDS (sizeof(struct fw_overlay_buf_hdr) / 4)
1578
1579 static u32 qed_get_overlay_addr_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id)
1580 {
1581         switch (storm_id) {
1582         case 0:
1583                 return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1584                     TSTORM_OVERLAY_BUF_ADDR_OFFSET;
1585         case 1:
1586                 return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1587                     MSTORM_OVERLAY_BUF_ADDR_OFFSET;
1588         case 2:
1589                 return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1590                     USTORM_OVERLAY_BUF_ADDR_OFFSET;
1591         case 3:
1592                 return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1593                     XSTORM_OVERLAY_BUF_ADDR_OFFSET;
1594         case 4:
1595                 return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1596                     YSTORM_OVERLAY_BUF_ADDR_OFFSET;
1597         case 5:
1598                 return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM +
1599                     PSTORM_OVERLAY_BUF_ADDR_OFFSET;
1600
1601         default:
1602                 return 0;
1603         }
1604 }
1605
1606 struct phys_mem_desc *qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
1607                                                const u32 * const
1608                                                fw_overlay_in_buf,
1609                                                u32 buf_size_in_bytes)
1610 {
1611         u32 buf_size = buf_size_in_bytes / sizeof(u32), buf_offset = 0;
1612         struct phys_mem_desc *allocated_mem;
1613
1614         if (!buf_size)
1615                 return NULL;
1616
1617         allocated_mem = kcalloc(NUM_STORMS, sizeof(struct phys_mem_desc),
1618                                 GFP_KERNEL);
1619         if (!allocated_mem)
1620                 return NULL;
1621
1622         memset(allocated_mem, 0, NUM_STORMS * sizeof(struct phys_mem_desc));
1623
1624         /* For each Storm, set physical address in RAM */
1625         while (buf_offset < buf_size) {
1626                 struct phys_mem_desc *storm_mem_desc;
1627                 struct fw_overlay_buf_hdr *hdr;
1628                 u32 storm_buf_size;
1629                 u8 storm_id;
1630
1631                 hdr =
1632                     (struct fw_overlay_buf_hdr *)&fw_overlay_in_buf[buf_offset];
1633                 storm_buf_size = GET_FIELD(hdr->data,
1634                                            FW_OVERLAY_BUF_HDR_BUF_SIZE);
1635                 storm_id = GET_FIELD(hdr->data, FW_OVERLAY_BUF_HDR_STORM_ID);
1636                 storm_mem_desc = allocated_mem + storm_id;
1637                 storm_mem_desc->size = storm_buf_size * sizeof(u32);
1638
1639                 /* Allocate physical memory for Storm's overlays buffer */
1640                 storm_mem_desc->virt_addr =
1641                     dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1642                                        storm_mem_desc->size,
1643                                        &storm_mem_desc->phys_addr, GFP_KERNEL);
1644                 if (!storm_mem_desc->virt_addr)
1645                         break;
1646
1647                 /* Skip overlays buffer header */
1648                 buf_offset += OVERLAY_HDR_SIZE_DWORDS;
1649
1650                 /* Copy Storm's overlays buffer to allocated memory */
1651                 memcpy(storm_mem_desc->virt_addr,
1652                        &fw_overlay_in_buf[buf_offset], storm_mem_desc->size);
1653
1654                 /* Advance to next Storm */
1655                 buf_offset += storm_buf_size;
1656         }
1657
1658         /* If memory allocation has failed, free all allocated memory */
1659         if (buf_offset < buf_size) {
1660                 qed_fw_overlay_mem_free(p_hwfn, allocated_mem);
1661                 return NULL;
1662         }
1663
1664         return allocated_mem;
1665 }
1666
1667 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
1668                              struct qed_ptt *p_ptt,
1669                              struct phys_mem_desc *fw_overlay_mem)
1670 {
1671         u8 storm_id;
1672
1673         for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
1674                 struct phys_mem_desc *storm_mem_desc =
1675                     (struct phys_mem_desc *)fw_overlay_mem + storm_id;
1676                 u32 ram_addr, i;
1677
1678                 /* Skip Storms with no FW overlays */
1679                 if (!storm_mem_desc->virt_addr)
1680                         continue;
1681
1682                 /* Calculate overlay RAM GRC address of current PF */
1683                 ram_addr = qed_get_overlay_addr_ram_addr(p_hwfn, storm_id) +
1684                            sizeof(dma_addr_t) * p_hwfn->rel_pf_id;
1685
1686                 /* Write Storm's overlay physical address to RAM */
1687                 for (i = 0; i < PHYS_ADDR_DWORDS; i++, ram_addr += sizeof(u32))
1688                         qed_wr(p_hwfn, p_ptt, ram_addr,
1689                                ((u32 *)&storm_mem_desc->phys_addr)[i]);
1690         }
1691 }
1692
1693 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
1694                              struct phys_mem_desc *fw_overlay_mem)
1695 {
1696         u8 storm_id;
1697
1698         if (!fw_overlay_mem)
1699                 return;
1700
1701         for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) {
1702                 struct phys_mem_desc *storm_mem_desc =
1703                     (struct phys_mem_desc *)fw_overlay_mem + storm_id;
1704
1705                 /* Free Storm's physical memory */
1706                 if (storm_mem_desc->virt_addr)
1707                         dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1708                                           storm_mem_desc->size,
1709                                           storm_mem_desc->virt_addr,
1710                                           storm_mem_desc->phys_addr);
1711         }
1712
1713         /* Free allocated virtual memory */
1714         kfree(fw_overlay_mem);
1715 }