drivers/net/ethernet/mellanox/mlx5/core/fw.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/driver.h>
  34 #include <linux/mlx5/cmd.h>
  35 #include <linux/mlx5/eswitch.h>
  36 #include <linux/module.h>
  37 #include "mlx5_core.h"
  38 #include "../../mlxfw/mlxfw.h"
  39
  40 enum {
  41         MCQS_IDENTIFIER_BOOT_IMG        = 0x1,
  42         MCQS_IDENTIFIER_OEM_NVCONFIG    = 0x4,
  43         MCQS_IDENTIFIER_MLNX_NVCONFIG   = 0x5,
  44         MCQS_IDENTIFIER_CS_TOKEN        = 0x6,
  45         MCQS_IDENTIFIER_DBG_TOKEN       = 0x7,
  46         MCQS_IDENTIFIER_GEARBOX         = 0xA,
  47 };
  48
  49 enum {
  50         MCQS_UPDATE_STATE_IDLE,
  51         MCQS_UPDATE_STATE_IN_PROGRESS,
  52         MCQS_UPDATE_STATE_APPLIED,
  53         MCQS_UPDATE_STATE_ACTIVE,
  54         MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET,
  55         MCQS_UPDATE_STATE_FAILED,
  56         MCQS_UPDATE_STATE_CANCELED,
  57         MCQS_UPDATE_STATE_BUSY,
  58 };
  59
  60 enum {
  61         MCQI_INFO_TYPE_CAPABILITIES       = 0x0,
  62         MCQI_INFO_TYPE_VERSION            = 0x1,
  63         MCQI_INFO_TYPE_ACTIVATION_METHOD  = 0x5,
  64 };
  65
  66 enum {
  67         MCQI_FW_RUNNING_VERSION = 0,
  68         MCQI_FW_STORED_VERSION  = 1,
  69 };
  70
  71 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
  72                                   int outlen)
  73 {
  74         u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0};
  75
  76         MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
  77         return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
  78 }
  79
  80 int mlx5_query_board_id(struct mlx5_core_dev *dev)
  81 {
  82         u32 *out;
  83         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  84         int err;
  85
  86         out = kzalloc(outlen, GFP_KERNEL);
  87         if (!out)
  88                 return -ENOMEM;
  89
  90         err = mlx5_cmd_query_adapter(dev, out, outlen);
  91         if (err)
  92                 goto out;
  93
  94         memcpy(dev->board_id,
  95                MLX5_ADDR_OF(query_adapter_out, out,
  96                             query_adapter_struct.vsd_contd_psid),
  97                MLX5_FLD_SZ_BYTES(query_adapter_out,
  98                                  query_adapter_struct.vsd_contd_psid));
  99
 100 out:
 101         kfree(out);
 102         return err;
 103 }
 104
 105 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
 106 {
 107         u32 *out;
 108         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
 109         int err;
 110
 111         out = kzalloc(outlen, GFP_KERNEL);
 112         if (!out)
 113                 return -ENOMEM;
 114
 115         err = mlx5_cmd_query_adapter(mdev, out, outlen);
 116         if (err)
 117                 goto out;
 118
 119         *vendor_id = MLX5_GET(query_adapter_out, out,
 120                               query_adapter_struct.ieee_vendor_id);
 121 out:
 122         kfree(out);
 123         return err;
 124 }
 125 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
 126
 127 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
 128 {
 129         return mlx5_query_pcam_reg(dev, dev->caps.pcam,
 130                                    MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
 131                                    MLX5_PCAM_REGS_5000_TO_507F);
 132 }
 133
 134 static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
 135                                           enum mlx5_mcam_reg_groups group)
 136 {
 137         return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
 138                                    MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
 139 }
 140
 141 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
 142 {
 143         return mlx5_query_qcam_reg(dev, dev->caps.qcam,
 144                                    MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
 145                                    MLX5_QCAM_REGS_FIRST_128);
 146 }
 147
 148 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
 149 {
 150         int err;
 151
 152         err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
 153         if (err)
 154                 return err;
 155
 156         if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
 157                 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
 158                 if (err)
 159                         return err;
 160         }
 161
 162         if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 163                 err = mlx5_core_get_caps(dev, MLX5_CAP_IPOIB_ENHANCED_OFFLOADS);
 164                 if (err)
 165                         return err;
 166         }
 167
 168         if (MLX5_CAP_GEN(dev, pg)) {
 169                 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
 170                 if (err)
 171                         return err;
 172         }
 173
 174         if (MLX5_CAP_GEN(dev, atomic)) {
 175                 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
 176                 if (err)
 177                         return err;
 178         }
 179
 180         if (MLX5_CAP_GEN(dev, roce)) {
 181                 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
 182                 if (err)
 183                         return err;
 184         }
 185
 186         if (MLX5_CAP_GEN(dev, nic_flow_table) ||
 187             MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 188                 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
 189                 if (err)
 190                         return err;
 191         }
 192
 193         if (MLX5_CAP_GEN(dev, vport_group_manager) &&
 194             MLX5_ESWITCH_MANAGER(dev)) {
 195                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
 196                 if (err)
 197                         return err;
 198         }
 199
 200         if (MLX5_ESWITCH_MANAGER(dev)) {
 201                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
 202                 if (err)
 203                         return err;
 204         }
 205
 206         if (MLX5_CAP_GEN(dev, vector_calc)) {
 207                 err = mlx5_core_get_caps(dev, MLX5_CAP_VECTOR_CALC);
 208                 if (err)
 209                         return err;
 210         }
 211
 212         if (MLX5_CAP_GEN(dev, qos)) {
 213                 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
 214                 if (err)
 215                         return err;
 216         }
 217
 218         if (MLX5_CAP_GEN(dev, debug))
 219                 mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
 220
 221         if (MLX5_CAP_GEN(dev, pcam_reg))
 222                 mlx5_get_pcam_reg(dev);
 223
 224         if (MLX5_CAP_GEN(dev, mcam_reg)) {
 225                 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
 226                 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF);
 227                 mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
 228         }
 229
 230         if (MLX5_CAP_GEN(dev, qcam_reg))
 231                 mlx5_get_qcam_reg(dev);
 232
 233         if (MLX5_CAP_GEN(dev, device_memory)) {
 234                 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_MEM);
 235                 if (err)
 236                         return err;
 237         }
 238
 239         if (MLX5_CAP_GEN(dev, event_cap)) {
 240                 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_EVENT);
 241                 if (err)
 242                         return err;
 243         }
 244
 245         if (MLX5_CAP_GEN(dev, tls_tx)) {
 246                 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
 247                 if (err)
 248                         return err;
 249         }
 250
 251         if (MLX5_CAP_GEN_64(dev, general_obj_types) &
 252                 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
 253                 err = mlx5_core_get_caps(dev, MLX5_CAP_VDPA_EMULATION);
 254                 if (err)
 255                         return err;
 256         }
 257
 258         return 0;
 259 }
 260
 261 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id)
 262 {
 263         u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0};
 264         u32 in[MLX5_ST_SZ_DW(init_hca_in)]   = {0};
 265         int i;
 266
 267         MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
 268
 269         if (MLX5_CAP_GEN(dev, sw_owner_id)) {
 270                 for (i = 0; i < 4; i++)
 271                         MLX5_ARRAY_SET(init_hca_in, in, sw_owner_id, i,
 272                                        sw_owner_id[i]);
 273         }
 274
 275         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 276 }
 277
 278 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
 279 {
 280         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 281         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)]   = {0};
 282
 283         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 284         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 285 }
 286
 287 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
 288 {
 289         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 290         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 291         int force_state;
 292         int ret;
 293
 294         if (!MLX5_CAP_GEN(dev, force_teardown)) {
 295                 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
 296                 return -EOPNOTSUPP;
 297         }
 298
 299         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 300         MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
 301
 302         ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
 303         if (ret)
 304                 return ret;
 305
 306         force_state = MLX5_GET(teardown_hca_out, out, state);
 307         if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
 308                 mlx5_core_warn(dev, "teardown with force mode failed, doing normal teardown\n");
 309                 return -EIO;
 310         }
 311
 312         return 0;
 313 }
 314
 315 #define MLX5_FAST_TEARDOWN_WAIT_MS   3000
 316 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
 317 {
 318         unsigned long end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
 319         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 320         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 321         int state;
 322         int ret;
 323
 324         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 325                 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
 326                 return -EOPNOTSUPP;
 327         }
 328
 329         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 330         MLX5_SET(teardown_hca_in, in, profile,
 331                  MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
 332
 333         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 334         if (ret)
 335                 return ret;
 336
 337         state = MLX5_GET(teardown_hca_out, out, state);
 338         if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
 339                 mlx5_core_warn(dev, "teardown with fast mode failed\n");
 340                 return -EIO;
 341         }
 342
 343         mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
 344
 345         /* Loop until device state turns to disable */
 346         end = jiffies + msecs_to_jiffies(delay_ms);
 347         do {
 348                 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
 349                         break;
 350
 351                 cond_resched();
 352         } while (!time_after(jiffies, end));
 353
 354         if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
 355                 dev_err(&dev->pdev->dev, "NIC IFC still %d after %lums.\n",
 356                         mlx5_get_nic_state(dev), delay_ms);
 357                 return -EIO;
 358         }
 359
 360         return 0;
 361 }
 362
 363 enum mlxsw_reg_mcc_instruction {
 364         MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
 365         MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
 366         MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
 367         MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
 368         MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
 369         MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
 370 };
 371
 372 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
 373                             enum mlxsw_reg_mcc_instruction instr,
 374                             u16 component_index, u32 update_handle,
 375                             u32 component_size)
 376 {
 377         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 378         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 379
 380         memset(in, 0, sizeof(in));
 381
 382         MLX5_SET(mcc_reg, in, instruction, instr);
 383         MLX5_SET(mcc_reg, in, component_index, component_index);
 384         MLX5_SET(mcc_reg, in, update_handle, update_handle);
 385         MLX5_SET(mcc_reg, in, component_size, component_size);
 386
 387         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 388                                     sizeof(out), MLX5_REG_MCC, 0, 1);
 389 }
 390
 391 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
 392                               u32 *update_handle, u8 *error_code,
 393                               u8 *control_state)
 394 {
 395         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 396         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 397         int err;
 398
 399         memset(in, 0, sizeof(in));
 400         memset(out, 0, sizeof(out));
 401         MLX5_SET(mcc_reg, in, update_handle, *update_handle);
 402
 403         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 404                                    sizeof(out), MLX5_REG_MCC, 0, 0);
 405         if (err)
 406                 goto out;
 407
 408         *update_handle = MLX5_GET(mcc_reg, out, update_handle);
 409         *error_code = MLX5_GET(mcc_reg, out, error_code);
 410         *control_state = MLX5_GET(mcc_reg, out, control_state);
 411
 412 out:
 413         return err;
 414 }
 415
 416 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
 417                              u32 update_handle,
 418                              u32 offset, u16 size,
 419                              u8 *data)
 420 {
 421         int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
 422         u32 out[MLX5_ST_SZ_DW(mcda_reg)];
 423         int i, j, dw_size = size >> 2;
 424         __be32 data_element;
 425         u32 *in;
 426
 427         in = kzalloc(in_size, GFP_KERNEL);
 428         if (!in)
 429                 return -ENOMEM;
 430
 431         MLX5_SET(mcda_reg, in, update_handle, update_handle);
 432         MLX5_SET(mcda_reg, in, offset, offset);
 433         MLX5_SET(mcda_reg, in, size, size);
 434
 435         for (i = 0; i < dw_size; i++) {
 436                 j = i * 4;
 437                 data_element = htonl(*(u32 *)&data[j]);
 438                 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
 439         }
 440
 441         err = mlx5_core_access_reg(dev, in, in_size, out,
 442                                    sizeof(out), MLX5_REG_MCDA, 0, 1);
 443         kfree(in);
 444         return err;
 445 }
 446
 447 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
 448                                u16 component_index, bool read_pending,
 449                                u8 info_type, u16 data_size, void *mcqi_data)
 450 {
 451         u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_UN_SZ_DW(mcqi_reg_data)] = {};
 452         u32 in[MLX5_ST_SZ_DW(mcqi_reg)] = {};
 453         void *data;
 454         int err;
 455
 456         MLX5_SET(mcqi_reg, in, component_index, component_index);
 457         MLX5_SET(mcqi_reg, in, read_pending_component, read_pending);
 458         MLX5_SET(mcqi_reg, in, info_type, info_type);
 459         MLX5_SET(mcqi_reg, in, data_size, data_size);
 460
 461         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 462                                    MLX5_ST_SZ_BYTES(mcqi_reg) + data_size,
 463                                    MLX5_REG_MCQI, 0, 0);
 464         if (err)
 465                 return err;
 466
 467         data = MLX5_ADDR_OF(mcqi_reg, out, data);
 468         memcpy(mcqi_data, data, data_size);
 469
 470         return 0;
 471 }
 472
 473 static int mlx5_reg_mcqi_caps_query(struct mlx5_core_dev *dev, u16 component_index,
 474                                     u32 *max_component_size, u8 *log_mcda_word_size,
 475                                     u16 *mcda_max_write_size)
 476 {
 477         u32 mcqi_reg[MLX5_ST_SZ_DW(mcqi_cap)] = {};
 478         int err;
 479
 480         err = mlx5_reg_mcqi_query(dev, component_index, 0,
 481                                   MCQI_INFO_TYPE_CAPABILITIES,
 482                                   MLX5_ST_SZ_BYTES(mcqi_cap), mcqi_reg);
 483         if (err)
 484                 return err;
 485
 486         *max_component_size = MLX5_GET(mcqi_cap, mcqi_reg, max_component_size);
 487         *log_mcda_word_size = MLX5_GET(mcqi_cap, mcqi_reg, log_mcda_word_size);
 488         *mcda_max_write_size = MLX5_GET(mcqi_cap, mcqi_reg, mcda_max_write_size);
 489
 490         return 0;
 491 }
 492
 493 struct mlx5_mlxfw_dev {
 494         struct mlxfw_dev mlxfw_dev;
 495         struct mlx5_core_dev *mlx5_core_dev;
 496 };
 497
 498 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
 499                                 u16 component_index, u32 *p_max_size,
 500                                 u8 *p_align_bits, u16 *p_max_write_size)
 501 {
 502         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 503                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 504         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 505
 506         if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi)) {
 507                 mlx5_core_warn(dev, "caps query isn't supported by running FW\n");
 508                 return -EOPNOTSUPP;
 509         }
 510
 511         return mlx5_reg_mcqi_caps_query(dev, component_index, p_max_size,
 512                                         p_align_bits, p_max_write_size);
 513 }
 514
 515 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 516 {
 517         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 518                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 519         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 520         u8 control_state, error_code;
 521         int err;
 522
 523         *fwhandle = 0;
 524         err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
 525         if (err)
 526                 return err;
 527
 528         if (control_state != MLXFW_FSM_STATE_IDLE)
 529                 return -EBUSY;
 530
 531         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 532                                 0, *fwhandle, 0);
 533 }
 534
 535 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 536                                      u16 component_index, u32 component_size)
 537 {
 538         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 539                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 540         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 541
 542         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 543                                 component_index, fwhandle, component_size);
 544 }
 545
 546 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 547                                    u8 *data, u16 size, u32 offset)
 548 {
 549         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 550                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 551         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 552
 553         return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
 554 }
 555
 556 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 557                                      u16 component_index)
 558 {
 559         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 560                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 561         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 562
 563         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 564                                 component_index, fwhandle, 0);
 565 }
 566
 567 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 568 {
 569         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 570                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 571         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 572
 573         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 574                                 fwhandle, 0);
 575 }
 576
 577 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 578                                 enum mlxfw_fsm_state *fsm_state,
 579                                 enum mlxfw_fsm_state_err *fsm_state_err)
 580 {
 581         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 582                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 583         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 584         u8 control_state, error_code;
 585         int err;
 586
 587         err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
 588         if (err)
 589                 return err;
 590
 591         *fsm_state = control_state;
 592         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 593                                MLXFW_FSM_STATE_ERR_MAX);
 594         return 0;
 595 }
 596
 597 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 598 {
 599         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 600                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 601         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 602
 603         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
 604 }
 605
 606 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 607 {
 608         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 609                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 610         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 611
 612         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 613                          fwhandle, 0);
 614 }
 615
 616 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
 617         .component_query        = mlx5_component_query,
 618         .fsm_lock               = mlx5_fsm_lock,
 619         .fsm_component_update   = mlx5_fsm_component_update,
 620         .fsm_block_download     = mlx5_fsm_block_download,
 621         .fsm_component_verify   = mlx5_fsm_component_verify,
 622         .fsm_activate           = mlx5_fsm_activate,
 623         .fsm_query_state        = mlx5_fsm_query_state,
 624         .fsm_cancel             = mlx5_fsm_cancel,
 625         .fsm_release            = mlx5_fsm_release
 626 };
 627
 628 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
 629                         const struct firmware *firmware,
 630                         struct netlink_ext_ack *extack)
 631 {
 632         struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
 633                 .mlxfw_dev = {
 634                         .ops = &mlx5_mlxfw_dev_ops,
 635                         .psid = dev->board_id,
 636                         .psid_size = strlen(dev->board_id),
 637                 },
 638                 .mlx5_core_dev = dev
 639         };
 640
 641         if (!MLX5_CAP_GEN(dev, mcam_reg)  ||
 642             !MLX5_CAP_MCAM_REG(dev, mcqi) ||
 643             !MLX5_CAP_MCAM_REG(dev, mcc)  ||
 644             !MLX5_CAP_MCAM_REG(dev, mcda)) {
 645                 pr_info("%s flashing isn't supported by the running FW\n", __func__);
 646                 return -EOPNOTSUPP;
 647         }
 648
 649         return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev,
 650                                     firmware, extack);
 651 }
 652
 653 static int mlx5_reg_mcqi_version_query(struct mlx5_core_dev *dev,
 654                                        u16 component_index, bool read_pending,
 655                                        u32 *mcqi_version_out)
 656 {
 657         return mlx5_reg_mcqi_query(dev, component_index, read_pending,
 658                                    MCQI_INFO_TYPE_VERSION,
 659                                    MLX5_ST_SZ_BYTES(mcqi_version),
 660                                    mcqi_version_out);
 661 }
 662
 663 static int mlx5_reg_mcqs_query(struct mlx5_core_dev *dev, u32 *out,
 664                                u16 component_index)
 665 {
 666         u8 out_sz = MLX5_ST_SZ_BYTES(mcqs_reg);
 667         u32 in[MLX5_ST_SZ_DW(mcqs_reg)] = {};
 668         int err;
 669
 670         memset(out, 0, out_sz);
 671
 672         MLX5_SET(mcqs_reg, in, component_index, component_index);
 673
 674         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 675                                    out_sz, MLX5_REG_MCQS, 0, 0);
 676         return err;
 677 }
 678
 679 /* scans component index sequentially, to find the boot img index */
 680 static int mlx5_get_boot_img_component_index(struct mlx5_core_dev *dev)
 681 {
 682         u32 out[MLX5_ST_SZ_DW(mcqs_reg)] = {};
 683         u16 identifier, component_idx = 0;
 684         bool quit;
 685         int err;
 686
 687         do {
 688                 err = mlx5_reg_mcqs_query(dev, out, component_idx);
 689                 if (err)
 690                         return err;
 691
 692                 identifier = MLX5_GET(mcqs_reg, out, identifier);
 693                 quit = !!MLX5_GET(mcqs_reg, out, last_index_flag);
 694                 quit |= identifier == MCQS_IDENTIFIER_BOOT_IMG;
 695         } while (!quit && ++component_idx);
 696
 697         if (identifier != MCQS_IDENTIFIER_BOOT_IMG) {
 698                 mlx5_core_warn(dev, "mcqs: can't find boot_img component ix, last scanned idx %d\n",
 699                                component_idx);
 700                 return -EOPNOTSUPP;
 701         }
 702
 703         return component_idx;
 704 }
 705
 706 static int
 707 mlx5_fw_image_pending(struct mlx5_core_dev *dev,
 708                       int component_index,
 709                       bool *pending_version_exists)
 710 {
 711         u32 out[MLX5_ST_SZ_DW(mcqs_reg)];
 712         u8 component_update_state;
 713         int err;
 714
 715         err = mlx5_reg_mcqs_query(dev, out, component_index);
 716         if (err)
 717                 return err;
 718
 719         component_update_state = MLX5_GET(mcqs_reg, out, component_update_state);
 720
 721         if (component_update_state == MCQS_UPDATE_STATE_IDLE) {
 722                 *pending_version_exists = false;
 723         } else if (component_update_state == MCQS_UPDATE_STATE_ACTIVE_PENDING_RESET) {
 724                 *pending_version_exists = true;
 725         } else {
 726                 mlx5_core_warn(dev,
 727                                "mcqs: can't read pending fw version while fw state is %d\n",
 728                                component_update_state);
 729                 return -ENODATA;
 730         }
 731         return 0;
 732 }
 733
 734 int mlx5_fw_version_query(struct mlx5_core_dev *dev,
 735                           u32 *running_ver, u32 *pending_ver)
 736 {
 737         u32 reg_mcqi_version[MLX5_ST_SZ_DW(mcqi_version)] = {};
 738         bool pending_version_exists;
 739         int component_index;
 740         int err;
 741
 742         if (!MLX5_CAP_GEN(dev, mcam_reg) || !MLX5_CAP_MCAM_REG(dev, mcqi) ||
 743             !MLX5_CAP_MCAM_REG(dev, mcqs)) {
 744                 mlx5_core_warn(dev, "fw query isn't supported by the FW\n");
 745                 return -EOPNOTSUPP;
 746         }
 747
 748         component_index = mlx5_get_boot_img_component_index(dev);
 749         if (component_index < 0)
 750                 return component_index;
 751
 752         err = mlx5_reg_mcqi_version_query(dev, component_index,
 753                                           MCQI_FW_RUNNING_VERSION,
 754                                           reg_mcqi_version);
 755         if (err)
 756                 return err;
 757
 758         *running_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
 759
 760         err = mlx5_fw_image_pending(dev, component_index, &pending_version_exists);
 761         if (err)
 762                 return err;
 763
 764         if (!pending_version_exists) {
 765                 *pending_ver = 0;
 766                 return 0;
 767         }
 768
 769         err = mlx5_reg_mcqi_version_query(dev, component_index,
 770                                           MCQI_FW_STORED_VERSION,
 771                                           reg_mcqi_version);
 772         if (err)
 773                 return err;
 774
 775         *pending_ver = MLX5_GET(mcqi_version, reg_mcqi_version, version);
 776
 777         return 0;
 778 }