drivers/net/ethernet/emulex/benet/be_cmds.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2005 - 2016 Broadcom
   4  * All rights reserved.
   5  *
   6  * Contact Information:
   7  * [email protected]
   8  *
   9  * Emulex
  10  * 3333 Susan Street
  11  * Costa Mesa, CA 92626
  12  */
  13
  14 #include <linux/module.h>
  15 #include "be.h"
  16 #include "be_cmds.h"
  17
  18 const char * const be_misconfig_evt_port_state[] = {
  19         "Physical Link is functional",
  20         "Optics faulted/incorrectly installed/not installed - Reseat optics. If issue not resolved, replace.",
  21         "Optics of two types installed – Remove one optic or install matching pair of optics.",
  22         "Incompatible optics – Replace with compatible optics for card to function.",
  23         "Unqualified optics – Replace with Avago optics for Warranty and Technical Support.",
  24         "Uncertified optics – Replace with Avago-certified optics to enable link operation."
  25 };
  26
  27 static char *be_port_misconfig_evt_severity[] = {
  28         "KERN_WARN",
  29         "KERN_INFO",
  30         "KERN_ERR",
  31         "KERN_WARN"
  32 };
  33
  34 static char *phy_state_oper_desc[] = {
  35         "Link is non-operational",
  36         "Link is operational",
  37         ""
  38 };
  39
  40 static struct be_cmd_priv_map cmd_priv_map[] = {
  41         {
  42                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  43                 CMD_SUBSYSTEM_ETH,
  44                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  45                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  46         },
  47         {
  48                 OPCODE_COMMON_GET_FLOW_CONTROL,
  49                 CMD_SUBSYSTEM_COMMON,
  50                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  51                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  52         },
  53         {
  54                 OPCODE_COMMON_SET_FLOW_CONTROL,
  55                 CMD_SUBSYSTEM_COMMON,
  56                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  57                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  58         },
  59         {
  60                 OPCODE_ETH_GET_PPORT_STATS,
  61                 CMD_SUBSYSTEM_ETH,
  62                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  63                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  64         },
  65         {
  66                 OPCODE_COMMON_GET_PHY_DETAILS,
  67                 CMD_SUBSYSTEM_COMMON,
  68                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  69                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  70         },
  71         {
  72                 OPCODE_LOWLEVEL_HOST_DDR_DMA,
  73                 CMD_SUBSYSTEM_LOWLEVEL,
  74                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  75         },
  76         {
  77                 OPCODE_LOWLEVEL_LOOPBACK_TEST,
  78                 CMD_SUBSYSTEM_LOWLEVEL,
  79                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  80         },
  81         {
  82                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
  83                 CMD_SUBSYSTEM_LOWLEVEL,
  84                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  85         },
  86         {
  87                 OPCODE_COMMON_SET_HSW_CONFIG,
  88                 CMD_SUBSYSTEM_COMMON,
  89                 BE_PRIV_DEVCFG | BE_PRIV_VHADM |
  90                 BE_PRIV_DEVSEC
  91         },
  92         {
  93                 OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
  94                 CMD_SUBSYSTEM_COMMON,
  95                 BE_PRIV_DEVCFG
  96         }
  97 };
  98
  99 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
 100 {
 101         int i;
 102         int num_entries = ARRAY_SIZE(cmd_priv_map);
 103         u32 cmd_privileges = adapter->cmd_privileges;
 104
 105         for (i = 0; i < num_entries; i++)
 106                 if (opcode == cmd_priv_map[i].opcode &&
 107                     subsystem == cmd_priv_map[i].subsystem)
 108                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
 109                                 return false;
 110
 111         return true;
 112 }
 113
 114 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 115 {
 116         return wrb->payload.embedded_payload;
 117 }
 118
 119 static int be_mcc_notify(struct be_adapter *adapter)
 120 {
 121         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 122         u32 val = 0;
 123
 124         if (be_check_error(adapter, BE_ERROR_ANY))
 125                 return -EIO;
 126
 127         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 128         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 129
 130         wmb();
 131         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 132
 133         return 0;
 134 }
 135
 136 /* To check if valid bit is set, check the entire word as we don't know
 137  * the endianness of the data (old entry is host endian while a new entry is
 138  * little endian) */
 139 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 140 {
 141         u32 flags;
 142
 143         if (compl->flags != 0) {
 144                 flags = le32_to_cpu(compl->flags);
 145                 if (flags & CQE_FLAGS_VALID_MASK) {
 146                         compl->flags = flags;
 147                         return true;
 148                 }
 149         }
 150         return false;
 151 }
 152
 153 /* Need to reset the entire word that houses the valid bit */
 154 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 155 {
 156         compl->flags = 0;
 157 }
 158
 159 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 160 {
 161         unsigned long addr;
 162
 163         addr = tag1;
 164         addr = ((addr << 16) << 16) | tag0;
 165         return (void *)addr;
 166 }
 167
 168 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 169 {
 170         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 171             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 172             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 173             addl_status == MCC_ADDL_STATUS_INSUFFICIENT_VLANS ||
 174             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 175             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 176              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 177                 return true;
 178         else
 179                 return false;
 180 }
 181
 182 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 183  * loop (has not issued be_mcc_notify_wait())
 184  */
 185 static void be_async_cmd_process(struct be_adapter *adapter,
 186                                  struct be_mcc_compl *compl,
 187                                  struct be_cmd_resp_hdr *resp_hdr)
 188 {
 189         enum mcc_base_status base_status = base_status(compl->status);
 190         u8 opcode = 0, subsystem = 0;
 191
 192         if (resp_hdr) {
 193                 opcode = resp_hdr->opcode;
 194                 subsystem = resp_hdr->subsystem;
 195         }
 196
 197         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 198             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 199                 complete(&adapter->et_cmd_compl);
 200                 return;
 201         }
 202
 203         if (opcode == OPCODE_LOWLEVEL_SET_LOOPBACK_MODE &&
 204             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 205                 complete(&adapter->et_cmd_compl);
 206                 return;
 207         }
 208
 209         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 210              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 211             subsystem == CMD_SUBSYSTEM_COMMON) {
 212                 adapter->flash_status = compl->status;
 213                 complete(&adapter->et_cmd_compl);
 214                 return;
 215         }
 216
 217         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 218              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 219             subsystem == CMD_SUBSYSTEM_ETH &&
 220             base_status == MCC_STATUS_SUCCESS) {
 221                 be_parse_stats(adapter);
 222                 adapter->stats_cmd_sent = false;
 223                 return;
 224         }
 225
 226         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 227             subsystem == CMD_SUBSYSTEM_COMMON) {
 228                 if (base_status == MCC_STATUS_SUCCESS) {
 229                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 230                                                         (void *)resp_hdr;
 231                         adapter->hwmon_info.be_on_die_temp =
 232                                                 resp->on_die_temperature;
 233                 } else {
 234                         adapter->be_get_temp_freq = 0;
 235                         adapter->hwmon_info.be_on_die_temp =
 236                                                 BE_INVALID_DIE_TEMP;
 237                 }
 238                 return;
 239         }
 240 }
 241
 242 static int be_mcc_compl_process(struct be_adapter *adapter,
 243                                 struct be_mcc_compl *compl)
 244 {
 245         enum mcc_base_status base_status;
 246         enum mcc_addl_status addl_status;
 247         struct be_cmd_resp_hdr *resp_hdr;
 248         u8 opcode = 0, subsystem = 0;
 249
 250         /* Just swap the status to host endian; mcc tag is opaquely copied
 251          * from mcc_wrb */
 252         be_dws_le_to_cpu(compl, 4);
 253
 254         base_status = base_status(compl->status);
 255         addl_status = addl_status(compl->status);
 256
 257         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 258         if (resp_hdr) {
 259                 opcode = resp_hdr->opcode;
 260                 subsystem = resp_hdr->subsystem;
 261         }
 262
 263         be_async_cmd_process(adapter, compl, resp_hdr);
 264
 265         if (base_status != MCC_STATUS_SUCCESS &&
 266             !be_skip_err_log(opcode, base_status, addl_status)) {
 267                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST ||
 268                     addl_status == MCC_ADDL_STATUS_INSUFFICIENT_PRIVILEGES) {
 269                         dev_warn(&adapter->pdev->dev,
 270                                  "VF is not privileged to issue opcode %d-%d\n",
 271                                  opcode, subsystem);
 272                 } else {
 273                         dev_err(&adapter->pdev->dev,
 274                                 "opcode %d-%d failed:status %d-%d\n",
 275                                 opcode, subsystem, base_status, addl_status);
 276                 }
 277         }
 278         return compl->status;
 279 }
 280
 281 /* Link state evt is a string of bytes; no need for endian swapping */
 282 static void be_async_link_state_process(struct be_adapter *adapter,
 283                                         struct be_mcc_compl *compl)
 284 {
 285         struct be_async_event_link_state *evt =
 286                         (struct be_async_event_link_state *)compl;
 287
 288         /* When link status changes, link speed must be re-queried from FW */
 289         adapter->phy.link_speed = -1;
 290
 291         /* On BEx the FW does not send a separate link status
 292          * notification for physical and logical link.
 293          * On other chips just process the logical link
 294          * status notification
 295          */
 296         if (!BEx_chip(adapter) &&
 297             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 298                 return;
 299
 300         /* For the initial link status do not rely on the ASYNC event as
 301          * it may not be received in some cases.
 302          */
 303         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 304                 be_link_status_update(adapter,
 305                                       evt->port_link_status & LINK_STATUS_MASK);
 306 }
 307
 308 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 309                                                   struct be_mcc_compl *compl)
 310 {
 311         struct be_async_event_misconfig_port *evt =
 312                         (struct be_async_event_misconfig_port *)compl;
 313         u32 sfp_misconfig_evt_word1 = le32_to_cpu(evt->event_data_word1);
 314         u32 sfp_misconfig_evt_word2 = le32_to_cpu(evt->event_data_word2);
 315         u8 phy_oper_state = PHY_STATE_OPER_MSG_NONE;
 316         struct device *dev = &adapter->pdev->dev;
 317         u8 msg_severity = DEFAULT_MSG_SEVERITY;
 318         u8 phy_state_info;
 319         u8 new_phy_state;
 320
 321         new_phy_state =
 322                 (sfp_misconfig_evt_word1 >> (adapter->hba_port_num * 8)) & 0xff;
 323
 324         if (new_phy_state == adapter->phy_state)
 325                 return;
 326
 327         adapter->phy_state = new_phy_state;
 328
 329         /* for older fw that doesn't populate link effect data */
 330         if (!sfp_misconfig_evt_word2)
 331                 goto log_message;
 332
 333         phy_state_info =
 334                 (sfp_misconfig_evt_word2 >> (adapter->hba_port_num * 8)) & 0xff;
 335
 336         if (phy_state_info & PHY_STATE_INFO_VALID) {
 337                 msg_severity = (phy_state_info & PHY_STATE_MSG_SEVERITY) >> 1;
 338
 339                 if (be_phy_unqualified(new_phy_state))
 340                         phy_oper_state = (phy_state_info & PHY_STATE_OPER);
 341         }
 342
 343 log_message:
 344         /* Log an error message that would allow a user to determine
 345          * whether the SFPs have an issue
 346          */
 347         if (be_phy_state_unknown(new_phy_state))
 348                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 349                            "Port %c: Unrecognized Optics state: 0x%x. %s",
 350                            adapter->port_name,
 351                            new_phy_state,
 352                            phy_state_oper_desc[phy_oper_state]);
 353         else
 354                 dev_printk(be_port_misconfig_evt_severity[msg_severity], dev,
 355                            "Port %c: %s %s",
 356                            adapter->port_name,
 357                            be_misconfig_evt_port_state[new_phy_state],
 358                            phy_state_oper_desc[phy_oper_state]);
 359
 360         /* Log Vendor name and part no. if a misconfigured SFP is detected */
 361         if (be_phy_misconfigured(new_phy_state))
 362                 adapter->flags |= BE_FLAGS_PHY_MISCONFIGURED;
 363 }
 364
 365 /* Grp5 CoS Priority evt */
 366 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 367                                                struct be_mcc_compl *compl)
 368 {
 369         struct be_async_event_grp5_cos_priority *evt =
 370                         (struct be_async_event_grp5_cos_priority *)compl;
 371
 372         if (evt->valid) {
 373                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 374                 adapter->recommended_prio_bits =
 375                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 376         }
 377 }
 378
 379 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 380 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 381                                             struct be_mcc_compl *compl)
 382 {
 383         struct be_async_event_grp5_qos_link_speed *evt =
 384                         (struct be_async_event_grp5_qos_link_speed *)compl;
 385
 386         if (adapter->phy.link_speed >= 0 &&
 387             evt->physical_port == adapter->port_num)
 388                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 389 }
 390
 391 /*Grp5 PVID evt*/
 392 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 393                                              struct be_mcc_compl *compl)
 394 {
 395         struct be_async_event_grp5_pvid_state *evt =
 396                         (struct be_async_event_grp5_pvid_state *)compl;
 397
 398         if (evt->enabled) {
 399                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 400                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 401         } else {
 402                 adapter->pvid = 0;
 403         }
 404 }
 405
 406 #define MGMT_ENABLE_MASK        0x4
 407 static void be_async_grp5_fw_control_process(struct be_adapter *adapter,
 408                                              struct be_mcc_compl *compl)
 409 {
 410         struct be_async_fw_control *evt = (struct be_async_fw_control *)compl;
 411         u32 evt_dw1 = le32_to_cpu(evt->event_data_word1);
 412
 413         if (evt_dw1 & MGMT_ENABLE_MASK) {
 414                 adapter->flags |= BE_FLAGS_OS2BMC;
 415                 adapter->bmc_filt_mask = le32_to_cpu(evt->event_data_word2);
 416         } else {
 417                 adapter->flags &= ~BE_FLAGS_OS2BMC;
 418         }
 419 }
 420
 421 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 422                                       struct be_mcc_compl *compl)
 423 {
 424         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 425                                 ASYNC_EVENT_TYPE_MASK;
 426
 427         switch (event_type) {
 428         case ASYNC_EVENT_COS_PRIORITY:
 429                 be_async_grp5_cos_priority_process(adapter, compl);
 430                 break;
 431         case ASYNC_EVENT_QOS_SPEED:
 432                 be_async_grp5_qos_speed_process(adapter, compl);
 433                 break;
 434         case ASYNC_EVENT_PVID_STATE:
 435                 be_async_grp5_pvid_state_process(adapter, compl);
 436                 break;
 437         /* Async event to disable/enable os2bmc and/or mac-learning */
 438         case ASYNC_EVENT_FW_CONTROL:
 439                 be_async_grp5_fw_control_process(adapter, compl);
 440                 break;
 441         default:
 442                 break;
 443         }
 444 }
 445
 446 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 447                                      struct be_mcc_compl *cmp)
 448 {
 449         u8 event_type = 0;
 450         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 451
 452         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 453                         ASYNC_EVENT_TYPE_MASK;
 454
 455         switch (event_type) {
 456         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 457                 if (evt->valid)
 458                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 459                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 460         break;
 461         default:
 462                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 463                          event_type);
 464         break;
 465         }
 466 }
 467
 468 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 469                                          struct be_mcc_compl *cmp)
 470 {
 471         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 472                         ASYNC_EVENT_TYPE_MASK;
 473
 474         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 475                 be_async_port_misconfig_event_process(adapter, cmp);
 476 }
 477
 478 static inline bool is_link_state_evt(u32 flags)
 479 {
 480         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 481                         ASYNC_EVENT_CODE_LINK_STATE;
 482 }
 483
 484 static inline bool is_grp5_evt(u32 flags)
 485 {
 486         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 487                         ASYNC_EVENT_CODE_GRP_5;
 488 }
 489
 490 static inline bool is_dbg_evt(u32 flags)
 491 {
 492         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 493                         ASYNC_EVENT_CODE_QNQ;
 494 }
 495
 496 static inline bool is_sliport_evt(u32 flags)
 497 {
 498         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 499                 ASYNC_EVENT_CODE_SLIPORT;
 500 }
 501
 502 static void be_mcc_event_process(struct be_adapter *adapter,
 503                                  struct be_mcc_compl *compl)
 504 {
 505         if (is_link_state_evt(compl->flags))
 506                 be_async_link_state_process(adapter, compl);
 507         else if (is_grp5_evt(compl->flags))
 508                 be_async_grp5_evt_process(adapter, compl);
 509         else if (is_dbg_evt(compl->flags))
 510                 be_async_dbg_evt_process(adapter, compl);
 511         else if (is_sliport_evt(compl->flags))
 512                 be_async_sliport_evt_process(adapter, compl);
 513 }
 514
 515 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 516 {
 517         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 518         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 519
 520         if (be_mcc_compl_is_new(compl)) {
 521                 queue_tail_inc(mcc_cq);
 522                 return compl;
 523         }
 524         return NULL;
 525 }
 526
 527 void be_async_mcc_enable(struct be_adapter *adapter)
 528 {
 529         spin_lock_bh(&adapter->mcc_cq_lock);
 530
 531         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 532         adapter->mcc_obj.rearm_cq = true;
 533
 534         spin_unlock_bh(&adapter->mcc_cq_lock);
 535 }
 536
 537 void be_async_mcc_disable(struct be_adapter *adapter)
 538 {
 539         spin_lock_bh(&adapter->mcc_cq_lock);
 540
 541         adapter->mcc_obj.rearm_cq = false;
 542         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 543
 544         spin_unlock_bh(&adapter->mcc_cq_lock);
 545 }
 546
 547 int be_process_mcc(struct be_adapter *adapter)
 548 {
 549         struct be_mcc_compl *compl;
 550         int num = 0, status = 0;
 551         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 552
 553         spin_lock_bh(&adapter->mcc_cq_lock);
 554
 555         while ((compl = be_mcc_compl_get(adapter))) {
 556                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 557                         be_mcc_event_process(adapter, compl);
 558                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 559                         status = be_mcc_compl_process(adapter, compl);
 560                         atomic_dec(&mcc_obj->q.used);
 561                 }
 562                 be_mcc_compl_use(compl);
 563                 num++;
 564         }
 565
 566         if (num)
 567                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 568
 569         spin_unlock_bh(&adapter->mcc_cq_lock);
 570         return status;
 571 }
 572
 573 /* Wait till no more pending mcc requests are present */
 574 static int be_mcc_wait_compl(struct be_adapter *adapter)
 575 {
 576 #define mcc_timeout             12000 /* 12s timeout */
 577         int i, status = 0;
 578         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 579
 580         for (i = 0; i < mcc_timeout; i++) {
 581                 if (be_check_error(adapter, BE_ERROR_ANY))
 582                         return -EIO;
 583
 584                 status = be_process_mcc(adapter);
 585
 586                 if (atomic_read(&mcc_obj->q.used) == 0)
 587                         break;
 588                 usleep_range(500, 1000);
 589         }
 590         if (i == mcc_timeout) {
 591                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 592                 be_set_error(adapter, BE_ERROR_FW);
 593                 return -EIO;
 594         }
 595         return status;
 596 }
 597
 598 /* Notify MCC requests and wait for completion */
 599 static int be_mcc_notify_wait(struct be_adapter *adapter)
 600 {
 601         int status;
 602         struct be_mcc_wrb *wrb;
 603         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 604         u32 index = mcc_obj->q.head;
 605         struct be_cmd_resp_hdr *resp;
 606
 607         index_dec(&index, mcc_obj->q.len);
 608         wrb = queue_index_node(&mcc_obj->q, index);
 609
 610         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 611
 612         status = be_mcc_notify(adapter);
 613         if (status)
 614                 goto out;
 615
 616         status = be_mcc_wait_compl(adapter);
 617         if (status == -EIO)
 618                 goto out;
 619
 620         status = (resp->base_status |
 621                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 622                    CQE_ADDL_STATUS_SHIFT));
 623 out:
 624         return status;
 625 }
 626
 627 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 628 {
 629         int msecs = 0;
 630         u32 ready;
 631
 632         do {
 633                 if (be_check_error(adapter, BE_ERROR_ANY))
 634                         return -EIO;
 635
 636                 ready = ioread32(db);
 637                 if (ready == 0xffffffff)
 638                         return -1;
 639
 640                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 641                 if (ready)
 642                         break;
 643
 644                 if (msecs > 4000) {
 645                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 646                         be_set_error(adapter, BE_ERROR_FW);
 647                         be_detect_error(adapter);
 648                         return -1;
 649                 }
 650
 651                 msleep(1);
 652                 msecs++;
 653         } while (true);
 654
 655         return 0;
 656 }
 657
 658 /*
 659  * Insert the mailbox address into the doorbell in two steps
 660  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 661  */
 662 static int be_mbox_notify_wait(struct be_adapter *adapter)
 663 {
 664         int status;
 665         u32 val = 0;
 666         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 667         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 668         struct be_mcc_mailbox *mbox = mbox_mem->va;
 669         struct be_mcc_compl *compl = &mbox->compl;
 670
 671         /* wait for ready to be set */
 672         status = be_mbox_db_ready_wait(adapter, db);
 673         if (status != 0)
 674                 return status;
 675
 676         val |= MPU_MAILBOX_DB_HI_MASK;
 677         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 678         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 679         iowrite32(val, db);
 680
 681         /* wait for ready to be set */
 682         status = be_mbox_db_ready_wait(adapter, db);
 683         if (status != 0)
 684                 return status;
 685
 686         val = 0;
 687         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 688         val |= (u32)(mbox_mem->dma >> 4) << 2;
 689         iowrite32(val, db);
 690
 691         status = be_mbox_db_ready_wait(adapter, db);
 692         if (status != 0)
 693                 return status;
 694
 695         /* A cq entry has been made now */
 696         if (be_mcc_compl_is_new(compl)) {
 697                 status = be_mcc_compl_process(adapter, &mbox->compl);
 698                 be_mcc_compl_use(compl);
 699                 if (status)
 700                         return status;
 701         } else {
 702                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 703                 return -1;
 704         }
 705         return 0;
 706 }
 707
 708 u16 be_POST_stage_get(struct be_adapter *adapter)
 709 {
 710         u32 sem;
 711
 712         if (BEx_chip(adapter))
 713                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 714         else
 715                 pci_read_config_dword(adapter->pdev,
 716                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 717
 718         return sem & POST_STAGE_MASK;
 719 }
 720
 721 static int lancer_wait_ready(struct be_adapter *adapter)
 722 {
 723 #define SLIPORT_READY_TIMEOUT 30
 724         u32 sliport_status;
 725         int i;
 726
 727         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 728                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 729                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 730                         return 0;
 731
 732                 if (sliport_status & SLIPORT_STATUS_ERR_MASK &&
 733                     !(sliport_status & SLIPORT_STATUS_RN_MASK))
 734                         return -EIO;
 735
 736                 msleep(1000);
 737         }
 738
 739         return sliport_status ? : -1;
 740 }
 741
 742 int be_fw_wait_ready(struct be_adapter *adapter)
 743 {
 744         u16 stage;
 745         int status, timeout = 0;
 746         struct device *dev = &adapter->pdev->dev;
 747
 748         if (lancer_chip(adapter)) {
 749                 status = lancer_wait_ready(adapter);
 750                 if (status) {
 751                         stage = status;
 752                         goto err;
 753                 }
 754                 return 0;
 755         }
 756
 757         do {
 758                 /* There's no means to poll POST state on BE2/3 VFs */
 759                 if (BEx_chip(adapter) && be_virtfn(adapter))
 760                         return 0;
 761
 762                 stage = be_POST_stage_get(adapter);
 763                 if (stage == POST_STAGE_ARMFW_RDY)
 764                         return 0;
 765
 766                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 767                 if (msleep_interruptible(2000)) {
 768                         dev_err(dev, "Waiting for POST aborted\n");
 769                         return -EINTR;
 770                 }
 771                 timeout += 2;
 772         } while (timeout < 60);
 773
 774 err:
 775         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 776         return -ETIMEDOUT;
 777 }
 778
 779 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 780 {
 781         return &wrb->payload.sgl[0];
 782 }
 783
 784 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 785 {
 786         wrb->tag0 = addr & 0xFFFFFFFF;
 787         wrb->tag1 = upper_32_bits(addr);
 788 }
 789
 790 /* Don't touch the hdr after it's prepared */
 791 /* mem will be NULL for embedded commands */
 792 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 793                                    u8 subsystem, u8 opcode, int cmd_len,
 794                                    struct be_mcc_wrb *wrb,
 795                                    struct be_dma_mem *mem)
 796 {
 797         struct be_sge *sge;
 798
 799         req_hdr->opcode = opcode;
 800         req_hdr->subsystem = subsystem;
 801         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 802         req_hdr->version = 0;
 803         fill_wrb_tags(wrb, (ulong) req_hdr);
 804         wrb->payload_length = cmd_len;
 805         if (mem) {
 806                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 807                         MCC_WRB_SGE_CNT_SHIFT;
 808                 sge = nonembedded_sgl(wrb);
 809                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 810                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 811                 sge->len = cpu_to_le32(mem->size);
 812         } else
 813                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 814         be_dws_cpu_to_le(wrb, 8);
 815 }
 816
 817 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 818                                       struct be_dma_mem *mem)
 819 {
 820         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 821         u64 dma = (u64)mem->dma;
 822
 823         for (i = 0; i < buf_pages; i++) {
 824                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 825                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 826                 dma += PAGE_SIZE_4K;
 827         }
 828 }
 829
 830 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 831 {
 832         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 833         struct be_mcc_wrb *wrb
 834                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 835         memset(wrb, 0, sizeof(*wrb));
 836         return wrb;
 837 }
 838
 839 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 840 {
 841         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 842         struct be_mcc_wrb *wrb;
 843
 844         if (!mccq->created)
 845                 return NULL;
 846
 847         if (atomic_read(&mccq->used) >= mccq->len)
 848                 return NULL;
 849
 850         wrb = queue_head_node(mccq);
 851         queue_head_inc(mccq);
 852         atomic_inc(&mccq->used);
 853         memset(wrb, 0, sizeof(*wrb));
 854         return wrb;
 855 }
 856
 857 static bool use_mcc(struct be_adapter *adapter)
 858 {
 859         return adapter->mcc_obj.q.created;
 860 }
 861
 862 /* Must be used only in process context */
 863 static int be_cmd_lock(struct be_adapter *adapter)
 864 {
 865         if (use_mcc(adapter)) {
 866                 mutex_lock(&adapter->mcc_lock);
 867                 return 0;
 868         } else {
 869                 return mutex_lock_interruptible(&adapter->mbox_lock);
 870         }
 871 }
 872
 873 /* Must be used only in process context */
 874 static void be_cmd_unlock(struct be_adapter *adapter)
 875 {
 876         if (use_mcc(adapter))
 877                 return mutex_unlock(&adapter->mcc_lock);
 878         else
 879                 return mutex_unlock(&adapter->mbox_lock);
 880 }
 881
 882 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 883                                       struct be_mcc_wrb *wrb)
 884 {
 885         struct be_mcc_wrb *dest_wrb;
 886
 887         if (use_mcc(adapter)) {
 888                 dest_wrb = wrb_from_mccq(adapter);
 889                 if (!dest_wrb)
 890                         return NULL;
 891         } else {
 892                 dest_wrb = wrb_from_mbox(adapter);
 893         }
 894
 895         memcpy(dest_wrb, wrb, sizeof(*wrb));
 896         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 897                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 898
 899         return dest_wrb;
 900 }
 901
 902 /* Must be used only in process context */
 903 static int be_cmd_notify_wait(struct be_adapter *adapter,
 904                               struct be_mcc_wrb *wrb)
 905 {
 906         struct be_mcc_wrb *dest_wrb;
 907         int status;
 908
 909         status = be_cmd_lock(adapter);
 910         if (status)
 911                 return status;
 912
 913         dest_wrb = be_cmd_copy(adapter, wrb);
 914         if (!dest_wrb) {
 915                 status = -EBUSY;
 916                 goto unlock;
 917         }
 918
 919         if (use_mcc(adapter))
 920                 status = be_mcc_notify_wait(adapter);
 921         else
 922                 status = be_mbox_notify_wait(adapter);
 923
 924         if (!status)
 925                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 926
 927 unlock:
 928         be_cmd_unlock(adapter);
 929         return status;
 930 }
 931
 932 /* Tell fw we're about to start firing cmds by writing a
 933  * special pattern across the wrb hdr; uses mbox
 934  */
 935 int be_cmd_fw_init(struct be_adapter *adapter)
 936 {
 937         u8 *wrb;
 938         int status;
 939
 940         if (lancer_chip(adapter))
 941                 return 0;
 942
 943         if (mutex_lock_interruptible(&adapter->mbox_lock))
 944                 return -1;
 945
 946         wrb = (u8 *)wrb_from_mbox(adapter);
 947         *wrb++ = 0xFF;
 948         *wrb++ = 0x12;
 949         *wrb++ = 0x34;
 950         *wrb++ = 0xFF;
 951         *wrb++ = 0xFF;
 952         *wrb++ = 0x56;
 953         *wrb++ = 0x78;
 954         *wrb = 0xFF;
 955
 956         status = be_mbox_notify_wait(adapter);
 957
 958         mutex_unlock(&adapter->mbox_lock);
 959         return status;
 960 }
 961
 962 /* Tell fw we're done with firing cmds by writing a
 963  * special pattern across the wrb hdr; uses mbox
 964  */
 965 int be_cmd_fw_clean(struct be_adapter *adapter)
 966 {
 967         u8 *wrb;
 968         int status;
 969
 970         if (lancer_chip(adapter))
 971                 return 0;
 972
 973         if (mutex_lock_interruptible(&adapter->mbox_lock))
 974                 return -1;
 975
 976         wrb = (u8 *)wrb_from_mbox(adapter);
 977         *wrb++ = 0xFF;
 978         *wrb++ = 0xAA;
 979         *wrb++ = 0xBB;
 980         *wrb++ = 0xFF;
 981         *wrb++ = 0xFF;
 982         *wrb++ = 0xCC;
 983         *wrb++ = 0xDD;
 984         *wrb = 0xFF;
 985
 986         status = be_mbox_notify_wait(adapter);
 987
 988         mutex_unlock(&adapter->mbox_lock);
 989         return status;
 990 }
 991
 992 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 993 {
 994         struct be_mcc_wrb *wrb;
 995         struct be_cmd_req_eq_create *req;
 996         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 997         int status, ver = 0;
 998
 999         if (mutex_lock_interruptible(&adapter->mbox_lock))
1000                 return -1;
1001
1002         wrb = wrb_from_mbox(adapter);
1003         req = embedded_payload(wrb);
1004
1005         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1006                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
1007                                NULL);
1008
1009         /* Support for EQ_CREATEv2 available only SH-R onwards */
1010         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
1011                 ver = 2;
1012
1013         req->hdr.version = ver;
1014         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1015
1016         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
1017         /* 4byte eqe*/
1018         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
1019         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
1020                       __ilog2_u32(eqo->q.len / 256));
1021         be_dws_cpu_to_le(req->context, sizeof(req->context));
1022
1023         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1024
1025         status = be_mbox_notify_wait(adapter);
1026         if (!status) {
1027                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
1028
1029                 eqo->q.id = le16_to_cpu(resp->eq_id);
1030                 eqo->msix_idx =
1031                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
1032                 eqo->q.created = true;
1033         }
1034
1035         mutex_unlock(&adapter->mbox_lock);
1036         return status;
1037 }
1038
1039 /* Use MCC */
1040 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1041                           bool permanent, u32 if_handle, u32 pmac_id)
1042 {
1043         struct be_mcc_wrb *wrb;
1044         struct be_cmd_req_mac_query *req;
1045         int status;
1046
1047         mutex_lock(&adapter->mcc_lock);
1048
1049         wrb = wrb_from_mccq(adapter);
1050         if (!wrb) {
1051                 status = -EBUSY;
1052                 goto err;
1053         }
1054         req = embedded_payload(wrb);
1055
1056         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1057                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1058                                NULL);
1059         req->type = MAC_ADDRESS_TYPE_NETWORK;
1060         if (permanent) {
1061                 req->permanent = 1;
1062         } else {
1063                 req->if_id = cpu_to_le16((u16)if_handle);
1064                 req->pmac_id = cpu_to_le32(pmac_id);
1065                 req->permanent = 0;
1066         }
1067
1068         status = be_mcc_notify_wait(adapter);
1069         if (!status) {
1070                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1071
1072                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1073         }
1074
1075 err:
1076         mutex_unlock(&adapter->mcc_lock);
1077         return status;
1078 }
1079
1080 /* Uses synchronous MCCQ */
1081 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1082                     u32 if_id, u32 *pmac_id, u32 domain)
1083 {
1084         struct be_mcc_wrb *wrb;
1085         struct be_cmd_req_pmac_add *req;
1086         int status;
1087
1088         mutex_lock(&adapter->mcc_lock);
1089
1090         wrb = wrb_from_mccq(adapter);
1091         if (!wrb) {
1092                 status = -EBUSY;
1093                 goto err;
1094         }
1095         req = embedded_payload(wrb);
1096
1097         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1098                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1099                                NULL);
1100
1101         req->hdr.domain = domain;
1102         req->if_id = cpu_to_le32(if_id);
1103         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1104
1105         status = be_mcc_notify_wait(adapter);
1106         if (!status) {
1107                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1108
1109                 *pmac_id = le32_to_cpu(resp->pmac_id);
1110         }
1111
1112 err:
1113         mutex_unlock(&adapter->mcc_lock);
1114
1115          if (base_status(status) == MCC_STATUS_UNAUTHORIZED_REQUEST)
1116                 status = -EPERM;
1117
1118         return status;
1119 }
1120
1121 /* Uses synchronous MCCQ */
1122 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1123 {
1124         struct be_mcc_wrb *wrb;
1125         struct be_cmd_req_pmac_del *req;
1126         int status;
1127
1128         if (pmac_id == -1)
1129                 return 0;
1130
1131         mutex_lock(&adapter->mcc_lock);
1132
1133         wrb = wrb_from_mccq(adapter);
1134         if (!wrb) {
1135                 status = -EBUSY;
1136                 goto err;
1137         }
1138         req = embedded_payload(wrb);
1139
1140         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1141                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1142                                wrb, NULL);
1143
1144         req->hdr.domain = dom;
1145         req->if_id = cpu_to_le32(if_id);
1146         req->pmac_id = cpu_to_le32(pmac_id);
1147
1148         status = be_mcc_notify_wait(adapter);
1149
1150 err:
1151         mutex_unlock(&adapter->mcc_lock);
1152         return status;
1153 }
1154
1155 /* Uses Mbox */
1156 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1157                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1158 {
1159         struct be_mcc_wrb *wrb;
1160         struct be_cmd_req_cq_create *req;
1161         struct be_dma_mem *q_mem = &cq->dma_mem;
1162         void *ctxt;
1163         int status;
1164
1165         if (mutex_lock_interruptible(&adapter->mbox_lock))
1166                 return -1;
1167
1168         wrb = wrb_from_mbox(adapter);
1169         req = embedded_payload(wrb);
1170         ctxt = &req->context;
1171
1172         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1173                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1174                                NULL);
1175
1176         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1177
1178         if (BEx_chip(adapter)) {
1179                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1180                               coalesce_wm);
1181                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1182                               ctxt, no_delay);
1183                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1184                               __ilog2_u32(cq->len / 256));
1185                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1186                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1187                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1188         } else {
1189                 req->hdr.version = 2;
1190                 req->page_size = 1; /* 1 for 4K */
1191
1192                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1193                  * Lancer uses COMMON_MODIFY_CQ to set this field
1194                  */
1195                 if (!lancer_chip(adapter))
1196                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1197                                       ctxt, coalesce_wm);
1198                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1199                               no_delay);
1200                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1201                               __ilog2_u32(cq->len / 256));
1202                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1203                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1204                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1205         }
1206
1207         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1208
1209         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1210
1211         status = be_mbox_notify_wait(adapter);
1212         if (!status) {
1213                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1214
1215                 cq->id = le16_to_cpu(resp->cq_id);
1216                 cq->created = true;
1217         }
1218
1219         mutex_unlock(&adapter->mbox_lock);
1220
1221         return status;
1222 }
1223
1224 static u32 be_encoded_q_len(int q_len)
1225 {
1226         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1227
1228         if (len_encoded == 16)
1229                 len_encoded = 0;
1230         return len_encoded;
1231 }
1232
1233 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1234                                   struct be_queue_info *mccq,
1235                                   struct be_queue_info *cq)
1236 {
1237         struct be_mcc_wrb *wrb;
1238         struct be_cmd_req_mcc_ext_create *req;
1239         struct be_dma_mem *q_mem = &mccq->dma_mem;
1240         void *ctxt;
1241         int status;
1242
1243         if (mutex_lock_interruptible(&adapter->mbox_lock))
1244                 return -1;
1245
1246         wrb = wrb_from_mbox(adapter);
1247         req = embedded_payload(wrb);
1248         ctxt = &req->context;
1249
1250         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1251                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1252                                NULL);
1253
1254         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1255         if (BEx_chip(adapter)) {
1256                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1257                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1258                               be_encoded_q_len(mccq->len));
1259                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1260         } else {
1261                 req->hdr.version = 1;
1262                 req->cq_id = cpu_to_le16(cq->id);
1263
1264                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1265                               be_encoded_q_len(mccq->len));
1266                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1267                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1268                               ctxt, cq->id);
1269                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1270                               ctxt, 1);
1271         }
1272
1273         /* Subscribe to Link State, Sliport Event and Group 5 Events
1274          * (bits 1, 5 and 17 set)
1275          */
1276         req->async_event_bitmap[0] =
1277                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1278                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1279                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1280                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1281
1282         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1283
1284         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1285
1286         status = be_mbox_notify_wait(adapter);
1287         if (!status) {
1288                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1289
1290                 mccq->id = le16_to_cpu(resp->id);
1291                 mccq->created = true;
1292         }
1293         mutex_unlock(&adapter->mbox_lock);
1294
1295         return status;
1296 }
1297
1298 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1299                                   struct be_queue_info *mccq,
1300                                   struct be_queue_info *cq)
1301 {
1302         struct be_mcc_wrb *wrb;
1303         struct be_cmd_req_mcc_create *req;
1304         struct be_dma_mem *q_mem = &mccq->dma_mem;
1305         void *ctxt;
1306         int status;
1307
1308         if (mutex_lock_interruptible(&adapter->mbox_lock))
1309                 return -1;
1310
1311         wrb = wrb_from_mbox(adapter);
1312         req = embedded_payload(wrb);
1313         ctxt = &req->context;
1314
1315         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1316                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1317                                NULL);
1318
1319         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1320
1321         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1322         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1323                       be_encoded_q_len(mccq->len));
1324         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1325
1326         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1327
1328         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1329
1330         status = be_mbox_notify_wait(adapter);
1331         if (!status) {
1332                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1333
1334                 mccq->id = le16_to_cpu(resp->id);
1335                 mccq->created = true;
1336         }
1337
1338         mutex_unlock(&adapter->mbox_lock);
1339         return status;
1340 }
1341
1342 int be_cmd_mccq_create(struct be_adapter *adapter,
1343                        struct be_queue_info *mccq, struct be_queue_info *cq)
1344 {
1345         int status;
1346
1347         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1348         if (status && BEx_chip(adapter)) {
1349                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1350                         "or newer to avoid conflicting priorities between NIC "
1351                         "and FCoE traffic");
1352                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1353         }
1354         return status;
1355 }
1356
1357 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1358 {
1359         struct be_mcc_wrb wrb = {0};
1360         struct be_cmd_req_eth_tx_create *req;
1361         struct be_queue_info *txq = &txo->q;
1362         struct be_queue_info *cq = &txo->cq;
1363         struct be_dma_mem *q_mem = &txq->dma_mem;
1364         int status, ver = 0;
1365
1366         req = embedded_payload(&wrb);
1367         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1368                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1369
1370         if (lancer_chip(adapter)) {
1371                 req->hdr.version = 1;
1372         } else if (BEx_chip(adapter)) {
1373                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1374                         req->hdr.version = 2;
1375         } else { /* For SH */
1376                 req->hdr.version = 2;
1377         }
1378
1379         if (req->hdr.version > 0)
1380                 req->if_id = cpu_to_le16(adapter->if_handle);
1381         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1382         req->ulp_num = BE_ULP1_NUM;
1383         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1384         req->cq_id = cpu_to_le16(cq->id);
1385         req->queue_size = be_encoded_q_len(txq->len);
1386         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1387         ver = req->hdr.version;
1388
1389         status = be_cmd_notify_wait(adapter, &wrb);
1390         if (!status) {
1391                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1392
1393                 txq->id = le16_to_cpu(resp->cid);
1394                 if (ver == 2)
1395                         txo->db_offset = le32_to_cpu(resp->db_offset);
1396                 else
1397                         txo->db_offset = DB_TXULP1_OFFSET;
1398                 txq->created = true;
1399         }
1400
1401         return status;
1402 }
1403
1404 /* Uses MCC */
1405 int be_cmd_rxq_create(struct be_adapter *adapter,
1406                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1407                       u32 if_id, u32 rss, u8 *rss_id)
1408 {
1409         struct be_mcc_wrb *wrb;
1410         struct be_cmd_req_eth_rx_create *req;
1411         struct be_dma_mem *q_mem = &rxq->dma_mem;
1412         int status;
1413
1414         mutex_lock(&adapter->mcc_lock);
1415
1416         wrb = wrb_from_mccq(adapter);
1417         if (!wrb) {
1418                 status = -EBUSY;
1419                 goto err;
1420         }
1421         req = embedded_payload(wrb);
1422
1423         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1424                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1425
1426         req->cq_id = cpu_to_le16(cq_id);
1427         req->frag_size = fls(frag_size) - 1;
1428         req->num_pages = 2;
1429         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1430         req->interface_id = cpu_to_le32(if_id);
1431         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1432         req->rss_queue = cpu_to_le32(rss);
1433
1434         status = be_mcc_notify_wait(adapter);
1435         if (!status) {
1436                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1437
1438                 rxq->id = le16_to_cpu(resp->id);
1439                 rxq->created = true;
1440                 *rss_id = resp->rss_id;
1441         }
1442
1443 err:
1444         mutex_unlock(&adapter->mcc_lock);
1445         return status;
1446 }
1447
1448 /* Generic destroyer function for all types of queues
1449  * Uses Mbox
1450  */
1451 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1452                      int queue_type)
1453 {
1454         struct be_mcc_wrb *wrb;
1455         struct be_cmd_req_q_destroy *req;
1456         u8 subsys = 0, opcode = 0;
1457         int status;
1458
1459         if (mutex_lock_interruptible(&adapter->mbox_lock))
1460                 return -1;
1461
1462         wrb = wrb_from_mbox(adapter);
1463         req = embedded_payload(wrb);
1464
1465         switch (queue_type) {
1466         case QTYPE_EQ:
1467                 subsys = CMD_SUBSYSTEM_COMMON;
1468                 opcode = OPCODE_COMMON_EQ_DESTROY;
1469                 break;
1470         case QTYPE_CQ:
1471                 subsys = CMD_SUBSYSTEM_COMMON;
1472                 opcode = OPCODE_COMMON_CQ_DESTROY;
1473                 break;
1474         case QTYPE_TXQ:
1475                 subsys = CMD_SUBSYSTEM_ETH;
1476                 opcode = OPCODE_ETH_TX_DESTROY;
1477                 break;
1478         case QTYPE_RXQ:
1479                 subsys = CMD_SUBSYSTEM_ETH;
1480                 opcode = OPCODE_ETH_RX_DESTROY;
1481                 break;
1482         case QTYPE_MCCQ:
1483                 subsys = CMD_SUBSYSTEM_COMMON;
1484                 opcode = OPCODE_COMMON_MCC_DESTROY;
1485                 break;
1486         default:
1487                 BUG();
1488         }
1489
1490         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1491                                NULL);
1492         req->id = cpu_to_le16(q->id);
1493
1494         status = be_mbox_notify_wait(adapter);
1495         q->created = false;
1496
1497         mutex_unlock(&adapter->mbox_lock);
1498         return status;
1499 }
1500
1501 /* Uses MCC */
1502 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1503 {
1504         struct be_mcc_wrb *wrb;
1505         struct be_cmd_req_q_destroy *req;
1506         int status;
1507
1508         mutex_lock(&adapter->mcc_lock);
1509
1510         wrb = wrb_from_mccq(adapter);
1511         if (!wrb) {
1512                 status = -EBUSY;
1513                 goto err;
1514         }
1515         req = embedded_payload(wrb);
1516
1517         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1518                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1519         req->id = cpu_to_le16(q->id);
1520
1521         status = be_mcc_notify_wait(adapter);
1522         q->created = false;
1523
1524 err:
1525         mutex_unlock(&adapter->mcc_lock);
1526         return status;
1527 }
1528
1529 /* Create an rx filtering policy configuration on an i/f
1530  * Will use MBOX only if MCCQ has not been created.
1531  */
1532 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1533                      u32 *if_handle, u32 domain)
1534 {
1535         struct be_mcc_wrb wrb = {0};
1536         struct be_cmd_req_if_create *req;
1537         int status;
1538
1539         req = embedded_payload(&wrb);
1540         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1541                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1542                                sizeof(*req), &wrb, NULL);
1543         req->hdr.domain = domain;
1544         req->capability_flags = cpu_to_le32(cap_flags);
1545         req->enable_flags = cpu_to_le32(en_flags);
1546         req->pmac_invalid = true;
1547
1548         status = be_cmd_notify_wait(adapter, &wrb);
1549         if (!status) {
1550                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1551
1552                 *if_handle = le32_to_cpu(resp->interface_id);
1553
1554                 /* Hack to retrieve VF's pmac-id on BE3 */
1555                 if (BE3_chip(adapter) && be_virtfn(adapter))
1556                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1557         }
1558         return status;
1559 }
1560
1561 /* Uses MCCQ if available else MBOX */
1562 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1563 {
1564         struct be_mcc_wrb wrb = {0};
1565         struct be_cmd_req_if_destroy *req;
1566         int status;
1567
1568         if (interface_id == -1)
1569                 return 0;
1570
1571         req = embedded_payload(&wrb);
1572
1573         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1574                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1575                                sizeof(*req), &wrb, NULL);
1576         req->hdr.domain = domain;
1577         req->interface_id = cpu_to_le32(interface_id);
1578
1579         status = be_cmd_notify_wait(adapter, &wrb);
1580         return status;
1581 }
1582
1583 /* Get stats is a non embedded command: the request is not embedded inside
1584  * WRB but is a separate dma memory block
1585  * Uses asynchronous MCC
1586  */
1587 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1588 {
1589         struct be_mcc_wrb *wrb;
1590         struct be_cmd_req_hdr *hdr;
1591         int status = 0;
1592
1593         mutex_lock(&adapter->mcc_lock);
1594
1595         wrb = wrb_from_mccq(adapter);
1596         if (!wrb) {
1597                 status = -EBUSY;
1598                 goto err;
1599         }
1600         hdr = nonemb_cmd->va;
1601
1602         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1603                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1604                                nonemb_cmd);
1605
1606         /* version 1 of the cmd is not supported only by BE2 */
1607         if (BE2_chip(adapter))
1608                 hdr->version = 0;
1609         if (BE3_chip(adapter) || lancer_chip(adapter))
1610                 hdr->version = 1;
1611         else
1612                 hdr->version = 2;
1613
1614         status = be_mcc_notify(adapter);
1615         if (status)
1616                 goto err;
1617
1618         adapter->stats_cmd_sent = true;
1619
1620 err:
1621         mutex_unlock(&adapter->mcc_lock);
1622         return status;
1623 }
1624
1625 /* Lancer Stats */
1626 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1627                                struct be_dma_mem *nonemb_cmd)
1628 {
1629         struct be_mcc_wrb *wrb;
1630         struct lancer_cmd_req_pport_stats *req;
1631         int status = 0;
1632
1633         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1634                             CMD_SUBSYSTEM_ETH))
1635                 return -EPERM;
1636
1637         mutex_lock(&adapter->mcc_lock);
1638
1639         wrb = wrb_from_mccq(adapter);
1640         if (!wrb) {
1641                 status = -EBUSY;
1642                 goto err;
1643         }
1644         req = nonemb_cmd->va;
1645
1646         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1647                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1648                                wrb, nonemb_cmd);
1649
1650         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1651         req->cmd_params.params.reset_stats = 0;
1652
1653         status = be_mcc_notify(adapter);
1654         if (status)
1655                 goto err;
1656
1657         adapter->stats_cmd_sent = true;
1658
1659 err:
1660         mutex_unlock(&adapter->mcc_lock);
1661         return status;
1662 }
1663
1664 static int be_mac_to_link_speed(int mac_speed)
1665 {
1666         switch (mac_speed) {
1667         case PHY_LINK_SPEED_ZERO:
1668                 return 0;
1669         case PHY_LINK_SPEED_10MBPS:
1670                 return 10;
1671         case PHY_LINK_SPEED_100MBPS:
1672                 return 100;
1673         case PHY_LINK_SPEED_1GBPS:
1674                 return 1000;
1675         case PHY_LINK_SPEED_10GBPS:
1676                 return 10000;
1677         case PHY_LINK_SPEED_20GBPS:
1678                 return 20000;
1679         case PHY_LINK_SPEED_25GBPS:
1680                 return 25000;
1681         case PHY_LINK_SPEED_40GBPS:
1682                 return 40000;
1683         }
1684         return 0;
1685 }
1686
1687 /* Uses synchronous mcc
1688  * Returns link_speed in Mbps
1689  */
1690 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1691                              u8 *link_status, u32 dom)
1692 {
1693         struct be_mcc_wrb *wrb;
1694         struct be_cmd_req_link_status *req;
1695         int status;
1696
1697         mutex_lock(&adapter->mcc_lock);
1698
1699         if (link_status)
1700                 *link_status = LINK_DOWN;
1701
1702         wrb = wrb_from_mccq(adapter);
1703         if (!wrb) {
1704                 status = -EBUSY;
1705                 goto err;
1706         }
1707         req = embedded_payload(wrb);
1708
1709         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1710                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1711                                sizeof(*req), wrb, NULL);
1712
1713         /* version 1 of the cmd is not supported only by BE2 */
1714         if (!BE2_chip(adapter))
1715                 req->hdr.version = 1;
1716
1717         req->hdr.domain = dom;
1718
1719         status = be_mcc_notify_wait(adapter);
1720         if (!status) {
1721                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1722
1723                 if (link_speed) {
1724                         *link_speed = resp->link_speed ?
1725                                       le16_to_cpu(resp->link_speed) * 10 :
1726                                       be_mac_to_link_speed(resp->mac_speed);
1727
1728                         if (!resp->logical_link_status)
1729                                 *link_speed = 0;
1730                 }
1731                 if (link_status)
1732                         *link_status = resp->logical_link_status;
1733         }
1734
1735 err:
1736         mutex_unlock(&adapter->mcc_lock);
1737         return status;
1738 }
1739
1740 /* Uses synchronous mcc */
1741 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1742 {
1743         struct be_mcc_wrb *wrb;
1744         struct be_cmd_req_get_cntl_addnl_attribs *req;
1745         int status = 0;
1746
1747         mutex_lock(&adapter->mcc_lock);
1748
1749         wrb = wrb_from_mccq(adapter);
1750         if (!wrb) {
1751                 status = -EBUSY;
1752                 goto err;
1753         }
1754         req = embedded_payload(wrb);
1755
1756         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1757                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1758                                sizeof(*req), wrb, NULL);
1759
1760         status = be_mcc_notify(adapter);
1761 err:
1762         mutex_unlock(&adapter->mcc_lock);
1763         return status;
1764 }
1765
1766 /* Uses synchronous mcc */
1767 int be_cmd_get_fat_dump_len(struct be_adapter *adapter, u32 *dump_size)
1768 {
1769         struct be_mcc_wrb wrb = {0};
1770         struct be_cmd_req_get_fat *req;
1771         int status;
1772
1773         req = embedded_payload(&wrb);
1774
1775         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1776                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req),
1777                                &wrb, NULL);
1778         req->fat_operation = cpu_to_le32(QUERY_FAT);
1779         status = be_cmd_notify_wait(adapter, &wrb);
1780         if (!status) {
1781                 struct be_cmd_resp_get_fat *resp = embedded_payload(&wrb);
1782
1783                 if (dump_size && resp->log_size)
1784                         *dump_size = le32_to_cpu(resp->log_size) -
1785                                         sizeof(u32);
1786         }
1787         return status;
1788 }
1789
1790 int be_cmd_get_fat_dump(struct be_adapter *adapter, u32 buf_len, void *buf)
1791 {
1792         struct be_dma_mem get_fat_cmd;
1793         struct be_mcc_wrb *wrb;
1794         struct be_cmd_req_get_fat *req;
1795         u32 offset = 0, total_size, buf_size,
1796                                 log_offset = sizeof(u32), payload_len;
1797         int status;
1798
1799         if (buf_len == 0)
1800                 return 0;
1801
1802         total_size = buf_len;
1803
1804         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1805         get_fat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
1806                                             get_fat_cmd.size,
1807                                             &get_fat_cmd.dma, GFP_ATOMIC);
1808         if (!get_fat_cmd.va)
1809                 return -ENOMEM;
1810
1811         mutex_lock(&adapter->mcc_lock);
1812
1813         while (total_size) {
1814                 buf_size = min(total_size, (u32)60*1024);
1815                 total_size -= buf_size;
1816
1817                 wrb = wrb_from_mccq(adapter);
1818                 if (!wrb) {
1819                         status = -EBUSY;
1820                         goto err;
1821                 }
1822                 req = get_fat_cmd.va;
1823
1824                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1825                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1826                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1827                                        wrb, &get_fat_cmd);
1828
1829                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1830                 req->read_log_offset = cpu_to_le32(log_offset);
1831                 req->read_log_length = cpu_to_le32(buf_size);
1832                 req->data_buffer_size = cpu_to_le32(buf_size);
1833
1834                 status = be_mcc_notify_wait(adapter);
1835                 if (!status) {
1836                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1837
1838                         memcpy(buf + offset,
1839                                resp->data_buffer,
1840                                le32_to_cpu(resp->read_log_length));
1841                 } else {
1842                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1843                         goto err;
1844                 }
1845                 offset += buf_size;
1846                 log_offset += buf_size;
1847         }
1848 err:
1849         dma_free_coherent(&adapter->pdev->dev, get_fat_cmd.size,
1850                           get_fat_cmd.va, get_fat_cmd.dma);
1851         mutex_unlock(&adapter->mcc_lock);
1852         return status;
1853 }
1854
1855 /* Uses synchronous mcc */
1856 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1857 {
1858         struct be_mcc_wrb *wrb;
1859         struct be_cmd_req_get_fw_version *req;
1860         int status;
1861
1862         mutex_lock(&adapter->mcc_lock);
1863
1864         wrb = wrb_from_mccq(adapter);
1865         if (!wrb) {
1866                 status = -EBUSY;
1867                 goto err;
1868         }
1869
1870         req = embedded_payload(wrb);
1871
1872         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1873                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1874                                NULL);
1875         status = be_mcc_notify_wait(adapter);
1876         if (!status) {
1877                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1878
1879                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1880                         sizeof(adapter->fw_ver));
1881                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1882                         sizeof(adapter->fw_on_flash));
1883         }
1884 err:
1885         mutex_unlock(&adapter->mcc_lock);
1886         return status;
1887 }
1888
1889 /* set the EQ delay interval of an EQ to specified value
1890  * Uses async mcc
1891  */
1892 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1893                                struct be_set_eqd *set_eqd, int num)
1894 {
1895         struct be_mcc_wrb *wrb;
1896         struct be_cmd_req_modify_eq_delay *req;
1897         int status = 0, i;
1898
1899         mutex_lock(&adapter->mcc_lock);
1900
1901         wrb = wrb_from_mccq(adapter);
1902         if (!wrb) {
1903                 status = -EBUSY;
1904                 goto err;
1905         }
1906         req = embedded_payload(wrb);
1907
1908         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1909                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1910                                NULL);
1911
1912         req->num_eq = cpu_to_le32(num);
1913         for (i = 0; i < num; i++) {
1914                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1915                 req->set_eqd[i].phase = 0;
1916                 req->set_eqd[i].delay_multiplier =
1917                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1918         }
1919
1920         status = be_mcc_notify(adapter);
1921 err:
1922         mutex_unlock(&adapter->mcc_lock);
1923         return status;
1924 }
1925
1926 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1927                       int num)
1928 {
1929         int num_eqs, i = 0;
1930
1931         while (num) {
1932                 num_eqs = min(num, 8);
1933                 __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1934                 i += num_eqs;
1935                 num -= num_eqs;
1936         }
1937
1938         return 0;
1939 }
1940
1941 /* Uses sycnhronous mcc */
1942 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1943                        u32 num, u32 domain)
1944 {
1945         struct be_mcc_wrb *wrb;
1946         struct be_cmd_req_vlan_config *req;
1947         int status;
1948
1949         mutex_lock(&adapter->mcc_lock);
1950
1951         wrb = wrb_from_mccq(adapter);
1952         if (!wrb) {
1953                 status = -EBUSY;
1954                 goto err;
1955         }
1956         req = embedded_payload(wrb);
1957
1958         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1959                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1960                                wrb, NULL);
1961         req->hdr.domain = domain;
1962
1963         req->interface_id = if_id;
1964         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1965         req->num_vlan = num;
1966         memcpy(req->normal_vlan, vtag_array,
1967                req->num_vlan * sizeof(vtag_array[0]));
1968
1969         status = be_mcc_notify_wait(adapter);
1970 err:
1971         mutex_unlock(&adapter->mcc_lock);
1972         return status;
1973 }
1974
1975 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1976 {
1977         struct be_mcc_wrb *wrb;
1978         struct be_dma_mem *mem = &adapter->rx_filter;
1979         struct be_cmd_req_rx_filter *req = mem->va;
1980         int status;
1981
1982         mutex_lock(&adapter->mcc_lock);
1983
1984         wrb = wrb_from_mccq(adapter);
1985         if (!wrb) {
1986                 status = -EBUSY;
1987                 goto err;
1988         }
1989         memset(req, 0, sizeof(*req));
1990         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1991                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1992                                wrb, mem);
1993
1994         req->if_id = cpu_to_le32(adapter->if_handle);
1995         req->if_flags_mask = cpu_to_le32(flags);
1996         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1997
1998         if (flags & BE_IF_FLAGS_MULTICAST) {
1999                 int i;
2000
2001                 /* Reset mcast promisc mode if already set by setting mask
2002                  * and not setting flags field
2003                  */
2004                 req->if_flags_mask |=
2005                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
2006                                     be_if_cap_flags(adapter));
2007                 req->mcast_num = cpu_to_le32(adapter->mc_count);
2008                 for (i = 0; i < adapter->mc_count; i++)
2009                         ether_addr_copy(req->mcast_mac[i].byte,
2010                                         adapter->mc_list[i].mac);
2011         }
2012
2013         status = be_mcc_notify_wait(adapter);
2014 err:
2015         mutex_unlock(&adapter->mcc_lock);
2016         return status;
2017 }
2018
2019 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
2020 {
2021         struct device *dev = &adapter->pdev->dev;
2022
2023         if ((flags & be_if_cap_flags(adapter)) != flags) {
2024                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2025                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2026                          be_if_cap_flags(adapter));
2027         }
2028         flags &= be_if_cap_flags(adapter);
2029         if (!flags)
2030                 return -ENOTSUPP;
2031
2032         return __be_cmd_rx_filter(adapter, flags, value);
2033 }
2034
2035 /* Uses synchrounous mcc */
2036 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2037 {
2038         struct be_mcc_wrb *wrb;
2039         struct be_cmd_req_set_flow_control *req;
2040         int status;
2041
2042         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2043                             CMD_SUBSYSTEM_COMMON))
2044                 return -EPERM;
2045
2046         mutex_lock(&adapter->mcc_lock);
2047
2048         wrb = wrb_from_mccq(adapter);
2049         if (!wrb) {
2050                 status = -EBUSY;
2051                 goto err;
2052         }
2053         req = embedded_payload(wrb);
2054
2055         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2056                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2057                                wrb, NULL);
2058
2059         req->hdr.version = 1;
2060         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2061         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2062
2063         status = be_mcc_notify_wait(adapter);
2064
2065 err:
2066         mutex_unlock(&adapter->mcc_lock);
2067
2068         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2069                 return  -EOPNOTSUPP;
2070
2071         return status;
2072 }
2073
2074 /* Uses sycn mcc */
2075 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2076 {
2077         struct be_mcc_wrb *wrb;
2078         struct be_cmd_req_get_flow_control *req;
2079         int status;
2080
2081         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2082                             CMD_SUBSYSTEM_COMMON))
2083                 return -EPERM;
2084
2085         mutex_lock(&adapter->mcc_lock);
2086
2087         wrb = wrb_from_mccq(adapter);
2088         if (!wrb) {
2089                 status = -EBUSY;
2090                 goto err;
2091         }
2092         req = embedded_payload(wrb);
2093
2094         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2095                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2096                                wrb, NULL);
2097
2098         status = be_mcc_notify_wait(adapter);
2099         if (!status) {
2100                 struct be_cmd_resp_get_flow_control *resp =
2101                                                 embedded_payload(wrb);
2102
2103                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2104                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2105         }
2106
2107 err:
2108         mutex_unlock(&adapter->mcc_lock);
2109         return status;
2110 }
2111
2112 /* Uses mbox */
2113 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2114 {
2115         struct be_mcc_wrb *wrb;
2116         struct be_cmd_req_query_fw_cfg *req;
2117         int status;
2118
2119         if (mutex_lock_interruptible(&adapter->mbox_lock))
2120                 return -1;
2121
2122         wrb = wrb_from_mbox(adapter);
2123         req = embedded_payload(wrb);
2124
2125         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2126                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2127                                sizeof(*req), wrb, NULL);
2128
2129         status = be_mbox_notify_wait(adapter);
2130         if (!status) {
2131                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2132
2133                 adapter->port_num = le32_to_cpu(resp->phys_port);
2134                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2135                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2136                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2137                 dev_info(&adapter->pdev->dev,
2138                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2139                          adapter->function_mode, adapter->function_caps);
2140         }
2141
2142         mutex_unlock(&adapter->mbox_lock);
2143         return status;
2144 }
2145
2146 /* Uses mbox */
2147 int be_cmd_reset_function(struct be_adapter *adapter)
2148 {
2149         struct be_mcc_wrb *wrb;
2150         struct be_cmd_req_hdr *req;
2151         int status;
2152
2153         if (lancer_chip(adapter)) {
2154                 iowrite32(SLI_PORT_CONTROL_IP_MASK,
2155                           adapter->db + SLIPORT_CONTROL_OFFSET);
2156                 status = lancer_wait_ready(adapter);
2157                 if (status)
2158                         dev_err(&adapter->pdev->dev,
2159                                 "Adapter in non recoverable error\n");
2160                 return status;
2161         }
2162
2163         if (mutex_lock_interruptible(&adapter->mbox_lock))
2164                 return -1;
2165
2166         wrb = wrb_from_mbox(adapter);
2167         req = embedded_payload(wrb);
2168
2169         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2170                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2171                                NULL);
2172
2173         status = be_mbox_notify_wait(adapter);
2174
2175         mutex_unlock(&adapter->mbox_lock);
2176         return status;
2177 }
2178
2179 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2180                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2181 {
2182         struct be_mcc_wrb *wrb;
2183         struct be_cmd_req_rss_config *req;
2184         int status;
2185
2186         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2187                 return 0;
2188
2189         mutex_lock(&adapter->mcc_lock);
2190
2191         wrb = wrb_from_mccq(adapter);
2192         if (!wrb) {
2193                 status = -EBUSY;
2194                 goto err;
2195         }
2196         req = embedded_payload(wrb);
2197
2198         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2199                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2200
2201         req->if_id = cpu_to_le32(adapter->if_handle);
2202         req->enable_rss = cpu_to_le16(rss_hash_opts);
2203         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2204
2205         if (!BEx_chip(adapter))
2206                 req->hdr.version = 1;
2207
2208         memcpy(req->cpu_table, rsstable, table_size);
2209         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2210         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2211
2212         status = be_mcc_notify_wait(adapter);
2213 err:
2214         mutex_unlock(&adapter->mcc_lock);
2215         return status;
2216 }
2217
2218 /* Uses sync mcc */
2219 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2220                             u8 bcn, u8 sts, u8 state)
2221 {
2222         struct be_mcc_wrb *wrb;
2223         struct be_cmd_req_enable_disable_beacon *req;
2224         int status;
2225
2226         mutex_lock(&adapter->mcc_lock);
2227
2228         wrb = wrb_from_mccq(adapter);
2229         if (!wrb) {
2230                 status = -EBUSY;
2231                 goto err;
2232         }
2233         req = embedded_payload(wrb);
2234
2235         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2236                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2237                                sizeof(*req), wrb, NULL);
2238
2239         req->port_num = port_num;
2240         req->beacon_state = state;
2241         req->beacon_duration = bcn;
2242         req->status_duration = sts;
2243
2244         status = be_mcc_notify_wait(adapter);
2245
2246 err:
2247         mutex_unlock(&adapter->mcc_lock);
2248         return status;
2249 }
2250
2251 /* Uses sync mcc */
2252 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2253 {
2254         struct be_mcc_wrb *wrb;
2255         struct be_cmd_req_get_beacon_state *req;
2256         int status;
2257
2258         mutex_lock(&adapter->mcc_lock);
2259
2260         wrb = wrb_from_mccq(adapter);
2261         if (!wrb) {
2262                 status = -EBUSY;
2263                 goto err;
2264         }
2265         req = embedded_payload(wrb);
2266
2267         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2268                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2269                                wrb, NULL);
2270
2271         req->port_num = port_num;
2272
2273         status = be_mcc_notify_wait(adapter);
2274         if (!status) {
2275                 struct be_cmd_resp_get_beacon_state *resp =
2276                                                 embedded_payload(wrb);
2277
2278                 *state = resp->beacon_state;
2279         }
2280
2281 err:
2282         mutex_unlock(&adapter->mcc_lock);
2283         return status;
2284 }
2285
2286 /* Uses sync mcc */
2287 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2288                                       u8 page_num, u8 *data)
2289 {
2290         struct be_dma_mem cmd;
2291         struct be_mcc_wrb *wrb;
2292         struct be_cmd_req_port_type *req;
2293         int status;
2294
2295         if (page_num > TR_PAGE_A2)
2296                 return -EINVAL;
2297
2298         cmd.size = sizeof(struct be_cmd_resp_port_type);
2299         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
2300                                     GFP_ATOMIC);
2301         if (!cmd.va) {
2302                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2303                 return -ENOMEM;
2304         }
2305
2306         mutex_lock(&adapter->mcc_lock);
2307
2308         wrb = wrb_from_mccq(adapter);
2309         if (!wrb) {
2310                 status = -EBUSY;
2311                 goto err;
2312         }
2313         req = cmd.va;
2314
2315         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2316                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2317                                cmd.size, wrb, &cmd);
2318
2319         req->port = cpu_to_le32(adapter->hba_port_num);
2320         req->page_num = cpu_to_le32(page_num);
2321         status = be_mcc_notify_wait(adapter);
2322         if (!status) {
2323                 struct be_cmd_resp_port_type *resp = cmd.va;
2324
2325                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2326         }
2327 err:
2328         mutex_unlock(&adapter->mcc_lock);
2329         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
2330         return status;
2331 }
2332
2333 static int lancer_cmd_write_object(struct be_adapter *adapter,
2334                                    struct be_dma_mem *cmd, u32 data_size,
2335                                    u32 data_offset, const char *obj_name,
2336                                    u32 *data_written, u8 *change_status,
2337                                    u8 *addn_status)
2338 {
2339         struct be_mcc_wrb *wrb;
2340         struct lancer_cmd_req_write_object *req;
2341         struct lancer_cmd_resp_write_object *resp;
2342         void *ctxt = NULL;
2343         int status;
2344
2345         mutex_lock(&adapter->mcc_lock);
2346         adapter->flash_status = 0;
2347
2348         wrb = wrb_from_mccq(adapter);
2349         if (!wrb) {
2350                 status = -EBUSY;
2351                 goto err_unlock;
2352         }
2353
2354         req = embedded_payload(wrb);
2355
2356         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2357                                OPCODE_COMMON_WRITE_OBJECT,
2358                                sizeof(struct lancer_cmd_req_write_object), wrb,
2359                                NULL);
2360
2361         ctxt = &req->context;
2362         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2363                       write_length, ctxt, data_size);
2364
2365         if (data_size == 0)
2366                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2367                               eof, ctxt, 1);
2368         else
2369                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2370                               eof, ctxt, 0);
2371
2372         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2373         req->write_offset = cpu_to_le32(data_offset);
2374         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2375         req->descriptor_count = cpu_to_le32(1);
2376         req->buf_len = cpu_to_le32(data_size);
2377         req->addr_low = cpu_to_le32((cmd->dma +
2378                                      sizeof(struct lancer_cmd_req_write_object))
2379                                     & 0xFFFFFFFF);
2380         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2381                                 sizeof(struct lancer_cmd_req_write_object)));
2382
2383         status = be_mcc_notify(adapter);
2384         if (status)
2385                 goto err_unlock;
2386
2387         mutex_unlock(&adapter->mcc_lock);
2388
2389         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2390                                          msecs_to_jiffies(60000)))
2391                 status = -ETIMEDOUT;
2392         else
2393                 status = adapter->flash_status;
2394
2395         resp = embedded_payload(wrb);
2396         if (!status) {
2397                 *data_written = le32_to_cpu(resp->actual_write_len);
2398                 *change_status = resp->change_status;
2399         } else {
2400                 *addn_status = resp->additional_status;
2401         }
2402
2403         return status;
2404
2405 err_unlock:
2406         mutex_unlock(&adapter->mcc_lock);
2407         return status;
2408 }
2409
2410 int be_cmd_query_cable_type(struct be_adapter *adapter)
2411 {
2412         u8 page_data[PAGE_DATA_LEN];
2413         int status;
2414
2415         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2416                                                    page_data);
2417         if (!status) {
2418                 switch (adapter->phy.interface_type) {
2419                 case PHY_TYPE_QSFP:
2420                         adapter->phy.cable_type =
2421                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2422                         break;
2423                 case PHY_TYPE_SFP_PLUS_10GB:
2424                         adapter->phy.cable_type =
2425                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2426                         break;
2427                 default:
2428                         adapter->phy.cable_type = 0;
2429                         break;
2430                 }
2431         }
2432         return status;
2433 }
2434
2435 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2436 {
2437         u8 page_data[PAGE_DATA_LEN];
2438         int status;
2439
2440         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2441                                                    page_data);
2442         if (!status) {
2443                 strlcpy(adapter->phy.vendor_name, page_data +
2444                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2445                 strlcpy(adapter->phy.vendor_pn,
2446                         page_data + SFP_VENDOR_PN_OFFSET,
2447                         SFP_VENDOR_NAME_LEN - 1);
2448         }
2449
2450         return status;
2451 }
2452
2453 static int lancer_cmd_delete_object(struct be_adapter *adapter,
2454                                     const char *obj_name)
2455 {
2456         struct lancer_cmd_req_delete_object *req;
2457         struct be_mcc_wrb *wrb;
2458         int status;
2459
2460         mutex_lock(&adapter->mcc_lock);
2461
2462         wrb = wrb_from_mccq(adapter);
2463         if (!wrb) {
2464                 status = -EBUSY;
2465                 goto err;
2466         }
2467
2468         req = embedded_payload(wrb);
2469
2470         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2471                                OPCODE_COMMON_DELETE_OBJECT,
2472                                sizeof(*req), wrb, NULL);
2473
2474         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2475
2476         status = be_mcc_notify_wait(adapter);
2477 err:
2478         mutex_unlock(&adapter->mcc_lock);
2479         return status;
2480 }
2481
2482 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2483                            u32 data_size, u32 data_offset, const char *obj_name,
2484                            u32 *data_read, u32 *eof, u8 *addn_status)
2485 {
2486         struct be_mcc_wrb *wrb;
2487         struct lancer_cmd_req_read_object *req;
2488         struct lancer_cmd_resp_read_object *resp;
2489         int status;
2490
2491         mutex_lock(&adapter->mcc_lock);
2492
2493         wrb = wrb_from_mccq(adapter);
2494         if (!wrb) {
2495                 status = -EBUSY;
2496                 goto err_unlock;
2497         }
2498
2499         req = embedded_payload(wrb);
2500
2501         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2502                                OPCODE_COMMON_READ_OBJECT,
2503                                sizeof(struct lancer_cmd_req_read_object), wrb,
2504                                NULL);
2505
2506         req->desired_read_len = cpu_to_le32(data_size);
2507         req->read_offset = cpu_to_le32(data_offset);
2508         strcpy(req->object_name, obj_name);
2509         req->descriptor_count = cpu_to_le32(1);
2510         req->buf_len = cpu_to_le32(data_size);
2511         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2512         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2513
2514         status = be_mcc_notify_wait(adapter);
2515
2516         resp = embedded_payload(wrb);
2517         if (!status) {
2518                 *data_read = le32_to_cpu(resp->actual_read_len);
2519                 *eof = le32_to_cpu(resp->eof);
2520         } else {
2521                 *addn_status = resp->additional_status;
2522         }
2523
2524 err_unlock:
2525         mutex_unlock(&adapter->mcc_lock);
2526         return status;
2527 }
2528
2529 static int be_cmd_write_flashrom(struct be_adapter *adapter,
2530                                  struct be_dma_mem *cmd, u32 flash_type,
2531                                  u32 flash_opcode, u32 img_offset, u32 buf_size)
2532 {
2533         struct be_mcc_wrb *wrb;
2534         struct be_cmd_write_flashrom *req;
2535         int status;
2536
2537         mutex_lock(&adapter->mcc_lock);
2538         adapter->flash_status = 0;
2539
2540         wrb = wrb_from_mccq(adapter);
2541         if (!wrb) {
2542                 status = -EBUSY;
2543                 goto err_unlock;
2544         }
2545         req = cmd->va;
2546
2547         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2548                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2549                                cmd);
2550
2551         req->params.op_type = cpu_to_le32(flash_type);
2552         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2553                 req->params.offset = cpu_to_le32(img_offset);
2554
2555         req->params.op_code = cpu_to_le32(flash_opcode);
2556         req->params.data_buf_size = cpu_to_le32(buf_size);
2557
2558         status = be_mcc_notify(adapter);
2559         if (status)
2560                 goto err_unlock;
2561
2562         mutex_unlock(&adapter->mcc_lock);
2563
2564         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2565                                          msecs_to_jiffies(40000)))
2566                 status = -ETIMEDOUT;
2567         else
2568                 status = adapter->flash_status;
2569
2570         return status;
2571
2572 err_unlock:
2573         mutex_unlock(&adapter->mcc_lock);
2574         return status;
2575 }
2576
2577 static int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2578                                 u16 img_optype, u32 img_offset, u32 crc_offset)
2579 {
2580         struct be_cmd_read_flash_crc *req;
2581         struct be_mcc_wrb *wrb;
2582         int status;
2583
2584         mutex_lock(&adapter->mcc_lock);
2585
2586         wrb = wrb_from_mccq(adapter);
2587         if (!wrb) {
2588                 status = -EBUSY;
2589                 goto err;
2590         }
2591         req = embedded_payload(wrb);
2592
2593         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2594                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2595                                wrb, NULL);
2596
2597         req->params.op_type = cpu_to_le32(img_optype);
2598         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2599                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2600         else
2601                 req->params.offset = cpu_to_le32(crc_offset);
2602
2603         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2604         req->params.data_buf_size = cpu_to_le32(0x4);
2605
2606         status = be_mcc_notify_wait(adapter);
2607         if (!status)
2608                 memcpy(flashed_crc, req->crc, 4);
2609
2610 err:
2611         mutex_unlock(&adapter->mcc_lock);
2612         return status;
2613 }
2614
2615 static char flash_cookie[2][16] = {"*** SE FLAS", "H DIRECTORY *** "};
2616
2617 static bool phy_flashing_required(struct be_adapter *adapter)
2618 {
2619         return (adapter->phy.phy_type == PHY_TYPE_TN_8022 &&
2620                 adapter->phy.interface_type == PHY_TYPE_BASET_10GB);
2621 }
2622
2623 static bool is_comp_in_ufi(struct be_adapter *adapter,
2624                            struct flash_section_info *fsec, int type)
2625 {
2626         int i = 0, img_type = 0;
2627         struct flash_section_info_g2 *fsec_g2 = NULL;
2628
2629         if (BE2_chip(adapter))
2630                 fsec_g2 = (struct flash_section_info_g2 *)fsec;
2631
2632         for (i = 0; i < MAX_FLASH_COMP; i++) {
2633                 if (fsec_g2)
2634                         img_type = le32_to_cpu(fsec_g2->fsec_entry[i].type);
2635                 else
2636                         img_type = le32_to_cpu(fsec->fsec_entry[i].type);
2637
2638                 if (img_type == type)
2639                         return true;
2640         }
2641         return false;
2642 }
2643
2644 static struct flash_section_info *get_fsec_info(struct be_adapter *adapter,
2645                                                 int header_size,
2646                                                 const struct firmware *fw)
2647 {
2648         struct flash_section_info *fsec = NULL;
2649         const u8 *p = fw->data;
2650
2651         p += header_size;
2652         while (p < (fw->data + fw->size)) {
2653                 fsec = (struct flash_section_info *)p;
2654                 if (!memcmp(flash_cookie, fsec->cookie, sizeof(flash_cookie)))
2655                         return fsec;
2656                 p += 32;
2657         }
2658         return NULL;
2659 }
2660
2661 static int be_check_flash_crc(struct be_adapter *adapter, const u8 *p,
2662                               u32 img_offset, u32 img_size, int hdr_size,
2663                               u16 img_optype, bool *crc_match)
2664 {
2665         u32 crc_offset;
2666         int status;
2667         u8 crc[4];
2668
2669         status = be_cmd_get_flash_crc(adapter, crc, img_optype, img_offset,
2670                                       img_size - 4);
2671         if (status)
2672                 return status;
2673
2674         crc_offset = hdr_size + img_offset + img_size - 4;
2675
2676         /* Skip flashing, if crc of flashed region matches */
2677         if (!memcmp(crc, p + crc_offset, 4))
2678                 *crc_match = true;
2679         else
2680                 *crc_match = false;
2681
2682         return status;
2683 }
2684
2685 static int be_flash(struct be_adapter *adapter, const u8 *img,
2686                     struct be_dma_mem *flash_cmd, int optype, int img_size,
2687                     u32 img_offset)
2688 {
2689         u32 flash_op, num_bytes, total_bytes = img_size, bytes_sent = 0;
2690         struct be_cmd_write_flashrom *req = flash_cmd->va;
2691         int status;
2692
2693         while (total_bytes) {
2694                 num_bytes = min_t(u32, 32 * 1024, total_bytes);
2695
2696                 total_bytes -= num_bytes;
2697
2698                 if (!total_bytes) {
2699                         if (optype == OPTYPE_PHY_FW)
2700                                 flash_op = FLASHROM_OPER_PHY_FLASH;
2701                         else
2702                                 flash_op = FLASHROM_OPER_FLASH;
2703                 } else {
2704                         if (optype == OPTYPE_PHY_FW)
2705                                 flash_op = FLASHROM_OPER_PHY_SAVE;
2706                         else
2707                                 flash_op = FLASHROM_OPER_SAVE;
2708                 }
2709
2710                 memcpy(req->data_buf, img, num_bytes);
2711                 img += num_bytes;
2712                 status = be_cmd_write_flashrom(adapter, flash_cmd, optype,
2713                                                flash_op, img_offset +
2714                                                bytes_sent, num_bytes);
2715                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST &&
2716                     optype == OPTYPE_PHY_FW)
2717                         break;
2718                 else if (status)
2719                         return status;
2720
2721                 bytes_sent += num_bytes;
2722         }
2723         return 0;
2724 }
2725
2726 #define NCSI_UPDATE_LOG "NCSI section update is not supported in FW ver %s\n"
2727 static bool be_fw_ncsi_supported(char *ver)
2728 {
2729         int v1[4] = {3, 102, 148, 0}; /* Min ver that supports NCSI FW */
2730         int v2[4];
2731         int i;
2732
2733         if (sscanf(ver, "%d.%d.%d.%d", &v2[0], &v2[1], &v2[2], &v2[3]) != 4)
2734                 return false;
2735
2736         for (i = 0; i < 4; i++) {
2737                 if (v1[i] < v2[i])
2738                         return true;
2739                 else if (v1[i] > v2[i])
2740                         return false;
2741         }
2742
2743         return true;
2744 }
2745
2746 /* For BE2, BE3 and BE3-R */
2747 static int be_flash_BEx(struct be_adapter *adapter,
2748                         const struct firmware *fw,
2749                         struct be_dma_mem *flash_cmd, int num_of_images)
2750 {
2751         int img_hdrs_size = (num_of_images * sizeof(struct image_hdr));
2752         struct device *dev = &adapter->pdev->dev;
2753         struct flash_section_info *fsec = NULL;
2754         int status, i, filehdr_size, num_comp;
2755         const struct flash_comp *pflashcomp;
2756         bool crc_match;
2757         const u8 *p;
2758
2759         static const struct flash_comp gen3_flash_types[] = {
2760                 { BE3_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2761                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2762                 { BE3_REDBOOT_START, OPTYPE_REDBOOT,
2763                         BE3_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2764                 { BE3_ISCSI_BIOS_START, OPTYPE_BIOS,
2765                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2766                 { BE3_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2767                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2768                 { BE3_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2769                         BE3_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2770                 { BE3_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2771                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2772                 { BE3_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2773                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2774                 { BE3_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2775                         BE3_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE},
2776                 { BE3_NCSI_START, OPTYPE_NCSI_FW,
2777                         BE3_NCSI_COMP_MAX_SIZE, IMAGE_NCSI},
2778                 { BE3_PHY_FW_START, OPTYPE_PHY_FW,
2779                         BE3_PHY_FW_COMP_MAX_SIZE, IMAGE_FIRMWARE_PHY}
2780         };
2781
2782         static const struct flash_comp gen2_flash_types[] = {
2783                 { BE2_ISCSI_PRIMARY_IMAGE_START, OPTYPE_ISCSI_ACTIVE,
2784                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_ISCSI},
2785                 { BE2_REDBOOT_START, OPTYPE_REDBOOT,
2786                         BE2_REDBOOT_COMP_MAX_SIZE, IMAGE_BOOT_CODE},
2787                 { BE2_ISCSI_BIOS_START, OPTYPE_BIOS,
2788                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_ISCSI},
2789                 { BE2_PXE_BIOS_START, OPTYPE_PXE_BIOS,
2790                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_PXE},
2791                 { BE2_FCOE_BIOS_START, OPTYPE_FCOE_BIOS,
2792                         BE2_BIOS_COMP_MAX_SIZE, IMAGE_OPTION_ROM_FCOE},
2793                 { BE2_ISCSI_BACKUP_IMAGE_START, OPTYPE_ISCSI_BACKUP,
2794                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_ISCSI},
2795                 { BE2_FCOE_PRIMARY_IMAGE_START, OPTYPE_FCOE_FW_ACTIVE,
2796                         BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_FCOE},
2797                 { BE2_FCOE_BACKUP_IMAGE_START, OPTYPE_FCOE_FW_BACKUP,
2798                          BE2_COMP_MAX_SIZE, IMAGE_FIRMWARE_BACKUP_FCOE}
2799         };
2800
2801         if (BE3_chip(adapter)) {
2802                 pflashcomp = gen3_flash_types;
2803                 filehdr_size = sizeof(struct flash_file_hdr_g3);
2804                 num_comp = ARRAY_SIZE(gen3_flash_types);
2805         } else {
2806                 pflashcomp = gen2_flash_types;
2807                 filehdr_size = sizeof(struct flash_file_hdr_g2);
2808                 num_comp = ARRAY_SIZE(gen2_flash_types);
2809                 img_hdrs_size = 0;
2810         }
2811
2812         /* Get flash section info*/
2813         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2814         if (!fsec) {
2815                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2816                 return -1;
2817         }
2818         for (i = 0; i < num_comp; i++) {
2819                 if (!is_comp_in_ufi(adapter, fsec, pflashcomp[i].img_type))
2820                         continue;
2821
2822                 if ((pflashcomp[i].optype == OPTYPE_NCSI_FW) &&
2823                     !be_fw_ncsi_supported(adapter->fw_ver)) {
2824                         dev_info(dev, NCSI_UPDATE_LOG, adapter->fw_ver);
2825                         continue;
2826                 }
2827
2828                 if (pflashcomp[i].optype == OPTYPE_PHY_FW  &&
2829                     !phy_flashing_required(adapter))
2830                         continue;
2831
2832                 if (pflashcomp[i].optype == OPTYPE_REDBOOT) {
2833                         status = be_check_flash_crc(adapter, fw->data,
2834                                                     pflashcomp[i].offset,
2835                                                     pflashcomp[i].size,
2836                                                     filehdr_size +
2837                                                     img_hdrs_size,
2838                                                     OPTYPE_REDBOOT, &crc_match);
2839                         if (status) {
2840                                 dev_err(dev,
2841                                         "Could not get CRC for 0x%x region\n",
2842                                         pflashcomp[i].optype);
2843                                 continue;
2844                         }
2845
2846                         if (crc_match)
2847                                 continue;
2848                 }
2849
2850                 p = fw->data + filehdr_size + pflashcomp[i].offset +
2851                         img_hdrs_size;
2852                 if (p + pflashcomp[i].size > fw->data + fw->size)
2853                         return -1;
2854
2855                 status = be_flash(adapter, p, flash_cmd, pflashcomp[i].optype,
2856                                   pflashcomp[i].size, 0);
2857                 if (status) {
2858                         dev_err(dev, "Flashing section type 0x%x failed\n",
2859                                 pflashcomp[i].img_type);
2860                         return status;
2861                 }
2862         }
2863         return 0;
2864 }
2865
2866 static u16 be_get_img_optype(struct flash_section_entry fsec_entry)
2867 {
2868         u32 img_type = le32_to_cpu(fsec_entry.type);
2869         u16 img_optype = le16_to_cpu(fsec_entry.optype);
2870
2871         if (img_optype != 0xFFFF)
2872                 return img_optype;
2873
2874         switch (img_type) {
2875         case IMAGE_FIRMWARE_ISCSI:
2876                 img_optype = OPTYPE_ISCSI_ACTIVE;
2877                 break;
2878         case IMAGE_BOOT_CODE:
2879                 img_optype = OPTYPE_REDBOOT;
2880                 break;
2881         case IMAGE_OPTION_ROM_ISCSI:
2882                 img_optype = OPTYPE_BIOS;
2883                 break;
2884         case IMAGE_OPTION_ROM_PXE:
2885                 img_optype = OPTYPE_PXE_BIOS;
2886                 break;
2887         case IMAGE_OPTION_ROM_FCOE:
2888                 img_optype = OPTYPE_FCOE_BIOS;
2889                 break;
2890         case IMAGE_FIRMWARE_BACKUP_ISCSI:
2891                 img_optype = OPTYPE_ISCSI_BACKUP;
2892                 break;
2893         case IMAGE_NCSI:
2894                 img_optype = OPTYPE_NCSI_FW;
2895                 break;
2896         case IMAGE_FLASHISM_JUMPVECTOR:
2897                 img_optype = OPTYPE_FLASHISM_JUMPVECTOR;
2898                 break;
2899         case IMAGE_FIRMWARE_PHY:
2900                 img_optype = OPTYPE_SH_PHY_FW;
2901                 break;
2902         case IMAGE_REDBOOT_DIR:
2903                 img_optype = OPTYPE_REDBOOT_DIR;
2904                 break;
2905         case IMAGE_REDBOOT_CONFIG:
2906                 img_optype = OPTYPE_REDBOOT_CONFIG;
2907                 break;
2908         case IMAGE_UFI_DIR:
2909                 img_optype = OPTYPE_UFI_DIR;
2910                 break;
2911         default:
2912                 break;
2913         }
2914
2915         return img_optype;
2916 }
2917
2918 static int be_flash_skyhawk(struct be_adapter *adapter,
2919                             const struct firmware *fw,
2920                             struct be_dma_mem *flash_cmd, int num_of_images)
2921 {
2922         int img_hdrs_size = num_of_images * sizeof(struct image_hdr);
2923         bool crc_match, old_fw_img, flash_offset_support = true;
2924         struct device *dev = &adapter->pdev->dev;
2925         struct flash_section_info *fsec = NULL;
2926         u32 img_offset, img_size, img_type;
2927         u16 img_optype, flash_optype;
2928         int status, i, filehdr_size;
2929         const u8 *p;
2930
2931         filehdr_size = sizeof(struct flash_file_hdr_g3);
2932         fsec = get_fsec_info(adapter, filehdr_size + img_hdrs_size, fw);
2933         if (!fsec) {
2934                 dev_err(dev, "Invalid Cookie. FW image may be corrupted\n");
2935                 return -EINVAL;
2936         }
2937
2938 retry_flash:
2939         for (i = 0; i < le32_to_cpu(fsec->fsec_hdr.num_images); i++) {
2940                 img_offset = le32_to_cpu(fsec->fsec_entry[i].offset);
2941                 img_size   = le32_to_cpu(fsec->fsec_entry[i].pad_size);
2942                 img_type   = le32_to_cpu(fsec->fsec_entry[i].type);
2943                 img_optype = be_get_img_optype(fsec->fsec_entry[i]);
2944                 old_fw_img = fsec->fsec_entry[i].optype == 0xFFFF;
2945
2946                 if (img_optype == 0xFFFF)
2947                         continue;
2948
2949                 if (flash_offset_support)
2950                         flash_optype = OPTYPE_OFFSET_SPECIFIED;
2951                 else
2952                         flash_optype = img_optype;
2953
2954                 /* Don't bother verifying CRC if an old FW image is being
2955                  * flashed
2956                  */
2957                 if (old_fw_img)
2958                         goto flash;
2959
2960                 status = be_check_flash_crc(adapter, fw->data, img_offset,
2961                                             img_size, filehdr_size +
2962                                             img_hdrs_size, flash_optype,
2963                                             &crc_match);
2964                 if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
2965                     base_status(status) == MCC_STATUS_ILLEGAL_FIELD) {
2966                         /* The current FW image on the card does not support
2967                          * OFFSET based flashing. Retry using older mechanism
2968                          * of OPTYPE based flashing
2969                          */
2970                         if (flash_optype == OPTYPE_OFFSET_SPECIFIED) {
2971                                 flash_offset_support = false;
2972                                 goto retry_flash;
2973                         }
2974
2975                         /* The current FW image on the card does not recognize
2976                          * the new FLASH op_type. The FW download is partially
2977                          * complete. Reboot the server now to enable FW image
2978                          * to recognize the new FLASH op_type. To complete the
2979                          * remaining process, download the same FW again after
2980                          * the reboot.
2981                          */
2982                         dev_err(dev, "Flash incomplete. Reset the server\n");
2983                         dev_err(dev, "Download FW image again after reset\n");
2984                         return -EAGAIN;
2985                 } else if (status) {
2986                         dev_err(dev, "Could not get CRC for 0x%x region\n",
2987                                 img_optype);
2988                         return -EFAULT;
2989                 }
2990
2991                 if (crc_match)
2992                         continue;
2993
2994 flash:
2995                 p = fw->data + filehdr_size + img_offset + img_hdrs_size;
2996                 if (p + img_size > fw->data + fw->size)
2997                         return -1;
2998
2999                 status = be_flash(adapter, p, flash_cmd, flash_optype, img_size,
3000                                   img_offset);
3001
3002                 /* The current FW image on the card does not support OFFSET
3003                  * based flashing. Retry using older mechanism of OPTYPE based
3004                  * flashing
3005                  */
3006                 if (base_status(status) == MCC_STATUS_ILLEGAL_FIELD &&
3007                     flash_optype == OPTYPE_OFFSET_SPECIFIED) {
3008                         flash_offset_support = false;
3009                         goto retry_flash;
3010                 }
3011
3012                 /* For old FW images ignore ILLEGAL_FIELD error or errors on
3013                  * UFI_DIR region
3014                  */
3015                 if (old_fw_img &&
3016                     (base_status(status) == MCC_STATUS_ILLEGAL_FIELD ||
3017                      (img_optype == OPTYPE_UFI_DIR &&
3018                       base_status(status) == MCC_STATUS_FAILED))) {
3019                         continue;
3020                 } else if (status) {
3021                         dev_err(dev, "Flashing section type 0x%x failed\n",
3022                                 img_type);
3023
3024                         switch (addl_status(status)) {
3025                         case MCC_ADDL_STATUS_MISSING_SIGNATURE:
3026                                 dev_err(dev,
3027                                         "Digital signature missing in FW\n");
3028                                 return -EINVAL;
3029                         case MCC_ADDL_STATUS_INVALID_SIGNATURE:
3030                                 dev_err(dev,
3031                                         "Invalid digital signature in FW\n");
3032                                 return -EINVAL;
3033                         default:
3034                                 return -EFAULT;
3035                         }
3036                 }
3037         }
3038         return 0;
3039 }
3040
3041 int lancer_fw_download(struct be_adapter *adapter,
3042                        const struct firmware *fw)
3043 {
3044         struct device *dev = &adapter->pdev->dev;
3045         struct be_dma_mem flash_cmd;
3046         const u8 *data_ptr = NULL;
3047         u8 *dest_image_ptr = NULL;
3048         size_t image_size = 0;
3049         u32 chunk_size = 0;
3050         u32 data_written = 0;
3051         u32 offset = 0;
3052         int status = 0;
3053         u8 add_status = 0;
3054         u8 change_status;
3055
3056         if (!IS_ALIGNED(fw->size, sizeof(u32))) {
3057                 dev_err(dev, "FW image size should be multiple of 4\n");
3058                 return -EINVAL;
3059         }
3060
3061         flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
3062                                 + LANCER_FW_DOWNLOAD_CHUNK;
3063         flash_cmd.va = dma_alloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3064                                           GFP_KERNEL);
3065         if (!flash_cmd.va)
3066                 return -ENOMEM;
3067
3068         dest_image_ptr = flash_cmd.va +
3069                                 sizeof(struct lancer_cmd_req_write_object);
3070         image_size = fw->size;
3071         data_ptr = fw->data;
3072
3073         while (image_size) {
3074                 chunk_size = min_t(u32, image_size, LANCER_FW_DOWNLOAD_CHUNK);
3075
3076                 /* Copy the image chunk content. */
3077                 memcpy(dest_image_ptr, data_ptr, chunk_size);
3078
3079                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3080                                                  chunk_size, offset,
3081                                                  LANCER_FW_DOWNLOAD_LOCATION,
3082                                                  &data_written, &change_status,
3083                                                  &add_status);
3084                 if (status)
3085                         break;
3086
3087                 offset += data_written;
3088                 data_ptr += data_written;
3089                 image_size -= data_written;
3090         }
3091
3092         if (!status) {
3093                 /* Commit the FW written */
3094                 status = lancer_cmd_write_object(adapter, &flash_cmd,
3095                                                  0, offset,
3096                                                  LANCER_FW_DOWNLOAD_LOCATION,
3097                                                  &data_written, &change_status,
3098                                                  &add_status);
3099         }
3100
3101         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3102         if (status) {
3103                 dev_err(dev, "Firmware load error\n");
3104                 return be_cmd_status(status);
3105         }
3106
3107         dev_info(dev, "Firmware flashed successfully\n");
3108
3109         if (change_status == LANCER_FW_RESET_NEEDED) {
3110                 dev_info(dev, "Resetting adapter to activate new FW\n");
3111                 status = lancer_physdev_ctrl(adapter,
3112                                              PHYSDEV_CONTROL_FW_RESET_MASK);
3113                 if (status) {
3114                         dev_err(dev, "Adapter busy, could not reset FW\n");
3115                         dev_err(dev, "Reboot server to activate new FW\n");
3116                 }
3117         } else if (change_status != LANCER_NO_RESET_NEEDED) {
3118                 dev_info(dev, "Reboot server to activate new FW\n");
3119         }
3120
3121         return 0;
3122 }
3123
3124 /* Check if the flash image file is compatible with the adapter that
3125  * is being flashed.
3126  */
3127 static bool be_check_ufi_compatibility(struct be_adapter *adapter,
3128                                        struct flash_file_hdr_g3 *fhdr)
3129 {
3130         if (!fhdr) {
3131                 dev_err(&adapter->pdev->dev, "Invalid FW UFI file");
3132                 return false;
3133         }
3134
3135         /* First letter of the build version is used to identify
3136          * which chip this image file is meant for.
3137          */
3138         switch (fhdr->build[0]) {
3139         case BLD_STR_UFI_TYPE_SH:
3140                 if (!skyhawk_chip(adapter))
3141                         return false;
3142                 break;
3143         case BLD_STR_UFI_TYPE_BE3:
3144                 if (!BE3_chip(adapter))
3145                         return false;
3146                 break;
3147         case BLD_STR_UFI_TYPE_BE2:
3148                 if (!BE2_chip(adapter))
3149                         return false;
3150                 break;
3151         default:
3152                 return false;
3153         }
3154
3155         /* In BE3 FW images the "asic_type_rev" field doesn't track the
3156          * asic_rev of the chips it is compatible with.
3157          * When asic_type_rev is 0 the image is compatible only with
3158          * pre-BE3-R chips (asic_rev < 0x10)
3159          */
3160         if (BEx_chip(adapter) && fhdr->asic_type_rev == 0)
3161                 return adapter->asic_rev < 0x10;
3162         else
3163                 return (fhdr->asic_type_rev >= adapter->asic_rev);
3164 }
3165
3166 int be_fw_download(struct be_adapter *adapter, const struct firmware *fw)
3167 {
3168         struct device *dev = &adapter->pdev->dev;
3169         struct flash_file_hdr_g3 *fhdr3;
3170         struct image_hdr *img_hdr_ptr;
3171         int status = 0, i, num_imgs;
3172         struct be_dma_mem flash_cmd;
3173
3174         fhdr3 = (struct flash_file_hdr_g3 *)fw->data;
3175         if (!be_check_ufi_compatibility(adapter, fhdr3)) {
3176                 dev_err(dev, "Flash image is not compatible with adapter\n");
3177                 return -EINVAL;
3178         }
3179
3180         flash_cmd.size = sizeof(struct be_cmd_write_flashrom);
3181         flash_cmd.va = dma_alloc_coherent(dev, flash_cmd.size, &flash_cmd.dma,
3182                                           GFP_KERNEL);
3183         if (!flash_cmd.va)
3184                 return -ENOMEM;
3185
3186         num_imgs = le32_to_cpu(fhdr3->num_imgs);
3187         for (i = 0; i < num_imgs; i++) {
3188                 img_hdr_ptr = (struct image_hdr *)(fw->data +
3189                                 (sizeof(struct flash_file_hdr_g3) +
3190                                  i * sizeof(struct image_hdr)));
3191                 if (!BE2_chip(adapter) &&
3192                     le32_to_cpu(img_hdr_ptr->imageid) != 1)
3193                         continue;
3194
3195                 if (skyhawk_chip(adapter))
3196                         status = be_flash_skyhawk(adapter, fw, &flash_cmd,
3197                                                   num_imgs);
3198                 else
3199                         status = be_flash_BEx(adapter, fw, &flash_cmd,
3200                                               num_imgs);
3201         }
3202
3203         dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
3204         if (!status)
3205                 dev_info(dev, "Firmware flashed successfully\n");
3206
3207         return status;
3208 }
3209
3210 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
3211                             struct be_dma_mem *nonemb_cmd)
3212 {
3213         struct be_mcc_wrb *wrb;
3214         struct be_cmd_req_acpi_wol_magic_config *req;
3215         int status;
3216
3217         mutex_lock(&adapter->mcc_lock);
3218
3219         wrb = wrb_from_mccq(adapter);
3220         if (!wrb) {
3221                 status = -EBUSY;
3222                 goto err;
3223         }
3224         req = nonemb_cmd->va;
3225
3226         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3227                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
3228                                wrb, nonemb_cmd);
3229         memcpy(req->magic_mac, mac, ETH_ALEN);
3230
3231         status = be_mcc_notify_wait(adapter);
3232
3233 err:
3234         mutex_unlock(&adapter->mcc_lock);
3235         return status;
3236 }
3237
3238 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
3239                         u8 loopback_type, u8 enable)
3240 {
3241         struct be_mcc_wrb *wrb;
3242         struct be_cmd_req_set_lmode *req;
3243         int status;
3244
3245         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
3246                             CMD_SUBSYSTEM_LOWLEVEL))
3247                 return -EPERM;
3248
3249         mutex_lock(&adapter->mcc_lock);
3250
3251         wrb = wrb_from_mccq(adapter);
3252         if (!wrb) {
3253                 status = -EBUSY;
3254                 goto err_unlock;
3255         }
3256
3257         req = embedded_payload(wrb);
3258
3259         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3260                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
3261                                wrb, NULL);
3262
3263         req->src_port = port_num;
3264         req->dest_port = port_num;
3265         req->loopback_type = loopback_type;
3266         req->loopback_state = enable;
3267
3268         status = be_mcc_notify(adapter);
3269         if (status)
3270                 goto err_unlock;
3271
3272         mutex_unlock(&adapter->mcc_lock);
3273
3274         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
3275                                          msecs_to_jiffies(SET_LB_MODE_TIMEOUT)))
3276                 status = -ETIMEDOUT;
3277
3278         return status;
3279
3280 err_unlock:
3281         mutex_unlock(&adapter->mcc_lock);
3282         return status;
3283 }
3284
3285 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
3286                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
3287                          u64 pattern)
3288 {
3289         struct be_mcc_wrb *wrb;
3290         struct be_cmd_req_loopback_test *req;
3291         struct be_cmd_resp_loopback_test *resp;
3292         int status;
3293
3294         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_LOOPBACK_TEST,
3295                             CMD_SUBSYSTEM_LOWLEVEL))
3296                 return -EPERM;
3297
3298         mutex_lock(&adapter->mcc_lock);
3299
3300         wrb = wrb_from_mccq(adapter);
3301         if (!wrb) {
3302                 status = -EBUSY;
3303                 goto err;
3304         }
3305
3306         req = embedded_payload(wrb);
3307
3308         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3309                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
3310                                NULL);
3311
3312         req->hdr.timeout = cpu_to_le32(15);
3313         req->pattern = cpu_to_le64(pattern);
3314         req->src_port = cpu_to_le32(port_num);
3315         req->dest_port = cpu_to_le32(port_num);
3316         req->pkt_size = cpu_to_le32(pkt_size);
3317         req->num_pkts = cpu_to_le32(num_pkts);
3318         req->loopback_type = cpu_to_le32(loopback_type);
3319
3320         status = be_mcc_notify(adapter);
3321         if (status)
3322                 goto err;
3323
3324         mutex_unlock(&adapter->mcc_lock);
3325
3326         wait_for_completion(&adapter->et_cmd_compl);
3327         resp = embedded_payload(wrb);
3328         status = le32_to_cpu(resp->status);
3329
3330         return status;
3331 err:
3332         mutex_unlock(&adapter->mcc_lock);
3333         return status;
3334 }
3335
3336 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
3337                         u32 byte_cnt, struct be_dma_mem *cmd)
3338 {
3339         struct be_mcc_wrb *wrb;
3340         struct be_cmd_req_ddrdma_test *req;
3341         int status;
3342         int i, j = 0;
3343
3344         if (!be_cmd_allowed(adapter, OPCODE_LOWLEVEL_HOST_DDR_DMA,
3345                             CMD_SUBSYSTEM_LOWLEVEL))
3346                 return -EPERM;
3347
3348         mutex_lock(&adapter->mcc_lock);
3349
3350         wrb = wrb_from_mccq(adapter);
3351         if (!wrb) {
3352                 status = -EBUSY;
3353                 goto err;
3354         }
3355         req = cmd->va;
3356         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
3357                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
3358                                cmd);
3359
3360         req->pattern = cpu_to_le64(pattern);
3361         req->byte_count = cpu_to_le32(byte_cnt);
3362         for (i = 0; i < byte_cnt; i++) {
3363                 req->snd_buff[i] = (u8)(pattern >> (j*8));
3364                 j++;
3365                 if (j > 7)
3366                         j = 0;
3367         }
3368
3369         status = be_mcc_notify_wait(adapter);
3370
3371         if (!status) {
3372                 struct be_cmd_resp_ddrdma_test *resp;
3373
3374                 resp = cmd->va;
3375                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
3376                     resp->snd_err) {
3377                         status = -1;
3378                 }
3379         }
3380
3381 err:
3382         mutex_unlock(&adapter->mcc_lock);
3383         return status;
3384 }
3385
3386 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
3387                             struct be_dma_mem *nonemb_cmd)
3388 {
3389         struct be_mcc_wrb *wrb;
3390         struct be_cmd_req_seeprom_read *req;
3391         int status;
3392
3393         mutex_lock(&adapter->mcc_lock);
3394
3395         wrb = wrb_from_mccq(adapter);
3396         if (!wrb) {
3397                 status = -EBUSY;
3398                 goto err;
3399         }
3400         req = nonemb_cmd->va;
3401
3402         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3403                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
3404                                nonemb_cmd);
3405
3406         status = be_mcc_notify_wait(adapter);
3407
3408 err:
3409         mutex_unlock(&adapter->mcc_lock);
3410         return status;
3411 }
3412
3413 int be_cmd_get_phy_info(struct be_adapter *adapter)
3414 {
3415         struct be_mcc_wrb *wrb;
3416         struct be_cmd_req_get_phy_info *req;
3417         struct be_dma_mem cmd;
3418         int status;
3419
3420         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
3421                             CMD_SUBSYSTEM_COMMON))
3422                 return -EPERM;
3423
3424         mutex_lock(&adapter->mcc_lock);
3425
3426         wrb = wrb_from_mccq(adapter);
3427         if (!wrb) {
3428                 status = -EBUSY;
3429                 goto err;
3430         }
3431         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
3432         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3433                                     GFP_ATOMIC);
3434         if (!cmd.va) {
3435                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3436                 status = -ENOMEM;
3437                 goto err;
3438         }
3439
3440         req = cmd.va;
3441
3442         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3443                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
3444                                wrb, &cmd);
3445
3446         status = be_mcc_notify_wait(adapter);
3447         if (!status) {
3448                 struct be_phy_info *resp_phy_info =
3449                                 cmd.va + sizeof(struct be_cmd_req_hdr);
3450
3451                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
3452                 adapter->phy.interface_type =
3453                         le16_to_cpu(resp_phy_info->interface_type);
3454                 adapter->phy.auto_speeds_supported =
3455                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
3456                 adapter->phy.fixed_speeds_supported =
3457                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
3458                 adapter->phy.misc_params =
3459                         le32_to_cpu(resp_phy_info->misc_params);
3460
3461                 if (BE2_chip(adapter)) {
3462                         adapter->phy.fixed_speeds_supported =
3463                                 BE_SUPPORTED_SPEED_10GBPS |
3464                                 BE_SUPPORTED_SPEED_1GBPS;
3465                 }
3466         }
3467         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3468 err:
3469         mutex_unlock(&adapter->mcc_lock);
3470         return status;
3471 }
3472
3473 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
3474 {
3475         struct be_mcc_wrb *wrb;
3476         struct be_cmd_req_set_qos *req;
3477         int status;
3478
3479         mutex_lock(&adapter->mcc_lock);
3480
3481         wrb = wrb_from_mccq(adapter);
3482         if (!wrb) {
3483                 status = -EBUSY;
3484                 goto err;
3485         }
3486
3487         req = embedded_payload(wrb);
3488
3489         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3490                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
3491
3492         req->hdr.domain = domain;
3493         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
3494         req->max_bps_nic = cpu_to_le32(bps);
3495
3496         status = be_mcc_notify_wait(adapter);
3497
3498 err:
3499         mutex_unlock(&adapter->mcc_lock);
3500         return status;
3501 }
3502
3503 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
3504 {
3505         struct be_mcc_wrb *wrb;
3506         struct be_cmd_req_cntl_attribs *req;
3507         struct be_cmd_resp_cntl_attribs *resp;
3508         int status, i;
3509         int payload_len = max(sizeof(*req), sizeof(*resp));
3510         struct mgmt_controller_attrib *attribs;
3511         struct be_dma_mem attribs_cmd;
3512         u32 *serial_num;
3513
3514         if (mutex_lock_interruptible(&adapter->mbox_lock))
3515                 return -1;
3516
3517         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
3518         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
3519         attribs_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
3520                                             attribs_cmd.size,
3521                                             &attribs_cmd.dma, GFP_ATOMIC);
3522         if (!attribs_cmd.va) {
3523                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3524                 status = -ENOMEM;
3525                 goto err;
3526         }
3527
3528         wrb = wrb_from_mbox(adapter);
3529         if (!wrb) {
3530                 status = -EBUSY;
3531                 goto err;
3532         }
3533         req = attribs_cmd.va;
3534
3535         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3536                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
3537                                wrb, &attribs_cmd);
3538
3539         status = be_mbox_notify_wait(adapter);
3540         if (!status) {
3541                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
3542                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
3543                 serial_num = attribs->hba_attribs.controller_serial_number;
3544                 for (i = 0; i < CNTL_SERIAL_NUM_WORDS; i++)
3545                         adapter->serial_num[i] = le32_to_cpu(serial_num[i]) &
3546                                 (BIT_MASK(16) - 1);
3547                 /* For BEx, since GET_FUNC_CONFIG command is not
3548                  * supported, we read funcnum here as a workaround.
3549                  */
3550                 if (BEx_chip(adapter))
3551                         adapter->pf_num = attribs->hba_attribs.pci_funcnum;
3552         }
3553
3554 err:
3555         mutex_unlock(&adapter->mbox_lock);
3556         if (attribs_cmd.va)
3557                 dma_free_coherent(&adapter->pdev->dev, attribs_cmd.size,
3558                                   attribs_cmd.va, attribs_cmd.dma);
3559         return status;
3560 }
3561
3562 /* Uses mbox */
3563 int be_cmd_req_native_mode(struct be_adapter *adapter)
3564 {
3565         struct be_mcc_wrb *wrb;
3566         struct be_cmd_req_set_func_cap *req;
3567         int status;
3568
3569         if (mutex_lock_interruptible(&adapter->mbox_lock))
3570                 return -1;
3571
3572         wrb = wrb_from_mbox(adapter);
3573         if (!wrb) {
3574                 status = -EBUSY;
3575                 goto err;
3576         }
3577
3578         req = embedded_payload(wrb);
3579
3580         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3581                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
3582                                sizeof(*req), wrb, NULL);
3583
3584         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
3585                                 CAPABILITY_BE3_NATIVE_ERX_API);
3586         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
3587
3588         status = be_mbox_notify_wait(adapter);
3589         if (!status) {
3590                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
3591
3592                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
3593                                         CAPABILITY_BE3_NATIVE_ERX_API;
3594                 if (!adapter->be3_native)
3595                         dev_warn(&adapter->pdev->dev,
3596                                  "adapter not in advanced mode\n");
3597         }
3598 err:
3599         mutex_unlock(&adapter->mbox_lock);
3600         return status;
3601 }
3602
3603 /* Get privilege(s) for a function */
3604 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
3605                              u32 domain)
3606 {
3607         struct be_mcc_wrb *wrb;
3608         struct be_cmd_req_get_fn_privileges *req;
3609         int status;
3610
3611         mutex_lock(&adapter->mcc_lock);
3612
3613         wrb = wrb_from_mccq(adapter);
3614         if (!wrb) {
3615                 status = -EBUSY;
3616                 goto err;
3617         }
3618
3619         req = embedded_payload(wrb);
3620
3621         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3622                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
3623                                wrb, NULL);
3624
3625         req->hdr.domain = domain;
3626
3627         status = be_mcc_notify_wait(adapter);
3628         if (!status) {
3629                 struct be_cmd_resp_get_fn_privileges *resp =
3630                                                 embedded_payload(wrb);
3631
3632                 *privilege = le32_to_cpu(resp->privilege_mask);
3633
3634                 /* In UMC mode FW does not return right privileges.
3635                  * Override with correct privilege equivalent to PF.
3636                  */
3637                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
3638                     be_physfn(adapter))
3639                         *privilege = MAX_PRIVILEGES;
3640         }
3641
3642 err:
3643         mutex_unlock(&adapter->mcc_lock);
3644         return status;
3645 }
3646
3647 /* Set privilege(s) for a function */
3648 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
3649                              u32 domain)
3650 {
3651         struct be_mcc_wrb *wrb;
3652         struct be_cmd_req_set_fn_privileges *req;
3653         int status;
3654
3655         mutex_lock(&adapter->mcc_lock);
3656
3657         wrb = wrb_from_mccq(adapter);
3658         if (!wrb) {
3659                 status = -EBUSY;
3660                 goto err;
3661         }
3662
3663         req = embedded_payload(wrb);
3664         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3665                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3666                                wrb, NULL);
3667         req->hdr.domain = domain;
3668         if (lancer_chip(adapter))
3669                 req->privileges_lancer = cpu_to_le32(privileges);
3670         else
3671                 req->privileges = cpu_to_le32(privileges);
3672
3673         status = be_mcc_notify_wait(adapter);
3674 err:
3675         mutex_unlock(&adapter->mcc_lock);
3676         return status;
3677 }
3678
3679 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3680  * pmac_id_valid: false => pmac_id or MAC address is requested.
3681  *                If pmac_id is returned, pmac_id_valid is returned as true
3682  */
3683 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3684                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3685                              u8 domain)
3686 {
3687         struct be_mcc_wrb *wrb;
3688         struct be_cmd_req_get_mac_list *req;
3689         int status;
3690         int mac_count;
3691         struct be_dma_mem get_mac_list_cmd;
3692         int i;
3693
3694         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3695         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3696         get_mac_list_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
3697                                                  get_mac_list_cmd.size,
3698                                                  &get_mac_list_cmd.dma,
3699                                                  GFP_ATOMIC);
3700
3701         if (!get_mac_list_cmd.va) {
3702                 dev_err(&adapter->pdev->dev,
3703                         "Memory allocation failure during GET_MAC_LIST\n");
3704                 return -ENOMEM;
3705         }
3706
3707         mutex_lock(&adapter->mcc_lock);
3708
3709         wrb = wrb_from_mccq(adapter);
3710         if (!wrb) {
3711                 status = -EBUSY;
3712                 goto out;
3713         }
3714
3715         req = get_mac_list_cmd.va;
3716
3717         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3718                                OPCODE_COMMON_GET_MAC_LIST,
3719                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3720         req->hdr.domain = domain;
3721         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3722         if (*pmac_id_valid) {
3723                 req->mac_id = cpu_to_le32(*pmac_id);
3724                 req->iface_id = cpu_to_le16(if_handle);
3725                 req->perm_override = 0;
3726         } else {
3727                 req->perm_override = 1;
3728         }
3729
3730         status = be_mcc_notify_wait(adapter);
3731         if (!status) {
3732                 struct be_cmd_resp_get_mac_list *resp =
3733                                                 get_mac_list_cmd.va;
3734
3735                 if (*pmac_id_valid) {
3736                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3737                                ETH_ALEN);
3738                         goto out;
3739                 }
3740
3741                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3742                 /* Mac list returned could contain one or more active mac_ids
3743                  * or one or more true or pseudo permanent mac addresses.
3744                  * If an active mac_id is present, return first active mac_id
3745                  * found.
3746                  */
3747                 for (i = 0; i < mac_count; i++) {
3748                         struct get_list_macaddr *mac_entry;
3749                         u16 mac_addr_size;
3750                         u32 mac_id;
3751
3752                         mac_entry = &resp->macaddr_list[i];
3753                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3754                         /* mac_id is a 32 bit value and mac_addr size
3755                          * is 6 bytes
3756                          */
3757                         if (mac_addr_size == sizeof(u32)) {
3758                                 *pmac_id_valid = true;
3759                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3760                                 *pmac_id = le32_to_cpu(mac_id);
3761                                 goto out;
3762                         }
3763                 }
3764                 /* If no active mac_id found, return first mac addr */
3765                 *pmac_id_valid = false;
3766                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3767                        ETH_ALEN);
3768         }
3769
3770 out:
3771         mutex_unlock(&adapter->mcc_lock);
3772         dma_free_coherent(&adapter->pdev->dev, get_mac_list_cmd.size,
3773                           get_mac_list_cmd.va, get_mac_list_cmd.dma);
3774         return status;
3775 }
3776
3777 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3778                           u8 *mac, u32 if_handle, bool active, u32 domain)
3779 {
3780         if (!active)
3781                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3782                                          if_handle, domain);
3783         if (BEx_chip(adapter))
3784                 return be_cmd_mac_addr_query(adapter, mac, false,
3785                                              if_handle, curr_pmac_id);
3786         else
3787                 /* Fetch the MAC address using pmac_id */
3788                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3789                                                 &curr_pmac_id,
3790                                                 if_handle, domain);
3791 }
3792
3793 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3794 {
3795         int status;
3796         bool pmac_valid = false;
3797
3798         eth_zero_addr(mac);
3799
3800         if (BEx_chip(adapter)) {
3801                 if (be_physfn(adapter))
3802                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3803                                                        0);
3804                 else
3805                         status = be_cmd_mac_addr_query(adapter, mac, false,
3806                                                        adapter->if_handle, 0);
3807         } else {
3808                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3809                                                   NULL, adapter->if_handle, 0);
3810         }
3811
3812         return status;
3813 }
3814
3815 /* Uses synchronous MCCQ */
3816 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3817                         u8 mac_count, u32 domain)
3818 {
3819         struct be_mcc_wrb *wrb;
3820         struct be_cmd_req_set_mac_list *req;
3821         int status;
3822         struct be_dma_mem cmd;
3823
3824         memset(&cmd, 0, sizeof(struct be_dma_mem));
3825         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3826         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
3827                                     GFP_KERNEL);
3828         if (!cmd.va)
3829                 return -ENOMEM;
3830
3831         mutex_lock(&adapter->mcc_lock);
3832
3833         wrb = wrb_from_mccq(adapter);
3834         if (!wrb) {
3835                 status = -EBUSY;
3836                 goto err;
3837         }
3838
3839         req = cmd.va;
3840         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3841                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3842                                wrb, &cmd);
3843
3844         req->hdr.domain = domain;
3845         req->mac_count = mac_count;
3846         if (mac_count)
3847                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3848
3849         status = be_mcc_notify_wait(adapter);
3850
3851 err:
3852         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3853         mutex_unlock(&adapter->mcc_lock);
3854         return status;
3855 }
3856
3857 /* Wrapper to delete any active MACs and provision the new mac.
3858  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3859  * current list are active.
3860  */
3861 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3862 {
3863         bool active_mac = false;
3864         u8 old_mac[ETH_ALEN];
3865         u32 pmac_id;
3866         int status;
3867
3868         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3869                                           &pmac_id, if_id, dom);
3870
3871         if (!status && active_mac)
3872                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3873
3874         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3875 }
3876
3877 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3878                           u32 domain, u16 intf_id, u16 hsw_mode, u8 spoofchk)
3879 {
3880         struct be_mcc_wrb *wrb;
3881         struct be_cmd_req_set_hsw_config *req;
3882         void *ctxt;
3883         int status;
3884
3885         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_HSW_CONFIG,
3886                             CMD_SUBSYSTEM_COMMON))
3887                 return -EPERM;
3888
3889         mutex_lock(&adapter->mcc_lock);
3890
3891         wrb = wrb_from_mccq(adapter);
3892         if (!wrb) {
3893                 status = -EBUSY;
3894                 goto err;
3895         }
3896
3897         req = embedded_payload(wrb);
3898         ctxt = &req->context;
3899
3900         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3901                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3902                                NULL);
3903
3904         req->hdr.domain = domain;
3905         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3906         if (pvid) {
3907                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3908                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3909         }
3910         if (hsw_mode) {
3911                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3912                               ctxt, adapter->hba_port_num);
3913                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3914                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3915                               ctxt, hsw_mode);
3916         }
3917
3918         /* Enable/disable both mac and vlan spoof checking */
3919         if (!BEx_chip(adapter) && spoofchk) {
3920                 AMAP_SET_BITS(struct amap_set_hsw_context, mac_spoofchk,
3921                               ctxt, spoofchk);
3922                 AMAP_SET_BITS(struct amap_set_hsw_context, vlan_spoofchk,
3923                               ctxt, spoofchk);
3924         }
3925
3926         be_dws_cpu_to_le(req->context, sizeof(req->context));
3927         status = be_mcc_notify_wait(adapter);
3928
3929 err:
3930         mutex_unlock(&adapter->mcc_lock);
3931         return status;
3932 }
3933
3934 /* Get Hyper switch config */
3935 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3936                           u32 domain, u16 intf_id, u8 *mode, bool *spoofchk)
3937 {
3938         struct be_mcc_wrb *wrb;
3939         struct be_cmd_req_get_hsw_config *req;
3940         void *ctxt;
3941         int status;
3942         u16 vid;
3943
3944         mutex_lock(&adapter->mcc_lock);
3945
3946         wrb = wrb_from_mccq(adapter);
3947         if (!wrb) {
3948                 status = -EBUSY;
3949                 goto err;
3950         }
3951
3952         req = embedded_payload(wrb);
3953         ctxt = &req->context;
3954
3955         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3956                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3957                                NULL);
3958
3959         req->hdr.domain = domain;
3960         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3961                       ctxt, intf_id);
3962         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3963
3964         if (!BEx_chip(adapter) && mode) {
3965                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3966                               ctxt, adapter->hba_port_num);
3967                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3968         }
3969         be_dws_cpu_to_le(req->context, sizeof(req->context));
3970
3971         status = be_mcc_notify_wait(adapter);
3972         if (!status) {
3973                 struct be_cmd_resp_get_hsw_config *resp =
3974                                                 embedded_payload(wrb);
3975
3976                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3977                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3978                                     pvid, &resp->context);
3979                 if (pvid)
3980                         *pvid = le16_to_cpu(vid);
3981                 if (mode)
3982                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3983                                               port_fwd_type, &resp->context);
3984                 if (spoofchk)
3985                         *spoofchk =
3986                                 AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3987                                               spoofchk, &resp->context);
3988         }
3989
3990 err:
3991         mutex_unlock(&adapter->mcc_lock);
3992         return status;
3993 }
3994
3995 static bool be_is_wol_excluded(struct be_adapter *adapter)
3996 {
3997         struct pci_dev *pdev = adapter->pdev;
3998
3999         if (be_virtfn(adapter))
4000                 return true;
4001
4002         switch (pdev->subsystem_device) {
4003         case OC_SUBSYS_DEVICE_ID1:
4004         case OC_SUBSYS_DEVICE_ID2:
4005         case OC_SUBSYS_DEVICE_ID3:
4006         case OC_SUBSYS_DEVICE_ID4:
4007                 return true;
4008         default:
4009                 return false;
4010         }
4011 }
4012
4013 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
4014 {
4015         struct be_mcc_wrb *wrb;
4016         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
4017         int status = 0;
4018         struct be_dma_mem cmd;
4019
4020         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4021                             CMD_SUBSYSTEM_ETH))
4022                 return -EPERM;
4023
4024         if (be_is_wol_excluded(adapter))
4025                 return status;
4026
4027         if (mutex_lock_interruptible(&adapter->mbox_lock))
4028                 return -1;
4029
4030         memset(&cmd, 0, sizeof(struct be_dma_mem));
4031         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
4032         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4033                                     GFP_ATOMIC);
4034         if (!cmd.va) {
4035                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
4036                 status = -ENOMEM;
4037                 goto err;
4038         }
4039
4040         wrb = wrb_from_mbox(adapter);
4041         if (!wrb) {
4042                 status = -EBUSY;
4043                 goto err;
4044         }
4045
4046         req = cmd.va;
4047
4048         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
4049                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
4050                                sizeof(*req), wrb, &cmd);
4051
4052         req->hdr.version = 1;
4053         req->query_options = BE_GET_WOL_CAP;
4054
4055         status = be_mbox_notify_wait(adapter);
4056         if (!status) {
4057                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
4058
4059                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
4060
4061                 adapter->wol_cap = resp->wol_settings;
4062
4063                 /* Non-zero macaddr indicates WOL is enabled */
4064                 if (adapter->wol_cap & BE_WOL_CAP &&
4065                     !is_zero_ether_addr(resp->magic_mac))
4066                         adapter->wol_en = true;
4067         }
4068 err:
4069         mutex_unlock(&adapter->mbox_lock);
4070         if (cmd.va)
4071                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4072                                   cmd.dma);
4073         return status;
4074
4075 }
4076
4077 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
4078 {
4079         struct be_dma_mem extfat_cmd;
4080         struct be_fat_conf_params *cfgs;
4081         int status;
4082         int i, j;
4083
4084         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4085         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4086         extfat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
4087                                            extfat_cmd.size, &extfat_cmd.dma,
4088                                            GFP_ATOMIC);
4089         if (!extfat_cmd.va)
4090                 return -ENOMEM;
4091
4092         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4093         if (status)
4094                 goto err;
4095
4096         cfgs = (struct be_fat_conf_params *)
4097                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
4098         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
4099                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
4100
4101                 for (j = 0; j < num_modes; j++) {
4102                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
4103                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
4104                                                         cpu_to_le32(level);
4105                 }
4106         }
4107
4108         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
4109 err:
4110         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4111                           extfat_cmd.dma);
4112         return status;
4113 }
4114
4115 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
4116 {
4117         struct be_dma_mem extfat_cmd;
4118         struct be_fat_conf_params *cfgs;
4119         int status, j;
4120         int level = 0;
4121
4122         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
4123         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
4124         extfat_cmd.va = dma_alloc_coherent(&adapter->pdev->dev,
4125                                            extfat_cmd.size, &extfat_cmd.dma,
4126                                            GFP_ATOMIC);
4127
4128         if (!extfat_cmd.va) {
4129                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
4130                         __func__);
4131                 goto err;
4132         }
4133
4134         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
4135         if (!status) {
4136                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
4137                                                 sizeof(struct be_cmd_resp_hdr));
4138
4139                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
4140                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
4141                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
4142                 }
4143         }
4144         dma_free_coherent(&adapter->pdev->dev, extfat_cmd.size, extfat_cmd.va,
4145                           extfat_cmd.dma);
4146 err:
4147         return level;
4148 }
4149
4150 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
4151                                    struct be_dma_mem *cmd)
4152 {
4153         struct be_mcc_wrb *wrb;
4154         struct be_cmd_req_get_ext_fat_caps *req;
4155         int status;
4156
4157         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4158                             CMD_SUBSYSTEM_COMMON))
4159                 return -EPERM;
4160
4161         if (mutex_lock_interruptible(&adapter->mbox_lock))
4162                 return -1;
4163
4164         wrb = wrb_from_mbox(adapter);
4165         if (!wrb) {
4166                 status = -EBUSY;
4167                 goto err;
4168         }
4169
4170         req = cmd->va;
4171         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4172                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITIES,
4173                                cmd->size, wrb, cmd);
4174         req->parameter_type = cpu_to_le32(1);
4175
4176         status = be_mbox_notify_wait(adapter);
4177 err:
4178         mutex_unlock(&adapter->mbox_lock);
4179         return status;
4180 }
4181
4182 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
4183                                    struct be_dma_mem *cmd,
4184                                    struct be_fat_conf_params *configs)
4185 {
4186         struct be_mcc_wrb *wrb;
4187         struct be_cmd_req_set_ext_fat_caps *req;
4188         int status;
4189
4190         mutex_lock(&adapter->mcc_lock);
4191
4192         wrb = wrb_from_mccq(adapter);
4193         if (!wrb) {
4194                 status = -EBUSY;
4195                 goto err;
4196         }
4197
4198         req = cmd->va;
4199         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
4200         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4201                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITIES,
4202                                cmd->size, wrb, cmd);
4203
4204         status = be_mcc_notify_wait(adapter);
4205 err:
4206         mutex_unlock(&adapter->mcc_lock);
4207         return status;
4208 }
4209
4210 int be_cmd_query_port_name(struct be_adapter *adapter)
4211 {
4212         struct be_cmd_req_get_port_name *req;
4213         struct be_mcc_wrb *wrb;
4214         int status;
4215
4216         if (mutex_lock_interruptible(&adapter->mbox_lock))
4217                 return -1;
4218
4219         wrb = wrb_from_mbox(adapter);
4220         req = embedded_payload(wrb);
4221
4222         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4223                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
4224                                NULL);
4225         if (!BEx_chip(adapter))
4226                 req->hdr.version = 1;
4227
4228         status = be_mbox_notify_wait(adapter);
4229         if (!status) {
4230                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
4231
4232                 adapter->port_name = resp->port_name[adapter->hba_port_num];
4233         } else {
4234                 adapter->port_name = adapter->hba_port_num + '0';
4235         }
4236
4237         mutex_unlock(&adapter->mbox_lock);
4238         return status;
4239 }
4240
4241 /* When more than 1 NIC descriptor is present in the descriptor list,
4242  * the caller must specify the pf_num to obtain the NIC descriptor
4243  * corresponding to its pci function.
4244  * get_vft must be true when the caller wants the VF-template desc of the
4245  * PF-pool.
4246  * The pf_num should be set to PF_NUM_IGNORE when the caller knows
4247  * that only it's NIC descriptor is present in the descriptor list.
4248  */
4249 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
4250                                                bool get_vft, u8 pf_num)
4251 {
4252         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4253         struct be_nic_res_desc *nic;
4254         int i;
4255
4256         for (i = 0; i < desc_count; i++) {
4257                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
4258                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
4259                         nic = (struct be_nic_res_desc *)hdr;
4260
4261                         if ((pf_num == PF_NUM_IGNORE ||
4262                              nic->pf_num == pf_num) &&
4263                             (!get_vft || nic->flags & BIT(VFT_SHIFT)))
4264                                 return nic;
4265                 }
4266                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4267                 hdr = (void *)hdr + hdr->desc_len;
4268         }
4269         return NULL;
4270 }
4271
4272 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count,
4273                                                u8 pf_num)
4274 {
4275         return be_get_nic_desc(buf, desc_count, true, pf_num);
4276 }
4277
4278 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count,
4279                                                     u8 pf_num)
4280 {
4281         return be_get_nic_desc(buf, desc_count, false, pf_num);
4282 }
4283
4284 static struct be_pcie_res_desc *be_get_pcie_desc(u8 *buf, u32 desc_count,
4285                                                  u8 pf_num)
4286 {
4287         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4288         struct be_pcie_res_desc *pcie;
4289         int i;
4290
4291         for (i = 0; i < desc_count; i++) {
4292                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4293                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4294                         pcie = (struct be_pcie_res_desc *)hdr;
4295                         if (pcie->pf_num == pf_num)
4296                                 return pcie;
4297                 }
4298
4299                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4300                 hdr = (void *)hdr + hdr->desc_len;
4301         }
4302         return NULL;
4303 }
4304
4305 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
4306 {
4307         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4308         int i;
4309
4310         for (i = 0; i < desc_count; i++) {
4311                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
4312                         return (struct be_port_res_desc *)hdr;
4313
4314                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4315                 hdr = (void *)hdr + hdr->desc_len;
4316         }
4317         return NULL;
4318 }
4319
4320 static void be_copy_nic_desc(struct be_resources *res,
4321                              struct be_nic_res_desc *desc)
4322 {
4323         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
4324         res->max_vlans = le16_to_cpu(desc->vlan_count);
4325         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
4326         res->max_tx_qs = le16_to_cpu(desc->txq_count);
4327         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
4328         res->max_rx_qs = le16_to_cpu(desc->rq_count);
4329         res->max_evt_qs = le16_to_cpu(desc->eq_count);
4330         res->max_cq_count = le16_to_cpu(desc->cq_count);
4331         res->max_iface_count = le16_to_cpu(desc->iface_count);
4332         res->max_mcc_count = le16_to_cpu(desc->mcc_count);
4333         /* Clear flags that driver is not interested in */
4334         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
4335                                 BE_IF_CAP_FLAGS_WANT;
4336 }
4337
4338 /* Uses Mbox */
4339 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
4340 {
4341         struct be_mcc_wrb *wrb;
4342         struct be_cmd_req_get_func_config *req;
4343         int status;
4344         struct be_dma_mem cmd;
4345
4346         if (mutex_lock_interruptible(&adapter->mbox_lock))
4347                 return -1;
4348
4349         memset(&cmd, 0, sizeof(struct be_dma_mem));
4350         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
4351         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4352                                     GFP_ATOMIC);
4353         if (!cmd.va) {
4354                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
4355                 status = -ENOMEM;
4356                 goto err;
4357         }
4358
4359         wrb = wrb_from_mbox(adapter);
4360         if (!wrb) {
4361                 status = -EBUSY;
4362                 goto err;
4363         }
4364
4365         req = cmd.va;
4366
4367         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4368                                OPCODE_COMMON_GET_FUNC_CONFIG,
4369                                cmd.size, wrb, &cmd);
4370
4371         if (skyhawk_chip(adapter))
4372                 req->hdr.version = 1;
4373
4374         status = be_mbox_notify_wait(adapter);
4375         if (!status) {
4376                 struct be_cmd_resp_get_func_config *resp = cmd.va;
4377                 u32 desc_count = le32_to_cpu(resp->desc_count);
4378                 struct be_nic_res_desc *desc;
4379
4380                 /* GET_FUNC_CONFIG returns resource descriptors of the
4381                  * current function only. So, pf_num should be set to
4382                  * PF_NUM_IGNORE.
4383                  */
4384                 desc = be_get_func_nic_desc(resp->func_param, desc_count,
4385                                             PF_NUM_IGNORE);
4386                 if (!desc) {
4387                         status = -EINVAL;
4388                         goto err;
4389                 }
4390
4391                 /* Store pf_num & vf_num for later use in GET_PROFILE_CONFIG */
4392                 adapter->pf_num = desc->pf_num;
4393                 adapter->vf_num = desc->vf_num;
4394
4395                 if (res)
4396                         be_copy_nic_desc(res, desc);
4397         }
4398 err:
4399         mutex_unlock(&adapter->mbox_lock);
4400         if (cmd.va)
4401                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4402                                   cmd.dma);
4403         return status;
4404 }
4405
4406 /* This routine returns a list of all the NIC PF_nums in the adapter */
4407 static u16 be_get_nic_pf_num_list(u8 *buf, u32 desc_count, u16 *nic_pf_nums)
4408 {
4409         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
4410         struct be_pcie_res_desc *pcie = NULL;
4411         int i;
4412         u16 nic_pf_count = 0;
4413
4414         for (i = 0; i < desc_count; i++) {
4415                 if (hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
4416                     hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1) {
4417                         pcie = (struct be_pcie_res_desc *)hdr;
4418                         if (pcie->pf_state && (pcie->pf_type == MISSION_NIC ||
4419                                                pcie->pf_type == MISSION_RDMA)) {
4420                                 nic_pf_nums[nic_pf_count++] = pcie->pf_num;
4421                         }
4422                 }
4423
4424                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
4425                 hdr = (void *)hdr + hdr->desc_len;
4426         }
4427         return nic_pf_count;
4428 }
4429
4430 /* Will use MBOX only if MCCQ has not been created */
4431 int be_cmd_get_profile_config(struct be_adapter *adapter,
4432                               struct be_resources *res,
4433                               struct be_port_resources *port_res,
4434                               u8 profile_type, u8 query, u8 domain)
4435 {
4436         struct be_cmd_resp_get_profile_config *resp;
4437         struct be_cmd_req_get_profile_config *req;
4438         struct be_nic_res_desc *vf_res;
4439         struct be_pcie_res_desc *pcie;
4440         struct be_port_res_desc *port;
4441         struct be_nic_res_desc *nic;
4442         struct be_mcc_wrb wrb = {0};
4443         struct be_dma_mem cmd;
4444         u16 desc_count;
4445         int status;
4446
4447         memset(&cmd, 0, sizeof(struct be_dma_mem));
4448         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
4449         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4450                                     GFP_ATOMIC);
4451         if (!cmd.va)
4452                 return -ENOMEM;
4453
4454         req = cmd.va;
4455         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4456                                OPCODE_COMMON_GET_PROFILE_CONFIG,
4457                                cmd.size, &wrb, &cmd);
4458
4459         if (!lancer_chip(adapter))
4460                 req->hdr.version = 1;
4461         req->type = profile_type;
4462         req->hdr.domain = domain;
4463
4464         /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
4465          * descriptors with all bits set to "1" for the fields which can be
4466          * modified using SET_PROFILE_CONFIG cmd.
4467          */
4468         if (query == RESOURCE_MODIFIABLE)
4469                 req->type |= QUERY_MODIFIABLE_FIELDS_TYPE;
4470
4471         status = be_cmd_notify_wait(adapter, &wrb);
4472         if (status)
4473                 goto err;
4474
4475         resp = cmd.va;
4476         desc_count = le16_to_cpu(resp->desc_count);
4477
4478         if (port_res) {
4479                 u16 nic_pf_cnt = 0, i;
4480                 u16 nic_pf_num_list[MAX_NIC_FUNCS];
4481
4482                 nic_pf_cnt = be_get_nic_pf_num_list(resp->func_param,
4483                                                     desc_count,
4484                                                     nic_pf_num_list);
4485
4486                 for (i = 0; i < nic_pf_cnt; i++) {
4487                         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4488                                                    nic_pf_num_list[i]);
4489                         if (nic->link_param == adapter->port_num) {
4490                                 port_res->nic_pfs++;
4491                                 pcie = be_get_pcie_desc(resp->func_param,
4492                                                         desc_count,
4493                                                         nic_pf_num_list[i]);
4494                                 port_res->max_vfs += le16_to_cpu(pcie->num_vfs);
4495                         }
4496                 }
4497                 goto err;
4498         }
4499
4500         pcie = be_get_pcie_desc(resp->func_param, desc_count,
4501                                 adapter->pf_num);
4502         if (pcie)
4503                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
4504
4505         port = be_get_port_desc(resp->func_param, desc_count);
4506         if (port)
4507                 adapter->mc_type = port->mc_type;
4508
4509         nic = be_get_func_nic_desc(resp->func_param, desc_count,
4510                                    adapter->pf_num);
4511         if (nic)
4512                 be_copy_nic_desc(res, nic);
4513
4514         vf_res = be_get_vft_desc(resp->func_param, desc_count,
4515                                  adapter->pf_num);
4516         if (vf_res)
4517                 res->vf_if_cap_flags = vf_res->cap_flags;
4518 err:
4519         if (cmd.va)
4520                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4521                                   cmd.dma);
4522         return status;
4523 }
4524
4525 /* Will use MBOX only if MCCQ has not been created */
4526 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
4527                                      int size, int count, u8 version, u8 domain)
4528 {
4529         struct be_cmd_req_set_profile_config *req;
4530         struct be_mcc_wrb wrb = {0};
4531         struct be_dma_mem cmd;
4532         int status;
4533
4534         memset(&cmd, 0, sizeof(struct be_dma_mem));
4535         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
4536         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size, &cmd.dma,
4537                                     GFP_ATOMIC);
4538         if (!cmd.va)
4539                 return -ENOMEM;
4540
4541         req = cmd.va;
4542         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4543                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
4544                                &wrb, &cmd);
4545         req->hdr.version = version;
4546         req->hdr.domain = domain;
4547         req->desc_count = cpu_to_le32(count);
4548         memcpy(req->desc, desc, size);
4549
4550         status = be_cmd_notify_wait(adapter, &wrb);
4551
4552         if (cmd.va)
4553                 dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va,
4554                                   cmd.dma);
4555         return status;
4556 }
4557
4558 /* Mark all fields invalid */
4559 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
4560 {
4561         memset(nic, 0, sizeof(*nic));
4562         nic->unicast_mac_count = 0xFFFF;
4563         nic->mcc_count = 0xFFFF;
4564         nic->vlan_count = 0xFFFF;
4565         nic->mcast_mac_count = 0xFFFF;
4566         nic->txq_count = 0xFFFF;
4567         nic->rq_count = 0xFFFF;
4568         nic->rssq_count = 0xFFFF;
4569         nic->lro_count = 0xFFFF;
4570         nic->cq_count = 0xFFFF;
4571         nic->toe_conn_count = 0xFFFF;
4572         nic->eq_count = 0xFFFF;
4573         nic->iface_count = 0xFFFF;
4574         nic->link_param = 0xFF;
4575         nic->channel_id_param = cpu_to_le16(0xF000);
4576         nic->acpi_params = 0xFF;
4577         nic->wol_param = 0x0F;
4578         nic->tunnel_iface_count = 0xFFFF;
4579         nic->direct_tenant_iface_count = 0xFFFF;
4580         nic->bw_min = 0xFFFFFFFF;
4581         nic->bw_max = 0xFFFFFFFF;
4582 }
4583
4584 /* Mark all fields invalid */
4585 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
4586 {
4587         memset(pcie, 0, sizeof(*pcie));
4588         pcie->sriov_state = 0xFF;
4589         pcie->pf_state = 0xFF;
4590         pcie->pf_type = 0xFF;
4591         pcie->num_vfs = 0xFFFF;
4592 }
4593
4594 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
4595                       u8 domain)
4596 {
4597         struct be_nic_res_desc nic_desc;
4598         u32 bw_percent;
4599         u16 version = 0;
4600
4601         if (BE3_chip(adapter))
4602                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
4603
4604         be_reset_nic_desc(&nic_desc);
4605         nic_desc.pf_num = adapter->pf_num;
4606         nic_desc.vf_num = domain;
4607         nic_desc.bw_min = 0;
4608         if (lancer_chip(adapter)) {
4609                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
4610                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
4611                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
4612                                         (1 << NOSV_SHIFT);
4613                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
4614         } else {
4615                 version = 1;
4616                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4617                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4618                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4619                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
4620                 nic_desc.bw_max = cpu_to_le32(bw_percent);
4621         }
4622
4623         return be_cmd_set_profile_config(adapter, &nic_desc,
4624                                          nic_desc.hdr.desc_len,
4625                                          1, version, domain);
4626 }
4627
4628 int be_cmd_set_sriov_config(struct be_adapter *adapter,
4629                             struct be_resources pool_res, u16 num_vfs,
4630                             struct be_resources *vft_res)
4631 {
4632         struct {
4633                 struct be_pcie_res_desc pcie;
4634                 struct be_nic_res_desc nic_vft;
4635         } __packed desc;
4636
4637         /* PF PCIE descriptor */
4638         be_reset_pcie_desc(&desc.pcie);
4639         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
4640         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4641         desc.pcie.flags = BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4642         desc.pcie.pf_num = adapter->pdev->devfn;
4643         desc.pcie.sriov_state = num_vfs ? 1 : 0;
4644         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
4645
4646         /* VF NIC Template descriptor */
4647         be_reset_nic_desc(&desc.nic_vft);
4648         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
4649         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4650         desc.nic_vft.flags = vft_res->flags | BIT(VFT_SHIFT) |
4651                              BIT(IMM_SHIFT) | BIT(NOSV_SHIFT);
4652         desc.nic_vft.pf_num = adapter->pdev->devfn;
4653         desc.nic_vft.vf_num = 0;
4654         desc.nic_vft.cap_flags = cpu_to_le32(vft_res->vf_if_cap_flags);
4655         desc.nic_vft.rq_count = cpu_to_le16(vft_res->max_rx_qs);
4656         desc.nic_vft.txq_count = cpu_to_le16(vft_res->max_tx_qs);
4657         desc.nic_vft.rssq_count = cpu_to_le16(vft_res->max_rss_qs);
4658         desc.nic_vft.cq_count = cpu_to_le16(vft_res->max_cq_count);
4659
4660         if (vft_res->max_uc_mac)
4661                 desc.nic_vft.unicast_mac_count =
4662                                         cpu_to_le16(vft_res->max_uc_mac);
4663         if (vft_res->max_vlans)
4664                 desc.nic_vft.vlan_count = cpu_to_le16(vft_res->max_vlans);
4665         if (vft_res->max_iface_count)
4666                 desc.nic_vft.iface_count =
4667                                 cpu_to_le16(vft_res->max_iface_count);
4668         if (vft_res->max_mcc_count)
4669                 desc.nic_vft.mcc_count = cpu_to_le16(vft_res->max_mcc_count);
4670
4671         return be_cmd_set_profile_config(adapter, &desc,
4672                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
4673 }
4674
4675 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
4676 {
4677         struct be_mcc_wrb *wrb;
4678         struct be_cmd_req_manage_iface_filters *req;
4679         int status;
4680
4681         if (iface == 0xFFFFFFFF)
4682                 return -1;
4683
4684         mutex_lock(&adapter->mcc_lock);
4685
4686         wrb = wrb_from_mccq(adapter);
4687         if (!wrb) {
4688                 status = -EBUSY;
4689                 goto err;
4690         }
4691         req = embedded_payload(wrb);
4692
4693         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4694                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
4695                                wrb, NULL);
4696         req->op = op;
4697         req->target_iface_id = cpu_to_le32(iface);
4698
4699         status = be_mcc_notify_wait(adapter);
4700 err:
4701         mutex_unlock(&adapter->mcc_lock);
4702         return status;
4703 }
4704
4705 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
4706 {
4707         struct be_port_res_desc port_desc;
4708
4709         memset(&port_desc, 0, sizeof(port_desc));
4710         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
4711         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
4712         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
4713         port_desc.link_num = adapter->hba_port_num;
4714         if (port) {
4715                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
4716                                         (1 << RCVID_SHIFT);
4717                 port_desc.nv_port = swab16(port);
4718         } else {
4719                 port_desc.nv_flags = NV_TYPE_DISABLED;
4720                 port_desc.nv_port = 0;
4721         }
4722
4723         return be_cmd_set_profile_config(adapter, &port_desc,
4724                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
4725 }
4726
4727 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
4728                      int vf_num)
4729 {
4730         struct be_mcc_wrb *wrb;
4731         struct be_cmd_req_get_iface_list *req;
4732         struct be_cmd_resp_get_iface_list *resp;
4733         int status;
4734
4735         mutex_lock(&adapter->mcc_lock);
4736
4737         wrb = wrb_from_mccq(adapter);
4738         if (!wrb) {
4739                 status = -EBUSY;
4740                 goto err;
4741         }
4742         req = embedded_payload(wrb);
4743
4744         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4745                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
4746                                wrb, NULL);
4747         req->hdr.domain = vf_num + 1;
4748
4749         status = be_mcc_notify_wait(adapter);
4750         if (!status) {
4751                 resp = (struct be_cmd_resp_get_iface_list *)req;
4752                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
4753         }
4754
4755 err:
4756         mutex_unlock(&adapter->mcc_lock);
4757         return status;
4758 }
4759
4760 static int lancer_wait_idle(struct be_adapter *adapter)
4761 {
4762 #define SLIPORT_IDLE_TIMEOUT 30
4763         u32 reg_val;
4764         int status = 0, i;
4765
4766         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4767                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4768                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4769                         break;
4770
4771                 ssleep(1);
4772         }
4773
4774         if (i == SLIPORT_IDLE_TIMEOUT)
4775                 status = -1;
4776
4777         return status;
4778 }
4779
4780 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4781 {
4782         int status = 0;
4783
4784         status = lancer_wait_idle(adapter);
4785         if (status)
4786                 return status;
4787
4788         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4789
4790         return status;
4791 }
4792
4793 /* Routine to check whether dump image is present or not */
4794 bool dump_present(struct be_adapter *adapter)
4795 {
4796         u32 sliport_status = 0;
4797
4798         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4799         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4800 }
4801
4802 int lancer_initiate_dump(struct be_adapter *adapter)
4803 {
4804         struct device *dev = &adapter->pdev->dev;
4805         int status;
4806
4807         if (dump_present(adapter)) {
4808                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4809                 return -EEXIST;
4810         }
4811
4812         /* give firmware reset and diagnostic dump */
4813         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4814                                      PHYSDEV_CONTROL_DD_MASK);
4815         if (status < 0) {
4816                 dev_err(dev, "FW reset failed\n");
4817                 return status;
4818         }
4819
4820         status = lancer_wait_idle(adapter);
4821         if (status)
4822                 return status;
4823
4824         if (!dump_present(adapter)) {
4825                 dev_err(dev, "FW dump not generated\n");
4826                 return -EIO;
4827         }
4828
4829         return 0;
4830 }
4831
4832 int lancer_delete_dump(struct be_adapter *adapter)
4833 {
4834         int status;
4835
4836         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4837         return be_cmd_status(status);
4838 }
4839
4840 /* Uses sync mcc */
4841 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4842 {
4843         struct be_mcc_wrb *wrb;
4844         struct be_cmd_enable_disable_vf *req;
4845         int status;
4846
4847         if (BEx_chip(adapter))
4848                 return 0;
4849
4850         mutex_lock(&adapter->mcc_lock);
4851
4852         wrb = wrb_from_mccq(adapter);
4853         if (!wrb) {
4854                 status = -EBUSY;
4855                 goto err;
4856         }
4857
4858         req = embedded_payload(wrb);
4859
4860         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4861                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4862                                wrb, NULL);
4863
4864         req->hdr.domain = domain;
4865         req->enable = 1;
4866         status = be_mcc_notify_wait(adapter);
4867 err:
4868         mutex_unlock(&adapter->mcc_lock);
4869         return status;
4870 }
4871
4872 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4873 {
4874         struct be_mcc_wrb *wrb;
4875         struct be_cmd_req_intr_set *req;
4876         int status;
4877
4878         if (mutex_lock_interruptible(&adapter->mbox_lock))
4879                 return -1;
4880
4881         wrb = wrb_from_mbox(adapter);
4882
4883         req = embedded_payload(wrb);
4884
4885         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4886                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4887                                wrb, NULL);
4888
4889         req->intr_enabled = intr_enable;
4890
4891         status = be_mbox_notify_wait(adapter);
4892
4893         mutex_unlock(&adapter->mbox_lock);
4894         return status;
4895 }
4896
4897 /* Uses MBOX */
4898 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4899 {
4900         struct be_cmd_req_get_active_profile *req;
4901         struct be_mcc_wrb *wrb;
4902         int status;
4903
4904         if (mutex_lock_interruptible(&adapter->mbox_lock))
4905                 return -1;
4906
4907         wrb = wrb_from_mbox(adapter);
4908         if (!wrb) {
4909                 status = -EBUSY;
4910                 goto err;
4911         }
4912
4913         req = embedded_payload(wrb);
4914
4915         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4916                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4917                                wrb, NULL);
4918
4919         status = be_mbox_notify_wait(adapter);
4920         if (!status) {
4921                 struct be_cmd_resp_get_active_profile *resp =
4922                                                         embedded_payload(wrb);
4923
4924                 *profile_id = le16_to_cpu(resp->active_profile_id);
4925         }
4926
4927 err:
4928         mutex_unlock(&adapter->mbox_lock);
4929         return status;
4930 }
4931
4932 static int
4933 __be_cmd_set_logical_link_config(struct be_adapter *adapter,
4934                                  int link_state, int version, u8 domain)
4935 {
4936         struct be_cmd_req_set_ll_link *req;
4937         struct be_mcc_wrb *wrb;
4938         u32 link_config = 0;
4939         int status;
4940
4941         mutex_lock(&adapter->mcc_lock);
4942
4943         wrb = wrb_from_mccq(adapter);
4944         if (!wrb) {
4945                 status = -EBUSY;
4946                 goto err;
4947         }
4948
4949         req = embedded_payload(wrb);
4950
4951         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4952                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4953                                sizeof(*req), wrb, NULL);
4954
4955         req->hdr.version = version;
4956         req->hdr.domain = domain;
4957
4958         if (link_state == IFLA_VF_LINK_STATE_ENABLE ||
4959             link_state == IFLA_VF_LINK_STATE_AUTO)
4960                 link_config |= PLINK_ENABLE;
4961
4962         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4963                 link_config |= PLINK_TRACK;
4964
4965         req->link_config = cpu_to_le32(link_config);
4966
4967         status = be_mcc_notify_wait(adapter);
4968 err:
4969         mutex_unlock(&adapter->mcc_lock);
4970         return status;
4971 }
4972
4973 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4974                                    int link_state, u8 domain)
4975 {
4976         int status;
4977
4978         if (BE2_chip(adapter))
4979                 return -EOPNOTSUPP;
4980
4981         status = __be_cmd_set_logical_link_config(adapter, link_state,
4982                                                   2, domain);
4983
4984         /* Version 2 of the command will not be recognized by older FW.
4985          * On such a failure issue version 1 of the command.
4986          */
4987         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST)
4988                 status = __be_cmd_set_logical_link_config(adapter, link_state,
4989                                                           1, domain);
4990         return status;
4991 }
4992
4993 int be_cmd_set_features(struct be_adapter *adapter)
4994 {
4995         struct be_cmd_resp_set_features *resp;
4996         struct be_cmd_req_set_features *req;
4997         struct be_mcc_wrb *wrb;
4998         int status;
4999
5000         if (mutex_lock_interruptible(&adapter->mcc_lock))
5001                 return -1;
5002
5003         wrb = wrb_from_mccq(adapter);
5004         if (!wrb) {
5005                 status = -EBUSY;
5006                 goto err;
5007         }
5008
5009         req = embedded_payload(wrb);
5010
5011         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
5012                                OPCODE_COMMON_SET_FEATURES,
5013                                sizeof(*req), wrb, NULL);
5014
5015         req->features = cpu_to_le32(BE_FEATURE_UE_RECOVERY);
5016         req->parameter_len = cpu_to_le32(sizeof(struct be_req_ue_recovery));
5017         req->parameter.req.uer = cpu_to_le32(BE_UE_RECOVERY_UER_MASK);
5018
5019         status = be_mcc_notify_wait(adapter);
5020         if (status)
5021                 goto err;
5022
5023         resp = embedded_payload(wrb);
5024
5025         adapter->error_recovery.ue_to_poll_time =
5026                 le16_to_cpu(resp->parameter.resp.ue2rp);
5027         adapter->error_recovery.ue_to_reset_time =
5028                 le16_to_cpu(resp->parameter.resp.ue2sr);
5029         adapter->error_recovery.recovery_supported = true;
5030 err:
5031         /* Checking "MCC_STATUS_INVALID_LENGTH" for SKH as FW
5032          * returns this error in older firmware versions
5033          */
5034         if (base_status(status) == MCC_STATUS_ILLEGAL_REQUEST ||
5035             base_status(status) == MCC_STATUS_INVALID_LENGTH)
5036                 dev_info(&adapter->pdev->dev,
5037                          "Adapter does not support HW error recovery\n");
5038
5039         mutex_unlock(&adapter->mcc_lock);
5040         return status;
5041 }
5042
5043 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
5044                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
5045 {
5046         struct be_adapter *adapter = netdev_priv(netdev_handle);
5047         struct be_mcc_wrb *wrb;
5048         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
5049         struct be_cmd_req_hdr *req;
5050         struct be_cmd_resp_hdr *resp;
5051         int status;
5052
5053         mutex_lock(&adapter->mcc_lock);
5054
5055         wrb = wrb_from_mccq(adapter);
5056         if (!wrb) {
5057                 status = -EBUSY;
5058                 goto err;
5059         }
5060         req = embedded_payload(wrb);
5061         resp = embedded_payload(wrb);
5062
5063         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
5064                                hdr->opcode, wrb_payload_size, wrb, NULL);
5065         memcpy(req, wrb_payload, wrb_payload_size);
5066         be_dws_cpu_to_le(req, wrb_payload_size);
5067
5068         status = be_mcc_notify_wait(adapter);
5069         if (cmd_status)
5070                 *cmd_status = (status & 0xffff);
5071         if (ext_status)
5072                 *ext_status = 0;
5073         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
5074         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
5075 err:
5076         mutex_unlock(&adapter->mcc_lock);
5077         return status;
5078 }
5079 EXPORT_SYMBOL(be_roce_mcc_cmd);