drivers/mmc/host/jz4740_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Copyright (C) 2009-2010, Lars-Peter Clausen <[email protected]>
   4  *  Copyright (C) 2013, Imagination Technologies
   5  *
   6  *  JZ4740 SD/MMC controller driver
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/err.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/irq.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/mmc/slot-gpio.h>
  20 #include <linux/module.h>
  21 #include <linux/of_device.h>
  22 #include <linux/pinctrl/consumer.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/scatterlist.h>
  25
  26 #include <asm/cacheflush.h>
  27
  28 #define JZ_REG_MMC_STRPCL       0x00
  29 #define JZ_REG_MMC_STATUS       0x04
  30 #define JZ_REG_MMC_CLKRT        0x08
  31 #define JZ_REG_MMC_CMDAT        0x0C
  32 #define JZ_REG_MMC_RESTO        0x10
  33 #define JZ_REG_MMC_RDTO         0x14
  34 #define JZ_REG_MMC_BLKLEN       0x18
  35 #define JZ_REG_MMC_NOB          0x1C
  36 #define JZ_REG_MMC_SNOB         0x20
  37 #define JZ_REG_MMC_IMASK        0x24
  38 #define JZ_REG_MMC_IREG         0x28
  39 #define JZ_REG_MMC_CMD          0x2C
  40 #define JZ_REG_MMC_ARG          0x30
  41 #define JZ_REG_MMC_RESP_FIFO    0x34
  42 #define JZ_REG_MMC_RXFIFO       0x38
  43 #define JZ_REG_MMC_TXFIFO       0x3C
  44 #define JZ_REG_MMC_LPM          0x40
  45 #define JZ_REG_MMC_DMAC         0x44
  46
  47 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
  48 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
  49 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
  50 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
  51 #define JZ_MMC_STRPCL_RESET BIT(3)
  52 #define JZ_MMC_STRPCL_START_OP BIT(2)
  53 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
  54 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
  55 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
  56
  57
  58 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
  59 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
  60 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
  61 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
  62 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
  63 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
  64 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
  65 #define JZ_MMC_STATUS_CLK_EN BIT(8)
  66 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
  67 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
  68 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
  69 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
  70 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
  71 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
  72 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
  73 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
  74
  75 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
  76 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
  77
  78
  79 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
  80 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
  81 #define JZ_MMC_CMDAT_BUS_WIDTH_8BIT (BIT(10) | BIT(9))
  82 #define JZ_MMC_CMDAT_BUS_WIDTH_MASK (BIT(10) | BIT(9))
  83 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
  84 #define JZ_MMC_CMDAT_INIT BIT(7)
  85 #define JZ_MMC_CMDAT_BUSY BIT(6)
  86 #define JZ_MMC_CMDAT_STREAM BIT(5)
  87 #define JZ_MMC_CMDAT_WRITE BIT(4)
  88 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
  89 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
  90 #define JZ_MMC_CMDAT_RSP_R1 1
  91 #define JZ_MMC_CMDAT_RSP_R2 2
  92 #define JZ_MMC_CMDAT_RSP_R3 3
  93
  94 #define JZ_MMC_IRQ_SDIO BIT(7)
  95 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
  96 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
  97 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
  98 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
  99 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
 100
 101 #define JZ_MMC_DMAC_DMA_SEL BIT(1)
 102 #define JZ_MMC_DMAC_DMA_EN BIT(0)
 103
 104 #define JZ_MMC_LPM_DRV_RISING BIT(31)
 105 #define JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY BIT(31)
 106 #define JZ_MMC_LPM_DRV_RISING_1NS_DLY BIT(30)
 107 #define JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY BIT(29)
 108 #define JZ_MMC_LPM_LOW_POWER_MODE_EN BIT(0)
 109
 110 #define JZ_MMC_CLK_RATE 24000000
 111
 112 enum jz4740_mmc_version {
 113         JZ_MMC_JZ4740,
 114         JZ_MMC_JZ4725B,
 115         JZ_MMC_JZ4760,
 116         JZ_MMC_JZ4780,
 117         JZ_MMC_X1000,
 118 };
 119
 120 enum jz4740_mmc_state {
 121         JZ4740_MMC_STATE_READ_RESPONSE,
 122         JZ4740_MMC_STATE_TRANSFER_DATA,
 123         JZ4740_MMC_STATE_SEND_STOP,
 124         JZ4740_MMC_STATE_DONE,
 125 };
 126
 127 /*
 128  * The MMC core allows to prepare a mmc_request while another mmc_request
 129  * is in-flight. This is used via the pre_req/post_req hooks.
 130  * This driver uses the pre_req/post_req hooks to map/unmap the mmc_request.
 131  * Following what other drivers do (sdhci, dw_mmc) we use the following cookie
 132  * flags to keep track of the mmc_request mapping state.
 133  *
 134  * COOKIE_UNMAPPED: the request is not mapped.
 135  * COOKIE_PREMAPPED: the request was mapped in pre_req,
 136  * and should be unmapped in post_req.
 137  * COOKIE_MAPPED: the request was mapped in the irq handler,
 138  * and should be unmapped before mmc_request_done is called..
 139  */
 140 enum jz4780_cookie {
 141         COOKIE_UNMAPPED = 0,
 142         COOKIE_PREMAPPED,
 143         COOKIE_MAPPED,
 144 };
 145
 146 struct jz4740_mmc_host {
 147         struct mmc_host *mmc;
 148         struct platform_device *pdev;
 149         struct clk *clk;
 150
 151         enum jz4740_mmc_version version;
 152
 153         int irq;
 154         int card_detect_irq;
 155
 156         void __iomem *base;
 157         struct resource *mem_res;
 158         struct mmc_request *req;
 159         struct mmc_command *cmd;
 160
 161         unsigned long waiting;
 162
 163         uint32_t cmdat;
 164
 165         uint32_t irq_mask;
 166
 167         spinlock_t lock;
 168
 169         struct timer_list timeout_timer;
 170         struct sg_mapping_iter miter;
 171         enum jz4740_mmc_state state;
 172
 173         /* DMA support */
 174         struct dma_chan *dma_rx;
 175         struct dma_chan *dma_tx;
 176         bool use_dma;
 177
 178 /* The DMA trigger level is 8 words, that is to say, the DMA read
 179  * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
 180  * trigger is when data words in MSC_TXFIFO is < 8.
 181  */
 182 #define JZ4740_MMC_FIFO_HALF_SIZE 8
 183 };
 184
 185 static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host,
 186                                       uint32_t val)
 187 {
 188         if (host->version >= JZ_MMC_JZ4725B)
 189                 return writel(val, host->base + JZ_REG_MMC_IMASK);
 190         else
 191                 return writew(val, host->base + JZ_REG_MMC_IMASK);
 192 }
 193
 194 static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host,
 195                                      uint32_t val)
 196 {
 197         if (host->version >= JZ_MMC_JZ4780)
 198                 writel(val, host->base + JZ_REG_MMC_IREG);
 199         else
 200                 writew(val, host->base + JZ_REG_MMC_IREG);
 201 }
 202
 203 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
 204 {
 205         if (host->version >= JZ_MMC_JZ4780)
 206                 return readl(host->base + JZ_REG_MMC_IREG);
 207         else
 208                 return readw(host->base + JZ_REG_MMC_IREG);
 209 }
 210
 211 /*----------------------------------------------------------------------------*/
 212 /* DMA infrastructure */
 213
 214 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
 215 {
 216         if (!host->use_dma)
 217                 return;
 218
 219         dma_release_channel(host->dma_tx);
 220         dma_release_channel(host->dma_rx);
 221 }
 222
 223 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
 224 {
 225         host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
 226         if (IS_ERR(host->dma_tx)) {
 227                 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
 228                 return PTR_ERR(host->dma_tx);
 229         }
 230
 231         host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
 232         if (IS_ERR(host->dma_rx)) {
 233                 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
 234                 dma_release_channel(host->dma_tx);
 235                 return PTR_ERR(host->dma_rx);
 236         }
 237
 238         return 0;
 239 }
 240
 241 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
 242                                                        struct mmc_data *data)
 243 {
 244         return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
 245 }
 246
 247 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
 248                                  struct mmc_data *data)
 249 {
 250         struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
 251         enum dma_data_direction dir = mmc_get_dma_dir(data);
 252
 253         dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
 254         data->host_cookie = COOKIE_UNMAPPED;
 255 }
 256
 257 /* Prepares DMA data for current or next transfer.
 258  * A request can be in-flight when this is called.
 259  */
 260 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
 261                                        struct mmc_data *data,
 262                                        int cookie)
 263 {
 264         struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
 265         enum dma_data_direction dir = mmc_get_dma_dir(data);
 266         int sg_count;
 267
 268         if (data->host_cookie == COOKIE_PREMAPPED)
 269                 return data->sg_count;
 270
 271         sg_count = dma_map_sg(chan->device->dev,
 272                         data->sg,
 273                         data->sg_len,
 274                         dir);
 275
 276         if (sg_count <= 0) {
 277                 dev_err(mmc_dev(host->mmc),
 278                         "Failed to map scatterlist for DMA operation\n");
 279                 return -EINVAL;
 280         }
 281
 282         data->sg_count = sg_count;
 283         data->host_cookie = cookie;
 284
 285         return data->sg_count;
 286 }
 287
 288 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
 289                                          struct mmc_data *data)
 290 {
 291         struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
 292         struct dma_async_tx_descriptor *desc;
 293         struct dma_slave_config conf = {
 294                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 295                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 296                 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
 297                 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
 298         };
 299         int sg_count;
 300
 301         if (data->flags & MMC_DATA_WRITE) {
 302                 conf.direction = DMA_MEM_TO_DEV;
 303                 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
 304         } else {
 305                 conf.direction = DMA_DEV_TO_MEM;
 306                 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
 307         }
 308
 309         sg_count = jz4740_mmc_prepare_dma_data(host, data, COOKIE_MAPPED);
 310         if (sg_count < 0)
 311                 return sg_count;
 312
 313         dmaengine_slave_config(chan, &conf);
 314         desc = dmaengine_prep_slave_sg(chan, data->sg, sg_count,
 315                         conf.direction,
 316                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 317         if (!desc) {
 318                 dev_err(mmc_dev(host->mmc),
 319                         "Failed to allocate DMA %s descriptor",
 320                          conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
 321                 goto dma_unmap;
 322         }
 323
 324         dmaengine_submit(desc);
 325         dma_async_issue_pending(chan);
 326
 327         return 0;
 328
 329 dma_unmap:
 330         if (data->host_cookie == COOKIE_MAPPED)
 331                 jz4740_mmc_dma_unmap(host, data);
 332         return -ENOMEM;
 333 }
 334
 335 static void jz4740_mmc_pre_request(struct mmc_host *mmc,
 336                                    struct mmc_request *mrq)
 337 {
 338         struct jz4740_mmc_host *host = mmc_priv(mmc);
 339         struct mmc_data *data = mrq->data;
 340
 341         if (!host->use_dma)
 342                 return;
 343
 344         data->host_cookie = COOKIE_UNMAPPED;
 345         if (jz4740_mmc_prepare_dma_data(host, data, COOKIE_PREMAPPED) < 0)
 346                 data->host_cookie = COOKIE_UNMAPPED;
 347 }
 348
 349 static void jz4740_mmc_post_request(struct mmc_host *mmc,
 350                                     struct mmc_request *mrq,
 351                                     int err)
 352 {
 353         struct jz4740_mmc_host *host = mmc_priv(mmc);
 354         struct mmc_data *data = mrq->data;
 355
 356         if (data && data->host_cookie != COOKIE_UNMAPPED)
 357                 jz4740_mmc_dma_unmap(host, data);
 358
 359         if (err) {
 360                 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
 361
 362                 dmaengine_terminate_all(chan);
 363         }
 364 }
 365
 366 /*----------------------------------------------------------------------------*/
 367
 368 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
 369         unsigned int irq, bool enabled)
 370 {
 371         unsigned long flags;
 372
 373         spin_lock_irqsave(&host->lock, flags);
 374         if (enabled)
 375                 host->irq_mask &= ~irq;
 376         else
 377                 host->irq_mask |= irq;
 378
 379         jz4740_mmc_write_irq_mask(host, host->irq_mask);
 380         spin_unlock_irqrestore(&host->lock, flags);
 381 }
 382
 383 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
 384         bool start_transfer)
 385 {
 386         uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
 387
 388         if (start_transfer)
 389                 val |= JZ_MMC_STRPCL_START_OP;
 390
 391         writew(val, host->base + JZ_REG_MMC_STRPCL);
 392 }
 393
 394 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
 395 {
 396         uint32_t status;
 397         unsigned int timeout = 1000;
 398
 399         writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
 400         do {
 401                 status = readl(host->base + JZ_REG_MMC_STATUS);
 402         } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
 403 }
 404
 405 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
 406 {
 407         uint32_t status;
 408         unsigned int timeout = 1000;
 409
 410         writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
 411         udelay(10);
 412         do {
 413                 status = readl(host->base + JZ_REG_MMC_STATUS);
 414         } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
 415 }
 416
 417 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
 418 {
 419         struct mmc_request *req;
 420         struct mmc_data *data;
 421
 422         req = host->req;
 423         data = req->data;
 424         host->req = NULL;
 425
 426         if (data && data->host_cookie == COOKIE_MAPPED)
 427                 jz4740_mmc_dma_unmap(host, data);
 428         mmc_request_done(host->mmc, req);
 429 }
 430
 431 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
 432         unsigned int irq)
 433 {
 434         unsigned int timeout = 0x800;
 435         uint32_t status;
 436
 437         do {
 438                 status = jz4740_mmc_read_irq_reg(host);
 439         } while (!(status & irq) && --timeout);
 440
 441         if (timeout == 0) {
 442                 set_bit(0, &host->waiting);
 443                 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
 444                 jz4740_mmc_set_irq_enabled(host, irq, true);
 445                 return true;
 446         }
 447
 448         return false;
 449 }
 450
 451 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
 452         struct mmc_data *data)
 453 {
 454         int status;
 455
 456         status = readl(host->base + JZ_REG_MMC_STATUS);
 457         if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
 458                 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
 459                         host->req->cmd->error = -ETIMEDOUT;
 460                         data->error = -ETIMEDOUT;
 461                 } else {
 462                         host->req->cmd->error = -EIO;
 463                         data->error = -EIO;
 464                 }
 465         } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
 466                 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
 467                         host->req->cmd->error = -ETIMEDOUT;
 468                         data->error = -ETIMEDOUT;
 469                 } else {
 470                         host->req->cmd->error = -EIO;
 471                         data->error = -EIO;
 472                 }
 473         }
 474 }
 475
 476 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
 477         struct mmc_data *data)
 478 {
 479         struct sg_mapping_iter *miter = &host->miter;
 480         void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
 481         uint32_t *buf;
 482         bool timeout;
 483         size_t i, j;
 484
 485         while (sg_miter_next(miter)) {
 486                 buf = miter->addr;
 487                 i = miter->length / 4;
 488                 j = i / 8;
 489                 i = i & 0x7;
 490                 while (j) {
 491                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
 492                         if (unlikely(timeout))
 493                                 goto poll_timeout;
 494
 495                         writel(buf[0], fifo_addr);
 496                         writel(buf[1], fifo_addr);
 497                         writel(buf[2], fifo_addr);
 498                         writel(buf[3], fifo_addr);
 499                         writel(buf[4], fifo_addr);
 500                         writel(buf[5], fifo_addr);
 501                         writel(buf[6], fifo_addr);
 502                         writel(buf[7], fifo_addr);
 503                         buf += 8;
 504                         --j;
 505                 }
 506                 if (unlikely(i)) {
 507                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
 508                         if (unlikely(timeout))
 509                                 goto poll_timeout;
 510
 511                         while (i) {
 512                                 writel(*buf, fifo_addr);
 513                                 ++buf;
 514                                 --i;
 515                         }
 516                 }
 517                 data->bytes_xfered += miter->length;
 518         }
 519         sg_miter_stop(miter);
 520
 521         return false;
 522
 523 poll_timeout:
 524         miter->consumed = (void *)buf - miter->addr;
 525         data->bytes_xfered += miter->consumed;
 526         sg_miter_stop(miter);
 527
 528         return true;
 529 }
 530
 531 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
 532                                 struct mmc_data *data)
 533 {
 534         struct sg_mapping_iter *miter = &host->miter;
 535         void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
 536         uint32_t *buf;
 537         uint32_t d;
 538         uint32_t status;
 539         size_t i, j;
 540         unsigned int timeout;
 541
 542         while (sg_miter_next(miter)) {
 543                 buf = miter->addr;
 544                 i = miter->length;
 545                 j = i / 32;
 546                 i = i & 0x1f;
 547                 while (j) {
 548                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
 549                         if (unlikely(timeout))
 550                                 goto poll_timeout;
 551
 552                         buf[0] = readl(fifo_addr);
 553                         buf[1] = readl(fifo_addr);
 554                         buf[2] = readl(fifo_addr);
 555                         buf[3] = readl(fifo_addr);
 556                         buf[4] = readl(fifo_addr);
 557                         buf[5] = readl(fifo_addr);
 558                         buf[6] = readl(fifo_addr);
 559                         buf[7] = readl(fifo_addr);
 560
 561                         buf += 8;
 562                         --j;
 563                 }
 564
 565                 if (unlikely(i)) {
 566                         timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
 567                         if (unlikely(timeout))
 568                                 goto poll_timeout;
 569
 570                         while (i >= 4) {
 571                                 *buf++ = readl(fifo_addr);
 572                                 i -= 4;
 573                         }
 574                         if (unlikely(i > 0)) {
 575                                 d = readl(fifo_addr);
 576                                 memcpy(buf, &d, i);
 577                         }
 578                 }
 579                 data->bytes_xfered += miter->length;
 580
 581                 /* This can go away once MIPS implements
 582                  * flush_kernel_dcache_page */
 583                 flush_dcache_page(miter->page);
 584         }
 585         sg_miter_stop(miter);
 586
 587         /* For whatever reason there is sometime one word more in the fifo then
 588          * requested */
 589         timeout = 1000;
 590         status = readl(host->base + JZ_REG_MMC_STATUS);
 591         while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
 592                 d = readl(fifo_addr);
 593                 status = readl(host->base + JZ_REG_MMC_STATUS);
 594         }
 595
 596         return false;
 597
 598 poll_timeout:
 599         miter->consumed = (void *)buf - miter->addr;
 600         data->bytes_xfered += miter->consumed;
 601         sg_miter_stop(miter);
 602
 603         return true;
 604 }
 605
 606 static void jz4740_mmc_timeout(struct timer_list *t)
 607 {
 608         struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer);
 609
 610         if (!test_and_clear_bit(0, &host->waiting))
 611                 return;
 612
 613         jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
 614
 615         host->req->cmd->error = -ETIMEDOUT;
 616         jz4740_mmc_request_done(host);
 617 }
 618
 619 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
 620         struct mmc_command *cmd)
 621 {
 622         int i;
 623         uint16_t tmp;
 624         void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
 625
 626         if (cmd->flags & MMC_RSP_136) {
 627                 tmp = readw(fifo_addr);
 628                 for (i = 0; i < 4; ++i) {
 629                         cmd->resp[i] = tmp << 24;
 630                         tmp = readw(fifo_addr);
 631                         cmd->resp[i] |= tmp << 8;
 632                         tmp = readw(fifo_addr);
 633                         cmd->resp[i] |= tmp >> 8;
 634                 }
 635         } else {
 636                 cmd->resp[0] = readw(fifo_addr) << 24;
 637                 cmd->resp[0] |= readw(fifo_addr) << 8;
 638                 cmd->resp[0] |= readw(fifo_addr) & 0xff;
 639         }
 640 }
 641
 642 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
 643         struct mmc_command *cmd)
 644 {
 645         uint32_t cmdat = host->cmdat;
 646
 647         host->cmdat &= ~JZ_MMC_CMDAT_INIT;
 648         jz4740_mmc_clock_disable(host);
 649
 650         host->cmd = cmd;
 651
 652         if (cmd->flags & MMC_RSP_BUSY)
 653                 cmdat |= JZ_MMC_CMDAT_BUSY;
 654
 655         switch (mmc_resp_type(cmd)) {
 656         case MMC_RSP_R1B:
 657         case MMC_RSP_R1:
 658                 cmdat |= JZ_MMC_CMDAT_RSP_R1;
 659                 break;
 660         case MMC_RSP_R2:
 661                 cmdat |= JZ_MMC_CMDAT_RSP_R2;
 662                 break;
 663         case MMC_RSP_R3:
 664                 cmdat |= JZ_MMC_CMDAT_RSP_R3;
 665                 break;
 666         default:
 667                 break;
 668         }
 669
 670         if (cmd->data) {
 671                 cmdat |= JZ_MMC_CMDAT_DATA_EN;
 672                 if (cmd->data->flags & MMC_DATA_WRITE)
 673                         cmdat |= JZ_MMC_CMDAT_WRITE;
 674                 if (host->use_dma) {
 675                         /*
 676                          * The 4780's MMC controller has integrated DMA ability
 677                          * in addition to being able to use the external DMA
 678                          * controller. It moves DMA control bits to a separate
 679                          * register. The DMA_SEL bit chooses the external
 680                          * controller over the integrated one. Earlier SoCs
 681                          * can only use the external controller, and have a
 682                          * single DMA enable bit in CMDAT.
 683                          */
 684                         if (host->version >= JZ_MMC_JZ4780) {
 685                                 writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL,
 686                                        host->base + JZ_REG_MMC_DMAC);
 687                         } else {
 688                                 cmdat |= JZ_MMC_CMDAT_DMA_EN;
 689                         }
 690                 } else if (host->version >= JZ_MMC_JZ4780) {
 691                         writel(0, host->base + JZ_REG_MMC_DMAC);
 692                 }
 693
 694                 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
 695                 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
 696         }
 697
 698         writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
 699         writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
 700         writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
 701
 702         jz4740_mmc_clock_enable(host, 1);
 703 }
 704
 705 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
 706 {
 707         struct mmc_command *cmd = host->req->cmd;
 708         struct mmc_data *data = cmd->data;
 709         int direction;
 710
 711         if (data->flags & MMC_DATA_READ)
 712                 direction = SG_MITER_TO_SG;
 713         else
 714                 direction = SG_MITER_FROM_SG;
 715
 716         sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
 717 }
 718
 719
 720 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
 721 {
 722         struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
 723         struct mmc_command *cmd = host->req->cmd;
 724         struct mmc_request *req = host->req;
 725         struct mmc_data *data = cmd->data;
 726         bool timeout = false;
 727
 728         if (cmd->error)
 729                 host->state = JZ4740_MMC_STATE_DONE;
 730
 731         switch (host->state) {
 732         case JZ4740_MMC_STATE_READ_RESPONSE:
 733                 if (cmd->flags & MMC_RSP_PRESENT)
 734                         jz4740_mmc_read_response(host, cmd);
 735
 736                 if (!data)
 737                         break;
 738
 739                 jz_mmc_prepare_data_transfer(host);
 740                 /* fall through */
 741
 742         case JZ4740_MMC_STATE_TRANSFER_DATA:
 743                 if (host->use_dma) {
 744                         /* Use DMA if enabled.
 745                          * Data transfer direction is defined later by
 746                          * relying on data flags in
 747                          * jz4740_mmc_prepare_dma_data() and
 748                          * jz4740_mmc_start_dma_transfer().
 749                          */
 750                         timeout = jz4740_mmc_start_dma_transfer(host, data);
 751                         data->bytes_xfered = data->blocks * data->blksz;
 752                 } else if (data->flags & MMC_DATA_READ)
 753                         /* Use PIO if DMA is not enabled.
 754                          * Data transfer direction was defined before
 755                          * by relying on data flags in
 756                          * jz_mmc_prepare_data_transfer().
 757                          */
 758                         timeout = jz4740_mmc_read_data(host, data);
 759                 else
 760                         timeout = jz4740_mmc_write_data(host, data);
 761
 762                 if (unlikely(timeout)) {
 763                         host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
 764                         break;
 765                 }
 766
 767                 jz4740_mmc_transfer_check_state(host, data);
 768
 769                 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
 770                 if (unlikely(timeout)) {
 771                         host->state = JZ4740_MMC_STATE_SEND_STOP;
 772                         break;
 773                 }
 774                 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
 775                 /* fall through */
 776
 777         case JZ4740_MMC_STATE_SEND_STOP:
 778                 if (!req->stop)
 779                         break;
 780
 781                 jz4740_mmc_send_command(host, req->stop);
 782
 783                 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
 784                         timeout = jz4740_mmc_poll_irq(host,
 785                                                       JZ_MMC_IRQ_PRG_DONE);
 786                         if (timeout) {
 787                                 host->state = JZ4740_MMC_STATE_DONE;
 788                                 break;
 789                         }
 790                 }
 791         case JZ4740_MMC_STATE_DONE:
 792                 break;
 793         }
 794
 795         if (!timeout)
 796                 jz4740_mmc_request_done(host);
 797
 798         return IRQ_HANDLED;
 799 }
 800
 801 static irqreturn_t jz_mmc_irq(int irq, void *devid)
 802 {
 803         struct jz4740_mmc_host *host = devid;
 804         struct mmc_command *cmd = host->cmd;
 805         uint32_t irq_reg, status, tmp;
 806
 807         status = readl(host->base + JZ_REG_MMC_STATUS);
 808         irq_reg = jz4740_mmc_read_irq_reg(host);
 809
 810         tmp = irq_reg;
 811         irq_reg &= ~host->irq_mask;
 812
 813         tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
 814                 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
 815
 816         if (tmp != irq_reg)
 817                 jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg);
 818
 819         if (irq_reg & JZ_MMC_IRQ_SDIO) {
 820                 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO);
 821                 mmc_signal_sdio_irq(host->mmc);
 822                 irq_reg &= ~JZ_MMC_IRQ_SDIO;
 823         }
 824
 825         if (host->req && cmd && irq_reg) {
 826                 if (test_and_clear_bit(0, &host->waiting)) {
 827                         del_timer(&host->timeout_timer);
 828
 829                         if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
 830                                 cmd->error = -ETIMEDOUT;
 831                         } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
 832                                 cmd->error = -EIO;
 833                         } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
 834                                     JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
 835                                 if (cmd->data)
 836                                         cmd->data->error = -EIO;
 837                                 cmd->error = -EIO;
 838                         }
 839
 840                         jz4740_mmc_set_irq_enabled(host, irq_reg, false);
 841                         jz4740_mmc_write_irq_reg(host, irq_reg);
 842
 843                         return IRQ_WAKE_THREAD;
 844                 }
 845         }
 846
 847         return IRQ_HANDLED;
 848 }
 849
 850 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
 851 {
 852         int div = 0;
 853         int real_rate;
 854
 855         jz4740_mmc_clock_disable(host);
 856         clk_set_rate(host->clk, host->mmc->f_max);
 857
 858         real_rate = clk_get_rate(host->clk);
 859
 860         while (real_rate > rate && div < 7) {
 861                 ++div;
 862                 real_rate >>= 1;
 863         }
 864
 865         writew(div, host->base + JZ_REG_MMC_CLKRT);
 866
 867         if (real_rate > 25000000) {
 868                 if (host->version >= JZ_MMC_X1000) {
 869                         writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY |
 870                                    JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY |
 871                                    JZ_MMC_LPM_LOW_POWER_MODE_EN,
 872                                    host->base + JZ_REG_MMC_LPM);
 873                 } else if (host->version >= JZ_MMC_JZ4760) {
 874                         writel(JZ_MMC_LPM_DRV_RISING |
 875                                    JZ_MMC_LPM_LOW_POWER_MODE_EN,
 876                                    host->base + JZ_REG_MMC_LPM);
 877                 } else if (host->version >= JZ_MMC_JZ4725B)
 878                         writel(JZ_MMC_LPM_LOW_POWER_MODE_EN,
 879                                    host->base + JZ_REG_MMC_LPM);
 880         }
 881
 882         return real_rate;
 883 }
 884
 885 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
 886 {
 887         struct jz4740_mmc_host *host = mmc_priv(mmc);
 888
 889         host->req = req;
 890
 891         jz4740_mmc_write_irq_reg(host, ~0);
 892         jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
 893
 894         host->state = JZ4740_MMC_STATE_READ_RESPONSE;
 895         set_bit(0, &host->waiting);
 896         mod_timer(&host->timeout_timer, jiffies + 5*HZ);
 897         jz4740_mmc_send_command(host, req->cmd);
 898 }
 899
 900 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 901 {
 902         struct jz4740_mmc_host *host = mmc_priv(mmc);
 903         if (ios->clock)
 904                 jz4740_mmc_set_clock_rate(host, ios->clock);
 905
 906         switch (ios->power_mode) {
 907         case MMC_POWER_UP:
 908                 jz4740_mmc_reset(host);
 909                 if (!IS_ERR(mmc->supply.vmmc))
 910                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
 911                 host->cmdat |= JZ_MMC_CMDAT_INIT;
 912                 clk_prepare_enable(host->clk);
 913                 break;
 914         case MMC_POWER_ON:
 915                 break;
 916         default:
 917                 if (!IS_ERR(mmc->supply.vmmc))
 918                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
 919                 clk_disable_unprepare(host->clk);
 920                 break;
 921         }
 922
 923         switch (ios->bus_width) {
 924         case MMC_BUS_WIDTH_1:
 925                 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
 926                 break;
 927         case MMC_BUS_WIDTH_4:
 928                 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
 929                 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
 930                 break;
 931         case MMC_BUS_WIDTH_8:
 932                 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_MASK;
 933                 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_8BIT;
 934                 break;
 935         default:
 936                 break;
 937         }
 938 }
 939
 940 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
 941 {
 942         struct jz4740_mmc_host *host = mmc_priv(mmc);
 943         jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
 944 }
 945
 946 static const struct mmc_host_ops jz4740_mmc_ops = {
 947         .request        = jz4740_mmc_request,
 948         .pre_req        = jz4740_mmc_pre_request,
 949         .post_req       = jz4740_mmc_post_request,
 950         .set_ios        = jz4740_mmc_set_ios,
 951         .get_ro         = mmc_gpio_get_ro,
 952         .get_cd         = mmc_gpio_get_cd,
 953         .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
 954 };
 955
 956 static const struct of_device_id jz4740_mmc_of_match[] = {
 957         { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 },
 958         { .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B },
 959         { .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 },
 960         { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 },
 961         { .compatible = "ingenic,x1000-mmc", .data = (void *) JZ_MMC_X1000 },
 962         {},
 963 };
 964 MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match);
 965
 966 static int jz4740_mmc_probe(struct platform_device* pdev)
 967 {
 968         int ret;
 969         struct mmc_host *mmc;
 970         struct jz4740_mmc_host *host;
 971         const struct of_device_id *match;
 972
 973         mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
 974         if (!mmc) {
 975                 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
 976                 return -ENOMEM;
 977         }
 978
 979         host = mmc_priv(mmc);
 980
 981         match = of_match_device(jz4740_mmc_of_match, &pdev->dev);
 982         if (match) {
 983                 host->version = (enum jz4740_mmc_version)match->data;
 984         } else {
 985                 /* JZ4740 should be the only one using legacy probe */
 986                 host->version = JZ_MMC_JZ4740;
 987         }
 988
 989         ret = mmc_of_parse(mmc);
 990         if (ret) {
 991                 if (ret != -EPROBE_DEFER)
 992                         dev_err(&pdev->dev,
 993                                 "could not parse device properties: %d\n", ret);
 994                 goto err_free_host;
 995         }
 996
 997         mmc_regulator_get_supply(mmc);
 998
 999         host->irq = platform_get_irq(pdev, 0);
1000         if (host->irq < 0) {
1001                 ret = host->irq;
1002                 goto err_free_host;
1003         }
1004
1005         host->clk = devm_clk_get(&pdev->dev, "mmc");
1006         if (IS_ERR(host->clk)) {
1007                 ret = PTR_ERR(host->clk);
1008                 dev_err(&pdev->dev, "Failed to get mmc clock\n");
1009                 goto err_free_host;
1010         }
1011
1012         host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1013         host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
1014         if (IS_ERR(host->base)) {
1015                 ret = PTR_ERR(host->base);
1016                 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
1017                 goto err_free_host;
1018         }
1019
1020         mmc->ops = &jz4740_mmc_ops;
1021         if (!mmc->f_max)
1022                 mmc->f_max = JZ_MMC_CLK_RATE;
1023         mmc->f_min = mmc->f_max / 128;
1024         mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1025
1026         mmc->max_blk_size = (1 << 10) - 1;
1027         mmc->max_blk_count = (1 << 15) - 1;
1028         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1029
1030         mmc->max_segs = 128;
1031         mmc->max_seg_size = mmc->max_req_size;
1032
1033         host->mmc = mmc;
1034         host->pdev = pdev;
1035         spin_lock_init(&host->lock);
1036         host->irq_mask = ~0;
1037
1038         jz4740_mmc_reset(host);
1039
1040         ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
1041                         dev_name(&pdev->dev), host);
1042         if (ret) {
1043                 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1044                 goto err_free_host;
1045         }
1046
1047         jz4740_mmc_clock_disable(host);
1048         timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0);
1049
1050         ret = jz4740_mmc_acquire_dma_channels(host);
1051         if (ret == -EPROBE_DEFER)
1052                 goto err_free_irq;
1053         host->use_dma = !ret;
1054
1055         platform_set_drvdata(pdev, host);
1056         ret = mmc_add_host(mmc);
1057
1058         if (ret) {
1059                 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
1060                 goto err_release_dma;
1061         }
1062         dev_info(&pdev->dev, "Ingenic SD/MMC card driver registered\n");
1063
1064         dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
1065                  host->use_dma ? "DMA" : "PIO",
1066                  (mmc->caps & MMC_CAP_8_BIT_DATA) ? 8 :
1067                  ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1));
1068
1069         return 0;
1070
1071 err_release_dma:
1072         if (host->use_dma)
1073                 jz4740_mmc_release_dma_channels(host);
1074 err_free_irq:
1075         free_irq(host->irq, host);
1076 err_free_host:
1077         mmc_free_host(mmc);
1078
1079         return ret;
1080 }
1081
1082 static int jz4740_mmc_remove(struct platform_device *pdev)
1083 {
1084         struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1085
1086         del_timer_sync(&host->timeout_timer);
1087         jz4740_mmc_set_irq_enabled(host, 0xff, false);
1088         jz4740_mmc_reset(host);
1089
1090         mmc_remove_host(host->mmc);
1091
1092         free_irq(host->irq, host);
1093
1094         if (host->use_dma)
1095                 jz4740_mmc_release_dma_channels(host);
1096
1097         mmc_free_host(host->mmc);
1098
1099         return 0;
1100 }
1101
1102 #ifdef CONFIG_PM_SLEEP
1103
1104 static int jz4740_mmc_suspend(struct device *dev)
1105 {
1106         return pinctrl_pm_select_sleep_state(dev);
1107 }
1108
1109 static int jz4740_mmc_resume(struct device *dev)
1110 {
1111         return pinctrl_select_default_state(dev);
1112 }
1113
1114 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
1115         jz4740_mmc_resume);
1116 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1117 #else
1118 #define JZ4740_MMC_PM_OPS NULL
1119 #endif
1120
1121 static struct platform_driver jz4740_mmc_driver = {
1122         .probe = jz4740_mmc_probe,
1123         .remove = jz4740_mmc_remove,
1124         .driver = {
1125                 .name = "jz4740-mmc",
1126                 .of_match_table = of_match_ptr(jz4740_mmc_of_match),
1127                 .pm = JZ4740_MMC_PM_OPS,
1128         },
1129 };
1130
1131 module_platform_driver(jz4740_mmc_driver);
1132
1133 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
1134 MODULE_LICENSE("GPL");
1135 MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");