drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "amdgpu.h"
  33 #include "amdgpu_ras.h"
  34 #include "amdgpu_atomfirmware.h"
  35 #include "amdgpu_xgmi.h"
  36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  37 #include "atom.h"
  38 #ifdef CONFIG_X86_MCE_AMD
  39 #include <asm/mce.h>
  40
  41 static bool notifier_registered;
  42 #endif
  43 static const char *RAS_FS_NAME = "ras";
  44
  45 const char *ras_error_string[] = {
  46         "none",
  47         "parity",
  48         "single_correctable",
  49         "multi_uncorrectable",
  50         "poison",
  51 };
  52
  53 const char *ras_block_string[] = {
  54         "umc",
  55         "sdma",
  56         "gfx",
  57         "mmhub",
  58         "athub",
  59         "pcie_bif",
  60         "hdp",
  61         "xgmi_wafl",
  62         "df",
  63         "smn",
  64         "sem",
  65         "mp0",
  66         "mp1",
  67         "fuse",
  68         "mca",
  69 };
  70
  71 const char *ras_mca_block_string[] = {
  72         "mca_mp0",
  73         "mca_mp1",
  74         "mca_mpio",
  75         "mca_iohc",
  76 };
  77
  78 const char *get_ras_block_str(struct ras_common_if *ras_block)
  79 {
  80         if (!ras_block)
  81                 return "NULL";
  82
  83         if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
  84                 return "OUT OF RANGE";
  85
  86         if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
  87                 return ras_mca_block_string[ras_block->sub_block_index];
  88
  89         return ras_block_string[ras_block->block];
  90 }
  91
  92 #define ras_err_str(i) (ras_error_string[ffs(i)])
  93
  94 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  95
  96 /* inject address is 52 bits */
  97 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  98
  99 /* typical ECC bad page rate is 1 bad page per 100MB VRAM */
 100 #define RAS_BAD_PAGE_COVER              (100 * 1024 * 1024ULL)
 101
 102 enum amdgpu_ras_retire_page_reservation {
 103         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
 104         AMDGPU_RAS_RETIRE_PAGE_PENDING,
 105         AMDGPU_RAS_RETIRE_PAGE_FAULT,
 106 };
 107
 108 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
 109
 110 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
 111                                 uint64_t addr);
 112 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
 113                                 uint64_t addr);
 114 #ifdef CONFIG_X86_MCE_AMD
 115 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
 116 struct mce_notifier_adev_list {
 117         struct amdgpu_device *devs[MAX_GPU_INSTANCE];
 118         int num_gpu;
 119 };
 120 static struct mce_notifier_adev_list mce_adev_list;
 121 #endif
 122
 123 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
 124 {
 125         if (adev && amdgpu_ras_get_context(adev))
 126                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 127 }
 128
 129 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 130 {
 131         if (adev && amdgpu_ras_get_context(adev))
 132                 return amdgpu_ras_get_context(adev)->error_query_ready;
 133
 134         return false;
 135 }
 136
 137 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 138 {
 139         struct ras_err_data err_data = {0, 0, 0, NULL};
 140         struct eeprom_table_record err_rec;
 141
 142         if ((address >= adev->gmc.mc_vram_size) ||
 143             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 144                 dev_warn(adev->dev,
 145                          "RAS WARN: input address 0x%llx is invalid.\n",
 146                          address);
 147                 return -EINVAL;
 148         }
 149
 150         if (amdgpu_ras_check_bad_page(adev, address)) {
 151                 dev_warn(adev->dev,
 152                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 153                          address);
 154                 return 0;
 155         }
 156
 157         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 158
 159         err_rec.address = address;
 160         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 161         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 162         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 163
 164         err_data.err_addr = &err_rec;
 165         err_data.err_addr_cnt = 1;
 166
 167         if (amdgpu_bad_page_threshold != 0) {
 168                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 169                                          err_data.err_addr_cnt);
 170                 amdgpu_ras_save_bad_pages(adev);
 171         }
 172
 173         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 174         dev_warn(adev->dev, "Clear EEPROM:\n");
 175         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 176
 177         return 0;
 178 }
 179
 180 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 181                                         size_t size, loff_t *pos)
 182 {
 183         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 184         struct ras_query_if info = {
 185                 .head = obj->head,
 186         };
 187         ssize_t s;
 188         char val[128];
 189
 190         if (amdgpu_ras_query_error_status(obj->adev, &info))
 191                 return -EINVAL;
 192
 193         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 194                         "ue", info.ue_count,
 195                         "ce", info.ce_count);
 196         if (*pos >= s)
 197                 return 0;
 198
 199         s -= *pos;
 200         s = min_t(u64, s, size);
 201
 202
 203         if (copy_to_user(buf, &val[*pos], s))
 204                 return -EINVAL;
 205
 206         *pos += s;
 207
 208         return s;
 209 }
 210
 211 static const struct file_operations amdgpu_ras_debugfs_ops = {
 212         .owner = THIS_MODULE,
 213         .read = amdgpu_ras_debugfs_read,
 214         .write = NULL,
 215         .llseek = default_llseek
 216 };
 217
 218 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 219 {
 220         int i;
 221
 222         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 223                 *block_id = i;
 224                 if (strcmp(name, ras_block_string[i]) == 0)
 225                         return 0;
 226         }
 227         return -EINVAL;
 228 }
 229
 230 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 231                 const char __user *buf, size_t size,
 232                 loff_t *pos, struct ras_debug_if *data)
 233 {
 234         ssize_t s = min_t(u64, 64, size);
 235         char str[65];
 236         char block_name[33];
 237         char err[9] = "ue";
 238         int op = -1;
 239         int block_id;
 240         uint32_t sub_block;
 241         u64 address, value;
 242
 243         if (*pos)
 244                 return -EINVAL;
 245         *pos = size;
 246
 247         memset(str, 0, sizeof(str));
 248         memset(data, 0, sizeof(*data));
 249
 250         if (copy_from_user(str, buf, s))
 251                 return -EINVAL;
 252
 253         if (sscanf(str, "disable %32s", block_name) == 1)
 254                 op = 0;
 255         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 256                 op = 1;
 257         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 258                 op = 2;
 259         else if (strstr(str, "retire_page") != NULL)
 260                 op = 3;
 261         else if (str[0] && str[1] && str[2] && str[3])
 262                 /* ascii string, but commands are not matched. */
 263                 return -EINVAL;
 264
 265         if (op != -1) {
 266                 if (op == 3) {
 267                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 268                             sscanf(str, "%*s %llu", &address) != 1)
 269                                 return -EINVAL;
 270
 271                         data->op = op;
 272                         data->inject.address = address;
 273
 274                         return 0;
 275                 }
 276
 277                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 278                         return -EINVAL;
 279
 280                 data->head.block = block_id;
 281                 /* only ue and ce errors are supported */
 282                 if (!memcmp("ue", err, 2))
 283                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 284                 else if (!memcmp("ce", err, 2))
 285                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 286                 else
 287                         return -EINVAL;
 288
 289                 data->op = op;
 290
 291                 if (op == 2) {
 292                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 293                                    &sub_block, &address, &value) != 3 &&
 294                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 295                                    &sub_block, &address, &value) != 3)
 296                                 return -EINVAL;
 297                         data->head.sub_block_index = sub_block;
 298                         data->inject.address = address;
 299                         data->inject.value = value;
 300                 }
 301         } else {
 302                 if (size < sizeof(*data))
 303                         return -EINVAL;
 304
 305                 if (copy_from_user(data, buf, sizeof(*data)))
 306                         return -EINVAL;
 307         }
 308
 309         return 0;
 310 }
 311
 312 /**
 313  * DOC: AMDGPU RAS debugfs control interface
 314  *
 315  * The control interface accepts struct ras_debug_if which has two members.
 316  *
 317  * First member: ras_debug_if::head or ras_debug_if::inject.
 318  *
 319  * head is used to indicate which IP block will be under control.
 320  *
 321  * head has four members, they are block, type, sub_block_index, name.
 322  * block: which IP will be under control.
 323  * type: what kind of error will be enabled/disabled/injected.
 324  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 325  * name: the name of IP.
 326  *
 327  * inject has two more members than head, they are address, value.
 328  * As their names indicate, inject operation will write the
 329  * value to the address.
 330  *
 331  * The second member: struct ras_debug_if::op.
 332  * It has three kinds of operations.
 333  *
 334  * - 0: disable RAS on the block. Take ::head as its data.
 335  * - 1: enable RAS on the block. Take ::head as its data.
 336  * - 2: inject errors on the block. Take ::inject as its data.
 337  *
 338  * How to use the interface?
 339  *
 340  * In a program
 341  *
 342  * Copy the struct ras_debug_if in your code and initialize it.
 343  * Write the struct to the control interface.
 344  *
 345  * From shell
 346  *
 347  * .. code-block:: bash
 348  *
 349  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 350  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 351  *      echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 352  *
 353  * Where N, is the card which you want to affect.
 354  *
 355  * "disable" requires only the block.
 356  * "enable" requires the block and error type.
 357  * "inject" requires the block, error type, address, and value.
 358  *
 359  * The block is one of: umc, sdma, gfx, etc.
 360  *      see ras_block_string[] for details
 361  *
 362  * The error type is one of: ue, ce, where,
 363  *      ue is multi-uncorrectable
 364  *      ce is single-correctable
 365  *
 366  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 367  * The address and value are hexadecimal numbers, leading 0x is optional.
 368  *
 369  * For instance,
 370  *
 371  * .. code-block:: bash
 372  *
 373  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 374  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 375  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 376  *
 377  * How to check the result of the operation?
 378  *
 379  * To check disable/enable, see "ras" features at,
 380  * /sys/class/drm/card[0/1/2...]/device/ras/features
 381  *
 382  * To check inject, see the corresponding error count at,
 383  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 384  *
 385  * .. note::
 386  *      Operations are only allowed on blocks which are supported.
 387  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 388  *      to see which blocks support RAS on a particular asic.
 389  *
 390  */
 391 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
 392                                              const char __user *buf,
 393                                              size_t size, loff_t *pos)
 394 {
 395         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 396         struct ras_debug_if data;
 397         int ret = 0;
 398
 399         if (!amdgpu_ras_get_error_query_ready(adev)) {
 400                 dev_warn(adev->dev, "RAS WARN: error injection "
 401                                 "currently inaccessible\n");
 402                 return size;
 403         }
 404
 405         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 406         if (ret)
 407                 return ret;
 408
 409         if (data.op == 3) {
 410                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 411                 if (!ret)
 412                         return size;
 413                 else
 414                         return ret;
 415         }
 416
 417         if (!amdgpu_ras_is_supported(adev, data.head.block))
 418                 return -EINVAL;
 419
 420         switch (data.op) {
 421         case 0:
 422                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 423                 break;
 424         case 1:
 425                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 426                 break;
 427         case 2:
 428                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 429                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 430                         dev_warn(adev->dev, "RAS WARN: input address "
 431                                         "0x%llx is invalid.",
 432                                         data.inject.address);
 433                         ret = -EINVAL;
 434                         break;
 435                 }
 436
 437                 /* umc ce/ue error injection for a bad page is not allowed */
 438                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 439                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 440                         dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
 441                                  "already been marked as bad!\n",
 442                                  data.inject.address);
 443                         break;
 444                 }
 445
 446                 /* data.inject.address is offset instead of absolute gpu address */
 447                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 448                 break;
 449         default:
 450                 ret = -EINVAL;
 451                 break;
 452         }
 453
 454         if (ret)
 455                 return -EINVAL;
 456
 457         return size;
 458 }
 459
 460 /**
 461  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 462  *
 463  * Some boards contain an EEPROM which is used to persistently store a list of
 464  * bad pages which experiences ECC errors in vram.  This interface provides
 465  * a way to reset the EEPROM, e.g., after testing error injection.
 466  *
 467  * Usage:
 468  *
 469  * .. code-block:: bash
 470  *
 471  *      echo 1 > ../ras/ras_eeprom_reset
 472  *
 473  * will reset EEPROM table to 0 entries.
 474  *
 475  */
 476 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
 477                                                const char __user *buf,
 478                                                size_t size, loff_t *pos)
 479 {
 480         struct amdgpu_device *adev =
 481                 (struct amdgpu_device *)file_inode(f)->i_private;
 482         int ret;
 483
 484         ret = amdgpu_ras_eeprom_reset_table(
 485                 &(amdgpu_ras_get_context(adev)->eeprom_control));
 486
 487         if (!ret) {
 488                 /* Something was written to EEPROM.
 489                  */
 490                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 491                 return size;
 492         } else {
 493                 return ret;
 494         }
 495 }
 496
 497 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 498         .owner = THIS_MODULE,
 499         .read = NULL,
 500         .write = amdgpu_ras_debugfs_ctrl_write,
 501         .llseek = default_llseek
 502 };
 503
 504 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 505         .owner = THIS_MODULE,
 506         .read = NULL,
 507         .write = amdgpu_ras_debugfs_eeprom_write,
 508         .llseek = default_llseek
 509 };
 510
 511 /**
 512  * DOC: AMDGPU RAS sysfs Error Count Interface
 513  *
 514  * It allows the user to read the error count for each IP block on the gpu through
 515  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 516  *
 517  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 518  * (ce) error counts.
 519  *
 520  * The format of one line is below,
 521  *
 522  * [ce|ue]: count
 523  *
 524  * Example:
 525  *
 526  * .. code-block:: bash
 527  *
 528  *      ue: 0
 529  *      ce: 1
 530  *
 531  */
 532 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 533                 struct device_attribute *attr, char *buf)
 534 {
 535         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 536         struct ras_query_if info = {
 537                 .head = obj->head,
 538         };
 539
 540         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 541                 return sysfs_emit(buf, "Query currently inaccessible\n");
 542
 543         if (amdgpu_ras_query_error_status(obj->adev, &info))
 544                 return -EINVAL;
 545
 546         if (obj->adev->asic_type == CHIP_ALDEBARAN) {
 547                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 548                         DRM_WARN("Failed to reset error counter and error status");
 549         }
 550
 551         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 552                           "ce", info.ce_count);
 553 }
 554
 555 /* obj begin */
 556
 557 #define get_obj(obj) do { (obj)->use++; } while (0)
 558 #define alive_obj(obj) ((obj)->use)
 559
 560 static inline void put_obj(struct ras_manager *obj)
 561 {
 562         if (obj && (--obj->use == 0))
 563                 list_del(&obj->node);
 564         if (obj && (obj->use < 0))
 565                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
 566 }
 567
 568 /* make one obj and return it. */
 569 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 570                 struct ras_common_if *head)
 571 {
 572         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 573         struct ras_manager *obj;
 574
 575         if (!adev->ras_enabled || !con)
 576                 return NULL;
 577
 578         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 579                 return NULL;
 580
 581         if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 582                 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 583                         return NULL;
 584
 585                 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 586         } else
 587                 obj = &con->objs[head->block];
 588
 589         /* already exist. return obj? */
 590         if (alive_obj(obj))
 591                 return NULL;
 592
 593         obj->head = *head;
 594         obj->adev = adev;
 595         list_add(&obj->node, &con->head);
 596         get_obj(obj);
 597
 598         return obj;
 599 }
 600
 601 /* return an obj equal to head, or the first when head is NULL */
 602 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 603                 struct ras_common_if *head)
 604 {
 605         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 606         struct ras_manager *obj;
 607         int i;
 608
 609         if (!adev->ras_enabled || !con)
 610                 return NULL;
 611
 612         if (head) {
 613                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 614                         return NULL;
 615
 616                 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
 617                         if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
 618                                 return NULL;
 619
 620                         obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
 621                 } else
 622                         obj = &con->objs[head->block];
 623
 624                 if (alive_obj(obj))
 625                         return obj;
 626         } else {
 627                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 628                         obj = &con->objs[i];
 629                         if (alive_obj(obj))
 630                                 return obj;
 631                 }
 632         }
 633
 634         return NULL;
 635 }
 636 /* obj end */
 637
 638 /* feature ctl begin */
 639 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 640                                          struct ras_common_if *head)
 641 {
 642         return adev->ras_hw_enabled & BIT(head->block);
 643 }
 644
 645 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 646                 struct ras_common_if *head)
 647 {
 648         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 649
 650         return con->features & BIT(head->block);
 651 }
 652
 653 /*
 654  * if obj is not created, then create one.
 655  * set feature enable flag.
 656  */
 657 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 658                 struct ras_common_if *head, int enable)
 659 {
 660         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 661         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 662
 663         /* If hardware does not support ras, then do not create obj.
 664          * But if hardware support ras, we can create the obj.
 665          * Ras framework checks con->hw_supported to see if it need do
 666          * corresponding initialization.
 667          * IP checks con->support to see if it need disable ras.
 668          */
 669         if (!amdgpu_ras_is_feature_allowed(adev, head))
 670                 return 0;
 671
 672         if (enable) {
 673                 if (!obj) {
 674                         obj = amdgpu_ras_create_obj(adev, head);
 675                         if (!obj)
 676                                 return -EINVAL;
 677                 } else {
 678                         /* In case we create obj somewhere else */
 679                         get_obj(obj);
 680                 }
 681                 con->features |= BIT(head->block);
 682         } else {
 683                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 684                         con->features &= ~BIT(head->block);
 685                         put_obj(obj);
 686                 }
 687         }
 688
 689         return 0;
 690 }
 691
 692 /* wrapper of psp_ras_enable_features */
 693 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 694                 struct ras_common_if *head, bool enable)
 695 {
 696         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 697         union ta_ras_cmd_input *info;
 698         int ret;
 699
 700         if (!con)
 701                 return -EINVAL;
 702
 703         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 704         if (!info)
 705                 return -ENOMEM;
 706
 707         if (!enable) {
 708                 info->disable_features = (struct ta_ras_disable_features_input) {
 709                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 710                         .error_type = amdgpu_ras_error_to_ta(head->type),
 711                 };
 712         } else {
 713                 info->enable_features = (struct ta_ras_enable_features_input) {
 714                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 715                         .error_type = amdgpu_ras_error_to_ta(head->type),
 716                 };
 717         }
 718
 719         /* Do not enable if it is not allowed. */
 720         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 721
 722         if (!amdgpu_ras_intr_triggered()) {
 723                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 724                 if (ret) {
 725                         dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
 726                                 enable ? "enable":"disable",
 727                                 get_ras_block_str(head),
 728                                 amdgpu_ras_is_poison_mode_supported(adev), ret);
 729                         goto out;
 730                 }
 731         }
 732
 733         /* setup the obj */
 734         __amdgpu_ras_feature_enable(adev, head, enable);
 735         ret = 0;
 736 out:
 737         kfree(info);
 738         return ret;
 739 }
 740
 741 /* Only used in device probe stage and called only once. */
 742 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 743                 struct ras_common_if *head, bool enable)
 744 {
 745         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 746         int ret;
 747
 748         if (!con)
 749                 return -EINVAL;
 750
 751         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 752                 if (enable) {
 753                         /* There is no harm to issue a ras TA cmd regardless of
 754                          * the currecnt ras state.
 755                          * If current state == target state, it will do nothing
 756                          * But sometimes it requests driver to reset and repost
 757                          * with error code -EAGAIN.
 758                          */
 759                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 760                         /* With old ras TA, we might fail to enable ras.
 761                          * Log it and just setup the object.
 762                          * TODO need remove this WA in the future.
 763                          */
 764                         if (ret == -EINVAL) {
 765                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 766                                 if (!ret)
 767                                         dev_info(adev->dev,
 768                                                 "RAS INFO: %s setup object\n",
 769                                                 get_ras_block_str(head));
 770                         }
 771                 } else {
 772                         /* setup the object then issue a ras TA disable cmd.*/
 773                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 774                         if (ret)
 775                                 return ret;
 776
 777                         /* gfx block ras dsiable cmd must send to ras-ta */
 778                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 779                                 con->features |= BIT(head->block);
 780
 781                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 782
 783                         /* clean gfx block ras features flag */
 784                         if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
 785                                 con->features &= ~BIT(head->block);
 786                 }
 787         } else
 788                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 789
 790         return ret;
 791 }
 792
 793 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 794                 bool bypass)
 795 {
 796         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 797         struct ras_manager *obj, *tmp;
 798
 799         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 800                 /* bypass psp.
 801                  * aka just release the obj and corresponding flags
 802                  */
 803                 if (bypass) {
 804                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 805                                 break;
 806                 } else {
 807                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 808                                 break;
 809                 }
 810         }
 811
 812         return con->features;
 813 }
 814
 815 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 816                 bool bypass)
 817 {
 818         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 819         int i;
 820         const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
 821
 822         for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 823                 struct ras_common_if head = {
 824                         .block = i,
 825                         .type = default_ras_type,
 826                         .sub_block_index = 0,
 827                 };
 828
 829                 if (i == AMDGPU_RAS_BLOCK__MCA)
 830                         continue;
 831
 832                 if (bypass) {
 833                         /*
 834                          * bypass psp. vbios enable ras for us.
 835                          * so just create the obj
 836                          */
 837                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 838                                 break;
 839                 } else {
 840                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 841                                 break;
 842                 }
 843         }
 844
 845         for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
 846                 struct ras_common_if head = {
 847                         .block = AMDGPU_RAS_BLOCK__MCA,
 848                         .type = default_ras_type,
 849                         .sub_block_index = i,
 850                 };
 851
 852                 if (bypass) {
 853                         /*
 854                          * bypass psp. vbios enable ras for us.
 855                          * so just create the obj
 856                          */
 857                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 858                                 break;
 859                 } else {
 860                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 861                                 break;
 862                 }
 863         }
 864
 865         return con->features;
 866 }
 867 /* feature ctl end */
 868
 869
 870 void amdgpu_ras_mca_query_error_status(struct amdgpu_device *adev,
 871                                        struct ras_common_if *ras_block,
 872                                        struct ras_err_data  *err_data)
 873 {
 874         switch (ras_block->sub_block_index) {
 875         case AMDGPU_RAS_MCA_BLOCK__MP0:
 876                 if (adev->mca.mp0.ras_funcs &&
 877                     adev->mca.mp0.ras_funcs->query_ras_error_count)
 878                         adev->mca.mp0.ras_funcs->query_ras_error_count(adev, &err_data);
 879                 break;
 880         case AMDGPU_RAS_MCA_BLOCK__MP1:
 881                 if (adev->mca.mp1.ras_funcs &&
 882                     adev->mca.mp1.ras_funcs->query_ras_error_count)
 883                         adev->mca.mp1.ras_funcs->query_ras_error_count(adev, &err_data);
 884                 break;
 885         case AMDGPU_RAS_MCA_BLOCK__MPIO:
 886                 if (adev->mca.mpio.ras_funcs &&
 887                     adev->mca.mpio.ras_funcs->query_ras_error_count)
 888                         adev->mca.mpio.ras_funcs->query_ras_error_count(adev, &err_data);
 889                 break;
 890         default:
 891                 break;
 892         }
 893 }
 894
 895 /* query/inject/cure begin */
 896 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 897                                   struct ras_query_if *info)
 898 {
 899         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 900         struct ras_err_data err_data = {0, 0, 0, NULL};
 901         int i;
 902
 903         if (!obj)
 904                 return -EINVAL;
 905
 906         switch (info->head.block) {
 907         case AMDGPU_RAS_BLOCK__UMC:
 908                 if (adev->umc.ras_funcs &&
 909                     adev->umc.ras_funcs->query_ras_error_count)
 910                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 911                 /* umc query_ras_error_address is also responsible for clearing
 912                  * error status
 913                  */
 914                 if (adev->umc.ras_funcs &&
 915                     adev->umc.ras_funcs->query_ras_error_address)
 916                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 917                 break;
 918         case AMDGPU_RAS_BLOCK__SDMA:
 919                 if (adev->sdma.funcs->query_ras_error_count) {
 920                         for (i = 0; i < adev->sdma.num_instances; i++)
 921                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 922                                                                         &err_data);
 923                 }
 924                 break;
 925         case AMDGPU_RAS_BLOCK__GFX:
 926                 if (adev->gfx.ras_funcs &&
 927                     adev->gfx.ras_funcs->query_ras_error_count)
 928                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 929
 930                 if (adev->gfx.ras_funcs &&
 931                     adev->gfx.ras_funcs->query_ras_error_status)
 932                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 933                 break;
 934         case AMDGPU_RAS_BLOCK__MMHUB:
 935                 if (adev->mmhub.ras_funcs &&
 936                     adev->mmhub.ras_funcs->query_ras_error_count)
 937                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 938
 939                 if (adev->mmhub.ras_funcs &&
 940                     adev->mmhub.ras_funcs->query_ras_error_status)
 941                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 942                 break;
 943         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 944                 if (adev->nbio.ras_funcs &&
 945                     adev->nbio.ras_funcs->query_ras_error_count)
 946                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 947                 break;
 948         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 949                 if (adev->gmc.xgmi.ras_funcs &&
 950                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 951                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 952                 break;
 953         case AMDGPU_RAS_BLOCK__HDP:
 954                 if (adev->hdp.ras_funcs &&
 955                     adev->hdp.ras_funcs->query_ras_error_count)
 956                         adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data);
 957                 break;
 958         case AMDGPU_RAS_BLOCK__MCA:
 959                 amdgpu_ras_mca_query_error_status(adev, &info->head, &err_data);
 960                 break;
 961         default:
 962                 break;
 963         }
 964
 965         obj->err_data.ue_count += err_data.ue_count;
 966         obj->err_data.ce_count += err_data.ce_count;
 967
 968         info->ue_count = obj->err_data.ue_count;
 969         info->ce_count = obj->err_data.ce_count;
 970
 971         if (err_data.ce_count) {
 972                 if (adev->smuio.funcs &&
 973                     adev->smuio.funcs->get_socket_id &&
 974                     adev->smuio.funcs->get_die_id) {
 975                         dev_info(adev->dev, "socket: %d, die: %d "
 976                                         "%ld correctable hardware errors "
 977                                         "detected in %s block, no user "
 978                                         "action is needed.\n",
 979                                         adev->smuio.funcs->get_socket_id(adev),
 980                                         adev->smuio.funcs->get_die_id(adev),
 981                                         obj->err_data.ce_count,
 982                                         get_ras_block_str(&info->head));
 983                 } else {
 984                         dev_info(adev->dev, "%ld correctable hardware errors "
 985                                         "detected in %s block, no user "
 986                                         "action is needed.\n",
 987                                         obj->err_data.ce_count,
 988                                         get_ras_block_str(&info->head));
 989                 }
 990         }
 991         if (err_data.ue_count) {
 992                 if (adev->smuio.funcs &&
 993                     adev->smuio.funcs->get_socket_id &&
 994                     adev->smuio.funcs->get_die_id) {
 995                         dev_info(adev->dev, "socket: %d, die: %d "
 996                                         "%ld uncorrectable hardware errors "
 997                                         "detected in %s block\n",
 998                                         adev->smuio.funcs->get_socket_id(adev),
 999                                         adev->smuio.funcs->get_die_id(adev),
1000                                         obj->err_data.ue_count,
1001                                         get_ras_block_str(&info->head));
1002                 } else {
1003                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
1004                                         "detected in %s block\n",
1005                                         obj->err_data.ue_count,
1006                                         get_ras_block_str(&info->head));
1007                 }
1008         }
1009
1010         if (!amdgpu_persistent_edc_harvesting_supported(adev))
1011                 amdgpu_ras_reset_error_status(adev, info->head.block);
1012
1013         return 0;
1014 }
1015
1016 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1017                 enum amdgpu_ras_block block)
1018 {
1019         if (!amdgpu_ras_is_supported(adev, block))
1020                 return -EINVAL;
1021
1022         switch (block) {
1023         case AMDGPU_RAS_BLOCK__GFX:
1024                 if (adev->gfx.ras_funcs &&
1025                     adev->gfx.ras_funcs->reset_ras_error_count)
1026                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
1027
1028                 if (adev->gfx.ras_funcs &&
1029                     adev->gfx.ras_funcs->reset_ras_error_status)
1030                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
1031                 break;
1032         case AMDGPU_RAS_BLOCK__MMHUB:
1033                 if (adev->mmhub.ras_funcs &&
1034                     adev->mmhub.ras_funcs->reset_ras_error_count)
1035                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
1036
1037                 if (adev->mmhub.ras_funcs &&
1038                     adev->mmhub.ras_funcs->reset_ras_error_status)
1039                         adev->mmhub.ras_funcs->reset_ras_error_status(adev);
1040                 break;
1041         case AMDGPU_RAS_BLOCK__SDMA:
1042                 if (adev->sdma.funcs->reset_ras_error_count)
1043                         adev->sdma.funcs->reset_ras_error_count(adev);
1044                 break;
1045         case AMDGPU_RAS_BLOCK__HDP:
1046                 if (adev->hdp.ras_funcs &&
1047                     adev->hdp.ras_funcs->reset_ras_error_count)
1048                         adev->hdp.ras_funcs->reset_ras_error_count(adev);
1049                 break;
1050         default:
1051                 break;
1052         }
1053
1054         return 0;
1055 }
1056
1057 /* Trigger XGMI/WAFL error */
1058 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
1059                                  struct ta_ras_trigger_error_input *block_info)
1060 {
1061         int ret;
1062
1063         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
1064                 dev_warn(adev->dev, "Failed to disallow df cstate");
1065
1066         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
1067                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
1068
1069         ret = psp_ras_trigger_error(&adev->psp, block_info);
1070
1071         if (amdgpu_ras_intr_triggered())
1072                 return ret;
1073
1074         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
1075                 dev_warn(adev->dev, "Failed to allow XGMI power down");
1076
1077         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
1078                 dev_warn(adev->dev, "Failed to allow df cstate");
1079
1080         return ret;
1081 }
1082
1083 /* wrapper of psp_ras_trigger_error */
1084 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1085                 struct ras_inject_if *info)
1086 {
1087         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1088         struct ta_ras_trigger_error_input block_info = {
1089                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1090                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1091                 .sub_block_index = info->head.sub_block_index,
1092                 .address = info->address,
1093                 .value = info->value,
1094         };
1095         int ret = 0;
1096
1097         if (!obj)
1098                 return -EINVAL;
1099
1100         /* Calculate XGMI relative offset */
1101         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1102                 block_info.address =
1103                         amdgpu_xgmi_get_relative_phy_addr(adev,
1104                                                           block_info.address);
1105         }
1106
1107         switch (info->head.block) {
1108         case AMDGPU_RAS_BLOCK__GFX:
1109                 if (adev->gfx.ras_funcs &&
1110                     adev->gfx.ras_funcs->ras_error_inject)
1111                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1112                 else
1113                         ret = -EINVAL;
1114                 break;
1115         case AMDGPU_RAS_BLOCK__UMC:
1116         case AMDGPU_RAS_BLOCK__SDMA:
1117         case AMDGPU_RAS_BLOCK__MMHUB:
1118         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1119         case AMDGPU_RAS_BLOCK__MCA:
1120                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1121                 break;
1122         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1123                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1124                 break;
1125         default:
1126                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1127                          get_ras_block_str(&info->head));
1128                 ret = -EINVAL;
1129         }
1130
1131         if (ret)
1132                 dev_err(adev->dev, "ras inject %s failed %d\n",
1133                         get_ras_block_str(&info->head), ret);
1134
1135         return ret;
1136 }
1137
1138 /**
1139  * amdgpu_ras_query_error_count -- Get error counts of all IPs
1140  * adev: pointer to AMD GPU device
1141  * ce_count: pointer to an integer to be set to the count of correctible errors.
1142  * ue_count: pointer to an integer to be set to the count of uncorrectible
1143  * errors.
1144  *
1145  * If set, @ce_count or @ue_count, count and return the corresponding
1146  * error counts in those integer pointers. Return 0 if the device
1147  * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1148  */
1149 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1150                                  unsigned long *ce_count,
1151                                  unsigned long *ue_count)
1152 {
1153         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1154         struct ras_manager *obj;
1155         unsigned long ce, ue;
1156
1157         if (!adev->ras_enabled || !con)
1158                 return -EOPNOTSUPP;
1159
1160         /* Don't count since no reporting.
1161          */
1162         if (!ce_count && !ue_count)
1163                 return 0;
1164
1165         ce = 0;
1166         ue = 0;
1167         list_for_each_entry(obj, &con->head, node) {
1168                 struct ras_query_if info = {
1169                         .head = obj->head,
1170                 };
1171                 int res;
1172
1173                 res = amdgpu_ras_query_error_status(adev, &info);
1174                 if (res)
1175                         return res;
1176
1177                 ce += info.ce_count;
1178                 ue += info.ue_count;
1179         }
1180
1181         if (ce_count)
1182                 *ce_count = ce;
1183
1184         if (ue_count)
1185                 *ue_count = ue;
1186
1187         return 0;
1188 }
1189 /* query/inject/cure end */
1190
1191
1192 /* sysfs begin */
1193
1194 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1195                 struct ras_badpage **bps, unsigned int *count);
1196
1197 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1198 {
1199         switch (flags) {
1200         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1201                 return "R";
1202         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1203                 return "P";
1204         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1205         default:
1206                 return "F";
1207         }
1208 }
1209
1210 /**
1211  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1212  *
1213  * It allows user to read the bad pages of vram on the gpu through
1214  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1215  *
1216  * It outputs multiple lines, and each line stands for one gpu page.
1217  *
1218  * The format of one line is below,
1219  * gpu pfn : gpu page size : flags
1220  *
1221  * gpu pfn and gpu page size are printed in hex format.
1222  * flags can be one of below character,
1223  *
1224  * R: reserved, this gpu page is reserved and not able to use.
1225  *
1226  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1227  * in next window of page_reserve.
1228  *
1229  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1230  *
1231  * Examples:
1232  *
1233  * .. code-block:: bash
1234  *
1235  *      0x00000001 : 0x00001000 : R
1236  *      0x00000002 : 0x00001000 : P
1237  *
1238  */
1239
1240 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1241                 struct kobject *kobj, struct bin_attribute *attr,
1242                 char *buf, loff_t ppos, size_t count)
1243 {
1244         struct amdgpu_ras *con =
1245                 container_of(attr, struct amdgpu_ras, badpages_attr);
1246         struct amdgpu_device *adev = con->adev;
1247         const unsigned int element_size =
1248                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1249         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1250         unsigned int end = div64_ul(ppos + count - 1, element_size);
1251         ssize_t s = 0;
1252         struct ras_badpage *bps = NULL;
1253         unsigned int bps_count = 0;
1254
1255         memset(buf, 0, count);
1256
1257         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1258                 return 0;
1259
1260         for (; start < end && start < bps_count; start++)
1261                 s += scnprintf(&buf[s], element_size + 1,
1262                                 "0x%08x : 0x%08x : %1s\n",
1263                                 bps[start].bp,
1264                                 bps[start].size,
1265                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1266
1267         kfree(bps);
1268
1269         return s;
1270 }
1271
1272 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1273                 struct device_attribute *attr, char *buf)
1274 {
1275         struct amdgpu_ras *con =
1276                 container_of(attr, struct amdgpu_ras, features_attr);
1277
1278         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1279 }
1280
1281 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1282 {
1283         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1284
1285         sysfs_remove_file_from_group(&adev->dev->kobj,
1286                                 &con->badpages_attr.attr,
1287                                 RAS_FS_NAME);
1288 }
1289
1290 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1291 {
1292         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1293         struct attribute *attrs[] = {
1294                 &con->features_attr.attr,
1295                 NULL
1296         };
1297         struct attribute_group group = {
1298                 .name = RAS_FS_NAME,
1299                 .attrs = attrs,
1300         };
1301
1302         sysfs_remove_group(&adev->dev->kobj, &group);
1303
1304         return 0;
1305 }
1306
1307 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1308                 struct ras_fs_if *head)
1309 {
1310         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1311
1312         if (!obj || obj->attr_inuse)
1313                 return -EINVAL;
1314
1315         get_obj(obj);
1316
1317         memcpy(obj->fs_data.sysfs_name,
1318                         head->sysfs_name,
1319                         sizeof(obj->fs_data.sysfs_name));
1320
1321         obj->sysfs_attr = (struct device_attribute){
1322                 .attr = {
1323                         .name = obj->fs_data.sysfs_name,
1324                         .mode = S_IRUGO,
1325                 },
1326                         .show = amdgpu_ras_sysfs_read,
1327         };
1328         sysfs_attr_init(&obj->sysfs_attr.attr);
1329
1330         if (sysfs_add_file_to_group(&adev->dev->kobj,
1331                                 &obj->sysfs_attr.attr,
1332                                 RAS_FS_NAME)) {
1333                 put_obj(obj);
1334                 return -EINVAL;
1335         }
1336
1337         obj->attr_inuse = 1;
1338
1339         return 0;
1340 }
1341
1342 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1343                 struct ras_common_if *head)
1344 {
1345         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1346
1347         if (!obj || !obj->attr_inuse)
1348                 return -EINVAL;
1349
1350         sysfs_remove_file_from_group(&adev->dev->kobj,
1351                                 &obj->sysfs_attr.attr,
1352                                 RAS_FS_NAME);
1353         obj->attr_inuse = 0;
1354         put_obj(obj);
1355
1356         return 0;
1357 }
1358
1359 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1360 {
1361         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1362         struct ras_manager *obj, *tmp;
1363
1364         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1365                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1366         }
1367
1368         if (amdgpu_bad_page_threshold != 0)
1369                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1370
1371         amdgpu_ras_sysfs_remove_feature_node(adev);
1372
1373         return 0;
1374 }
1375 /* sysfs end */
1376
1377 /**
1378  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1379  *
1380  * Normally when there is an uncorrectable error, the driver will reset
1381  * the GPU to recover.  However, in the event of an unrecoverable error,
1382  * the driver provides an interface to reboot the system automatically
1383  * in that event.
1384  *
1385  * The following file in debugfs provides that interface:
1386  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1387  *
1388  * Usage:
1389  *
1390  * .. code-block:: bash
1391  *
1392  *      echo true > .../ras/auto_reboot
1393  *
1394  */
1395 /* debugfs begin */
1396 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1397 {
1398         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1399         struct drm_minor  *minor = adev_to_drm(adev)->primary;
1400         struct dentry     *dir;
1401
1402         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1403         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1404                             &amdgpu_ras_debugfs_ctrl_ops);
1405         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1406                             &amdgpu_ras_debugfs_eeprom_ops);
1407         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1408                            &con->bad_page_cnt_threshold);
1409         debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1410         debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
1411         debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1412                             &amdgpu_ras_debugfs_eeprom_size_ops);
1413         con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1414                                                        S_IRUGO, dir, adev,
1415                                                        &amdgpu_ras_debugfs_eeprom_table_ops);
1416         amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
1417
1418         /*
1419          * After one uncorrectable error happens, usually GPU recovery will
1420          * be scheduled. But due to the known problem in GPU recovery failing
1421          * to bring GPU back, below interface provides one direct way to
1422          * user to reboot system automatically in such case within
1423          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1424          * will never be called.
1425          */
1426         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1427
1428         /*
1429          * User could set this not to clean up hardware's error count register
1430          * of RAS IPs during ras recovery.
1431          */
1432         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1433                             &con->disable_ras_err_cnt_harvest);
1434         return dir;
1435 }
1436
1437 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1438                                       struct ras_fs_if *head,
1439                                       struct dentry *dir)
1440 {
1441         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1442
1443         if (!obj || !dir)
1444                 return;
1445
1446         get_obj(obj);
1447
1448         memcpy(obj->fs_data.debugfs_name,
1449                         head->debugfs_name,
1450                         sizeof(obj->fs_data.debugfs_name));
1451
1452         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1453                             obj, &amdgpu_ras_debugfs_ops);
1454 }
1455
1456 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1457 {
1458         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1459         struct dentry *dir;
1460         struct ras_manager *obj;
1461         struct ras_fs_if fs_info;
1462
1463         /*
1464          * it won't be called in resume path, no need to check
1465          * suspend and gpu reset status
1466          */
1467         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1468                 return;
1469
1470         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1471
1472         list_for_each_entry(obj, &con->head, node) {
1473                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1474                         (obj->attr_inuse == 1)) {
1475                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1476                                         get_ras_block_str(&obj->head));
1477                         fs_info.head = obj->head;
1478                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1479                 }
1480         }
1481 }
1482
1483 /* debugfs end */
1484
1485 /* ras fs */
1486 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1487                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1488 static DEVICE_ATTR(features, S_IRUGO,
1489                 amdgpu_ras_sysfs_features_read, NULL);
1490 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1491 {
1492         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1493         struct attribute_group group = {
1494                 .name = RAS_FS_NAME,
1495         };
1496         struct attribute *attrs[] = {
1497                 &con->features_attr.attr,
1498                 NULL
1499         };
1500         struct bin_attribute *bin_attrs[] = {
1501                 NULL,
1502                 NULL,
1503         };
1504         int r;
1505
1506         /* add features entry */
1507         con->features_attr = dev_attr_features;
1508         group.attrs = attrs;
1509         sysfs_attr_init(attrs[0]);
1510
1511         if (amdgpu_bad_page_threshold != 0) {
1512                 /* add bad_page_features entry */
1513                 bin_attr_gpu_vram_bad_pages.private = NULL;
1514                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1515                 bin_attrs[0] = &con->badpages_attr;
1516                 group.bin_attrs = bin_attrs;
1517                 sysfs_bin_attr_init(bin_attrs[0]);
1518         }
1519
1520         r = sysfs_create_group(&adev->dev->kobj, &group);
1521         if (r)
1522                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1523
1524         return 0;
1525 }
1526
1527 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1528 {
1529         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1530         struct ras_manager *con_obj, *ip_obj, *tmp;
1531
1532         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1533                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1534                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1535                         if (ip_obj)
1536                                 put_obj(ip_obj);
1537                 }
1538         }
1539
1540         amdgpu_ras_sysfs_remove_all(adev);
1541         return 0;
1542 }
1543 /* ras fs end */
1544
1545 /* ih begin */
1546 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1547 {
1548         struct ras_ih_data *data = &obj->ih_data;
1549         struct amdgpu_iv_entry entry;
1550         int ret;
1551         struct ras_err_data err_data = {0, 0, 0, NULL};
1552
1553         while (data->rptr != data->wptr) {
1554                 rmb();
1555                 memcpy(&entry, &data->ring[data->rptr],
1556                                 data->element_size);
1557
1558                 wmb();
1559                 data->rptr = (data->aligned_element_size +
1560                                 data->rptr) % data->ring_size;
1561
1562                 if (data->cb) {
1563                         if (amdgpu_ras_is_poison_mode_supported(obj->adev) &&
1564                             obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1565                                 dev_info(obj->adev->dev,
1566                                                 "Poison is created, no user action is needed.\n");
1567                         else {
1568                                 /* Let IP handle its data, maybe we need get the output
1569                                  * from the callback to udpate the error type/count, etc
1570                                  */
1571                                 ret = data->cb(obj->adev, &err_data, &entry);
1572                                 /* ue will trigger an interrupt, and in that case
1573                                  * we need do a reset to recovery the whole system.
1574                                  * But leave IP do that recovery, here we just dispatch
1575                                  * the error.
1576                                  */
1577                                 if (ret == AMDGPU_RAS_SUCCESS) {
1578                                         /* these counts could be left as 0 if
1579                                          * some blocks do not count error number
1580                                          */
1581                                         obj->err_data.ue_count += err_data.ue_count;
1582                                         obj->err_data.ce_count += err_data.ce_count;
1583                                 }
1584                         }
1585                 }
1586         }
1587 }
1588
1589 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1590 {
1591         struct ras_ih_data *data =
1592                 container_of(work, struct ras_ih_data, ih_work);
1593         struct ras_manager *obj =
1594                 container_of(data, struct ras_manager, ih_data);
1595
1596         amdgpu_ras_interrupt_handler(obj);
1597 }
1598
1599 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1600                 struct ras_dispatch_if *info)
1601 {
1602         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1603         struct ras_ih_data *data = &obj->ih_data;
1604
1605         if (!obj)
1606                 return -EINVAL;
1607
1608         if (data->inuse == 0)
1609                 return 0;
1610
1611         /* Might be overflow... */
1612         memcpy(&data->ring[data->wptr], info->entry,
1613                         data->element_size);
1614
1615         wmb();
1616         data->wptr = (data->aligned_element_size +
1617                         data->wptr) % data->ring_size;
1618
1619         schedule_work(&data->ih_work);
1620
1621         return 0;
1622 }
1623
1624 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1625                 struct ras_ih_if *info)
1626 {
1627         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1628         struct ras_ih_data *data;
1629
1630         if (!obj)
1631                 return -EINVAL;
1632
1633         data = &obj->ih_data;
1634         if (data->inuse == 0)
1635                 return 0;
1636
1637         cancel_work_sync(&data->ih_work);
1638
1639         kfree(data->ring);
1640         memset(data, 0, sizeof(*data));
1641         put_obj(obj);
1642
1643         return 0;
1644 }
1645
1646 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1647                 struct ras_ih_if *info)
1648 {
1649         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1650         struct ras_ih_data *data;
1651
1652         if (!obj) {
1653                 /* in case we registe the IH before enable ras feature */
1654                 obj = amdgpu_ras_create_obj(adev, &info->head);
1655                 if (!obj)
1656                         return -EINVAL;
1657         } else
1658                 get_obj(obj);
1659
1660         data = &obj->ih_data;
1661         /* add the callback.etc */
1662         *data = (struct ras_ih_data) {
1663                 .inuse = 0,
1664                 .cb = info->cb,
1665                 .element_size = sizeof(struct amdgpu_iv_entry),
1666                 .rptr = 0,
1667                 .wptr = 0,
1668         };
1669
1670         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1671
1672         data->aligned_element_size = ALIGN(data->element_size, 8);
1673         /* the ring can store 64 iv entries. */
1674         data->ring_size = 64 * data->aligned_element_size;
1675         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1676         if (!data->ring) {
1677                 put_obj(obj);
1678                 return -ENOMEM;
1679         }
1680
1681         /* IH is ready */
1682         data->inuse = 1;
1683
1684         return 0;
1685 }
1686
1687 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1688 {
1689         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1690         struct ras_manager *obj, *tmp;
1691
1692         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1693                 struct ras_ih_if info = {
1694                         .head = obj->head,
1695                 };
1696                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1697         }
1698
1699         return 0;
1700 }
1701 /* ih end */
1702
1703 /* traversal all IPs except NBIO to query error counter */
1704 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1705 {
1706         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1707         struct ras_manager *obj;
1708
1709         if (!adev->ras_enabled || !con)
1710                 return;
1711
1712         list_for_each_entry(obj, &con->head, node) {
1713                 struct ras_query_if info = {
1714                         .head = obj->head,
1715                 };
1716
1717                 /*
1718                  * PCIE_BIF IP has one different isr by ras controller
1719                  * interrupt, the specific ras counter query will be
1720                  * done in that isr. So skip such block from common
1721                  * sync flood interrupt isr calling.
1722                  */
1723                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1724                         continue;
1725
1726                 amdgpu_ras_query_error_status(adev, &info);
1727         }
1728 }
1729
1730 /* Parse RdRspStatus and WrRspStatus */
1731 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1732                                           struct ras_query_if *info)
1733 {
1734         /*
1735          * Only two block need to query read/write
1736          * RspStatus at current state
1737          */
1738         switch (info->head.block) {
1739         case AMDGPU_RAS_BLOCK__GFX:
1740                 if (adev->gfx.ras_funcs &&
1741                     adev->gfx.ras_funcs->query_ras_error_status)
1742                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1743                 break;
1744         case AMDGPU_RAS_BLOCK__MMHUB:
1745                 if (adev->mmhub.ras_funcs &&
1746                     adev->mmhub.ras_funcs->query_ras_error_status)
1747                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1748                 break;
1749         default:
1750                 break;
1751         }
1752 }
1753
1754 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1755 {
1756         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1757         struct ras_manager *obj;
1758
1759         if (!adev->ras_enabled || !con)
1760                 return;
1761
1762         list_for_each_entry(obj, &con->head, node) {
1763                 struct ras_query_if info = {
1764                         .head = obj->head,
1765                 };
1766
1767                 amdgpu_ras_error_status_query(adev, &info);
1768         }
1769 }
1770
1771 /* recovery begin */
1772
1773 /* return 0 on success.
1774  * caller need free bps.
1775  */
1776 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1777                 struct ras_badpage **bps, unsigned int *count)
1778 {
1779         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1780         struct ras_err_handler_data *data;
1781         int i = 0;
1782         int ret = 0, status;
1783
1784         if (!con || !con->eh_data || !bps || !count)
1785                 return -EINVAL;
1786
1787         mutex_lock(&con->recovery_lock);
1788         data = con->eh_data;
1789         if (!data || data->count == 0) {
1790                 *bps = NULL;
1791                 ret = -EINVAL;
1792                 goto out;
1793         }
1794
1795         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1796         if (!*bps) {
1797                 ret = -ENOMEM;
1798                 goto out;
1799         }
1800
1801         for (; i < data->count; i++) {
1802                 (*bps)[i] = (struct ras_badpage){
1803                         .bp = data->bps[i].retired_page,
1804                         .size = AMDGPU_GPU_PAGE_SIZE,
1805                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1806                 };
1807                 status = amdgpu_vram_mgr_query_page_status(
1808                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1809                                 data->bps[i].retired_page);
1810                 if (status == -EBUSY)
1811                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1812                 else if (status == -ENOENT)
1813                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1814         }
1815
1816         *count = data->count;
1817 out:
1818         mutex_unlock(&con->recovery_lock);
1819         return ret;
1820 }
1821
1822 static void amdgpu_ras_do_recovery(struct work_struct *work)
1823 {
1824         struct amdgpu_ras *ras =
1825                 container_of(work, struct amdgpu_ras, recovery_work);
1826         struct amdgpu_device *remote_adev = NULL;
1827         struct amdgpu_device *adev = ras->adev;
1828         struct list_head device_list, *device_list_handle =  NULL;
1829
1830         if (!ras->disable_ras_err_cnt_harvest) {
1831                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1832
1833                 /* Build list of devices to query RAS related errors */
1834                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1835                         device_list_handle = &hive->device_list;
1836                 } else {
1837                         INIT_LIST_HEAD(&device_list);
1838                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1839                         device_list_handle = &device_list;
1840                 }
1841
1842                 list_for_each_entry(remote_adev,
1843                                 device_list_handle, gmc.xgmi.head) {
1844                         amdgpu_ras_query_err_status(remote_adev);
1845                         amdgpu_ras_log_on_err_counter(remote_adev);
1846                 }
1847
1848                 amdgpu_put_xgmi_hive(hive);
1849         }
1850
1851         if (amdgpu_device_should_recover_gpu(ras->adev))
1852                 amdgpu_device_gpu_recover(ras->adev, NULL);
1853         atomic_set(&ras->in_recovery, 0);
1854 }
1855
1856 /* alloc/realloc bps array */
1857 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1858                 struct ras_err_handler_data *data, int pages)
1859 {
1860         unsigned int old_space = data->count + data->space_left;
1861         unsigned int new_space = old_space + pages;
1862         unsigned int align_space = ALIGN(new_space, 512);
1863         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1864
1865         if (!bps) {
1866                 kfree(bps);
1867                 return -ENOMEM;
1868         }
1869
1870         if (data->bps) {
1871                 memcpy(bps, data->bps,
1872                                 data->count * sizeof(*data->bps));
1873                 kfree(data->bps);
1874         }
1875
1876         data->bps = bps;
1877         data->space_left += align_space - old_space;
1878         return 0;
1879 }
1880
1881 /* it deal with vram only. */
1882 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1883                 struct eeprom_table_record *bps, int pages)
1884 {
1885         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1886         struct ras_err_handler_data *data;
1887         int ret = 0;
1888         uint32_t i;
1889
1890         if (!con || !con->eh_data || !bps || pages <= 0)
1891                 return 0;
1892
1893         mutex_lock(&con->recovery_lock);
1894         data = con->eh_data;
1895         if (!data)
1896                 goto out;
1897
1898         for (i = 0; i < pages; i++) {
1899                 if (amdgpu_ras_check_bad_page_unlock(con,
1900                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1901                         continue;
1902
1903                 if (!data->space_left &&
1904                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1905                         ret = -ENOMEM;
1906                         goto out;
1907                 }
1908
1909                 amdgpu_vram_mgr_reserve_range(
1910                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1911                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1912                         AMDGPU_GPU_PAGE_SIZE);
1913
1914                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1915                 data->count++;
1916                 data->space_left--;
1917         }
1918 out:
1919         mutex_unlock(&con->recovery_lock);
1920
1921         return ret;
1922 }
1923
1924 /*
1925  * write error record array to eeprom, the function should be
1926  * protected by recovery_lock
1927  */
1928 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1929 {
1930         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1931         struct ras_err_handler_data *data;
1932         struct amdgpu_ras_eeprom_control *control;
1933         int save_count;
1934
1935         if (!con || !con->eh_data)
1936                 return 0;
1937
1938         control = &con->eeprom_control;
1939         data = con->eh_data;
1940         save_count = data->count - control->ras_num_recs;
1941         /* only new entries are saved */
1942         if (save_count > 0) {
1943                 if (amdgpu_ras_eeprom_append(control,
1944                                              &data->bps[control->ras_num_recs],
1945                                              save_count)) {
1946                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1947                         return -EIO;
1948                 }
1949
1950                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1951         }
1952
1953         return 0;
1954 }
1955
1956 /*
1957  * read error record array in eeprom and reserve enough space for
1958  * storing new bad pages
1959  */
1960 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1961 {
1962         struct amdgpu_ras_eeprom_control *control =
1963                 &adev->psp.ras_context.ras->eeprom_control;
1964         struct eeprom_table_record *bps;
1965         int ret;
1966
1967         /* no bad page record, skip eeprom access */
1968         if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
1969                 return 0;
1970
1971         bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
1972         if (!bps)
1973                 return -ENOMEM;
1974
1975         ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
1976         if (ret)
1977                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1978         else
1979                 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
1980
1981         kfree(bps);
1982         return ret;
1983 }
1984
1985 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1986                                 uint64_t addr)
1987 {
1988         struct ras_err_handler_data *data = con->eh_data;
1989         int i;
1990
1991         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1992         for (i = 0; i < data->count; i++)
1993                 if (addr == data->bps[i].retired_page)
1994                         return true;
1995
1996         return false;
1997 }
1998
1999 /*
2000  * check if an address belongs to bad page
2001  *
2002  * Note: this check is only for umc block
2003  */
2004 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2005                                 uint64_t addr)
2006 {
2007         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2008         bool ret = false;
2009
2010         if (!con || !con->eh_data)
2011                 return ret;
2012
2013         mutex_lock(&con->recovery_lock);
2014         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
2015         mutex_unlock(&con->recovery_lock);
2016         return ret;
2017 }
2018
2019 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
2020                                           uint32_t max_count)
2021 {
2022         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2023
2024         /*
2025          * Justification of value bad_page_cnt_threshold in ras structure
2026          *
2027          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
2028          * in eeprom, and introduce two scenarios accordingly.
2029          *
2030          * Bad page retirement enablement:
2031          *    - If amdgpu_bad_page_threshold = -1,
2032          *      bad_page_cnt_threshold = typical value by formula.
2033          *
2034          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
2035          *      max record length in eeprom, use it directly.
2036          *
2037          * Bad page retirement disablement:
2038          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
2039          *      functionality is disabled, and bad_page_cnt_threshold will
2040          *      take no effect.
2041          */
2042
2043         if (amdgpu_bad_page_threshold < 0) {
2044                 u64 val = adev->gmc.mc_vram_size;
2045
2046                 do_div(val, RAS_BAD_PAGE_COVER);
2047                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
2048                                                   max_count);
2049         } else {
2050                 con->bad_page_cnt_threshold = min_t(int, max_count,
2051                                                     amdgpu_bad_page_threshold);
2052         }
2053 }
2054
2055 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2056 {
2057         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2058         struct ras_err_handler_data **data;
2059         u32  max_eeprom_records_count = 0;
2060         bool exc_err_limit = false;
2061         int ret;
2062
2063         if (!con)
2064                 return 0;
2065
2066         /* Allow access to RAS EEPROM via debugfs, when the ASIC
2067          * supports RAS and debugfs is enabled, but when
2068          * adev->ras_enabled is unset, i.e. when "ras_enable"
2069          * module parameter is set to 0.
2070          */
2071         con->adev = adev;
2072
2073         if (!adev->ras_enabled)
2074                 return 0;
2075
2076         data = &con->eh_data;
2077         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2078         if (!*data) {
2079                 ret = -ENOMEM;
2080                 goto out;
2081         }
2082
2083         mutex_init(&con->recovery_lock);
2084         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2085         atomic_set(&con->in_recovery, 0);
2086
2087         max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
2088         amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
2089
2090         /* Todo: During test the SMU might fail to read the eeprom through I2C
2091          * when the GPU is pending on XGMI reset during probe time
2092          * (Mostly after second bus reset), skip it now
2093          */
2094         if (adev->gmc.xgmi.pending_reset)
2095                 return 0;
2096         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2097         /*
2098          * This calling fails when exc_err_limit is true or
2099          * ret != 0.
2100          */
2101         if (exc_err_limit || ret)
2102                 goto free;
2103
2104         if (con->eeprom_control.ras_num_recs) {
2105                 ret = amdgpu_ras_load_bad_pages(adev);
2106                 if (ret)
2107                         goto free;
2108
2109                 if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num)
2110                         adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
2111         }
2112
2113 #ifdef CONFIG_X86_MCE_AMD
2114         if ((adev->asic_type == CHIP_ALDEBARAN) &&
2115             (adev->gmc.xgmi.connected_to_cpu))
2116                 amdgpu_register_bad_pages_mca_notifier(adev);
2117 #endif
2118         return 0;
2119
2120 free:
2121         kfree((*data)->bps);
2122         kfree(*data);
2123         con->eh_data = NULL;
2124 out:
2125         dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
2126
2127         /*
2128          * Except error threshold exceeding case, other failure cases in this
2129          * function would not fail amdgpu driver init.
2130          */
2131         if (!exc_err_limit)
2132                 ret = 0;
2133         else
2134                 ret = -EINVAL;
2135
2136         return ret;
2137 }
2138
2139 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2140 {
2141         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2142         struct ras_err_handler_data *data = con->eh_data;
2143
2144         /* recovery_init failed to init it, fini is useless */
2145         if (!data)
2146                 return 0;
2147
2148         cancel_work_sync(&con->recovery_work);
2149
2150         mutex_lock(&con->recovery_lock);
2151         con->eh_data = NULL;
2152         kfree(data->bps);
2153         kfree(data);
2154         mutex_unlock(&con->recovery_lock);
2155
2156         return 0;
2157 }
2158 /* recovery end */
2159
2160 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2161 {
2162         return adev->asic_type == CHIP_VEGA10 ||
2163                 adev->asic_type == CHIP_VEGA20 ||
2164                 adev->asic_type == CHIP_ARCTURUS ||
2165                 adev->asic_type == CHIP_ALDEBARAN ||
2166                 adev->asic_type == CHIP_SIENNA_CICHLID;
2167 }
2168
2169 /*
2170  * this is workaround for vega20 workstation sku,
2171  * force enable gfx ras, ignore vbios gfx ras flag
2172  * due to GC EDC can not write
2173  */
2174 static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2175 {
2176         struct atom_context *ctx = adev->mode_info.atom_context;
2177
2178         if (!ctx)
2179                 return;
2180
2181         if (strnstr(ctx->vbios_version, "D16406",
2182                     sizeof(ctx->vbios_version)) ||
2183                 strnstr(ctx->vbios_version, "D36002",
2184                         sizeof(ctx->vbios_version)))
2185                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2186 }
2187
2188 /*
2189  * check hardware's ras ability which will be saved in hw_supported.
2190  * if hardware does not support ras, we can skip some ras initializtion and
2191  * forbid some ras operations from IP.
2192  * if software itself, say boot parameter, limit the ras ability. We still
2193  * need allow IP do some limited operations, like disable. In such case,
2194  * we have to initialize ras as normal. but need check if operation is
2195  * allowed or not in each function.
2196  */
2197 static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2198 {
2199         adev->ras_hw_enabled = adev->ras_enabled = 0;
2200
2201         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2202             !amdgpu_ras_asic_supported(adev))
2203                 return;
2204
2205         if (!adev->gmc.xgmi.connected_to_cpu) {
2206                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2207                         dev_info(adev->dev, "MEM ECC is active.\n");
2208                         adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
2209                                                    1 << AMDGPU_RAS_BLOCK__DF);
2210                 } else {
2211                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2212                 }
2213
2214                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2215                         dev_info(adev->dev, "SRAM ECC is active.\n");
2216                         adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2217                                                     1 << AMDGPU_RAS_BLOCK__DF);
2218                 } else {
2219                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2220                 }
2221         } else {
2222                 /* driver only manages a few IP blocks RAS feature
2223                  * when GPU is connected cpu through XGMI */
2224                 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
2225                                            1 << AMDGPU_RAS_BLOCK__SDMA |
2226                                            1 << AMDGPU_RAS_BLOCK__MMHUB);
2227         }
2228
2229         amdgpu_ras_get_quirks(adev);
2230
2231         /* hw_supported needs to be aligned with RAS block mask. */
2232         adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
2233
2234         adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2235                 adev->ras_hw_enabled & amdgpu_ras_mask;
2236 }
2237
2238 static void amdgpu_ras_counte_dw(struct work_struct *work)
2239 {
2240         struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2241                                               ras_counte_delay_work.work);
2242         struct amdgpu_device *adev = con->adev;
2243         struct drm_device *dev = adev_to_drm(adev);
2244         unsigned long ce_count, ue_count;
2245         int res;
2246
2247         res = pm_runtime_get_sync(dev->dev);
2248         if (res < 0)
2249                 goto Out;
2250
2251         /* Cache new values.
2252          */
2253         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2254                 atomic_set(&con->ras_ce_count, ce_count);
2255                 atomic_set(&con->ras_ue_count, ue_count);
2256         }
2257
2258         pm_runtime_mark_last_busy(dev->dev);
2259 Out:
2260         pm_runtime_put_autosuspend(dev->dev);
2261 }
2262
2263 int amdgpu_ras_init(struct amdgpu_device *adev)
2264 {
2265         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2266         int r;
2267         bool df_poison, umc_poison;
2268
2269         if (con)
2270                 return 0;
2271
2272         con = kmalloc(sizeof(struct amdgpu_ras) +
2273                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2274                         sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
2275                         GFP_KERNEL|__GFP_ZERO);
2276         if (!con)
2277                 return -ENOMEM;
2278
2279         con->adev = adev;
2280         INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2281         atomic_set(&con->ras_ce_count, 0);
2282         atomic_set(&con->ras_ue_count, 0);
2283
2284         con->objs = (struct ras_manager *)(con + 1);
2285
2286         amdgpu_ras_set_context(adev, con);
2287
2288         amdgpu_ras_check_supported(adev);
2289
2290         if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
2291                 /* set gfx block ras context feature for VEGA20 Gaming
2292                  * send ras disable cmd to ras ta during ras late init.
2293                  */
2294                 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
2295                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2296
2297                         return 0;
2298                 }
2299
2300                 r = 0;
2301                 goto release_con;
2302         }
2303
2304         con->features = 0;
2305         INIT_LIST_HEAD(&con->head);
2306         /* Might need get this flag from vbios. */
2307         con->flags = RAS_DEFAULT_FLAGS;
2308
2309         /* initialize nbio ras function ahead of any other
2310          * ras functions so hardware fatal error interrupt
2311          * can be enabled as early as possible */
2312         switch (adev->asic_type) {
2313         case CHIP_VEGA20:
2314         case CHIP_ARCTURUS:
2315         case CHIP_ALDEBARAN:
2316                 if (!adev->gmc.xgmi.connected_to_cpu)
2317                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2318                 break;
2319         default:
2320                 /* nbio ras is not available */
2321                 break;
2322         }
2323
2324         if (adev->nbio.ras_funcs &&
2325             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2326                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2327                 if (r)
2328                         goto release_con;
2329         }
2330
2331         if (adev->nbio.ras_funcs &&
2332             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2333                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2334                 if (r)
2335                         goto release_con;
2336         }
2337
2338         /* Init poison supported flag, the default value is false */
2339         if (adev->df.funcs &&
2340             adev->df.funcs->query_ras_poison_mode &&
2341             adev->umc.ras_funcs &&
2342             adev->umc.ras_funcs->query_ras_poison_mode) {
2343                 df_poison =
2344                         adev->df.funcs->query_ras_poison_mode(adev);
2345                 umc_poison =
2346                         adev->umc.ras_funcs->query_ras_poison_mode(adev);
2347                 /* Only poison is set in both DF and UMC, we can support it */
2348                 if (df_poison && umc_poison)
2349                         con->poison_supported = true;
2350                 else if (df_poison != umc_poison)
2351                         dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2352                                         df_poison, umc_poison);
2353         }
2354
2355         if (amdgpu_ras_fs_init(adev)) {
2356                 r = -EINVAL;
2357                 goto release_con;
2358         }
2359
2360         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2361                  "hardware ability[%x] ras_mask[%x]\n",
2362                  adev->ras_hw_enabled, adev->ras_enabled);
2363
2364         return 0;
2365 release_con:
2366         amdgpu_ras_set_context(adev, NULL);
2367         kfree(con);
2368
2369         return r;
2370 }
2371
2372 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2373 {
2374         if (adev->gmc.xgmi.connected_to_cpu)
2375                 return 1;
2376         return 0;
2377 }
2378
2379 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2380                                         struct ras_common_if *ras_block)
2381 {
2382         struct ras_query_if info = {
2383                 .head = *ras_block,
2384         };
2385
2386         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2387                 return 0;
2388
2389         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2390                 DRM_WARN("RAS init harvest failure");
2391
2392         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2393                 DRM_WARN("RAS init harvest reset failure");
2394
2395         return 0;
2396 }
2397
2398 bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2399 {
2400        struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2401
2402        if (!con)
2403                return false;
2404
2405        return con->poison_supported;
2406 }
2407
2408 /* helper function to handle common stuff in ip late init phase */
2409 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2410                          struct ras_common_if *ras_block,
2411                          struct ras_fs_if *fs_info,
2412                          struct ras_ih_if *ih_info)
2413 {
2414         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2415         unsigned long ue_count, ce_count;
2416         int r;
2417
2418         /* disable RAS feature per IP block if it is not supported */
2419         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2420                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2421                 return 0;
2422         }
2423
2424         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2425         if (r) {
2426                 if (adev->in_suspend || amdgpu_in_reset(adev)) {
2427                         /* in resume phase, if fail to enable ras,
2428                          * clean up all ras fs nodes, and disable ras */
2429                         goto cleanup;
2430                 } else
2431                         return r;
2432         }
2433
2434         /* check for errors on warm reset edc persisant supported ASIC */
2435         amdgpu_persistent_edc_harvesting(adev, ras_block);
2436
2437         /* in resume phase, no need to create ras fs node */
2438         if (adev->in_suspend || amdgpu_in_reset(adev))
2439                 return 0;
2440
2441         if (ih_info->cb) {
2442                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2443                 if (r)
2444                         goto interrupt;
2445         }
2446
2447         r = amdgpu_ras_sysfs_create(adev, fs_info);
2448         if (r)
2449                 goto sysfs;
2450
2451         /* Those are the cached values at init.
2452          */
2453         if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2454                 atomic_set(&con->ras_ce_count, ce_count);
2455                 atomic_set(&con->ras_ue_count, ue_count);
2456         }
2457
2458         return 0;
2459 cleanup:
2460         amdgpu_ras_sysfs_remove(adev, ras_block);
2461 sysfs:
2462         if (ih_info->cb)
2463                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2464 interrupt:
2465         amdgpu_ras_feature_enable(adev, ras_block, 0);
2466         return r;
2467 }
2468
2469 /* helper function to remove ras fs node and interrupt handler */
2470 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2471                           struct ras_common_if *ras_block,
2472                           struct ras_ih_if *ih_info)
2473 {
2474         if (!ras_block || !ih_info)
2475                 return;
2476
2477         amdgpu_ras_sysfs_remove(adev, ras_block);
2478         if (ih_info->cb)
2479                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2480         amdgpu_ras_feature_enable(adev, ras_block, 0);
2481 }
2482
2483 /* do some init work after IP late init as dependence.
2484  * and it runs in resume/gpu reset/booting up cases.
2485  */
2486 void amdgpu_ras_resume(struct amdgpu_device *adev)
2487 {
2488         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2489         struct ras_manager *obj, *tmp;
2490
2491         if (!adev->ras_enabled || !con) {
2492                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2493                 amdgpu_release_ras_context(adev);
2494
2495                 return;
2496         }
2497
2498         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2499                 /* Set up all other IPs which are not implemented. There is a
2500                  * tricky thing that IP's actual ras error type should be
2501                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2502                  * ERROR_NONE make sense anyway.
2503                  */
2504                 amdgpu_ras_enable_all_features(adev, 1);
2505
2506                 /* We enable ras on all hw_supported block, but as boot
2507                  * parameter might disable some of them and one or more IP has
2508                  * not implemented yet. So we disable them on behalf.
2509                  */
2510                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2511                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2512                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2513                                 /* there should be no any reference. */
2514                                 WARN_ON(alive_obj(obj));
2515                         }
2516                 }
2517         }
2518 }
2519
2520 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2521 {
2522         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2523
2524         if (!adev->ras_enabled || !con)
2525                 return;
2526
2527         amdgpu_ras_disable_all_features(adev, 0);
2528         /* Make sure all ras objects are disabled. */
2529         if (con->features)
2530                 amdgpu_ras_disable_all_features(adev, 1);
2531 }
2532
2533 /* do some fini work before IP fini as dependence */
2534 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2535 {
2536         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2537
2538         if (!adev->ras_enabled || !con)
2539                 return 0;
2540
2541
2542         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2543         amdgpu_ras_disable_all_features(adev, 0);
2544         amdgpu_ras_recovery_fini(adev);
2545         return 0;
2546 }
2547
2548 int amdgpu_ras_fini(struct amdgpu_device *adev)
2549 {
2550         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2551
2552         if (!adev->ras_enabled || !con)
2553                 return 0;
2554
2555         amdgpu_ras_fs_fini(adev);
2556         amdgpu_ras_interrupt_remove_all(adev);
2557
2558         WARN(con->features, "Feature mask is not cleared");
2559
2560         if (con->features)
2561                 amdgpu_ras_disable_all_features(adev, 1);
2562
2563         cancel_delayed_work_sync(&con->ras_counte_delay_work);
2564
2565         amdgpu_ras_set_context(adev, NULL);
2566         kfree(con);
2567
2568         return 0;
2569 }
2570
2571 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2572 {
2573         amdgpu_ras_check_supported(adev);
2574         if (!adev->ras_hw_enabled)
2575                 return;
2576
2577         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2578                 dev_info(adev->dev, "uncorrectable hardware error"
2579                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2580
2581                 amdgpu_ras_reset_gpu(adev);
2582         }
2583 }
2584
2585 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2586 {
2587         if (adev->asic_type == CHIP_VEGA20 &&
2588             adev->pm.fw_version <= 0x283400) {
2589                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2590                                 amdgpu_ras_intr_triggered();
2591         }
2592
2593         return false;
2594 }
2595
2596 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2597 {
2598         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2599
2600         if (!con)
2601                 return;
2602
2603         if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2604                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2605                 amdgpu_ras_set_context(adev, NULL);
2606                 kfree(con);
2607         }
2608 }
2609
2610 #ifdef CONFIG_X86_MCE_AMD
2611 static struct amdgpu_device *find_adev(uint32_t node_id)
2612 {
2613         int i;
2614         struct amdgpu_device *adev = NULL;
2615
2616         for (i = 0; i < mce_adev_list.num_gpu; i++) {
2617                 adev = mce_adev_list.devs[i];
2618
2619                 if (adev && adev->gmc.xgmi.connected_to_cpu &&
2620                     adev->gmc.xgmi.physical_node_id == node_id)
2621                         break;
2622                 adev = NULL;
2623         }
2624
2625         return adev;
2626 }
2627
2628 #define GET_MCA_IPID_GPUID(m)   (((m) >> 44) & 0xF)
2629 #define GET_UMC_INST(m)         (((m) >> 21) & 0x7)
2630 #define GET_CHAN_INDEX(m)       ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
2631 #define GPU_ID_OFFSET           8
2632
2633 static int amdgpu_bad_page_notifier(struct notifier_block *nb,
2634                                     unsigned long val, void *data)
2635 {
2636         struct mce *m = (struct mce *)data;
2637         struct amdgpu_device *adev = NULL;
2638         uint32_t gpu_id = 0;
2639         uint32_t umc_inst = 0;
2640         uint32_t ch_inst, channel_index = 0;
2641         struct ras_err_data err_data = {0, 0, 0, NULL};
2642         struct eeprom_table_record err_rec;
2643         uint64_t retired_page;
2644
2645         /*
2646          * If the error was generated in UMC_V2, which belongs to GPU UMCs,
2647          * and error occurred in DramECC (Extended error code = 0) then only
2648          * process the error, else bail out.
2649          */
2650         if (!m || !((smca_get_bank_type(m->bank) == SMCA_UMC_V2) &&
2651                     (XEC(m->status, 0x3f) == 0x0)))
2652                 return NOTIFY_DONE;
2653
2654         /*
2655          * If it is correctable error, return.
2656          */
2657         if (mce_is_correctable(m))
2658                 return NOTIFY_OK;
2659
2660         /*
2661          * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
2662          */
2663         gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
2664
2665         adev = find_adev(gpu_id);
2666         if (!adev) {
2667                 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
2668                                                                 gpu_id);
2669                 return NOTIFY_DONE;
2670         }
2671
2672         /*
2673          * If it is uncorrectable error, then find out UMC instance and
2674          * channel index.
2675          */
2676         umc_inst = GET_UMC_INST(m->ipid);
2677         ch_inst = GET_CHAN_INDEX(m->ipid);
2678
2679         dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
2680                              umc_inst, ch_inst);
2681
2682         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
2683
2684         /*
2685          * Translate UMC channel address to Physical address
2686          */
2687         channel_index =
2688                 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num
2689                                           + ch_inst];
2690
2691         retired_page = ADDR_OF_8KB_BLOCK(m->addr) |
2692                         ADDR_OF_256B_BLOCK(channel_index) |
2693                         OFFSET_IN_256B_BLOCK(m->addr);
2694
2695         err_rec.address = m->addr;
2696         err_rec.retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
2697         err_rec.ts = (uint64_t)ktime_get_real_seconds();
2698         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
2699         err_rec.cu = 0;
2700         err_rec.mem_channel = channel_index;
2701         err_rec.mcumc_id = umc_inst;
2702
2703         err_data.err_addr = &err_rec;
2704         err_data.err_addr_cnt = 1;
2705
2706         if (amdgpu_bad_page_threshold != 0) {
2707                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
2708                                                 err_data.err_addr_cnt);
2709                 amdgpu_ras_save_bad_pages(adev);
2710         }
2711
2712         return NOTIFY_OK;
2713 }
2714
2715 static struct notifier_block amdgpu_bad_page_nb = {
2716         .notifier_call  = amdgpu_bad_page_notifier,
2717         .priority       = MCE_PRIO_UC,
2718 };
2719
2720 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
2721 {
2722         /*
2723          * Add the adev to the mce_adev_list.
2724          * During mode2 reset, amdgpu device is temporarily
2725          * removed from the mgpu_info list which can cause
2726          * page retirement to fail.
2727          * Use this list instead of mgpu_info to find the amdgpu
2728          * device on which the UMC error was reported.
2729          */
2730         mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
2731
2732         /*
2733          * Register the x86 notifier only once
2734          * with MCE subsystem.
2735          */
2736         if (notifier_registered == false) {
2737                 mce_register_decode_chain(&amdgpu_bad_page_nb);
2738                 notifier_registered = true;
2739         }
2740 }
2741 #endif