drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/kthread.h>
  29 #include <linux/console.h>
  30 #include <linux/slab.h>
  31 #include <linux/debugfs.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/amdgpu_drm.h>
  35 #include <linux/vgaarb.h>
  36 #include <linux/vga_switcheroo.h>
  37 #include <linux/efi.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40 #include "amdgpu_i2c.h"
  41 #include "atom.h"
  42 #include "amdgpu_atombios.h"
  43 #include "amd_pcie.h"
  44 #ifdef CONFIG_DRM_AMDGPU_SI
  45 #include "si.h"
  46 #endif
  47 #ifdef CONFIG_DRM_AMDGPU_CIK
  48 #include "cik.h"
  49 #endif
  50 #include "vi.h"
  51 #include "bif/bif_4_1_d.h"
  52 #include <linux/pci.h>
  53 #include <linux/firmware.h>
  54
  55 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  56 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  57
  58 static const char *amdgpu_asic_name[] = {
  59         "TAHITI",
  60         "PITCAIRN",
  61         "VERDE",
  62         "OLAND",
  63         "HAINAN",
  64         "BONAIRE",
  65         "KAVERI",
  66         "KABINI",
  67         "HAWAII",
  68         "MULLINS",
  69         "TOPAZ",
  70         "TONGA",
  71         "FIJI",
  72         "CARRIZO",
  73         "STONEY",
  74         "POLARIS10",
  75         "POLARIS11",
  76         "LAST",
  77 };
  78
  79 bool amdgpu_device_is_px(struct drm_device *dev)
  80 {
  81         struct amdgpu_device *adev = dev->dev_private;
  82
  83         if (adev->flags & AMD_IS_PX)
  84                 return true;
  85         return false;
  86 }
  87
  88 /*
  89  * MMIO register access helper functions.
  90  */
  91 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  92                         bool always_indirect)
  93 {
  94         uint32_t ret;
  95
  96         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  97                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
  98         else {
  99                 unsigned long flags;
 100
 101                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 102                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 103                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 104                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 105         }
 106         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
 107         return ret;
 108 }
 109
 110 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
 111                     bool always_indirect)
 112 {
 113         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
 114
 115         if ((reg * 4) < adev->rmmio_size && !always_indirect)
 116                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
 117         else {
 118                 unsigned long flags;
 119
 120                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 121                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 122                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 123                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 124         }
 125 }
 126
 127 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 128 {
 129         if ((reg * 4) < adev->rio_mem_size)
 130                 return ioread32(adev->rio_mem + (reg * 4));
 131         else {
 132                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 133                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 134         }
 135 }
 136
 137 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 138 {
 139
 140         if ((reg * 4) < adev->rio_mem_size)
 141                 iowrite32(v, adev->rio_mem + (reg * 4));
 142         else {
 143                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 144                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 145         }
 146 }
 147
 148 /**
 149  * amdgpu_mm_rdoorbell - read a doorbell dword
 150  *
 151  * @adev: amdgpu_device pointer
 152  * @index: doorbell index
 153  *
 154  * Returns the value in the doorbell aperture at the
 155  * requested doorbell index (CIK).
 156  */
 157 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 158 {
 159         if (index < adev->doorbell.num_doorbells) {
 160                 return readl(adev->doorbell.ptr + index);
 161         } else {
 162                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 163                 return 0;
 164         }
 165 }
 166
 167 /**
 168  * amdgpu_mm_wdoorbell - write a doorbell dword
 169  *
 170  * @adev: amdgpu_device pointer
 171  * @index: doorbell index
 172  * @v: value to write
 173  *
 174  * Writes @v to the doorbell aperture at the
 175  * requested doorbell index (CIK).
 176  */
 177 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 178 {
 179         if (index < adev->doorbell.num_doorbells) {
 180                 writel(v, adev->doorbell.ptr + index);
 181         } else {
 182                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 183         }
 184 }
 185
 186 /**
 187  * amdgpu_invalid_rreg - dummy reg read function
 188  *
 189  * @adev: amdgpu device pointer
 190  * @reg: offset of register
 191  *
 192  * Dummy register read function.  Used for register blocks
 193  * that certain asics don't have (all asics).
 194  * Returns the value in the register.
 195  */
 196 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 197 {
 198         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 199         BUG();
 200         return 0;
 201 }
 202
 203 /**
 204  * amdgpu_invalid_wreg - dummy reg write function
 205  *
 206  * @adev: amdgpu device pointer
 207  * @reg: offset of register
 208  * @v: value to write to the register
 209  *
 210  * Dummy register read function.  Used for register blocks
 211  * that certain asics don't have (all asics).
 212  */
 213 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 214 {
 215         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 216                   reg, v);
 217         BUG();
 218 }
 219
 220 /**
 221  * amdgpu_block_invalid_rreg - dummy reg read function
 222  *
 223  * @adev: amdgpu device pointer
 224  * @block: offset of instance
 225  * @reg: offset of register
 226  *
 227  * Dummy register read function.  Used for register blocks
 228  * that certain asics don't have (all asics).
 229  * Returns the value in the register.
 230  */
 231 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 232                                           uint32_t block, uint32_t reg)
 233 {
 234         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 235                   reg, block);
 236         BUG();
 237         return 0;
 238 }
 239
 240 /**
 241  * amdgpu_block_invalid_wreg - dummy reg write function
 242  *
 243  * @adev: amdgpu device pointer
 244  * @block: offset of instance
 245  * @reg: offset of register
 246  * @v: value to write to the register
 247  *
 248  * Dummy register read function.  Used for register blocks
 249  * that certain asics don't have (all asics).
 250  */
 251 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 252                                       uint32_t block,
 253                                       uint32_t reg, uint32_t v)
 254 {
 255         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 256                   reg, block, v);
 257         BUG();
 258 }
 259
 260 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 261 {
 262         int r;
 263
 264         if (adev->vram_scratch.robj == NULL) {
 265                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 266                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
 267                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 268                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 269                                      NULL, NULL, &adev->vram_scratch.robj);
 270                 if (r) {
 271                         return r;
 272                 }
 273         }
 274
 275         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 276         if (unlikely(r != 0))
 277                 return r;
 278         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 279                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 280         if (r) {
 281                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 282                 return r;
 283         }
 284         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 285                                 (void **)&adev->vram_scratch.ptr);
 286         if (r)
 287                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 288         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 289
 290         return r;
 291 }
 292
 293 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 294 {
 295         int r;
 296
 297         if (adev->vram_scratch.robj == NULL) {
 298                 return;
 299         }
 300         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 301         if (likely(r == 0)) {
 302                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 303                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 304                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 305         }
 306         amdgpu_bo_unref(&adev->vram_scratch.robj);
 307 }
 308
 309 /**
 310  * amdgpu_program_register_sequence - program an array of registers.
 311  *
 312  * @adev: amdgpu_device pointer
 313  * @registers: pointer to the register array
 314  * @array_size: size of the register array
 315  *
 316  * Programs an array or registers with and and or masks.
 317  * This is a helper for setting golden registers.
 318  */
 319 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 320                                       const u32 *registers,
 321                                       const u32 array_size)
 322 {
 323         u32 tmp, reg, and_mask, or_mask;
 324         int i;
 325
 326         if (array_size % 3)
 327                 return;
 328
 329         for (i = 0; i < array_size; i +=3) {
 330                 reg = registers[i + 0];
 331                 and_mask = registers[i + 1];
 332                 or_mask = registers[i + 2];
 333
 334                 if (and_mask == 0xffffffff) {
 335                         tmp = or_mask;
 336                 } else {
 337                         tmp = RREG32(reg);
 338                         tmp &= ~and_mask;
 339                         tmp |= or_mask;
 340                 }
 341                 WREG32(reg, tmp);
 342         }
 343 }
 344
 345 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 346 {
 347         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 348 }
 349
 350 /*
 351  * GPU doorbell aperture helpers function.
 352  */
 353 /**
 354  * amdgpu_doorbell_init - Init doorbell driver information.
 355  *
 356  * @adev: amdgpu_device pointer
 357  *
 358  * Init doorbell driver information (CIK)
 359  * Returns 0 on success, error on failure.
 360  */
 361 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 362 {
 363         /* doorbell bar mapping */
 364         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 365         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 366
 367         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 368                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 369         if (adev->doorbell.num_doorbells == 0)
 370                 return -EINVAL;
 371
 372         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 373         if (adev->doorbell.ptr == NULL) {
 374                 return -ENOMEM;
 375         }
 376         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 377         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 378
 379         return 0;
 380 }
 381
 382 /**
 383  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 384  *
 385  * @adev: amdgpu_device pointer
 386  *
 387  * Tear down doorbell driver information (CIK)
 388  */
 389 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 390 {
 391         iounmap(adev->doorbell.ptr);
 392         adev->doorbell.ptr = NULL;
 393 }
 394
 395 /**
 396  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 397  *                                setup amdkfd
 398  *
 399  * @adev: amdgpu_device pointer
 400  * @aperture_base: output returning doorbell aperture base physical address
 401  * @aperture_size: output returning doorbell aperture size in bytes
 402  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 403  *
 404  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 405  * takes doorbells required for its own rings and reports the setup to amdkfd.
 406  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 407  */
 408 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 409                                 phys_addr_t *aperture_base,
 410                                 size_t *aperture_size,
 411                                 size_t *start_offset)
 412 {
 413         /*
 414          * The first num_doorbells are used by amdgpu.
 415          * amdkfd takes whatever's left in the aperture.
 416          */
 417         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 418                 *aperture_base = adev->doorbell.base;
 419                 *aperture_size = adev->doorbell.size;
 420                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 421         } else {
 422                 *aperture_base = 0;
 423                 *aperture_size = 0;
 424                 *start_offset = 0;
 425         }
 426 }
 427
 428 /*
 429  * amdgpu_wb_*()
 430  * Writeback is the the method by which the the GPU updates special pages
 431  * in memory with the status of certain GPU events (fences, ring pointers,
 432  * etc.).
 433  */
 434
 435 /**
 436  * amdgpu_wb_fini - Disable Writeback and free memory
 437  *
 438  * @adev: amdgpu_device pointer
 439  *
 440  * Disables Writeback and frees the Writeback memory (all asics).
 441  * Used at driver shutdown.
 442  */
 443 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 444 {
 445         if (adev->wb.wb_obj) {
 446                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
 447                                       &adev->wb.gpu_addr,
 448                                       (void **)&adev->wb.wb);
 449                 adev->wb.wb_obj = NULL;
 450         }
 451 }
 452
 453 /**
 454  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 455  *
 456  * @adev: amdgpu_device pointer
 457  *
 458  * Disables Writeback and frees the Writeback memory (all asics).
 459  * Used at driver startup.
 460  * Returns 0 on success or an -error on failure.
 461  */
 462 static int amdgpu_wb_init(struct amdgpu_device *adev)
 463 {
 464         int r;
 465
 466         if (adev->wb.wb_obj == NULL) {
 467                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * 4,
 468                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 469                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
 470                                             (void **)&adev->wb.wb);
 471                 if (r) {
 472                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 473                         return r;
 474                 }
 475
 476                 adev->wb.num_wb = AMDGPU_MAX_WB;
 477                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 478
 479                 /* clear wb memory */
 480                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 481         }
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * amdgpu_wb_get - Allocate a wb entry
 488  *
 489  * @adev: amdgpu_device pointer
 490  * @wb: wb index
 491  *
 492  * Allocate a wb slot for use by the driver (all asics).
 493  * Returns 0 on success or -EINVAL on failure.
 494  */
 495 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 496 {
 497         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 498         if (offset < adev->wb.num_wb) {
 499                 __set_bit(offset, adev->wb.used);
 500                 *wb = offset;
 501                 return 0;
 502         } else {
 503                 return -EINVAL;
 504         }
 505 }
 506
 507 /**
 508  * amdgpu_wb_free - Free a wb entry
 509  *
 510  * @adev: amdgpu_device pointer
 511  * @wb: wb index
 512  *
 513  * Free a wb slot allocated for use by the driver (all asics)
 514  */
 515 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 516 {
 517         if (wb < adev->wb.num_wb)
 518                 __clear_bit(wb, adev->wb.used);
 519 }
 520
 521 /**
 522  * amdgpu_vram_location - try to find VRAM location
 523  * @adev: amdgpu device structure holding all necessary informations
 524  * @mc: memory controller structure holding memory informations
 525  * @base: base address at which to put VRAM
 526  *
 527  * Function will place try to place VRAM at base address provided
 528  * as parameter (which is so far either PCI aperture address or
 529  * for IGP TOM base address).
 530  *
 531  * If there is not enough space to fit the unvisible VRAM in the 32bits
 532  * address space then we limit the VRAM size to the aperture.
 533  *
 534  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 535  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 536  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 537  * not IGP.
 538  *
 539  * Note: we use mc_vram_size as on some board we need to program the mc to
 540  * cover the whole aperture even if VRAM size is inferior to aperture size
 541  * Novell bug 204882 + along with lots of ubuntu ones
 542  *
 543  * Note: when limiting vram it's safe to overwritte real_vram_size because
 544  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 545  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 546  * ones)
 547  *
 548  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 549  * explicitly check for that thought.
 550  *
 551  * FIXME: when reducing VRAM size align new size on power of 2.
 552  */
 553 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 554 {
 555         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 556
 557         mc->vram_start = base;
 558         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 559                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 560                 mc->real_vram_size = mc->aper_size;
 561                 mc->mc_vram_size = mc->aper_size;
 562         }
 563         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 564         if (limit && limit < mc->real_vram_size)
 565                 mc->real_vram_size = limit;
 566         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 567                         mc->mc_vram_size >> 20, mc->vram_start,
 568                         mc->vram_end, mc->real_vram_size >> 20);
 569 }
 570
 571 /**
 572  * amdgpu_gtt_location - try to find GTT location
 573  * @adev: amdgpu device structure holding all necessary informations
 574  * @mc: memory controller structure holding memory informations
 575  *
 576  * Function will place try to place GTT before or after VRAM.
 577  *
 578  * If GTT size is bigger than space left then we ajust GTT size.
 579  * Thus function will never fails.
 580  *
 581  * FIXME: when reducing GTT size align new size on power of 2.
 582  */
 583 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 584 {
 585         u64 size_af, size_bf;
 586
 587         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 588         size_bf = mc->vram_start & ~mc->gtt_base_align;
 589         if (size_bf > size_af) {
 590                 if (mc->gtt_size > size_bf) {
 591                         dev_warn(adev->dev, "limiting GTT\n");
 592                         mc->gtt_size = size_bf;
 593                 }
 594                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 595         } else {
 596                 if (mc->gtt_size > size_af) {
 597                         dev_warn(adev->dev, "limiting GTT\n");
 598                         mc->gtt_size = size_af;
 599                 }
 600                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 601         }
 602         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 603         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 604                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 605 }
 606
 607 /*
 608  * GPU helpers function.
 609  */
 610 /**
 611  * amdgpu_card_posted - check if the hw has already been initialized
 612  *
 613  * @adev: amdgpu_device pointer
 614  *
 615  * Check if the asic has been initialized (all asics).
 616  * Used at driver startup.
 617  * Returns true if initialized or false if not.
 618  */
 619 bool amdgpu_card_posted(struct amdgpu_device *adev)
 620 {
 621         uint32_t reg;
 622
 623         /* then check MEM_SIZE, in case the crtcs are off */
 624         reg = RREG32(mmCONFIG_MEMSIZE);
 625
 626         if (reg)
 627                 return true;
 628
 629         return false;
 630
 631 }
 632
 633 static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
 634 {
 635         if (amdgpu_sriov_vf(adev))
 636                 return false;
 637
 638         if (amdgpu_passthrough(adev)) {
 639                 /* for FIJI: In whole GPU pass-through virtualization case
 640                  * old smc fw won't clear some registers (e.g. MEM_SIZE, BIOS_SCRATCH)
 641                  * so amdgpu_card_posted return false and driver will incorrectly skip vPost.
 642                  * but if we force vPost do in pass-through case, the driver reload will hang.
 643                  * whether doing vPost depends on amdgpu_card_posted if smc version is above
 644                  * 00160e00 for FIJI.
 645                  */
 646                 if (adev->asic_type == CHIP_FIJI) {
 647                         int err;
 648                         uint32_t fw_ver;
 649                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
 650                         /* force vPost if error occured */
 651                         if (err)
 652                                 return true;
 653
 654                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
 655                         if (fw_ver >= 0x00160e00)
 656                                 return !amdgpu_card_posted(adev);
 657                 }
 658         } else {
 659                 /* in bare-metal case, amdgpu_card_posted return false
 660                  * after system reboot/boot, and return true if driver
 661                  * reloaded.
 662                  * we shouldn't do vPost after driver reload otherwise GPU
 663                  * could hang.
 664                  */
 665                 if (amdgpu_card_posted(adev))
 666                         return false;
 667         }
 668
 669         /* we assume vPost is neede for all other cases */
 670         return true;
 671 }
 672
 673 /**
 674  * amdgpu_dummy_page_init - init dummy page used by the driver
 675  *
 676  * @adev: amdgpu_device pointer
 677  *
 678  * Allocate the dummy page used by the driver (all asics).
 679  * This dummy page is used by the driver as a filler for gart entries
 680  * when pages are taken out of the GART
 681  * Returns 0 on sucess, -ENOMEM on failure.
 682  */
 683 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 684 {
 685         if (adev->dummy_page.page)
 686                 return 0;
 687         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 688         if (adev->dummy_page.page == NULL)
 689                 return -ENOMEM;
 690         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 691                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 692         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 693                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 694                 __free_page(adev->dummy_page.page);
 695                 adev->dummy_page.page = NULL;
 696                 return -ENOMEM;
 697         }
 698         return 0;
 699 }
 700
 701 /**
 702  * amdgpu_dummy_page_fini - free dummy page used by the driver
 703  *
 704  * @adev: amdgpu_device pointer
 705  *
 706  * Frees the dummy page used by the driver (all asics).
 707  */
 708 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 709 {
 710         if (adev->dummy_page.page == NULL)
 711                 return;
 712         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 713                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 714         __free_page(adev->dummy_page.page);
 715         adev->dummy_page.page = NULL;
 716 }
 717
 718
 719 /* ATOM accessor methods */
 720 /*
 721  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 722  * driver registers callbacks to access registers and the interpreter
 723  * in the driver parses the tables and executes then to program specific
 724  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 725  * atombios.h, and atom.c
 726  */
 727
 728 /**
 729  * cail_pll_read - read PLL register
 730  *
 731  * @info: atom card_info pointer
 732  * @reg: PLL register offset
 733  *
 734  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 735  * Returns the value of the PLL register.
 736  */
 737 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 738 {
 739         return 0;
 740 }
 741
 742 /**
 743  * cail_pll_write - write PLL register
 744  *
 745  * @info: atom card_info pointer
 746  * @reg: PLL register offset
 747  * @val: value to write to the pll register
 748  *
 749  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 750  */
 751 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 752 {
 753
 754 }
 755
 756 /**
 757  * cail_mc_read - read MC (Memory Controller) register
 758  *
 759  * @info: atom card_info pointer
 760  * @reg: MC register offset
 761  *
 762  * Provides an MC register accessor for the atom interpreter (r4xx+).
 763  * Returns the value of the MC register.
 764  */
 765 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 766 {
 767         return 0;
 768 }
 769
 770 /**
 771  * cail_mc_write - write MC (Memory Controller) register
 772  *
 773  * @info: atom card_info pointer
 774  * @reg: MC register offset
 775  * @val: value to write to the pll register
 776  *
 777  * Provides a MC register accessor for the atom interpreter (r4xx+).
 778  */
 779 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 780 {
 781
 782 }
 783
 784 /**
 785  * cail_reg_write - write MMIO register
 786  *
 787  * @info: atom card_info pointer
 788  * @reg: MMIO register offset
 789  * @val: value to write to the pll register
 790  *
 791  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 792  */
 793 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 794 {
 795         struct amdgpu_device *adev = info->dev->dev_private;
 796
 797         WREG32(reg, val);
 798 }
 799
 800 /**
 801  * cail_reg_read - read MMIO register
 802  *
 803  * @info: atom card_info pointer
 804  * @reg: MMIO register offset
 805  *
 806  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 807  * Returns the value of the MMIO register.
 808  */
 809 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 810 {
 811         struct amdgpu_device *adev = info->dev->dev_private;
 812         uint32_t r;
 813
 814         r = RREG32(reg);
 815         return r;
 816 }
 817
 818 /**
 819  * cail_ioreg_write - write IO register
 820  *
 821  * @info: atom card_info pointer
 822  * @reg: IO register offset
 823  * @val: value to write to the pll register
 824  *
 825  * Provides a IO register accessor for the atom interpreter (r4xx+).
 826  */
 827 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 828 {
 829         struct amdgpu_device *adev = info->dev->dev_private;
 830
 831         WREG32_IO(reg, val);
 832 }
 833
 834 /**
 835  * cail_ioreg_read - read IO register
 836  *
 837  * @info: atom card_info pointer
 838  * @reg: IO register offset
 839  *
 840  * Provides an IO register accessor for the atom interpreter (r4xx+).
 841  * Returns the value of the IO register.
 842  */
 843 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 844 {
 845         struct amdgpu_device *adev = info->dev->dev_private;
 846         uint32_t r;
 847
 848         r = RREG32_IO(reg);
 849         return r;
 850 }
 851
 852 /**
 853  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 854  *
 855  * @adev: amdgpu_device pointer
 856  *
 857  * Frees the driver info and register access callbacks for the ATOM
 858  * interpreter (r4xx+).
 859  * Called at driver shutdown.
 860  */
 861 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 862 {
 863         if (adev->mode_info.atom_context) {
 864                 kfree(adev->mode_info.atom_context->scratch);
 865                 kfree(adev->mode_info.atom_context->iio);
 866         }
 867         kfree(adev->mode_info.atom_context);
 868         adev->mode_info.atom_context = NULL;
 869         kfree(adev->mode_info.atom_card_info);
 870         adev->mode_info.atom_card_info = NULL;
 871 }
 872
 873 /**
 874  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 875  *
 876  * @adev: amdgpu_device pointer
 877  *
 878  * Initializes the driver info and register access callbacks for the
 879  * ATOM interpreter (r4xx+).
 880  * Returns 0 on sucess, -ENOMEM on failure.
 881  * Called at driver startup.
 882  */
 883 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 884 {
 885         struct card_info *atom_card_info =
 886             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 887
 888         if (!atom_card_info)
 889                 return -ENOMEM;
 890
 891         adev->mode_info.atom_card_info = atom_card_info;
 892         atom_card_info->dev = adev->ddev;
 893         atom_card_info->reg_read = cail_reg_read;
 894         atom_card_info->reg_write = cail_reg_write;
 895         /* needed for iio ops */
 896         if (adev->rio_mem) {
 897                 atom_card_info->ioreg_read = cail_ioreg_read;
 898                 atom_card_info->ioreg_write = cail_ioreg_write;
 899         } else {
 900                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 901                 atom_card_info->ioreg_read = cail_reg_read;
 902                 atom_card_info->ioreg_write = cail_reg_write;
 903         }
 904         atom_card_info->mc_read = cail_mc_read;
 905         atom_card_info->mc_write = cail_mc_write;
 906         atom_card_info->pll_read = cail_pll_read;
 907         atom_card_info->pll_write = cail_pll_write;
 908
 909         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 910         if (!adev->mode_info.atom_context) {
 911                 amdgpu_atombios_fini(adev);
 912                 return -ENOMEM;
 913         }
 914
 915         mutex_init(&adev->mode_info.atom_context->mutex);
 916         amdgpu_atombios_scratch_regs_init(adev);
 917         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 918         return 0;
 919 }
 920
 921 /* if we get transitioned to only one device, take VGA back */
 922 /**
 923  * amdgpu_vga_set_decode - enable/disable vga decode
 924  *
 925  * @cookie: amdgpu_device pointer
 926  * @state: enable/disable vga decode
 927  *
 928  * Enable/disable vga decode (all asics).
 929  * Returns VGA resource flags.
 930  */
 931 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 932 {
 933         struct amdgpu_device *adev = cookie;
 934         amdgpu_asic_set_vga_state(adev, state);
 935         if (state)
 936                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 937                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 938         else
 939                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 940 }
 941
 942 /**
 943  * amdgpu_check_pot_argument - check that argument is a power of two
 944  *
 945  * @arg: value to check
 946  *
 947  * Validates that a certain argument is a power of two (all asics).
 948  * Returns true if argument is valid.
 949  */
 950 static bool amdgpu_check_pot_argument(int arg)
 951 {
 952         return (arg & (arg - 1)) == 0;
 953 }
 954
 955 /**
 956  * amdgpu_check_arguments - validate module params
 957  *
 958  * @adev: amdgpu_device pointer
 959  *
 960  * Validates certain module parameters and updates
 961  * the associated values used by the driver (all asics).
 962  */
 963 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 964 {
 965         if (amdgpu_sched_jobs < 4) {
 966                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 967                          amdgpu_sched_jobs);
 968                 amdgpu_sched_jobs = 4;
 969         } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
 970                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 971                          amdgpu_sched_jobs);
 972                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
 973         }
 974
 975         if (amdgpu_gart_size != -1) {
 976                 /* gtt size must be greater or equal to 32M */
 977                 if (amdgpu_gart_size < 32) {
 978                         dev_warn(adev->dev, "gart size (%d) too small\n",
 979                                  amdgpu_gart_size);
 980                         amdgpu_gart_size = -1;
 981                 }
 982         }
 983
 984         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 985                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 986                          amdgpu_vm_size);
 987                 amdgpu_vm_size = 8;
 988         }
 989
 990         if (amdgpu_vm_size < 1) {
 991                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 992                          amdgpu_vm_size);
 993                 amdgpu_vm_size = 8;
 994         }
 995
 996         /*
 997          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 998          */
 999         if (amdgpu_vm_size > 1024) {
1000                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1001                          amdgpu_vm_size);
1002                 amdgpu_vm_size = 8;
1003         }
1004
1005         /* defines number of bits in page table versus page directory,
1006          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1007          * page table and the remaining bits are in the page directory */
1008         if (amdgpu_vm_block_size == -1) {
1009
1010                 /* Total bits covered by PD + PTs */
1011                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
1012
1013                 /* Make sure the PD is 4K in size up to 8GB address space.
1014                    Above that split equal between PD and PTs */
1015                 if (amdgpu_vm_size <= 8)
1016                         amdgpu_vm_block_size = bits - 9;
1017                 else
1018                         amdgpu_vm_block_size = (bits + 3) / 2;
1019
1020         } else if (amdgpu_vm_block_size < 9) {
1021                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1022                          amdgpu_vm_block_size);
1023                 amdgpu_vm_block_size = 9;
1024         }
1025
1026         if (amdgpu_vm_block_size > 24 ||
1027             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1028                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1029                          amdgpu_vm_block_size);
1030                 amdgpu_vm_block_size = 9;
1031         }
1032
1033         if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) ||
1034             !amdgpu_check_pot_argument(amdgpu_vram_page_split)) {
1035                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1036                          amdgpu_vram_page_split);
1037                 amdgpu_vram_page_split = 1024;
1038         }
1039 }
1040
1041 /**
1042  * amdgpu_switcheroo_set_state - set switcheroo state
1043  *
1044  * @pdev: pci dev pointer
1045  * @state: vga_switcheroo state
1046  *
1047  * Callback for the switcheroo driver.  Suspends or resumes the
1048  * the asics before or after it is powered up using ACPI methods.
1049  */
1050 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1051 {
1052         struct drm_device *dev = pci_get_drvdata(pdev);
1053
1054         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1055                 return;
1056
1057         if (state == VGA_SWITCHEROO_ON) {
1058                 unsigned d3_delay = dev->pdev->d3_delay;
1059
1060                 printk(KERN_INFO "amdgpu: switched on\n");
1061                 /* don't suspend or resume card normally */
1062                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1063
1064                 amdgpu_device_resume(dev, true, true);
1065
1066                 dev->pdev->d3_delay = d3_delay;
1067
1068                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1069                 drm_kms_helper_poll_enable(dev);
1070         } else {
1071                 printk(KERN_INFO "amdgpu: switched off\n");
1072                 drm_kms_helper_poll_disable(dev);
1073                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1074                 amdgpu_device_suspend(dev, true, true);
1075                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1076         }
1077 }
1078
1079 /**
1080  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1081  *
1082  * @pdev: pci dev pointer
1083  *
1084  * Callback for the switcheroo driver.  Check of the switcheroo
1085  * state can be changed.
1086  * Returns true if the state can be changed, false if not.
1087  */
1088 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1089 {
1090         struct drm_device *dev = pci_get_drvdata(pdev);
1091
1092         /*
1093         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1094         * locking inversion with the driver load path. And the access here is
1095         * completely racy anyway. So don't bother with locking for now.
1096         */
1097         return dev->open_count == 0;
1098 }
1099
1100 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1101         .set_gpu_state = amdgpu_switcheroo_set_state,
1102         .reprobe = NULL,
1103         .can_switch = amdgpu_switcheroo_can_switch,
1104 };
1105
1106 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1107                                   enum amd_ip_block_type block_type,
1108                                   enum amd_clockgating_state state)
1109 {
1110         int i, r = 0;
1111
1112         for (i = 0; i < adev->num_ip_blocks; i++) {
1113                 if (!adev->ip_blocks[i].status.valid)
1114                         continue;
1115                 if (adev->ip_blocks[i].version->type == block_type) {
1116                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1117                                                                                      state);
1118                         if (r)
1119                                 return r;
1120                         break;
1121                 }
1122         }
1123         return r;
1124 }
1125
1126 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1127                                   enum amd_ip_block_type block_type,
1128                                   enum amd_powergating_state state)
1129 {
1130         int i, r = 0;
1131
1132         for (i = 0; i < adev->num_ip_blocks; i++) {
1133                 if (!adev->ip_blocks[i].status.valid)
1134                         continue;
1135                 if (adev->ip_blocks[i].version->type == block_type) {
1136                         r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
1137                                                                                      state);
1138                         if (r)
1139                                 return r;
1140                         break;
1141                 }
1142         }
1143         return r;
1144 }
1145
1146 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1147                          enum amd_ip_block_type block_type)
1148 {
1149         int i, r;
1150
1151         for (i = 0; i < adev->num_ip_blocks; i++) {
1152                 if (!adev->ip_blocks[i].status.valid)
1153                         continue;
1154                 if (adev->ip_blocks[i].version->type == block_type) {
1155                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1156                         if (r)
1157                                 return r;
1158                         break;
1159                 }
1160         }
1161         return 0;
1162
1163 }
1164
1165 bool amdgpu_is_idle(struct amdgpu_device *adev,
1166                     enum amd_ip_block_type block_type)
1167 {
1168         int i;
1169
1170         for (i = 0; i < adev->num_ip_blocks; i++) {
1171                 if (!adev->ip_blocks[i].status.valid)
1172                         continue;
1173                 if (adev->ip_blocks[i].version->type == block_type)
1174                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1175         }
1176         return true;
1177
1178 }
1179
1180 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1181                                              enum amd_ip_block_type type)
1182 {
1183         int i;
1184
1185         for (i = 0; i < adev->num_ip_blocks; i++)
1186                 if (adev->ip_blocks[i].version->type == type)
1187                         return &adev->ip_blocks[i];
1188
1189         return NULL;
1190 }
1191
1192 /**
1193  * amdgpu_ip_block_version_cmp
1194  *
1195  * @adev: amdgpu_device pointer
1196  * @type: enum amd_ip_block_type
1197  * @major: major version
1198  * @minor: minor version
1199  *
1200  * return 0 if equal or greater
1201  * return 1 if smaller or the ip_block doesn't exist
1202  */
1203 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1204                                 enum amd_ip_block_type type,
1205                                 u32 major, u32 minor)
1206 {
1207         struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1208
1209         if (ip_block && ((ip_block->version->major > major) ||
1210                         ((ip_block->version->major == major) &&
1211                         (ip_block->version->minor >= minor))))
1212                 return 0;
1213
1214         return 1;
1215 }
1216
1217 /**
1218  * amdgpu_ip_block_add
1219  *
1220  * @adev: amdgpu_device pointer
1221  * @ip_block_version: pointer to the IP to add
1222  *
1223  * Adds the IP block driver information to the collection of IPs
1224  * on the asic.
1225  */
1226 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1227                         const struct amdgpu_ip_block_version *ip_block_version)
1228 {
1229         if (!ip_block_version)
1230                 return -EINVAL;
1231
1232         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1233
1234         return 0;
1235 }
1236
1237 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1238 {
1239         adev->enable_virtual_display = false;
1240
1241         if (amdgpu_virtual_display) {
1242                 struct drm_device *ddev = adev->ddev;
1243                 const char *pci_address_name = pci_name(ddev->pdev);
1244                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1245
1246                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1247                 pciaddstr_tmp = pciaddstr;
1248                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1249                         pciaddname = strsep(&pciaddname_tmp, ",");
1250                         if (!strcmp(pci_address_name, pciaddname)) {
1251                                 long num_crtc;
1252                                 int res = -1;
1253
1254                                 adev->enable_virtual_display = true;
1255
1256                                 if (pciaddname_tmp)
1257                                         res = kstrtol(pciaddname_tmp, 10,
1258                                                       &num_crtc);
1259
1260                                 if (!res) {
1261                                         if (num_crtc < 1)
1262                                                 num_crtc = 1;
1263                                         if (num_crtc > 6)
1264                                                 num_crtc = 6;
1265                                         adev->mode_info.num_crtc = num_crtc;
1266                                 } else {
1267                                         adev->mode_info.num_crtc = 1;
1268                                 }
1269                                 break;
1270                         }
1271                 }
1272
1273                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1274                          amdgpu_virtual_display, pci_address_name,
1275                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1276
1277                 kfree(pciaddstr);
1278         }
1279 }
1280
1281 static int amdgpu_early_init(struct amdgpu_device *adev)
1282 {
1283         int i, r;
1284
1285         amdgpu_device_enable_virtual_display(adev);
1286
1287         switch (adev->asic_type) {
1288         case CHIP_TOPAZ:
1289         case CHIP_TONGA:
1290         case CHIP_FIJI:
1291         case CHIP_POLARIS11:
1292         case CHIP_POLARIS10:
1293         case CHIP_CARRIZO:
1294         case CHIP_STONEY:
1295                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1296                         adev->family = AMDGPU_FAMILY_CZ;
1297                 else
1298                         adev->family = AMDGPU_FAMILY_VI;
1299
1300                 r = vi_set_ip_blocks(adev);
1301                 if (r)
1302                         return r;
1303                 break;
1304 #ifdef CONFIG_DRM_AMDGPU_SI
1305         case CHIP_VERDE:
1306         case CHIP_TAHITI:
1307         case CHIP_PITCAIRN:
1308         case CHIP_OLAND:
1309         case CHIP_HAINAN:
1310                 adev->family = AMDGPU_FAMILY_SI;
1311                 r = si_set_ip_blocks(adev);
1312                 if (r)
1313                         return r;
1314                 break;
1315 #endif
1316 #ifdef CONFIG_DRM_AMDGPU_CIK
1317         case CHIP_BONAIRE:
1318         case CHIP_HAWAII:
1319         case CHIP_KAVERI:
1320         case CHIP_KABINI:
1321         case CHIP_MULLINS:
1322                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1323                         adev->family = AMDGPU_FAMILY_CI;
1324                 else
1325                         adev->family = AMDGPU_FAMILY_KV;
1326
1327                 r = cik_set_ip_blocks(adev);
1328                 if (r)
1329                         return r;
1330                 break;
1331 #endif
1332         default:
1333                 /* FIXME: not supported yet */
1334                 return -EINVAL;
1335         }
1336
1337         for (i = 0; i < adev->num_ip_blocks; i++) {
1338                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1339                         DRM_ERROR("disabled ip block: %d\n", i);
1340                         adev->ip_blocks[i].status.valid = false;
1341                 } else {
1342                         if (adev->ip_blocks[i].version->funcs->early_init) {
1343                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1344                                 if (r == -ENOENT) {
1345                                         adev->ip_blocks[i].status.valid = false;
1346                                 } else if (r) {
1347                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1348                                                   adev->ip_blocks[i].version->funcs->name, r);
1349                                         return r;
1350                                 } else {
1351                                         adev->ip_blocks[i].status.valid = true;
1352                                 }
1353                         } else {
1354                                 adev->ip_blocks[i].status.valid = true;
1355                         }
1356                 }
1357         }
1358
1359         adev->cg_flags &= amdgpu_cg_mask;
1360         adev->pg_flags &= amdgpu_pg_mask;
1361
1362         return 0;
1363 }
1364
1365 static int amdgpu_init(struct amdgpu_device *adev)
1366 {
1367         int i, r;
1368
1369         for (i = 0; i < adev->num_ip_blocks; i++) {
1370                 if (!adev->ip_blocks[i].status.valid)
1371                         continue;
1372                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1373                 if (r) {
1374                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1375                                   adev->ip_blocks[i].version->funcs->name, r);
1376                         return r;
1377                 }
1378                 adev->ip_blocks[i].status.sw = true;
1379                 /* need to do gmc hw init early so we can allocate gpu mem */
1380                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1381                         r = amdgpu_vram_scratch_init(adev);
1382                         if (r) {
1383                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1384                                 return r;
1385                         }
1386                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1387                         if (r) {
1388                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1389                                 return r;
1390                         }
1391                         r = amdgpu_wb_init(adev);
1392                         if (r) {
1393                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1394                                 return r;
1395                         }
1396                         adev->ip_blocks[i].status.hw = true;
1397                 }
1398         }
1399
1400         for (i = 0; i < adev->num_ip_blocks; i++) {
1401                 if (!adev->ip_blocks[i].status.sw)
1402                         continue;
1403                 /* gmc hw init is done early */
1404                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1405                         continue;
1406                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1407                 if (r) {
1408                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1409                                   adev->ip_blocks[i].version->funcs->name, r);
1410                         return r;
1411                 }
1412                 adev->ip_blocks[i].status.hw = true;
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int amdgpu_late_init(struct amdgpu_device *adev)
1419 {
1420         int i = 0, r;
1421
1422         for (i = 0; i < adev->num_ip_blocks; i++) {
1423                 if (!adev->ip_blocks[i].status.valid)
1424                         continue;
1425                 if (adev->ip_blocks[i].version->funcs->late_init) {
1426                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1427                         if (r) {
1428                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1429                                           adev->ip_blocks[i].version->funcs->name, r);
1430                                 return r;
1431                         }
1432                         adev->ip_blocks[i].status.late_initialized = true;
1433                 }
1434                 /* skip CG for VCE/UVD, it's handled specially */
1435                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1436                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1437                         /* enable clockgating to save power */
1438                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1439                                                                                      AMD_CG_STATE_GATE);
1440                         if (r) {
1441                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1442                                           adev->ip_blocks[i].version->funcs->name, r);
1443                                 return r;
1444                         }
1445                 }
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int amdgpu_fini(struct amdgpu_device *adev)
1452 {
1453         int i, r;
1454
1455         /* need to disable SMC first */
1456         for (i = 0; i < adev->num_ip_blocks; i++) {
1457                 if (!adev->ip_blocks[i].status.hw)
1458                         continue;
1459                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1460                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1461                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1462                                                                                      AMD_CG_STATE_UNGATE);
1463                         if (r) {
1464                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1465                                           adev->ip_blocks[i].version->funcs->name, r);
1466                                 return r;
1467                         }
1468                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1469                         /* XXX handle errors */
1470                         if (r) {
1471                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1472                                           adev->ip_blocks[i].version->funcs->name, r);
1473                         }
1474                         adev->ip_blocks[i].status.hw = false;
1475                         break;
1476                 }
1477         }
1478
1479         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1480                 if (!adev->ip_blocks[i].status.hw)
1481                         continue;
1482                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1483                         amdgpu_wb_fini(adev);
1484                         amdgpu_vram_scratch_fini(adev);
1485                 }
1486                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1487                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1488                                                                              AMD_CG_STATE_UNGATE);
1489                 if (r) {
1490                         DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1491                                   adev->ip_blocks[i].version->funcs->name, r);
1492                         return r;
1493                 }
1494                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1495                 /* XXX handle errors */
1496                 if (r) {
1497                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1498                                   adev->ip_blocks[i].version->funcs->name, r);
1499                 }
1500                 adev->ip_blocks[i].status.hw = false;
1501         }
1502
1503         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1504                 if (!adev->ip_blocks[i].status.sw)
1505                         continue;
1506                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1507                 /* XXX handle errors */
1508                 if (r) {
1509                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1510                                   adev->ip_blocks[i].version->funcs->name, r);
1511                 }
1512                 adev->ip_blocks[i].status.sw = false;
1513                 adev->ip_blocks[i].status.valid = false;
1514         }
1515
1516         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1517                 if (!adev->ip_blocks[i].status.late_initialized)
1518                         continue;
1519                 if (adev->ip_blocks[i].version->funcs->late_fini)
1520                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1521                 adev->ip_blocks[i].status.late_initialized = false;
1522         }
1523
1524         return 0;
1525 }
1526
1527 static int amdgpu_suspend(struct amdgpu_device *adev)
1528 {
1529         int i, r;
1530
1531         /* ungate SMC block first */
1532         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1533                                          AMD_CG_STATE_UNGATE);
1534         if (r) {
1535                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1536         }
1537
1538         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1539                 if (!adev->ip_blocks[i].status.valid)
1540                         continue;
1541                 /* ungate blocks so that suspend can properly shut them down */
1542                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1543                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1544                                                                                      AMD_CG_STATE_UNGATE);
1545                         if (r) {
1546                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1547                                           adev->ip_blocks[i].version->funcs->name, r);
1548                         }
1549                 }
1550                 /* XXX handle errors */
1551                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1552                 /* XXX handle errors */
1553                 if (r) {
1554                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
1555                                   adev->ip_blocks[i].version->funcs->name, r);
1556                 }
1557         }
1558
1559         return 0;
1560 }
1561
1562 static int amdgpu_resume(struct amdgpu_device *adev)
1563 {
1564         int i, r;
1565
1566         for (i = 0; i < adev->num_ip_blocks; i++) {
1567                 if (!adev->ip_blocks[i].status.valid)
1568                         continue;
1569                 r = adev->ip_blocks[i].version->funcs->resume(adev);
1570                 if (r) {
1571                         DRM_ERROR("resume of IP block <%s> failed %d\n",
1572                                   adev->ip_blocks[i].version->funcs->name, r);
1573                         return r;
1574                 }
1575         }
1576
1577         return 0;
1578 }
1579
1580 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
1581 {
1582         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
1583                 adev->virtualization.virtual_caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
1584 }
1585
1586 /**
1587  * amdgpu_device_init - initialize the driver
1588  *
1589  * @adev: amdgpu_device pointer
1590  * @pdev: drm dev pointer
1591  * @pdev: pci dev pointer
1592  * @flags: driver flags
1593  *
1594  * Initializes the driver info and hw (all asics).
1595  * Returns 0 for success or an error on failure.
1596  * Called at driver startup.
1597  */
1598 int amdgpu_device_init(struct amdgpu_device *adev,
1599                        struct drm_device *ddev,
1600                        struct pci_dev *pdev,
1601                        uint32_t flags)
1602 {
1603         int r, i;
1604         bool runtime = false;
1605         u32 max_MBps;
1606
1607         adev->shutdown = false;
1608         adev->dev = &pdev->dev;
1609         adev->ddev = ddev;
1610         adev->pdev = pdev;
1611         adev->flags = flags;
1612         adev->asic_type = flags & AMD_ASIC_MASK;
1613         adev->is_atom_bios = false;
1614         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1615         adev->mc.gtt_size = 512 * 1024 * 1024;
1616         adev->accel_working = false;
1617         adev->num_rings = 0;
1618         adev->mman.buffer_funcs = NULL;
1619         adev->mman.buffer_funcs_ring = NULL;
1620         adev->vm_manager.vm_pte_funcs = NULL;
1621         adev->vm_manager.vm_pte_num_rings = 0;
1622         adev->gart.gart_funcs = NULL;
1623         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
1624
1625         adev->smc_rreg = &amdgpu_invalid_rreg;
1626         adev->smc_wreg = &amdgpu_invalid_wreg;
1627         adev->pcie_rreg = &amdgpu_invalid_rreg;
1628         adev->pcie_wreg = &amdgpu_invalid_wreg;
1629         adev->pciep_rreg = &amdgpu_invalid_rreg;
1630         adev->pciep_wreg = &amdgpu_invalid_wreg;
1631         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1632         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1633         adev->didt_rreg = &amdgpu_invalid_rreg;
1634         adev->didt_wreg = &amdgpu_invalid_wreg;
1635         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
1636         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
1637         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1638         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1639
1640
1641         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1642                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1643                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1644
1645         /* mutex initialization are all done here so we
1646          * can recall function without having locking issues */
1647         mutex_init(&adev->vm_manager.lock);
1648         atomic_set(&adev->irq.ih.lock, 0);
1649         mutex_init(&adev->pm.mutex);
1650         mutex_init(&adev->gfx.gpu_clock_mutex);
1651         mutex_init(&adev->srbm_mutex);
1652         mutex_init(&adev->grbm_idx_mutex);
1653         mutex_init(&adev->mn_lock);
1654         hash_init(adev->mn_hash);
1655
1656         amdgpu_check_arguments(adev);
1657
1658         /* Registers mapping */
1659         /* TODO: block userspace mapping of io register */
1660         spin_lock_init(&adev->mmio_idx_lock);
1661         spin_lock_init(&adev->smc_idx_lock);
1662         spin_lock_init(&adev->pcie_idx_lock);
1663         spin_lock_init(&adev->uvd_ctx_idx_lock);
1664         spin_lock_init(&adev->didt_idx_lock);
1665         spin_lock_init(&adev->gc_cac_idx_lock);
1666         spin_lock_init(&adev->audio_endpt_idx_lock);
1667         spin_lock_init(&adev->mm_stats.lock);
1668
1669         INIT_LIST_HEAD(&adev->shadow_list);
1670         mutex_init(&adev->shadow_list_lock);
1671
1672         INIT_LIST_HEAD(&adev->gtt_list);
1673         spin_lock_init(&adev->gtt_list_lock);
1674
1675         if (adev->asic_type >= CHIP_BONAIRE) {
1676                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1677                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1678         } else {
1679                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
1680                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
1681         }
1682
1683         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1684         if (adev->rmmio == NULL) {
1685                 return -ENOMEM;
1686         }
1687         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1688         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1689
1690         if (adev->asic_type >= CHIP_BONAIRE)
1691                 /* doorbell bar mapping */
1692                 amdgpu_doorbell_init(adev);
1693
1694         /* io port mapping */
1695         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1696                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1697                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1698                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1699                         break;
1700                 }
1701         }
1702         if (adev->rio_mem == NULL)
1703                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1704
1705         /* early init functions */
1706         r = amdgpu_early_init(adev);
1707         if (r)
1708                 return r;
1709
1710         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1711         /* this will fail for cards that aren't VGA class devices, just
1712          * ignore it */
1713         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1714
1715         if (amdgpu_runtime_pm == 1)
1716                 runtime = true;
1717         if (amdgpu_device_is_px(ddev))
1718                 runtime = true;
1719         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1720         if (runtime)
1721                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1722
1723         /* Read BIOS */
1724         if (!amdgpu_get_bios(adev)) {
1725                 r = -EINVAL;
1726                 goto failed;
1727         }
1728         /* Must be an ATOMBIOS */
1729         if (!adev->is_atom_bios) {
1730                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1731                 r = -EINVAL;
1732                 goto failed;
1733         }
1734         r = amdgpu_atombios_init(adev);
1735         if (r) {
1736                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1737                 goto failed;
1738         }
1739
1740         /* detect if we are with an SRIOV vbios */
1741         amdgpu_device_detect_sriov_bios(adev);
1742
1743         /* Post card if necessary */
1744         if (amdgpu_vpost_needed(adev)) {
1745                 if (!adev->bios) {
1746                         dev_err(adev->dev, "no vBIOS found\n");
1747                         r = -EINVAL;
1748                         goto failed;
1749                 }
1750                 DRM_INFO("GPU posting now...\n");
1751                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
1752                 if (r) {
1753                         dev_err(adev->dev, "gpu post error!\n");
1754                         goto failed;
1755                 }
1756         } else {
1757                 DRM_INFO("GPU post is not needed\n");
1758         }
1759
1760         /* Initialize clocks */
1761         r = amdgpu_atombios_get_clock_info(adev);
1762         if (r) {
1763                 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1764                 goto failed;
1765         }
1766         /* init i2c buses */
1767         amdgpu_atombios_i2c_init(adev);
1768
1769         /* Fence driver */
1770         r = amdgpu_fence_driver_init(adev);
1771         if (r) {
1772                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1773                 goto failed;
1774         }
1775
1776         /* init the mode config */
1777         drm_mode_config_init(adev->ddev);
1778
1779         r = amdgpu_init(adev);
1780         if (r) {
1781                 dev_err(adev->dev, "amdgpu_init failed\n");
1782                 amdgpu_fini(adev);
1783                 goto failed;
1784         }
1785
1786         adev->accel_working = true;
1787
1788         /* Initialize the buffer migration limit. */
1789         if (amdgpu_moverate >= 0)
1790                 max_MBps = amdgpu_moverate;
1791         else
1792                 max_MBps = 8; /* Allow 8 MB/s. */
1793         /* Get a log2 for easy divisions. */
1794         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
1795
1796         amdgpu_fbdev_init(adev);
1797
1798         r = amdgpu_ib_pool_init(adev);
1799         if (r) {
1800                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1801                 goto failed;
1802         }
1803
1804         r = amdgpu_ib_ring_tests(adev);
1805         if (r)
1806                 DRM_ERROR("ib ring test failed (%d).\n", r);
1807
1808         r = amdgpu_gem_debugfs_init(adev);
1809         if (r) {
1810                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1811         }
1812
1813         r = amdgpu_debugfs_regs_init(adev);
1814         if (r) {
1815                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1816         }
1817
1818         r = amdgpu_debugfs_firmware_init(adev);
1819         if (r) {
1820                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1821                 return r;
1822         }
1823
1824         if ((amdgpu_testing & 1)) {
1825                 if (adev->accel_working)
1826                         amdgpu_test_moves(adev);
1827                 else
1828                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1829         }
1830         if ((amdgpu_testing & 2)) {
1831                 if (adev->accel_working)
1832                         amdgpu_test_syncing(adev);
1833                 else
1834                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1835         }
1836         if (amdgpu_benchmarking) {
1837                 if (adev->accel_working)
1838                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1839                 else
1840                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1841         }
1842
1843         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1844          * explicit gating rather than handling it automatically.
1845          */
1846         r = amdgpu_late_init(adev);
1847         if (r) {
1848                 dev_err(adev->dev, "amdgpu_late_init failed\n");
1849                 goto failed;
1850         }
1851
1852         return 0;
1853
1854 failed:
1855         if (runtime)
1856                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1857         return r;
1858 }
1859
1860 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1861
1862 /**
1863  * amdgpu_device_fini - tear down the driver
1864  *
1865  * @adev: amdgpu_device pointer
1866  *
1867  * Tear down the driver info (all asics).
1868  * Called at driver shutdown.
1869  */
1870 void amdgpu_device_fini(struct amdgpu_device *adev)
1871 {
1872         int r;
1873
1874         DRM_INFO("amdgpu: finishing device.\n");
1875         adev->shutdown = true;
1876         drm_crtc_force_disable_all(adev->ddev);
1877         /* evict vram memory */
1878         amdgpu_bo_evict_vram(adev);
1879         amdgpu_ib_pool_fini(adev);
1880         amdgpu_fence_driver_fini(adev);
1881         amdgpu_fbdev_fini(adev);
1882         r = amdgpu_fini(adev);
1883         adev->accel_working = false;
1884         /* free i2c buses */
1885         amdgpu_i2c_fini(adev);
1886         amdgpu_atombios_fini(adev);
1887         kfree(adev->bios);
1888         adev->bios = NULL;
1889         vga_switcheroo_unregister_client(adev->pdev);
1890         if (adev->flags & AMD_IS_PX)
1891                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
1892         vga_client_register(adev->pdev, NULL, NULL, NULL);
1893         if (adev->rio_mem)
1894                 pci_iounmap(adev->pdev, adev->rio_mem);
1895         adev->rio_mem = NULL;
1896         iounmap(adev->rmmio);
1897         adev->rmmio = NULL;
1898         if (adev->asic_type >= CHIP_BONAIRE)
1899                 amdgpu_doorbell_fini(adev);
1900         amdgpu_debugfs_regs_cleanup(adev);
1901         amdgpu_debugfs_remove_files(adev);
1902 }
1903
1904
1905 /*
1906  * Suspend & resume.
1907  */
1908 /**
1909  * amdgpu_device_suspend - initiate device suspend
1910  *
1911  * @pdev: drm dev pointer
1912  * @state: suspend state
1913  *
1914  * Puts the hw in the suspend state (all asics).
1915  * Returns 0 for success or an error on failure.
1916  * Called at driver suspend.
1917  */
1918 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
1919 {
1920         struct amdgpu_device *adev;
1921         struct drm_crtc *crtc;
1922         struct drm_connector *connector;
1923         int r;
1924
1925         if (dev == NULL || dev->dev_private == NULL) {
1926                 return -ENODEV;
1927         }
1928
1929         adev = dev->dev_private;
1930
1931         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1932                 return 0;
1933
1934         drm_kms_helper_poll_disable(dev);
1935
1936         /* turn off display hw */
1937         drm_modeset_lock_all(dev);
1938         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1939                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1940         }
1941         drm_modeset_unlock_all(dev);
1942
1943         /* unpin the front buffers and cursors */
1944         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1945                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1946                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1947                 struct amdgpu_bo *robj;
1948
1949                 if (amdgpu_crtc->cursor_bo) {
1950                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1951                         r = amdgpu_bo_reserve(aobj, false);
1952                         if (r == 0) {
1953                                 amdgpu_bo_unpin(aobj);
1954                                 amdgpu_bo_unreserve(aobj);
1955                         }
1956                 }
1957
1958                 if (rfb == NULL || rfb->obj == NULL) {
1959                         continue;
1960                 }
1961                 robj = gem_to_amdgpu_bo(rfb->obj);
1962                 /* don't unpin kernel fb objects */
1963                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1964                         r = amdgpu_bo_reserve(robj, false);
1965                         if (r == 0) {
1966                                 amdgpu_bo_unpin(robj);
1967                                 amdgpu_bo_unreserve(robj);
1968                         }
1969                 }
1970         }
1971         /* evict vram memory */
1972         amdgpu_bo_evict_vram(adev);
1973
1974         amdgpu_fence_driver_suspend(adev);
1975
1976         r = amdgpu_suspend(adev);
1977
1978         /* evict remaining vram memory
1979          * This second call to evict vram is to evict the gart page table
1980          * using the CPU.
1981          */
1982         amdgpu_bo_evict_vram(adev);
1983
1984         pci_save_state(dev->pdev);
1985         if (suspend) {
1986                 /* Shut down the device */
1987                 pci_disable_device(dev->pdev);
1988                 pci_set_power_state(dev->pdev, PCI_D3hot);
1989         } else {
1990                 r = amdgpu_asic_reset(adev);
1991                 if (r)
1992                         DRM_ERROR("amdgpu asic reset failed\n");
1993         }
1994
1995         if (fbcon) {
1996                 console_lock();
1997                 amdgpu_fbdev_set_suspend(adev, 1);
1998                 console_unlock();
1999         }
2000         return 0;
2001 }
2002
2003 /**
2004  * amdgpu_device_resume - initiate device resume
2005  *
2006  * @pdev: drm dev pointer
2007  *
2008  * Bring the hw back to operating state (all asics).
2009  * Returns 0 for success or an error on failure.
2010  * Called at driver resume.
2011  */
2012 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2013 {
2014         struct drm_connector *connector;
2015         struct amdgpu_device *adev = dev->dev_private;
2016         struct drm_crtc *crtc;
2017         int r;
2018
2019         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2020                 return 0;
2021
2022         if (fbcon)
2023                 console_lock();
2024
2025         if (resume) {
2026                 pci_set_power_state(dev->pdev, PCI_D0);
2027                 pci_restore_state(dev->pdev);
2028                 r = pci_enable_device(dev->pdev);
2029                 if (r) {
2030                         if (fbcon)
2031                                 console_unlock();
2032                         return r;
2033                 }
2034         }
2035
2036         /* post card */
2037         if (!amdgpu_card_posted(adev) || !resume) {
2038                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2039                 if (r)
2040                         DRM_ERROR("amdgpu asic init failed\n");
2041         }
2042
2043         r = amdgpu_resume(adev);
2044         if (r)
2045                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2046
2047         amdgpu_fence_driver_resume(adev);
2048
2049         if (resume) {
2050                 r = amdgpu_ib_ring_tests(adev);
2051                 if (r)
2052                         DRM_ERROR("ib ring test failed (%d).\n", r);
2053         }
2054
2055         r = amdgpu_late_init(adev);
2056         if (r)
2057                 return r;
2058
2059         /* pin cursors */
2060         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2061                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2062
2063                 if (amdgpu_crtc->cursor_bo) {
2064                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2065                         r = amdgpu_bo_reserve(aobj, false);
2066                         if (r == 0) {
2067                                 r = amdgpu_bo_pin(aobj,
2068                                                   AMDGPU_GEM_DOMAIN_VRAM,
2069                                                   &amdgpu_crtc->cursor_addr);
2070                                 if (r != 0)
2071                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2072                                 amdgpu_bo_unreserve(aobj);
2073                         }
2074                 }
2075         }
2076
2077         /* blat the mode back in */
2078         if (fbcon) {
2079                 drm_helper_resume_force_mode(dev);
2080                 /* turn on display hw */
2081                 drm_modeset_lock_all(dev);
2082                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2083                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2084                 }
2085                 drm_modeset_unlock_all(dev);
2086         }
2087
2088         drm_kms_helper_poll_enable(dev);
2089
2090         /*
2091          * Most of the connector probing functions try to acquire runtime pm
2092          * refs to ensure that the GPU is powered on when connector polling is
2093          * performed. Since we're calling this from a runtime PM callback,
2094          * trying to acquire rpm refs will cause us to deadlock.
2095          *
2096          * Since we're guaranteed to be holding the rpm lock, it's safe to
2097          * temporarily disable the rpm helpers so this doesn't deadlock us.
2098          */
2099 #ifdef CONFIG_PM
2100         dev->dev->power.disable_depth++;
2101 #endif
2102         drm_helper_hpd_irq_event(dev);
2103 #ifdef CONFIG_PM
2104         dev->dev->power.disable_depth--;
2105 #endif
2106
2107         if (fbcon) {
2108                 amdgpu_fbdev_set_suspend(adev, 0);
2109                 console_unlock();
2110         }
2111
2112         return 0;
2113 }
2114
2115 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2116 {
2117         int i;
2118         bool asic_hang = false;
2119
2120         for (i = 0; i < adev->num_ip_blocks; i++) {
2121                 if (!adev->ip_blocks[i].status.valid)
2122                         continue;
2123                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2124                         adev->ip_blocks[i].status.hang =
2125                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2126                 if (adev->ip_blocks[i].status.hang) {
2127                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2128                         asic_hang = true;
2129                 }
2130         }
2131         return asic_hang;
2132 }
2133
2134 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2135 {
2136         int i, r = 0;
2137
2138         for (i = 0; i < adev->num_ip_blocks; i++) {
2139                 if (!adev->ip_blocks[i].status.valid)
2140                         continue;
2141                 if (adev->ip_blocks[i].status.hang &&
2142                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2143                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2144                         if (r)
2145                                 return r;
2146                 }
2147         }
2148
2149         return 0;
2150 }
2151
2152 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2153 {
2154         int i;
2155
2156         for (i = 0; i < adev->num_ip_blocks; i++) {
2157                 if (!adev->ip_blocks[i].status.valid)
2158                         continue;
2159                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2160                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2161                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2162                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE)) {
2163                         if (adev->ip_blocks[i].status.hang) {
2164                                 DRM_INFO("Some block need full reset!\n");
2165                                 return true;
2166                         }
2167                 }
2168         }
2169         return false;
2170 }
2171
2172 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2173 {
2174         int i, r = 0;
2175
2176         for (i = 0; i < adev->num_ip_blocks; i++) {
2177                 if (!adev->ip_blocks[i].status.valid)
2178                         continue;
2179                 if (adev->ip_blocks[i].status.hang &&
2180                     adev->ip_blocks[i].version->funcs->soft_reset) {
2181                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2182                         if (r)
2183                                 return r;
2184                 }
2185         }
2186
2187         return 0;
2188 }
2189
2190 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2191 {
2192         int i, r = 0;
2193
2194         for (i = 0; i < adev->num_ip_blocks; i++) {
2195                 if (!adev->ip_blocks[i].status.valid)
2196                         continue;
2197                 if (adev->ip_blocks[i].status.hang &&
2198                     adev->ip_blocks[i].version->funcs->post_soft_reset)
2199                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2200                 if (r)
2201                         return r;
2202         }
2203
2204         return 0;
2205 }
2206
2207 bool amdgpu_need_backup(struct amdgpu_device *adev)
2208 {
2209         if (adev->flags & AMD_IS_APU)
2210                 return false;
2211
2212         return amdgpu_lockup_timeout > 0 ? true : false;
2213 }
2214
2215 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2216                                            struct amdgpu_ring *ring,
2217                                            struct amdgpu_bo *bo,
2218                                            struct dma_fence **fence)
2219 {
2220         uint32_t domain;
2221         int r;
2222
2223        if (!bo->shadow)
2224                return 0;
2225
2226        r = amdgpu_bo_reserve(bo, false);
2227        if (r)
2228                return r;
2229        domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2230        /* if bo has been evicted, then no need to recover */
2231        if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2232                r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2233                                                  NULL, fence, true);
2234                if (r) {
2235                        DRM_ERROR("recover page table failed!\n");
2236                        goto err;
2237                }
2238        }
2239 err:
2240        amdgpu_bo_unreserve(bo);
2241        return r;
2242 }
2243
2244 /**
2245  * amdgpu_gpu_reset - reset the asic
2246  *
2247  * @adev: amdgpu device pointer
2248  *
2249  * Attempt the reset the GPU if it has hung (all asics).
2250  * Returns 0 for success or an error on failure.
2251  */
2252 int amdgpu_gpu_reset(struct amdgpu_device *adev)
2253 {
2254         int i, r;
2255         int resched;
2256         bool need_full_reset;
2257
2258         if (!amdgpu_check_soft_reset(adev)) {
2259                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
2260                 return 0;
2261         }
2262
2263         atomic_inc(&adev->gpu_reset_counter);
2264
2265         /* block TTM */
2266         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
2267
2268         /* block scheduler */
2269         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2270                 struct amdgpu_ring *ring = adev->rings[i];
2271
2272                 if (!ring)
2273                         continue;
2274                 kthread_park(ring->sched.thread);
2275                 amd_sched_hw_job_reset(&ring->sched);
2276         }
2277         /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
2278         amdgpu_fence_driver_force_completion(adev);
2279
2280         need_full_reset = amdgpu_need_full_reset(adev);
2281
2282         if (!need_full_reset) {
2283                 amdgpu_pre_soft_reset(adev);
2284                 r = amdgpu_soft_reset(adev);
2285                 amdgpu_post_soft_reset(adev);
2286                 if (r || amdgpu_check_soft_reset(adev)) {
2287                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2288                         need_full_reset = true;
2289                 }
2290         }
2291
2292         if (need_full_reset) {
2293                 /* save scratch */
2294                 amdgpu_atombios_scratch_regs_save(adev);
2295                 r = amdgpu_suspend(adev);
2296
2297 retry:
2298                 /* Disable fb access */
2299                 if (adev->mode_info.num_crtc) {
2300                         struct amdgpu_mode_mc_save save;
2301                         amdgpu_display_stop_mc_access(adev, &save);
2302                         amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
2303                 }
2304
2305                 r = amdgpu_asic_reset(adev);
2306                 /* post card */
2307                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2308
2309                 if (!r) {
2310                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2311                         r = amdgpu_resume(adev);
2312                 }
2313                 /* restore scratch */
2314                 amdgpu_atombios_scratch_regs_restore(adev);
2315         }
2316         if (!r) {
2317                 amdgpu_irq_gpu_reset_resume_helper(adev);
2318                 if (need_full_reset && amdgpu_need_backup(adev)) {
2319                         r = amdgpu_ttm_recover_gart(adev);
2320                         if (r)
2321                                 DRM_ERROR("gart recovery failed!!!\n");
2322                 }
2323                 r = amdgpu_ib_ring_tests(adev);
2324                 if (r) {
2325                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2326                         r = amdgpu_suspend(adev);
2327                         need_full_reset = true;
2328                         goto retry;
2329                 }
2330                 /**
2331                  * recovery vm page tables, since we cannot depend on VRAM is
2332                  * consistent after gpu full reset.
2333                  */
2334                 if (need_full_reset && amdgpu_need_backup(adev)) {
2335                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2336                         struct amdgpu_bo *bo, *tmp;
2337                         struct dma_fence *fence = NULL, *next = NULL;
2338
2339                         DRM_INFO("recover vram bo from shadow\n");
2340                         mutex_lock(&adev->shadow_list_lock);
2341                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
2342                                 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
2343                                 if (fence) {
2344                                         r = dma_fence_wait(fence, false);
2345                                         if (r) {
2346                                                 WARN(r, "recovery from shadow isn't comleted\n");
2347                                                 break;
2348                                         }
2349                                 }
2350
2351                                 dma_fence_put(fence);
2352                                 fence = next;
2353                         }
2354                         mutex_unlock(&adev->shadow_list_lock);
2355                         if (fence) {
2356                                 r = dma_fence_wait(fence, false);
2357                                 if (r)
2358                                         WARN(r, "recovery from shadow isn't comleted\n");
2359                         }
2360                         dma_fence_put(fence);
2361                 }
2362                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2363                         struct amdgpu_ring *ring = adev->rings[i];
2364                         if (!ring)
2365                                 continue;
2366
2367                         amd_sched_job_recovery(&ring->sched);
2368                         kthread_unpark(ring->sched.thread);
2369                 }
2370         } else {
2371                 dev_err(adev->dev, "asic resume failed (%d).\n", r);
2372                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2373                         if (adev->rings[i]) {
2374                                 kthread_unpark(adev->rings[i]->sched.thread);
2375                         }
2376                 }
2377         }
2378
2379         drm_helper_resume_force_mode(adev->ddev);
2380
2381         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
2382         if (r) {
2383                 /* bad news, how to tell it to userspace ? */
2384                 dev_info(adev->dev, "GPU reset failed\n");
2385         }
2386
2387         return r;
2388 }
2389
2390 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
2391 {
2392         u32 mask;
2393         int ret;
2394
2395         if (amdgpu_pcie_gen_cap)
2396                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
2397
2398         if (amdgpu_pcie_lane_cap)
2399                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
2400
2401         /* covers APUs as well */
2402         if (pci_is_root_bus(adev->pdev->bus)) {
2403                 if (adev->pm.pcie_gen_mask == 0)
2404                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2405                 if (adev->pm.pcie_mlw_mask == 0)
2406                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2407                 return;
2408         }
2409
2410         if (adev->pm.pcie_gen_mask == 0) {
2411                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
2412                 if (!ret) {
2413                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
2414                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2415                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
2416
2417                         if (mask & DRM_PCIE_SPEED_25)
2418                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
2419                         if (mask & DRM_PCIE_SPEED_50)
2420                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
2421                         if (mask & DRM_PCIE_SPEED_80)
2422                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
2423                 } else {
2424                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
2425                 }
2426         }
2427         if (adev->pm.pcie_mlw_mask == 0) {
2428                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
2429                 if (!ret) {
2430                         switch (mask) {
2431                         case 32:
2432                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
2433                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2434                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2435                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2436                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2437                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2438                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2439                                 break;
2440                         case 16:
2441                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
2442                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2443                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2444                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2445                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2446                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2447                                 break;
2448                         case 12:
2449                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
2450                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2451                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2452                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2453                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2454                                 break;
2455                         case 8:
2456                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
2457                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2458                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2459                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2460                                 break;
2461                         case 4:
2462                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
2463                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2464                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2465                                 break;
2466                         case 2:
2467                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
2468                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
2469                                 break;
2470                         case 1:
2471                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
2472                                 break;
2473                         default:
2474                                 break;
2475                         }
2476                 } else {
2477                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2478                 }
2479         }
2480 }
2481
2482 /*
2483  * Debugfs
2484  */
2485 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2486                              const struct drm_info_list *files,
2487                              unsigned nfiles)
2488 {
2489         unsigned i;
2490
2491         for (i = 0; i < adev->debugfs_count; i++) {
2492                 if (adev->debugfs[i].files == files) {
2493                         /* Already registered */
2494                         return 0;
2495                 }
2496         }
2497
2498         i = adev->debugfs_count + 1;
2499         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2500                 DRM_ERROR("Reached maximum number of debugfs components.\n");
2501                 DRM_ERROR("Report so we increase "
2502                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2503                 return -EINVAL;
2504         }
2505         adev->debugfs[adev->debugfs_count].files = files;
2506         adev->debugfs[adev->debugfs_count].num_files = nfiles;
2507         adev->debugfs_count = i;
2508 #if defined(CONFIG_DEBUG_FS)
2509         drm_debugfs_create_files(files, nfiles,
2510                                  adev->ddev->control->debugfs_root,
2511                                  adev->ddev->control);
2512         drm_debugfs_create_files(files, nfiles,
2513                                  adev->ddev->primary->debugfs_root,
2514                                  adev->ddev->primary);
2515 #endif
2516         return 0;
2517 }
2518
2519 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2520 {
2521 #if defined(CONFIG_DEBUG_FS)
2522         unsigned i;
2523
2524         for (i = 0; i < adev->debugfs_count; i++) {
2525                 drm_debugfs_remove_files(adev->debugfs[i].files,
2526                                          adev->debugfs[i].num_files,
2527                                          adev->ddev->control);
2528                 drm_debugfs_remove_files(adev->debugfs[i].files,
2529                                          adev->debugfs[i].num_files,
2530                                          adev->ddev->primary);
2531         }
2532 #endif
2533 }
2534
2535 #if defined(CONFIG_DEBUG_FS)
2536
2537 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2538                                         size_t size, loff_t *pos)
2539 {
2540         struct amdgpu_device *adev = f->f_inode->i_private;
2541         ssize_t result = 0;
2542         int r;
2543         bool pm_pg_lock, use_bank;
2544         unsigned instance_bank, sh_bank, se_bank;
2545
2546         if (size & 0x3 || *pos & 0x3)
2547                 return -EINVAL;
2548
2549         /* are we reading registers for which a PG lock is necessary? */
2550         pm_pg_lock = (*pos >> 23) & 1;
2551
2552         if (*pos & (1ULL << 62)) {
2553                 se_bank = (*pos >> 24) & 0x3FF;
2554                 sh_bank = (*pos >> 34) & 0x3FF;
2555                 instance_bank = (*pos >> 44) & 0x3FF;
2556
2557                 if (se_bank == 0x3FF)
2558                         se_bank = 0xFFFFFFFF;
2559                 if (sh_bank == 0x3FF)
2560                         sh_bank = 0xFFFFFFFF;
2561                 if (instance_bank == 0x3FF)
2562                         instance_bank = 0xFFFFFFFF;
2563                 use_bank = 1;
2564         } else {
2565                 use_bank = 0;
2566         }
2567
2568         *pos &= 0x3FFFF;
2569
2570         if (use_bank) {
2571                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2572                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2573                         return -EINVAL;
2574                 mutex_lock(&adev->grbm_idx_mutex);
2575                 amdgpu_gfx_select_se_sh(adev, se_bank,
2576                                         sh_bank, instance_bank);
2577         }
2578
2579         if (pm_pg_lock)
2580                 mutex_lock(&adev->pm.mutex);
2581
2582         while (size) {
2583                 uint32_t value;
2584
2585                 if (*pos > adev->rmmio_size)
2586                         goto end;
2587
2588                 value = RREG32(*pos >> 2);
2589                 r = put_user(value, (uint32_t *)buf);
2590                 if (r) {
2591                         result = r;
2592                         goto end;
2593                 }
2594
2595                 result += 4;
2596                 buf += 4;
2597                 *pos += 4;
2598                 size -= 4;
2599         }
2600
2601 end:
2602         if (use_bank) {
2603                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2604                 mutex_unlock(&adev->grbm_idx_mutex);
2605         }
2606
2607         if (pm_pg_lock)
2608                 mutex_unlock(&adev->pm.mutex);
2609
2610         return result;
2611 }
2612
2613 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2614                                          size_t size, loff_t *pos)
2615 {
2616         struct amdgpu_device *adev = f->f_inode->i_private;
2617         ssize_t result = 0;
2618         int r;
2619         bool pm_pg_lock, use_bank;
2620         unsigned instance_bank, sh_bank, se_bank;
2621
2622         if (size & 0x3 || *pos & 0x3)
2623                 return -EINVAL;
2624
2625         /* are we reading registers for which a PG lock is necessary? */
2626         pm_pg_lock = (*pos >> 23) & 1;
2627
2628         if (*pos & (1ULL << 62)) {
2629                 se_bank = (*pos >> 24) & 0x3FF;
2630                 sh_bank = (*pos >> 34) & 0x3FF;
2631                 instance_bank = (*pos >> 44) & 0x3FF;
2632
2633                 if (se_bank == 0x3FF)
2634                         se_bank = 0xFFFFFFFF;
2635                 if (sh_bank == 0x3FF)
2636                         sh_bank = 0xFFFFFFFF;
2637                 if (instance_bank == 0x3FF)
2638                         instance_bank = 0xFFFFFFFF;
2639                 use_bank = 1;
2640         } else {
2641                 use_bank = 0;
2642         }
2643
2644         *pos &= 0x3FFFF;
2645
2646         if (use_bank) {
2647                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
2648                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
2649                         return -EINVAL;
2650                 mutex_lock(&adev->grbm_idx_mutex);
2651                 amdgpu_gfx_select_se_sh(adev, se_bank,
2652                                         sh_bank, instance_bank);
2653         }
2654
2655         if (pm_pg_lock)
2656                 mutex_lock(&adev->pm.mutex);
2657
2658         while (size) {
2659                 uint32_t value;
2660
2661                 if (*pos > adev->rmmio_size)
2662                         return result;
2663
2664                 r = get_user(value, (uint32_t *)buf);
2665                 if (r)
2666                         return r;
2667
2668                 WREG32(*pos >> 2, value);
2669
2670                 result += 4;
2671                 buf += 4;
2672                 *pos += 4;
2673                 size -= 4;
2674         }
2675
2676         if (use_bank) {
2677                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2678                 mutex_unlock(&adev->grbm_idx_mutex);
2679         }
2680
2681         if (pm_pg_lock)
2682                 mutex_unlock(&adev->pm.mutex);
2683
2684         return result;
2685 }
2686
2687 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
2688                                         size_t size, loff_t *pos)
2689 {
2690         struct amdgpu_device *adev = f->f_inode->i_private;
2691         ssize_t result = 0;
2692         int r;
2693
2694         if (size & 0x3 || *pos & 0x3)
2695                 return -EINVAL;
2696
2697         while (size) {
2698                 uint32_t value;
2699
2700                 value = RREG32_PCIE(*pos >> 2);
2701                 r = put_user(value, (uint32_t *)buf);
2702                 if (r)
2703                         return r;
2704
2705                 result += 4;
2706                 buf += 4;
2707                 *pos += 4;
2708                 size -= 4;
2709         }
2710
2711         return result;
2712 }
2713
2714 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
2715                                          size_t size, loff_t *pos)
2716 {
2717         struct amdgpu_device *adev = f->f_inode->i_private;
2718         ssize_t result = 0;
2719         int r;
2720
2721         if (size & 0x3 || *pos & 0x3)
2722                 return -EINVAL;
2723
2724         while (size) {
2725                 uint32_t value;
2726
2727                 r = get_user(value, (uint32_t *)buf);
2728                 if (r)
2729                         return r;
2730
2731                 WREG32_PCIE(*pos >> 2, value);
2732
2733                 result += 4;
2734                 buf += 4;
2735                 *pos += 4;
2736                 size -= 4;
2737         }
2738
2739         return result;
2740 }
2741
2742 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
2743                                         size_t size, loff_t *pos)
2744 {
2745         struct amdgpu_device *adev = f->f_inode->i_private;
2746         ssize_t result = 0;
2747         int r;
2748
2749         if (size & 0x3 || *pos & 0x3)
2750                 return -EINVAL;
2751
2752         while (size) {
2753                 uint32_t value;
2754
2755                 value = RREG32_DIDT(*pos >> 2);
2756                 r = put_user(value, (uint32_t *)buf);
2757                 if (r)
2758                         return r;
2759
2760                 result += 4;
2761                 buf += 4;
2762                 *pos += 4;
2763                 size -= 4;
2764         }
2765
2766         return result;
2767 }
2768
2769 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
2770                                          size_t size, loff_t *pos)
2771 {
2772         struct amdgpu_device *adev = f->f_inode->i_private;
2773         ssize_t result = 0;
2774         int r;
2775
2776         if (size & 0x3 || *pos & 0x3)
2777                 return -EINVAL;
2778
2779         while (size) {
2780                 uint32_t value;
2781
2782                 r = get_user(value, (uint32_t *)buf);
2783                 if (r)
2784                         return r;
2785
2786                 WREG32_DIDT(*pos >> 2, value);
2787
2788                 result += 4;
2789                 buf += 4;
2790                 *pos += 4;
2791                 size -= 4;
2792         }
2793
2794         return result;
2795 }
2796
2797 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
2798                                         size_t size, loff_t *pos)
2799 {
2800         struct amdgpu_device *adev = f->f_inode->i_private;
2801         ssize_t result = 0;
2802         int r;
2803
2804         if (size & 0x3 || *pos & 0x3)
2805                 return -EINVAL;
2806
2807         while (size) {
2808                 uint32_t value;
2809
2810                 value = RREG32_SMC(*pos);
2811                 r = put_user(value, (uint32_t *)buf);
2812                 if (r)
2813                         return r;
2814
2815                 result += 4;
2816                 buf += 4;
2817                 *pos += 4;
2818                 size -= 4;
2819         }
2820
2821         return result;
2822 }
2823
2824 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
2825                                          size_t size, loff_t *pos)
2826 {
2827         struct amdgpu_device *adev = f->f_inode->i_private;
2828         ssize_t result = 0;
2829         int r;
2830
2831         if (size & 0x3 || *pos & 0x3)
2832                 return -EINVAL;
2833
2834         while (size) {
2835                 uint32_t value;
2836
2837                 r = get_user(value, (uint32_t *)buf);
2838                 if (r)
2839                         return r;
2840
2841                 WREG32_SMC(*pos, value);
2842
2843                 result += 4;
2844                 buf += 4;
2845                 *pos += 4;
2846                 size -= 4;
2847         }
2848
2849         return result;
2850 }
2851
2852 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
2853                                         size_t size, loff_t *pos)
2854 {
2855         struct amdgpu_device *adev = f->f_inode->i_private;
2856         ssize_t result = 0;
2857         int r;
2858         uint32_t *config, no_regs = 0;
2859
2860         if (size & 0x3 || *pos & 0x3)
2861                 return -EINVAL;
2862
2863         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
2864         if (!config)
2865                 return -ENOMEM;
2866
2867         /* version, increment each time something is added */
2868         config[no_regs++] = 2;
2869         config[no_regs++] = adev->gfx.config.max_shader_engines;
2870         config[no_regs++] = adev->gfx.config.max_tile_pipes;
2871         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
2872         config[no_regs++] = adev->gfx.config.max_sh_per_se;
2873         config[no_regs++] = adev->gfx.config.max_backends_per_se;
2874         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
2875         config[no_regs++] = adev->gfx.config.max_gprs;
2876         config[no_regs++] = adev->gfx.config.max_gs_threads;
2877         config[no_regs++] = adev->gfx.config.max_hw_contexts;
2878         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
2879         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
2880         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
2881         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
2882         config[no_regs++] = adev->gfx.config.num_tile_pipes;
2883         config[no_regs++] = adev->gfx.config.backend_enable_mask;
2884         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
2885         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
2886         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
2887         config[no_regs++] = adev->gfx.config.num_gpus;
2888         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
2889         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
2890         config[no_regs++] = adev->gfx.config.gb_addr_config;
2891         config[no_regs++] = adev->gfx.config.num_rbs;
2892
2893         /* rev==1 */
2894         config[no_regs++] = adev->rev_id;
2895         config[no_regs++] = adev->pg_flags;
2896         config[no_regs++] = adev->cg_flags;
2897
2898         /* rev==2 */
2899         config[no_regs++] = adev->family;
2900         config[no_regs++] = adev->external_rev_id;
2901
2902         while (size && (*pos < no_regs * 4)) {
2903                 uint32_t value;
2904
2905                 value = config[*pos >> 2];
2906                 r = put_user(value, (uint32_t *)buf);
2907                 if (r) {
2908                         kfree(config);
2909                         return r;
2910                 }
2911
2912                 result += 4;
2913                 buf += 4;
2914                 *pos += 4;
2915                 size -= 4;
2916         }
2917
2918         kfree(config);
2919         return result;
2920 }
2921
2922 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
2923                                         size_t size, loff_t *pos)
2924 {
2925         struct amdgpu_device *adev = f->f_inode->i_private;
2926         int idx, r;
2927         int32_t value;
2928
2929         if (size != 4 || *pos & 0x3)
2930                 return -EINVAL;
2931
2932         /* convert offset to sensor number */
2933         idx = *pos >> 2;
2934
2935         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
2936                 r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &value);
2937         else
2938                 return -EINVAL;
2939
2940         if (!r)
2941                 r = put_user(value, (int32_t *)buf);
2942
2943         return !r ? 4 : r;
2944 }
2945
2946 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
2947                                         size_t size, loff_t *pos)
2948 {
2949         struct amdgpu_device *adev = f->f_inode->i_private;
2950         int r, x;
2951         ssize_t result=0;
2952         uint32_t offset, se, sh, cu, wave, simd, data[32];
2953
2954         if (size & 3 || *pos & 3)
2955                 return -EINVAL;
2956
2957         /* decode offset */
2958         offset = (*pos & 0x7F);
2959         se = ((*pos >> 7) & 0xFF);
2960         sh = ((*pos >> 15) & 0xFF);
2961         cu = ((*pos >> 23) & 0xFF);
2962         wave = ((*pos >> 31) & 0xFF);
2963         simd = ((*pos >> 37) & 0xFF);
2964
2965         /* switch to the specific se/sh/cu */
2966         mutex_lock(&adev->grbm_idx_mutex);
2967         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
2968
2969         x = 0;
2970         if (adev->gfx.funcs->read_wave_data)
2971                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
2972
2973         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
2974         mutex_unlock(&adev->grbm_idx_mutex);
2975
2976         if (!x)
2977                 return -EINVAL;
2978
2979         while (size && (offset < x * 4)) {
2980                 uint32_t value;
2981
2982                 value = data[offset >> 2];
2983                 r = put_user(value, (uint32_t *)buf);
2984                 if (r)
2985                         return r;
2986
2987                 result += 4;
2988                 buf += 4;
2989                 offset += 4;
2990                 size -= 4;
2991         }
2992
2993         return result;
2994 }
2995
2996 static const struct file_operations amdgpu_debugfs_regs_fops = {
2997         .owner = THIS_MODULE,
2998         .read = amdgpu_debugfs_regs_read,
2999         .write = amdgpu_debugfs_regs_write,
3000         .llseek = default_llseek
3001 };
3002 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3003         .owner = THIS_MODULE,
3004         .read = amdgpu_debugfs_regs_didt_read,
3005         .write = amdgpu_debugfs_regs_didt_write,
3006         .llseek = default_llseek
3007 };
3008 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3009         .owner = THIS_MODULE,
3010         .read = amdgpu_debugfs_regs_pcie_read,
3011         .write = amdgpu_debugfs_regs_pcie_write,
3012         .llseek = default_llseek
3013 };
3014 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3015         .owner = THIS_MODULE,
3016         .read = amdgpu_debugfs_regs_smc_read,
3017         .write = amdgpu_debugfs_regs_smc_write,
3018         .llseek = default_llseek
3019 };
3020
3021 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3022         .owner = THIS_MODULE,
3023         .read = amdgpu_debugfs_gca_config_read,
3024         .llseek = default_llseek
3025 };
3026
3027 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3028         .owner = THIS_MODULE,
3029         .read = amdgpu_debugfs_sensor_read,
3030         .llseek = default_llseek
3031 };
3032
3033 static const struct file_operations amdgpu_debugfs_wave_fops = {
3034         .owner = THIS_MODULE,
3035         .read = amdgpu_debugfs_wave_read,
3036         .llseek = default_llseek
3037 };
3038
3039 static const struct file_operations *debugfs_regs[] = {
3040         &amdgpu_debugfs_regs_fops,
3041         &amdgpu_debugfs_regs_didt_fops,
3042         &amdgpu_debugfs_regs_pcie_fops,
3043         &amdgpu_debugfs_regs_smc_fops,
3044         &amdgpu_debugfs_gca_config_fops,
3045         &amdgpu_debugfs_sensors_fops,
3046         &amdgpu_debugfs_wave_fops,
3047 };
3048
3049 static const char *debugfs_regs_names[] = {
3050         "amdgpu_regs",
3051         "amdgpu_regs_didt",
3052         "amdgpu_regs_pcie",
3053         "amdgpu_regs_smc",
3054         "amdgpu_gca_config",
3055         "amdgpu_sensors",
3056         "amdgpu_wave",
3057 };
3058
3059 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3060 {
3061         struct drm_minor *minor = adev->ddev->primary;
3062         struct dentry *ent, *root = minor->debugfs_root;
3063         unsigned i, j;
3064
3065         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3066                 ent = debugfs_create_file(debugfs_regs_names[i],
3067                                           S_IFREG | S_IRUGO, root,
3068                                           adev, debugfs_regs[i]);
3069                 if (IS_ERR(ent)) {
3070                         for (j = 0; j < i; j++) {
3071                                 debugfs_remove(adev->debugfs_regs[i]);
3072                                 adev->debugfs_regs[i] = NULL;
3073                         }
3074                         return PTR_ERR(ent);
3075                 }
3076
3077                 if (!i)
3078                         i_size_write(ent->d_inode, adev->rmmio_size);
3079                 adev->debugfs_regs[i] = ent;
3080         }
3081
3082         return 0;
3083 }
3084
3085 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3086 {
3087         unsigned i;
3088
3089         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3090                 if (adev->debugfs_regs[i]) {
3091                         debugfs_remove(adev->debugfs_regs[i]);
3092                         adev->debugfs_regs[i] = NULL;
3093                 }
3094         }
3095 }
3096
3097 int amdgpu_debugfs_init(struct drm_minor *minor)
3098 {
3099         return 0;
3100 }
3101
3102 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
3103 {
3104 }
3105 #else
3106 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3107 {
3108         return 0;
3109 }
3110 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
3111 #endif