1 // SPDX-License-Identifier: GPL-2.0-only
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
8 #include <linux/delay.h>
9 #include <linux/slab.h>
10 #include <linux/vmalloc.h>
11 #include <linux/uaccess.h>
14 * NVRAM support routines
18 * qla2x00_lock_nvram_access() -
22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = rd_reg_word(®->nvram);
29 while (data & NVR_BUSY) {
31 data = rd_reg_word(®->nvram);
35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1);
36 rd_reg_word(®->u.isp2300.host_semaphore);
38 data = rd_reg_word(®->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1);
43 rd_reg_word(®->u.isp2300.host_semaphore);
45 data = rd_reg_word(®->u.isp2300.host_semaphore);
51 * qla2x00_unlock_nvram_access() -
55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 wrt_reg_word(®->u.isp2300.host_semaphore, 0);
61 rd_reg_word(®->u.isp2300.host_semaphore);
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @data: Serial interface selector
71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 rd_reg_word(®->nvram); /* PCI Posting. */
78 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_CLOCK |
80 rd_reg_word(®->nvram); /* PCI Posting. */
82 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 rd_reg_word(®->nvram); /* PCI Posting. */
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
91 * @nv_cmd: NVRAM command
93 * Bit definitions for NVRAM command:
98 * Bit 15-0 = write data
100 * Returns the word read from nvram @addr.
103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
110 /* Send command to NVRAM. */
112 for (cnt = 0; cnt < 11; cnt++) {
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 qla2x00_nv_write(ha, 0);
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 wrt_reg_word(®->nvram, NVR_SELECT | NVR_CLOCK);
123 rd_reg_word(®->nvram); /* PCI Posting. */
126 reg_data = rd_reg_word(®->nvram);
127 if (reg_data & NVR_DATA_IN)
129 wrt_reg_word(®->nvram, NVR_SELECT);
130 rd_reg_word(®->nvram); /* PCI Posting. */
135 wrt_reg_word(®->nvram, NVR_DESELECT);
136 rd_reg_word(®->nvram); /* PCI Posting. */
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
147 * @addr: Address in NVRAM to read
149 * Returns the word read from nvram @addr.
152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
169 qla2x00_nv_deselect(struct qla_hw_data *ha)
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173 wrt_reg_word(®->nvram, NVR_DESELECT);
174 rd_reg_word(®->nvram); /* PCI Posting. */
179 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @addr: Address in NVRAM to write
182 * @data: word to program
185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, __le16 data)
189 uint32_t nv_cmd, wait_cnt;
190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
191 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
193 qla2x00_nv_write(ha, NVR_DATA_OUT);
194 qla2x00_nv_write(ha, 0);
195 qla2x00_nv_write(ha, 0);
197 for (word = 0; word < 8; word++)
198 qla2x00_nv_write(ha, NVR_DATA_OUT);
200 qla2x00_nv_deselect(ha);
203 nv_cmd = (addr << 16) | NV_WRITE_OP;
204 nv_cmd |= (__force u16)data;
206 for (count = 0; count < 27; count++) {
208 qla2x00_nv_write(ha, NVR_DATA_OUT);
210 qla2x00_nv_write(ha, 0);
215 qla2x00_nv_deselect(ha);
217 /* Wait for NVRAM to become ready */
218 wrt_reg_word(®->nvram, NVR_SELECT);
219 rd_reg_word(®->nvram); /* PCI Posting. */
220 wait_cnt = NVR_WAIT_CNT;
223 ql_dbg(ql_dbg_user, vha, 0x708d,
224 "NVRAM didn't go ready...\n");
228 word = rd_reg_word(®->nvram);
229 } while ((word & NVR_DATA_IN) == 0);
231 qla2x00_nv_deselect(ha);
234 qla2x00_nv_write(ha, NVR_DATA_OUT);
235 for (count = 0; count < 10; count++)
236 qla2x00_nv_write(ha, 0);
238 qla2x00_nv_deselect(ha);
242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
243 __le16 data, uint32_t tmo)
248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
252 qla2x00_nv_write(ha, NVR_DATA_OUT);
253 qla2x00_nv_write(ha, 0);
254 qla2x00_nv_write(ha, 0);
256 for (word = 0; word < 8; word++)
257 qla2x00_nv_write(ha, NVR_DATA_OUT);
259 qla2x00_nv_deselect(ha);
262 nv_cmd = (addr << 16) | NV_WRITE_OP;
263 nv_cmd |= (__force u16)data;
265 for (count = 0; count < 27; count++) {
267 qla2x00_nv_write(ha, NVR_DATA_OUT);
269 qla2x00_nv_write(ha, 0);
274 qla2x00_nv_deselect(ha);
276 /* Wait for NVRAM to become ready */
277 wrt_reg_word(®->nvram, NVR_SELECT);
278 rd_reg_word(®->nvram); /* PCI Posting. */
281 word = rd_reg_word(®->nvram);
283 ret = QLA_FUNCTION_FAILED;
286 } while ((word & NVR_DATA_IN) == 0);
288 qla2x00_nv_deselect(ha);
291 qla2x00_nv_write(ha, NVR_DATA_OUT);
292 for (count = 0; count < 10; count++)
293 qla2x00_nv_write(ha, 0);
295 qla2x00_nv_deselect(ha);
301 * qla2x00_clear_nvram_protection() -
305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
309 uint32_t word, wait_cnt;
310 __le16 wprot, wprot_old;
311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
313 /* Clear NVRAM write protection. */
314 ret = QLA_FUNCTION_FAILED;
316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
318 cpu_to_le16(0x1234), 100000);
319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
320 if (stat != QLA_SUCCESS || wprot != cpu_to_le16(0x1234)) {
322 qla2x00_nv_write(ha, NVR_DATA_OUT);
323 qla2x00_nv_write(ha, 0);
324 qla2x00_nv_write(ha, 0);
325 for (word = 0; word < 8; word++)
326 qla2x00_nv_write(ha, NVR_DATA_OUT);
328 qla2x00_nv_deselect(ha);
330 /* Enable protection register. */
331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
332 qla2x00_nv_write(ha, NVR_PR_ENABLE);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 for (word = 0; word < 8; word++)
335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337 qla2x00_nv_deselect(ha);
339 /* Clear protection register (ffff is cleared). */
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 for (word = 0; word < 8; word++)
344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346 qla2x00_nv_deselect(ha);
348 /* Wait for NVRAM to become ready. */
349 wrt_reg_word(®->nvram, NVR_SELECT);
350 rd_reg_word(®->nvram); /* PCI Posting. */
351 wait_cnt = NVR_WAIT_CNT;
354 ql_dbg(ql_dbg_user, vha, 0x708e,
355 "NVRAM didn't go ready...\n");
359 word = rd_reg_word(®->nvram);
360 } while ((word & NVR_DATA_IN) == 0);
365 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
371 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
374 uint32_t word, wait_cnt;
375 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
377 if (stat != QLA_SUCCESS)
380 /* Set NVRAM write protection. */
382 qla2x00_nv_write(ha, NVR_DATA_OUT);
383 qla2x00_nv_write(ha, 0);
384 qla2x00_nv_write(ha, 0);
385 for (word = 0; word < 8; word++)
386 qla2x00_nv_write(ha, NVR_DATA_OUT);
388 qla2x00_nv_deselect(ha);
390 /* Enable protection register. */
391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
392 qla2x00_nv_write(ha, NVR_PR_ENABLE);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 for (word = 0; word < 8; word++)
395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397 qla2x00_nv_deselect(ha);
399 /* Enable protection register. */
400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
403 for (word = 0; word < 8; word++)
404 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406 qla2x00_nv_deselect(ha);
408 /* Wait for NVRAM to become ready. */
409 wrt_reg_word(®->nvram, NVR_SELECT);
410 rd_reg_word(®->nvram); /* PCI Posting. */
411 wait_cnt = NVR_WAIT_CNT;
414 ql_dbg(ql_dbg_user, vha, 0x708f,
415 "NVRAM didn't go ready...\n");
419 word = rd_reg_word(®->nvram);
420 } while ((word & NVR_DATA_IN) == 0);
424 /*****************************************************************************/
425 /* Flash Manipulation Routines */
426 /*****************************************************************************/
428 static inline uint32_t
429 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
431 return ha->flash_conf_off + faddr;
434 static inline uint32_t
435 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
437 return ha->flash_data_off + faddr;
440 static inline uint32_t
441 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
443 return ha->nvram_conf_off + naddr;
446 static inline uint32_t
447 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
449 return ha->nvram_data_off + naddr;
453 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data)
455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458 wrt_reg_dword(®->flash_addr, addr & ~FARX_DATA_FLAG);
461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) {
462 *data = rd_reg_dword(®->flash_data);
469 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
470 "Flash read dword at %x timeout.\n", addr);
472 return QLA_FUNCTION_TIMEOUT;
476 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
480 int ret = QLA_SUCCESS;
481 struct qla_hw_data *ha = vha->hw;
483 /* Dword reads to flash. */
484 faddr = flash_data_addr(ha, faddr);
485 for (i = 0; i < dwords; i++, faddr++, dwptr++) {
486 ret = qla24xx_read_flash_dword(ha, faddr, dwptr);
487 if (ret != QLA_SUCCESS)
496 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
501 wrt_reg_dword(®->flash_data, data);
502 wrt_reg_dword(®->flash_addr, addr | FARX_DATA_FLAG);
505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG))
511 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090,
512 "Flash write dword at %x timeout.\n", addr);
513 return QLA_FUNCTION_TIMEOUT;
517 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
520 uint32_t faddr, ids = 0;
522 *man_id = *flash_id = 0;
524 faddr = flash_conf_addr(ha, 0x03ab);
525 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
527 *flash_id = MSB(ids);
530 /* Check if man_id and flash_id are valid. */
531 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
532 /* Read information using 0x9f opcode
533 * Device ID, Mfg ID would be read in the format:
534 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
535 * Example: ATMEL 0x00 01 45 1F
536 * Extract MFG and Dev ID from last two bytes.
538 faddr = flash_conf_addr(ha, 0x009f);
539 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) {
541 *flash_id = MSB(ids);
547 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
549 const char *loc, *locations[] = { "DEF", "PCI" };
550 uint32_t pcihdr, pcids;
551 uint16_t cnt, chksum;
553 struct qla_hw_data *ha = vha->hw;
554 struct req_que *req = ha->req_q_map[0];
555 struct qla_flt_location *fltl = (void *)req->ring;
556 uint32_t *dcode = (uint32_t *)req->ring;
557 uint8_t *buf = (void *)req->ring, *bcode, last_image;
561 * FLT-location structure resides after the last PCI region.
564 /* Begin with sane defaults. */
567 if (IS_QLA24XX_TYPE(ha))
568 *start = FA_FLASH_LAYOUT_ADDR_24;
569 else if (IS_QLA25XX(ha))
570 *start = FA_FLASH_LAYOUT_ADDR;
571 else if (IS_QLA81XX(ha))
572 *start = FA_FLASH_LAYOUT_ADDR_81;
573 else if (IS_P3P_TYPE(ha)) {
574 *start = FA_FLASH_LAYOUT_ADDR_82;
576 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
577 *start = FA_FLASH_LAYOUT_ADDR_83;
579 } else if (IS_QLA28XX(ha)) {
580 *start = FA_FLASH_LAYOUT_ADDR_28;
584 /* Begin with first PCI expansion ROM header. */
587 /* Verify PCI expansion ROM header. */
588 rc = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
590 ql_log(ql_log_info, vha, 0x016d,
591 "Unable to read PCI Expansion Rom Header (%x).\n", rc);
592 return QLA_FUNCTION_FAILED;
594 bcode = buf + (pcihdr % 4);
595 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
598 /* Locate PCI data structure. */
599 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
600 rc = qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
602 ql_log(ql_log_info, vha, 0x0179,
603 "Unable to read PCI Data Structure (%x).\n", rc);
604 return QLA_FUNCTION_FAILED;
606 bcode = buf + (pcihdr % 4);
608 /* Validate signature of PCI data structure. */
609 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
610 bcode[0x2] != 'I' || bcode[0x3] != 'R')
613 last_image = bcode[0x15] & BIT_7;
615 /* Locate next PCI expansion ROM. */
616 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
617 } while (!last_image);
619 /* Now verify FLT-location structure. */
620 rc = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2);
622 ql_log(ql_log_info, vha, 0x017a,
623 "Unable to read FLT (%x).\n", rc);
624 return QLA_FUNCTION_FAILED;
626 if (memcmp(fltl->sig, "QFLT", 4))
629 wptr = (__force __le16 *)req->ring;
630 cnt = sizeof(*fltl) / sizeof(*wptr);
631 for (chksum = 0; cnt--; wptr++)
632 chksum += le16_to_cpu(*wptr);
634 ql_log(ql_log_fatal, vha, 0x0045,
635 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
636 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
637 fltl, sizeof(*fltl));
638 return QLA_FUNCTION_FAILED;
641 /* Good data. Use specified location. */
643 *start = (le16_to_cpu(fltl->start_hi) << 16 |
644 le16_to_cpu(fltl->start_lo)) >> 2;
646 ql_dbg(ql_dbg_init, vha, 0x0046,
647 "FLTL[%s] = 0x%x.\n",
653 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
655 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1];
656 const uint32_t def_fw[] =
657 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
658 const uint32_t def_boot[] =
659 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
660 const uint32_t def_vpd_nvram[] =
661 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
662 const uint32_t def_vpd0[] =
663 { 0, 0, FA_VPD0_ADDR_81 };
664 const uint32_t def_vpd1[] =
665 { 0, 0, FA_VPD1_ADDR_81 };
666 const uint32_t def_nvram0[] =
667 { 0, 0, FA_NVRAM0_ADDR_81 };
668 const uint32_t def_nvram1[] =
669 { 0, 0, FA_NVRAM1_ADDR_81 };
670 const uint32_t def_fdt[] =
671 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
672 FA_FLASH_DESCR_ADDR_81 };
673 const uint32_t def_npiv_conf0[] =
674 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
675 FA_NPIV_CONF0_ADDR_81 };
676 const uint32_t def_npiv_conf1[] =
677 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
678 FA_NPIV_CONF1_ADDR_81 };
679 const uint32_t fcp_prio_cfg0[] =
680 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
682 const uint32_t fcp_prio_cfg1[] =
683 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
686 struct qla_hw_data *ha = vha->hw;
687 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0;
688 struct qla_flt_header *flt = ha->flt;
689 struct qla_flt_region *region = &flt->region[0];
691 uint16_t cnt, chksum;
694 /* Assign FCP prio region since older adapters may not have FLT, or
695 FCP prio region in it's FLT.
697 ha->flt_region_fcp_prio = (ha->port_no == 0) ?
698 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
700 ha->flt_region_flt = flt_addr;
701 wptr = (__force __le16 *)ha->flt;
702 ha->isp_ops->read_optrom(vha, flt, flt_addr << 2,
703 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE));
705 if (le16_to_cpu(*wptr) == 0xffff)
707 if (flt->version != cpu_to_le16(1)) {
708 ql_log(ql_log_warn, vha, 0x0047,
709 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
710 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
711 le16_to_cpu(flt->checksum));
715 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr);
716 for (chksum = 0; cnt--; wptr++)
717 chksum += le16_to_cpu(*wptr);
719 ql_log(ql_log_fatal, vha, 0x0048,
720 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
721 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
722 le16_to_cpu(flt->checksum));
726 cnt = le16_to_cpu(flt->length) / sizeof(*region);
727 for ( ; cnt; cnt--, region++) {
728 /* Store addresses as DWORD offsets. */
729 start = le32_to_cpu(region->start) >> 2;
730 ql_dbg(ql_dbg_init, vha, 0x0049,
731 "FLT[%#x]: start=%#x end=%#x size=%#x.\n",
732 le16_to_cpu(region->code), start,
733 le32_to_cpu(region->end) >> 2,
734 le32_to_cpu(region->size) >> 2);
735 if (region->attribute)
736 ql_log(ql_dbg_init, vha, 0xffff,
737 "Region %x is secure\n", region->code);
739 switch (le16_to_cpu(region->code)) {
740 case FLT_REG_FCOE_FW:
743 ha->flt_region_fw = start;
748 ha->flt_region_fw = start;
750 case FLT_REG_BOOT_CODE:
751 ha->flt_region_boot = start;
756 ha->flt_region_vpd_nvram = start;
759 if (ha->port_no == 0)
760 ha->flt_region_vpd = start;
763 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
765 if (ha->port_no == 1)
766 ha->flt_region_vpd = start;
769 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
771 if (ha->port_no == 2)
772 ha->flt_region_vpd = start;
775 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
777 if (ha->port_no == 3)
778 ha->flt_region_vpd = start;
780 case FLT_REG_NVRAM_0:
783 if (ha->port_no == 0)
784 ha->flt_region_nvram = start;
786 case FLT_REG_NVRAM_1:
789 if (ha->port_no == 1)
790 ha->flt_region_nvram = start;
792 case FLT_REG_NVRAM_2:
793 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
795 if (ha->port_no == 2)
796 ha->flt_region_nvram = start;
798 case FLT_REG_NVRAM_3:
799 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
801 if (ha->port_no == 3)
802 ha->flt_region_nvram = start;
805 ha->flt_region_fdt = start;
807 case FLT_REG_NPIV_CONF_0:
808 if (ha->port_no == 0)
809 ha->flt_region_npiv_conf = start;
811 case FLT_REG_NPIV_CONF_1:
812 if (ha->port_no == 1)
813 ha->flt_region_npiv_conf = start;
815 case FLT_REG_GOLD_FW:
816 ha->flt_region_gold_fw = start;
818 case FLT_REG_FCP_PRIO_0:
819 if (ha->port_no == 0)
820 ha->flt_region_fcp_prio = start;
822 case FLT_REG_FCP_PRIO_1:
823 if (ha->port_no == 1)
824 ha->flt_region_fcp_prio = start;
826 case FLT_REG_BOOT_CODE_82XX:
827 ha->flt_region_boot = start;
829 case FLT_REG_BOOT_CODE_8044:
831 ha->flt_region_boot = start;
833 case FLT_REG_FW_82XX:
834 ha->flt_region_fw = start;
837 if (IS_CNA_CAPABLE(ha))
838 ha->flt_region_fw = start;
840 case FLT_REG_GOLD_FW_82XX:
841 ha->flt_region_gold_fw = start;
843 case FLT_REG_BOOTLOAD_82XX:
844 ha->flt_region_bootload = start;
846 case FLT_REG_VPD_8XXX:
847 if (IS_CNA_CAPABLE(ha))
848 ha->flt_region_vpd = start;
850 case FLT_REG_FCOE_NVRAM_0:
851 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
853 if (ha->port_no == 0)
854 ha->flt_region_nvram = start;
856 case FLT_REG_FCOE_NVRAM_1:
857 if (!(IS_QLA8031(ha) || IS_QLA8044(ha)))
859 if (ha->port_no == 1)
860 ha->flt_region_nvram = start;
862 case FLT_REG_IMG_PRI_27XX:
863 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
864 ha->flt_region_img_status_pri = start;
866 case FLT_REG_IMG_SEC_27XX:
867 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
868 ha->flt_region_img_status_sec = start;
870 case FLT_REG_FW_SEC_27XX:
871 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
872 ha->flt_region_fw_sec = start;
874 case FLT_REG_BOOTLOAD_SEC_27XX:
875 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
876 ha->flt_region_boot_sec = start;
878 case FLT_REG_AUX_IMG_PRI_28XX:
879 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
880 ha->flt_region_aux_img_status_pri = start;
882 case FLT_REG_AUX_IMG_SEC_28XX:
883 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
884 ha->flt_region_aux_img_status_sec = start;
886 case FLT_REG_NVRAM_SEC_28XX_0:
887 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
888 if (ha->port_no == 0)
889 ha->flt_region_nvram_sec = start;
891 case FLT_REG_NVRAM_SEC_28XX_1:
892 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
893 if (ha->port_no == 1)
894 ha->flt_region_nvram_sec = start;
896 case FLT_REG_NVRAM_SEC_28XX_2:
897 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
898 if (ha->port_no == 2)
899 ha->flt_region_nvram_sec = start;
901 case FLT_REG_NVRAM_SEC_28XX_3:
902 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
903 if (ha->port_no == 3)
904 ha->flt_region_nvram_sec = start;
906 case FLT_REG_VPD_SEC_27XX_0:
907 case FLT_REG_VPD_SEC_28XX_0:
908 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
909 ha->flt_region_vpd_nvram_sec = start;
910 if (ha->port_no == 0)
911 ha->flt_region_vpd_sec = start;
914 case FLT_REG_VPD_SEC_27XX_1:
915 case FLT_REG_VPD_SEC_28XX_1:
916 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
917 if (ha->port_no == 1)
918 ha->flt_region_vpd_sec = start;
920 case FLT_REG_VPD_SEC_27XX_2:
921 case FLT_REG_VPD_SEC_28XX_2:
922 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
923 if (ha->port_no == 2)
924 ha->flt_region_vpd_sec = start;
926 case FLT_REG_VPD_SEC_27XX_3:
927 case FLT_REG_VPD_SEC_28XX_3:
928 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
929 if (ha->port_no == 3)
930 ha->flt_region_vpd_sec = start;
937 /* Use hardcoded defaults. */
939 ha->flt_region_fw = def_fw[def];
940 ha->flt_region_boot = def_boot[def];
941 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
942 ha->flt_region_vpd = (ha->port_no == 0) ?
943 def_vpd0[def] : def_vpd1[def];
944 ha->flt_region_nvram = (ha->port_no == 0) ?
945 def_nvram0[def] : def_nvram1[def];
946 ha->flt_region_fdt = def_fdt[def];
947 ha->flt_region_npiv_conf = (ha->port_no == 0) ?
948 def_npiv_conf0[def] : def_npiv_conf1[def];
950 ql_dbg(ql_dbg_init, vha, 0x004a,
951 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
952 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
953 loc, ha->flt_region_boot, ha->flt_region_fw,
954 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
955 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
956 ha->flt_region_fcp_prio);
960 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
962 #define FLASH_BLK_SIZE_4K 0x1000
963 #define FLASH_BLK_SIZE_32K 0x8000
964 #define FLASH_BLK_SIZE_64K 0x10000
965 const char *loc, *locations[] = { "MID", "FDT" };
966 struct qla_hw_data *ha = vha->hw;
967 struct req_que *req = ha->req_q_map[0];
968 uint16_t cnt, chksum;
969 __le16 *wptr = (__force __le16 *)req->ring;
970 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring;
971 uint8_t man_id, flash_id;
972 uint16_t mid = 0, fid = 0;
974 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2,
975 OPTROM_BURST_DWORDS);
976 if (le16_to_cpu(*wptr) == 0xffff)
978 if (memcmp(fdt->sig, "QLID", 4))
981 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++)
982 chksum += le16_to_cpu(*wptr);
984 ql_dbg(ql_dbg_init, vha, 0x004c,
985 "Inconsistent FDT detected:"
986 " checksum=0x%x id=%c version0x%x.\n", chksum,
987 fdt->sig[0], le16_to_cpu(fdt->version));
988 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
994 mid = le16_to_cpu(fdt->man_id);
995 fid = le16_to_cpu(fdt->id);
996 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
997 ha->fdt_wrt_enable = fdt->wrt_enable_bits;
998 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd;
1000 ha->fdt_erase_cmd = fdt->erase_cmd;
1003 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
1004 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
1005 if (fdt->unprotect_sec_cmd) {
1006 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
1007 fdt->unprotect_sec_cmd);
1008 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
1009 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) :
1010 flash_conf_addr(ha, 0x0336);
1015 if (IS_P3P_TYPE(ha)) {
1016 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1019 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
1022 ha->fdt_wrt_disable = 0x9c;
1023 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
1025 case 0xbf: /* STT flash. */
1026 if (flash_id == 0x8e)
1027 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1029 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
1031 if (flash_id == 0x80)
1032 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
1034 case 0x13: /* ST M25P80. */
1035 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1037 case 0x1f: /* Atmel 26DF081A. */
1038 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
1039 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
1040 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
1041 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
1044 /* Default to 64 kb sector size. */
1045 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
1049 ql_dbg(ql_dbg_init, vha, 0x004d,
1050 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
1051 "pr=%x wrtd=0x%x blk=0x%x.\n",
1053 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
1054 ha->fdt_wrt_disable, ha->fdt_block_size);
1059 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
1061 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
1063 struct qla_hw_data *ha = vha->hw;
1064 struct req_que *req = ha->req_q_map[0];
1066 if (!(IS_P3P_TYPE(ha)))
1069 wptr = (__force __le32 *)req->ring;
1070 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8);
1072 if (*wptr == cpu_to_le32(0xffffffff)) {
1073 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
1074 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
1076 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr);
1078 ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
1080 ql_dbg(ql_dbg_init, vha, 0x004e,
1081 "fcoe_dev_init_timeout=%d "
1082 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
1083 ha->fcoe_reset_timeout);
1088 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
1092 struct qla_hw_data *ha = vha->hw;
1094 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1095 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) &&
1096 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1099 ret = qla2xxx_find_flt_start(vha, &flt_addr);
1100 if (ret != QLA_SUCCESS)
1103 qla2xxx_get_flt_info(vha, flt_addr);
1104 qla2xxx_get_fdt_info(vha);
1105 qla2xxx_get_idc_param(vha);
1111 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
1113 #define NPIV_CONFIG_SIZE (16*1024)
1116 uint16_t cnt, chksum;
1118 struct qla_npiv_header hdr;
1119 struct qla_npiv_entry *entry;
1120 struct qla_hw_data *ha = vha->hw;
1122 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1123 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1126 if (ha->flags.nic_core_reset_hdlr_active)
1132 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2,
1133 sizeof(struct qla_npiv_header));
1134 if (hdr.version == cpu_to_le16(0xffff))
1136 if (hdr.version != cpu_to_le16(1)) {
1137 ql_dbg(ql_dbg_user, vha, 0x7090,
1138 "Unsupported NPIV-Config "
1139 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1140 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1141 le16_to_cpu(hdr.checksum));
1145 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1147 ql_log(ql_log_warn, vha, 0x7091,
1148 "Unable to allocate memory for data.\n");
1152 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2,
1155 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1;
1156 for (wptr = data, chksum = 0; cnt--; wptr++)
1157 chksum += le16_to_cpu(*wptr);
1159 ql_dbg(ql_dbg_user, vha, 0x7092,
1160 "Inconsistent NPIV-Config "
1161 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1162 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1163 le16_to_cpu(hdr.checksum));
1167 entry = data + sizeof(struct qla_npiv_header);
1168 cnt = le16_to_cpu(hdr.entries);
1169 for (i = 0; cnt; cnt--, entry++, i++) {
1171 struct fc_vport_identifiers vid;
1172 struct fc_vport *vport;
1174 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1176 flags = le16_to_cpu(entry->flags);
1177 if (flags == 0xffff)
1179 if ((flags & BIT_0) == 0)
1182 memset(&vid, 0, sizeof(vid));
1183 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1184 vid.vport_type = FC_PORTTYPE_NPIV;
1185 vid.disable = false;
1186 vid.port_name = wwn_to_u64(entry->port_name);
1187 vid.node_name = wwn_to_u64(entry->node_name);
1189 ql_dbg(ql_dbg_user, vha, 0x7093,
1190 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n",
1191 cnt, vid.port_name, vid.node_name,
1192 le16_to_cpu(entry->vf_id),
1193 entry->q_qos, entry->f_qos);
1195 if (i < QLA_PRECONFIG_VPORTS) {
1196 vport = fc_vport_create(vha->host, 0, &vid);
1198 ql_log(ql_log_warn, vha, 0x7094,
1199 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n",
1200 cnt, vid.port_name, vid.node_name);
1208 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1210 struct qla_hw_data *ha = vha->hw;
1211 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1213 if (ha->flags.fac_supported)
1214 return qla81xx_fac_do_write_enable(vha, 1);
1216 /* Enable flash write. */
1217 wrt_reg_dword(®->ctrl_status,
1218 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE);
1219 rd_reg_dword(®->ctrl_status); /* PCI Posting. */
1221 if (!ha->fdt_wrt_disable)
1224 /* Disable flash write-protection, first clear SR protection bit */
1225 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1226 /* Then write zero again to clear remaining SR bits.*/
1227 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1233 qla24xx_protect_flash(scsi_qla_host_t *vha)
1235 struct qla_hw_data *ha = vha->hw;
1236 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1238 uint32_t faddr, dword;
1240 if (ha->flags.fac_supported)
1241 return qla81xx_fac_do_write_enable(vha, 0);
1243 if (!ha->fdt_wrt_disable)
1244 goto skip_wrt_protect;
1246 /* Enable flash write-protection and wait for completion. */
1247 faddr = flash_conf_addr(ha, 0x101);
1248 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable);
1249 faddr = flash_conf_addr(ha, 0x5);
1251 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) {
1252 if (!(dword & BIT_0))
1259 /* Disable flash write. */
1260 wrt_reg_dword(®->ctrl_status,
1261 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1267 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1269 struct qla_hw_data *ha = vha->hw;
1270 uint32_t start, finish;
1272 if (ha->flags.fac_supported) {
1274 finish = start + (ha->fdt_block_size >> 2) - 1;
1275 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1276 start), flash_data_addr(ha, finish));
1279 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1280 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1281 ((fdata >> 16) & 0xff));
1285 qla24xx_write_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr,
1290 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */
1291 uint32_t sec_mask, rest_addr, fdata;
1292 dma_addr_t optrom_dma;
1293 void *optrom = NULL;
1294 struct qla_hw_data *ha = vha->hw;
1296 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
1297 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1300 /* Allocate dma buffer for burst write */
1301 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1302 &optrom_dma, GFP_KERNEL);
1304 ql_log(ql_log_warn, vha, 0x7095,
1305 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE);
1309 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1310 "Unprotect flash...\n");
1311 ret = qla24xx_unprotect_flash(vha);
1313 ql_log(ql_log_warn, vha, 0x7096,
1314 "Failed to unprotect flash.\n");
1318 rest_addr = (ha->fdt_block_size >> 2) - 1;
1319 sec_mask = ~rest_addr;
1320 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1321 fdata = (faddr & sec_mask) << 2;
1323 /* Are we at the beginning of a sector? */
1324 if (!(faddr & rest_addr)) {
1325 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1326 "Erase sector %#x...\n", faddr);
1328 ret = qla24xx_erase_sector(vha, fdata);
1330 ql_dbg(ql_dbg_user, vha, 0x7007,
1331 "Failed to erase sector %x.\n", faddr);
1337 /* If smaller than a burst remaining */
1338 if (dwords - liter < dburst)
1339 dburst = dwords - liter;
1341 /* Copy to dma buffer */
1342 memcpy(optrom, dwptr, dburst << 2);
1345 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1346 "Write burst (%#lx dwords)...\n", dburst);
1347 ret = qla2x00_load_ram(vha, optrom_dma,
1348 flash_data_addr(ha, faddr), dburst);
1350 liter += dburst - 1;
1351 faddr += dburst - 1;
1352 dwptr += dburst - 1;
1356 ql_log(ql_log_warn, vha, 0x7097,
1357 "Failed burst-write at %x (%p/%#llx)....\n",
1358 flash_data_addr(ha, faddr), optrom,
1361 dma_free_coherent(&ha->pdev->dev,
1362 OPTROM_BURST_SIZE, optrom, optrom_dma);
1364 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
1366 ql_log(ql_log_warn, vha, 0x7098,
1367 "Reverting to slow write...\n");
1371 ret = qla24xx_write_flash_dword(ha,
1372 flash_data_addr(ha, faddr), le32_to_cpu(*dwptr));
1374 ql_dbg(ql_dbg_user, vha, 0x7006,
1375 "Failed slow write %x (%x)\n", faddr, *dwptr);
1380 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
1381 "Protect flash...\n");
1382 ret = qla24xx_protect_flash(vha);
1384 ql_log(ql_log_warn, vha, 0x7099,
1385 "Failed to protect flash\n");
1388 dma_free_coherent(&ha->pdev->dev,
1389 OPTROM_BURST_SIZE, optrom, optrom_dma);
1395 qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1400 struct qla_hw_data *ha = vha->hw;
1402 /* Word reads to NVRAM via registers. */
1404 qla2x00_lock_nvram_access(ha);
1405 for (i = 0; i < bytes >> 1; i++, naddr++)
1406 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1408 qla2x00_unlock_nvram_access(ha);
1414 qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1417 struct qla_hw_data *ha = vha->hw;
1418 uint32_t *dwptr = buf;
1421 if (IS_P3P_TYPE(ha))
1424 /* Dword reads to flash. */
1425 naddr = nvram_data_addr(ha, naddr);
1427 for (i = 0; i < bytes; i++, naddr++, dwptr++) {
1428 if (qla24xx_read_flash_dword(ha, naddr, dwptr))
1430 cpu_to_le32s(dwptr);
1437 qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1443 unsigned long flags;
1444 struct qla_hw_data *ha = vha->hw;
1448 spin_lock_irqsave(&ha->hardware_lock, flags);
1449 qla2x00_lock_nvram_access(ha);
1451 /* Disable NVRAM write-protection. */
1452 stat = qla2x00_clear_nvram_protection(ha);
1454 wptr = (uint16_t *)buf;
1455 for (i = 0; i < bytes >> 1; i++, naddr++) {
1456 qla2x00_write_nvram_word(ha, naddr,
1457 cpu_to_le16(*wptr));
1461 /* Enable NVRAM write-protection. */
1462 qla2x00_set_nvram_protection(ha, stat);
1464 qla2x00_unlock_nvram_access(ha);
1465 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1471 qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1474 struct qla_hw_data *ha = vha->hw;
1475 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1476 __le32 *dwptr = buf;
1482 if (IS_P3P_TYPE(ha))
1485 /* Enable flash write. */
1486 wrt_reg_dword(®->ctrl_status,
1487 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE);
1488 rd_reg_dword(®->ctrl_status); /* PCI Posting. */
1490 /* Disable NVRAM write-protection. */
1491 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1492 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1494 /* Dword writes to flash. */
1495 naddr = nvram_data_addr(ha, naddr);
1497 for (i = 0; i < bytes; i++, naddr++, dwptr++) {
1498 if (qla24xx_write_flash_dword(ha, naddr, le32_to_cpu(*dwptr))) {
1499 ql_dbg(ql_dbg_user, vha, 0x709a,
1500 "Unable to program nvram address=%x data=%x.\n",
1506 /* Enable NVRAM write-protection. */
1507 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1509 /* Disable flash write. */
1510 wrt_reg_dword(®->ctrl_status,
1511 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1512 rd_reg_dword(®->ctrl_status); /* PCI Posting. */
1518 qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1521 struct qla_hw_data *ha = vha->hw;
1522 uint32_t *dwptr = buf;
1525 /* Dword reads to flash. */
1526 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr);
1528 for (i = 0; i < bytes; i++, naddr++, dwptr++) {
1529 if (qla24xx_read_flash_dword(ha, naddr, dwptr))
1532 cpu_to_le32s(dwptr);
1538 #define RMW_BUFFER_SIZE (64 * 1024)
1540 qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr,
1543 struct qla_hw_data *ha = vha->hw;
1544 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE);
1547 return QLA_MEMORY_ALLOC_FAILED;
1548 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1550 memcpy(dbuf + (naddr << 2), buf, bytes);
1551 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1559 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1561 if (IS_QLA2322(ha)) {
1562 /* Flip all colors. */
1563 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1565 ha->beacon_color_state = 0;
1566 *pflags = GPIO_LED_ALL_OFF;
1569 ha->beacon_color_state = QLA_LED_ALL_ON;
1570 *pflags = GPIO_LED_RGA_ON;
1573 /* Flip green led only. */
1574 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1576 ha->beacon_color_state = 0;
1577 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1580 ha->beacon_color_state = QLA_LED_GRN_ON;
1581 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1586 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1589 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1591 uint16_t gpio_enable;
1593 uint16_t led_color = 0;
1594 unsigned long flags;
1595 struct qla_hw_data *ha = vha->hw;
1596 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1598 if (IS_P3P_TYPE(ha))
1601 spin_lock_irqsave(&ha->hardware_lock, flags);
1603 /* Save the Original GPIOE. */
1604 if (ha->pio_address) {
1605 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1606 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1608 gpio_enable = rd_reg_word(®->gpioe);
1609 gpio_data = rd_reg_word(®->gpiod);
1612 /* Set the modified gpio_enable values */
1613 gpio_enable |= GPIO_LED_MASK;
1615 if (ha->pio_address) {
1616 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1618 wrt_reg_word(®->gpioe, gpio_enable);
1619 rd_reg_word(®->gpioe);
1622 qla2x00_flip_colors(ha, &led_color);
1624 /* Clear out any previously set LED color. */
1625 gpio_data &= ~GPIO_LED_MASK;
1627 /* Set the new input LED color to GPIOD. */
1628 gpio_data |= led_color;
1630 /* Set the modified gpio_data values */
1631 if (ha->pio_address) {
1632 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1634 wrt_reg_word(®->gpiod, gpio_data);
1635 rd_reg_word(®->gpiod);
1638 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1642 qla2x00_beacon_on(struct scsi_qla_host *vha)
1644 uint16_t gpio_enable;
1646 unsigned long flags;
1647 struct qla_hw_data *ha = vha->hw;
1648 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1650 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1651 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1653 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1654 ql_log(ql_log_warn, vha, 0x709b,
1655 "Unable to update fw options (beacon on).\n");
1656 return QLA_FUNCTION_FAILED;
1659 /* Turn off LEDs. */
1660 spin_lock_irqsave(&ha->hardware_lock, flags);
1661 if (ha->pio_address) {
1662 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1663 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1665 gpio_enable = rd_reg_word(®->gpioe);
1666 gpio_data = rd_reg_word(®->gpiod);
1668 gpio_enable |= GPIO_LED_MASK;
1670 /* Set the modified gpio_enable values. */
1671 if (ha->pio_address) {
1672 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1674 wrt_reg_word(®->gpioe, gpio_enable);
1675 rd_reg_word(®->gpioe);
1678 /* Clear out previously set LED colour. */
1679 gpio_data &= ~GPIO_LED_MASK;
1680 if (ha->pio_address) {
1681 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1683 wrt_reg_word(®->gpiod, gpio_data);
1684 rd_reg_word(®->gpiod);
1686 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1689 * Let the per HBA timer kick off the blinking process based on
1690 * the following flags. No need to do anything else now.
1692 ha->beacon_blink_led = 1;
1693 ha->beacon_color_state = 0;
1699 qla2x00_beacon_off(struct scsi_qla_host *vha)
1701 int rval = QLA_SUCCESS;
1702 struct qla_hw_data *ha = vha->hw;
1704 ha->beacon_blink_led = 0;
1706 /* Set the on flag so when it gets flipped it will be off. */
1708 ha->beacon_color_state = QLA_LED_ALL_ON;
1710 ha->beacon_color_state = QLA_LED_GRN_ON;
1712 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1714 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1715 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1717 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1718 if (rval != QLA_SUCCESS)
1719 ql_log(ql_log_warn, vha, 0x709c,
1720 "Unable to update fw options (beacon off).\n");
1726 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1728 /* Flip all colors. */
1729 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1731 ha->beacon_color_state = 0;
1735 ha->beacon_color_state = QLA_LED_ALL_ON;
1736 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1741 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1743 uint16_t led_color = 0;
1745 unsigned long flags;
1746 struct qla_hw_data *ha = vha->hw;
1747 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1749 /* Save the Original GPIOD. */
1750 spin_lock_irqsave(&ha->hardware_lock, flags);
1751 gpio_data = rd_reg_dword(®->gpiod);
1753 /* Enable the gpio_data reg for update. */
1754 gpio_data |= GPDX_LED_UPDATE_MASK;
1756 wrt_reg_dword(®->gpiod, gpio_data);
1757 gpio_data = rd_reg_dword(®->gpiod);
1759 /* Set the color bits. */
1760 qla24xx_flip_colors(ha, &led_color);
1762 /* Clear out any previously set LED color. */
1763 gpio_data &= ~GPDX_LED_COLOR_MASK;
1765 /* Set the new input LED color to GPIOD. */
1766 gpio_data |= led_color;
1768 /* Set the modified gpio_data values. */
1769 wrt_reg_dword(®->gpiod, gpio_data);
1770 gpio_data = rd_reg_dword(®->gpiod);
1771 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1775 qla83xx_select_led_port(struct qla_hw_data *ha)
1777 uint32_t led_select_value = 0;
1779 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
1782 if (ha->port_no == 0)
1783 led_select_value = QLA83XX_LED_PORT0;
1785 led_select_value = QLA83XX_LED_PORT1;
1788 return led_select_value;
1792 qla83xx_beacon_blink(struct scsi_qla_host *vha)
1794 uint32_t led_select_value;
1795 struct qla_hw_data *ha = vha->hw;
1796 uint16_t led_cfg[6];
1797 uint16_t orig_led_cfg[6];
1798 uint32_t led_10_value, led_43_value;
1800 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) &&
1804 if (!ha->beacon_blink_led)
1807 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
1808 qla2x00_write_ram_word(vha, 0x1003, 0x40000230);
1809 qla2x00_write_ram_word(vha, 0x1004, 0x40000230);
1810 } else if (IS_QLA2031(ha)) {
1811 led_select_value = qla83xx_select_led_port(ha);
1813 qla83xx_wr_reg(vha, led_select_value, 0x40000230);
1814 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230);
1815 } else if (IS_QLA8031(ha)) {
1816 led_select_value = qla83xx_select_led_port(ha);
1818 qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1819 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1820 qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1822 qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1824 qla83xx_wr_reg(vha, led_select_value, led_10_value);
1825 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1826 } else if (IS_QLA81XX(ha)) {
1830 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1832 if (rval == QLA_SUCCESS) {
1833 if (IS_QLA81XX(ha)) {
1834 led_cfg[0] = 0x4000;
1835 led_cfg[1] = 0x2000;
1841 led_cfg[0] = 0x4000;
1842 led_cfg[1] = 0x4000;
1843 led_cfg[2] = 0x4000;
1844 led_cfg[3] = 0x2000;
1846 led_cfg[5] = 0x2000;
1848 rval = qla81xx_set_led_config(vha, led_cfg);
1850 if (IS_QLA81XX(ha)) {
1851 led_cfg[0] = 0x4000;
1852 led_cfg[1] = 0x2000;
1855 led_cfg[0] = 0x4000;
1856 led_cfg[1] = 0x2000;
1857 led_cfg[2] = 0x4000;
1858 led_cfg[3] = 0x4000;
1860 led_cfg[5] = 0x2000;
1862 rval = qla81xx_set_led_config(vha, led_cfg);
1864 /* On exit, restore original (presumes no status change) */
1865 qla81xx_set_led_config(vha, orig_led_cfg);
1870 qla24xx_beacon_on(struct scsi_qla_host *vha)
1873 unsigned long flags;
1874 struct qla_hw_data *ha = vha->hw;
1875 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1877 if (IS_P3P_TYPE(ha))
1880 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1881 goto skip_gpio; /* let blink handle it */
1883 if (ha->beacon_blink_led == 0) {
1884 /* Enable firmware for update */
1885 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1887 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1888 return QLA_FUNCTION_FAILED;
1890 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1892 ql_log(ql_log_warn, vha, 0x7009,
1893 "Unable to update fw options (beacon on).\n");
1894 return QLA_FUNCTION_FAILED;
1897 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
1900 spin_lock_irqsave(&ha->hardware_lock, flags);
1901 gpio_data = rd_reg_dword(®->gpiod);
1903 /* Enable the gpio_data reg for update. */
1904 gpio_data |= GPDX_LED_UPDATE_MASK;
1905 wrt_reg_dword(®->gpiod, gpio_data);
1906 rd_reg_dword(®->gpiod);
1908 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1911 /* So all colors blink together. */
1912 ha->beacon_color_state = 0;
1915 /* Let the per HBA timer kick off the blinking process. */
1916 ha->beacon_blink_led = 1;
1922 qla24xx_beacon_off(struct scsi_qla_host *vha)
1925 unsigned long flags;
1926 struct qla_hw_data *ha = vha->hw;
1927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1929 if (IS_P3P_TYPE(ha))
1932 if (!ha->flags.fw_started)
1935 ha->beacon_blink_led = 0;
1937 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
1938 goto set_fw_options;
1940 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1943 ha->beacon_color_state = QLA_LED_ALL_ON;
1945 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1947 /* Give control back to firmware. */
1948 spin_lock_irqsave(&ha->hardware_lock, flags);
1949 gpio_data = rd_reg_dword(®->gpiod);
1951 /* Disable the gpio_data reg for update. */
1952 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1953 wrt_reg_dword(®->gpiod, gpio_data);
1954 rd_reg_dword(®->gpiod);
1955 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1958 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1960 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1961 ql_log(ql_log_warn, vha, 0x704d,
1962 "Unable to update fw options (beacon on).\n");
1963 return QLA_FUNCTION_FAILED;
1966 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1967 ql_log(ql_log_warn, vha, 0x704e,
1968 "Unable to update fw options (beacon on).\n");
1969 return QLA_FUNCTION_FAILED;
1977 * Flash support routines
1981 * qla2x00_flash_enable() - Setup flash for reading and writing.
1985 qla2x00_flash_enable(struct qla_hw_data *ha)
1988 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1990 data = rd_reg_word(®->ctrl_status);
1991 data |= CSR_FLASH_ENABLE;
1992 wrt_reg_word(®->ctrl_status, data);
1993 rd_reg_word(®->ctrl_status); /* PCI Posting. */
1997 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
2001 qla2x00_flash_disable(struct qla_hw_data *ha)
2004 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2006 data = rd_reg_word(®->ctrl_status);
2007 data &= ~(CSR_FLASH_ENABLE);
2008 wrt_reg_word(®->ctrl_status, data);
2009 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2013 * qla2x00_read_flash_byte() - Reads a byte from flash
2015 * @addr: Address in flash to read
2017 * A word is read from the chip, but, only the lower byte is valid.
2019 * Returns the byte read from flash @addr.
2022 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
2025 uint16_t bank_select;
2026 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2028 bank_select = rd_reg_word(®->ctrl_status);
2030 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2031 /* Specify 64K address range: */
2032 /* clear out Module Select and Flash Address bits [19:16]. */
2033 bank_select &= ~0xf8;
2034 bank_select |= addr >> 12 & 0xf0;
2035 bank_select |= CSR_FLASH_64K_BANK;
2036 wrt_reg_word(®->ctrl_status, bank_select);
2037 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2039 wrt_reg_word(®->flash_address, (uint16_t)addr);
2040 data = rd_reg_word(®->flash_data);
2042 return (uint8_t)data;
2045 /* Setup bit 16 of flash address. */
2046 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2047 bank_select |= CSR_FLASH_64K_BANK;
2048 wrt_reg_word(®->ctrl_status, bank_select);
2049 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2050 } else if (((addr & BIT_16) == 0) &&
2051 (bank_select & CSR_FLASH_64K_BANK)) {
2052 bank_select &= ~(CSR_FLASH_64K_BANK);
2053 wrt_reg_word(®->ctrl_status, bank_select);
2054 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2057 /* Always perform IO mapped accesses to the FLASH registers. */
2058 if (ha->pio_address) {
2061 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2063 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2066 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
2067 } while (data != data2);
2069 wrt_reg_word(®->flash_address, (uint16_t)addr);
2070 data = qla2x00_debounce_register(®->flash_data);
2073 return (uint8_t)data;
2077 * qla2x00_write_flash_byte() - Write a byte to flash
2079 * @addr: Address in flash to write
2080 * @data: Data to write
2083 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
2085 uint16_t bank_select;
2086 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2088 bank_select = rd_reg_word(®->ctrl_status);
2089 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2090 /* Specify 64K address range: */
2091 /* clear out Module Select and Flash Address bits [19:16]. */
2092 bank_select &= ~0xf8;
2093 bank_select |= addr >> 12 & 0xf0;
2094 bank_select |= CSR_FLASH_64K_BANK;
2095 wrt_reg_word(®->ctrl_status, bank_select);
2096 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2098 wrt_reg_word(®->flash_address, (uint16_t)addr);
2099 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2100 wrt_reg_word(®->flash_data, (uint16_t)data);
2101 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2106 /* Setup bit 16 of flash address. */
2107 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
2108 bank_select |= CSR_FLASH_64K_BANK;
2109 wrt_reg_word(®->ctrl_status, bank_select);
2110 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2111 } else if (((addr & BIT_16) == 0) &&
2112 (bank_select & CSR_FLASH_64K_BANK)) {
2113 bank_select &= ~(CSR_FLASH_64K_BANK);
2114 wrt_reg_word(®->ctrl_status, bank_select);
2115 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2118 /* Always perform IO mapped accesses to the FLASH registers. */
2119 if (ha->pio_address) {
2120 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
2121 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
2123 wrt_reg_word(®->flash_address, (uint16_t)addr);
2124 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2125 wrt_reg_word(®->flash_data, (uint16_t)data);
2126 rd_reg_word(®->ctrl_status); /* PCI Posting. */
2131 * qla2x00_poll_flash() - Polls flash for completion.
2133 * @addr: Address in flash to poll
2134 * @poll_data: Data to be polled
2135 * @man_id: Flash manufacturer ID
2136 * @flash_id: Flash ID
2138 * This function polls the device until bit 7 of what is read matches data
2139 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
2140 * out (a fatal error). The flash book recommeds reading bit 7 again after
2141 * reading bit 5 as a 1.
2143 * Returns 0 on success, else non-zero.
2146 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2147 uint8_t man_id, uint8_t flash_id)
2155 /* Wait for 30 seconds for command to finish. */
2157 for (cnt = 3000000; cnt; cnt--) {
2158 flash_data = qla2x00_read_flash_byte(ha, addr);
2159 if ((flash_data & BIT_7) == poll_data) {
2164 if (man_id != 0x40 && man_id != 0xda) {
2165 if ((flash_data & BIT_5) && cnt > 2)
2176 * qla2x00_program_flash_address() - Programs a flash address
2178 * @addr: Address in flash to program
2179 * @data: Data to be written in flash
2180 * @man_id: Flash manufacturer ID
2181 * @flash_id: Flash ID
2183 * Returns 0 on success, else non-zero.
2186 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2187 uint8_t data, uint8_t man_id, uint8_t flash_id)
2189 /* Write Program Command Sequence. */
2190 if (IS_OEM_001(ha)) {
2191 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2192 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2193 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2194 qla2x00_write_flash_byte(ha, addr, data);
2196 if (man_id == 0xda && flash_id == 0xc1) {
2197 qla2x00_write_flash_byte(ha, addr, data);
2201 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2202 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2203 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2204 qla2x00_write_flash_byte(ha, addr, data);
2210 /* Wait for write to complete. */
2211 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2215 * qla2x00_erase_flash() - Erase the flash.
2217 * @man_id: Flash manufacturer ID
2218 * @flash_id: Flash ID
2220 * Returns 0 on success, else non-zero.
2223 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2225 /* Individual Sector Erase Command Sequence */
2226 if (IS_OEM_001(ha)) {
2227 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2228 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2229 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2230 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2231 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2232 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2234 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2235 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2236 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2237 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2238 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2239 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2244 /* Wait for erase to complete. */
2245 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2249 * qla2x00_erase_flash_sector() - Erase a flash sector.
2251 * @addr: Flash sector to erase
2252 * @sec_mask: Sector address mask
2253 * @man_id: Flash manufacturer ID
2254 * @flash_id: Flash ID
2256 * Returns 0 on success, else non-zero.
2259 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2260 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2262 /* Individual Sector Erase Command Sequence */
2263 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2264 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2265 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2266 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2267 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2268 if (man_id == 0x1f && flash_id == 0x13)
2269 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2271 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2275 /* Wait for erase to complete. */
2276 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2280 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2282 * @man_id: Flash manufacturer ID
2283 * @flash_id: Flash ID
2286 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2289 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2290 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2291 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2292 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2293 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2294 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2295 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2296 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2300 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2301 uint32_t saddr, uint32_t length)
2303 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2304 uint32_t midpoint, ilength;
2307 midpoint = length / 2;
2309 wrt_reg_word(®->nvram, 0);
2310 rd_reg_word(®->nvram);
2311 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2312 if (ilength == midpoint) {
2313 wrt_reg_word(®->nvram, NVR_SELECT);
2314 rd_reg_word(®->nvram);
2316 data = qla2x00_read_flash_byte(ha, saddr);
2325 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2328 unsigned long flags;
2329 struct qla_hw_data *ha = vha->hw;
2330 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2333 scsi_block_requests(vha->host);
2334 ha->isp_ops->disable_intrs(ha);
2335 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2338 spin_lock_irqsave(&ha->hardware_lock, flags);
2339 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
2340 rd_reg_word(®->hccr);
2341 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2342 for (cnt = 0; cnt < 30000; cnt++) {
2343 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0)
2350 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2354 qla2x00_resume_hba(struct scsi_qla_host *vha)
2356 struct qla_hw_data *ha = vha->hw;
2359 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2360 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2361 qla2xxx_wake_dpc(vha);
2362 qla2x00_wait_for_chip_reset(vha);
2363 scsi_unblock_requests(vha->host);
2367 qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2368 uint32_t offset, uint32_t length)
2370 uint32_t addr, midpoint;
2372 struct qla_hw_data *ha = vha->hw;
2373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2376 qla2x00_suspend_hba(vha);
2379 midpoint = ha->optrom_size / 2;
2381 qla2x00_flash_enable(ha);
2382 wrt_reg_word(®->nvram, 0);
2383 rd_reg_word(®->nvram); /* PCI Posting. */
2384 for (addr = offset, data = buf; addr < length; addr++, data++) {
2385 if (addr == midpoint) {
2386 wrt_reg_word(®->nvram, NVR_SELECT);
2387 rd_reg_word(®->nvram); /* PCI Posting. */
2390 *data = qla2x00_read_flash_byte(ha, addr);
2392 qla2x00_flash_disable(ha);
2395 qla2x00_resume_hba(vha);
2401 qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2402 uint32_t offset, uint32_t length)
2406 uint8_t man_id, flash_id, sec_number, *data;
2408 uint32_t addr, liter, sec_mask, rest_addr;
2409 struct qla_hw_data *ha = vha->hw;
2410 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2413 qla2x00_suspend_hba(vha);
2418 /* Reset ISP chip. */
2419 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
2420 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2422 /* Go with write. */
2423 qla2x00_flash_enable(ha);
2424 do { /* Loop once to provide quick error exit */
2425 /* Structure of flash memory based on manufacturer */
2426 if (IS_OEM_001(ha)) {
2427 /* OEM variant with special flash part. */
2428 man_id = flash_id = 0;
2433 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2435 case 0x20: /* ST flash. */
2436 if (flash_id == 0xd2 || flash_id == 0xe3) {
2438 * ST m29w008at part - 64kb sector size with
2439 * 32kb,8kb,8kb,16kb sectors at memory address
2447 * ST m29w010b part - 16kb sector size
2448 * Default to 16kb sectors
2453 case 0x40: /* Mostel flash. */
2454 /* Mostel v29c51001 part - 512 byte sector size. */
2458 case 0xbf: /* SST flash. */
2459 /* SST39sf10 part - 4kb sector size. */
2463 case 0xda: /* Winbond flash. */
2464 /* Winbond W29EE011 part - 256 byte sector size. */
2468 case 0xc2: /* Macronix flash. */
2469 /* 64k sector size. */
2470 if (flash_id == 0x38 || flash_id == 0x4f) {
2477 case 0x1f: /* Atmel flash. */
2478 /* 512k sector size. */
2479 if (flash_id == 0x13) {
2480 rest_addr = 0x7fffffff;
2481 sec_mask = 0x80000000;
2486 case 0x01: /* AMD flash. */
2487 if (flash_id == 0x38 || flash_id == 0x40 ||
2489 /* Am29LV081 part - 64kb sector size. */
2490 /* Am29LV002BT part - 64kb sector size. */
2494 } else if (flash_id == 0x3e) {
2496 * Am29LV008b part - 64kb sector size with
2497 * 32kb,8kb,8kb,16kb sector at memory address
2503 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2505 * Am29LV010 part or AM29f010 - 16kb sector
2511 } else if (flash_id == 0x6d) {
2512 /* Am29LV001 part - 8kb sector size. */
2519 /* Default to 16 kb sector size. */
2526 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2527 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2528 rval = QLA_FUNCTION_FAILED;
2533 for (addr = offset, liter = 0; liter < length; liter++,
2536 /* Are we at the beginning of a sector? */
2537 if ((addr & rest_addr) == 0) {
2538 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2539 if (addr >= 0x10000UL) {
2540 if (((addr >> 12) & 0xf0) &&
2542 flash_id == 0x3e) ||
2544 flash_id == 0xd2))) {
2546 if (sec_number == 1) {
2567 } else if (addr == ha->optrom_size / 2) {
2568 wrt_reg_word(®->nvram, NVR_SELECT);
2569 rd_reg_word(®->nvram);
2572 if (flash_id == 0xda && man_id == 0xc1) {
2573 qla2x00_write_flash_byte(ha, 0x5555,
2575 qla2x00_write_flash_byte(ha, 0x2aaa,
2577 qla2x00_write_flash_byte(ha, 0x5555,
2579 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2581 if (qla2x00_erase_flash_sector(ha,
2582 addr, sec_mask, man_id,
2584 rval = QLA_FUNCTION_FAILED;
2587 if (man_id == 0x01 && flash_id == 0x6d)
2592 if (man_id == 0x01 && flash_id == 0x6d) {
2593 if (sec_number == 1 &&
2594 addr == (rest_addr - 1)) {
2597 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2603 if (qla2x00_program_flash_address(ha, addr, *data,
2604 man_id, flash_id)) {
2605 rval = QLA_FUNCTION_FAILED;
2611 qla2x00_flash_disable(ha);
2614 qla2x00_resume_hba(vha);
2620 qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2621 uint32_t offset, uint32_t length)
2623 struct qla_hw_data *ha = vha->hw;
2627 scsi_block_requests(vha->host);
2628 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2631 rc = qla24xx_read_flash_data(vha, buf, offset >> 2, length >> 2);
2633 ql_log(ql_log_info, vha, 0x01a0,
2634 "Unable to perform optrom read(%x).\n", rc);
2638 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2639 scsi_unblock_requests(vha->host);
2645 qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, __le32 *buf,
2646 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf)
2648 uint32_t check_sum = 0;
2652 p = buf + buf_size_without_sfub;
2654 /* Extract SFUB from end of file */
2655 memcpy(sfub_buf, (uint8_t *)p,
2656 sizeof(struct secure_flash_update_block));
2658 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++)
2659 check_sum += le32_to_cpu(p[i]);
2661 check_sum = (~check_sum) + 1;
2663 if (check_sum != le32_to_cpu(p[i])) {
2664 ql_log(ql_log_warn, vha, 0x7097,
2665 "SFUB checksum failed, 0x%x, 0x%x\n",
2666 check_sum, le32_to_cpu(p[i]));
2667 return QLA_COMMAND_ERROR;
2674 qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start,
2675 struct qla_flt_region *region)
2677 struct qla_hw_data *ha = vha->hw;
2678 struct qla_flt_header *flt = ha->flt;
2679 struct qla_flt_region *flt_reg = &flt->region[0];
2681 int rval = QLA_FUNCTION_FAILED;
2684 return QLA_FUNCTION_FAILED;
2686 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
2687 for (; cnt; cnt--, flt_reg++) {
2688 if (le32_to_cpu(flt_reg->start) == start) {
2689 memcpy((uint8_t *)region, flt_reg,
2690 sizeof(struct qla_flt_region));
2700 qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2703 struct qla_hw_data *ha = vha->hw;
2705 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */
2706 uint32_t sec_mask, rest_addr, fdata;
2707 void *optrom = NULL;
2708 dma_addr_t optrom_dma;
2710 struct secure_flash_update_block *sfub;
2711 dma_addr_t sfub_dma;
2712 uint32_t offset = faddr << 2;
2713 uint32_t buf_size_without_sfub = 0;
2714 struct qla_flt_region region;
2715 bool reset_to_rom = false;
2716 uint32_t risc_size, risc_attr = 0;
2717 __be32 *fw_array = NULL;
2719 /* Retrieve region info - must be a start address passed in */
2720 rval = qla28xx_get_flash_region(vha, offset, ®ion);
2722 if (rval != QLA_SUCCESS) {
2723 ql_log(ql_log_warn, vha, 0xffff,
2724 "Invalid address %x - not a region start address\n",
2729 /* Allocate dma buffer for burst write */
2730 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2731 &optrom_dma, GFP_KERNEL);
2733 ql_log(ql_log_warn, vha, 0x7095,
2734 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE);
2735 rval = QLA_COMMAND_ERROR;
2740 * If adapter supports secure flash and region is secure
2741 * extract secure flash update block (SFUB) and verify
2743 if (ha->flags.secure_adapter && region.attribute) {
2745 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2746 "Region %x is secure\n", le16_to_cpu(region.code));
2748 switch (le16_to_cpu(region.code)) {
2750 case FLT_REG_FW_SEC_27XX:
2751 case FLT_REG_MPI_PRI_28XX:
2752 case FLT_REG_MPI_SEC_28XX:
2753 fw_array = (__force __be32 *)dwptr;
2756 risc_size = be32_to_cpu(fw_array[3]);
2757 risc_attr = be32_to_cpu(fw_array[9]);
2759 buf_size_without_sfub = risc_size;
2760 fw_array += risc_size;
2763 risc_size = be32_to_cpu(fw_array[3]);
2765 buf_size_without_sfub += risc_size;
2766 fw_array += risc_size;
2768 /* 1st dump template */
2769 risc_size = be32_to_cpu(fw_array[2]);
2771 /* skip header and ignore checksum */
2772 buf_size_without_sfub += risc_size;
2773 fw_array += risc_size;
2775 if (risc_attr & BIT_9) {
2776 /* 2nd dump template */
2777 risc_size = be32_to_cpu(fw_array[2]);
2779 /* skip header and ignore checksum */
2780 buf_size_without_sfub += risc_size;
2781 fw_array += risc_size;
2785 case FLT_REG_PEP_PRI_28XX:
2786 case FLT_REG_PEP_SEC_28XX:
2787 fw_array = (__force __be32 *)dwptr;
2790 risc_size = be32_to_cpu(fw_array[3]);
2791 risc_attr = be32_to_cpu(fw_array[9]);
2793 buf_size_without_sfub = risc_size;
2794 fw_array += risc_size;
2798 ql_log(ql_log_warn + ql_dbg_verbose, vha,
2799 0xffff, "Secure region %x not supported\n",
2800 le16_to_cpu(region.code));
2801 rval = QLA_COMMAND_ERROR;
2805 sfub = dma_alloc_coherent(&ha->pdev->dev,
2806 sizeof(struct secure_flash_update_block), &sfub_dma,
2809 ql_log(ql_log_warn, vha, 0xffff,
2810 "Unable to allocate memory for SFUB\n");
2811 rval = QLA_COMMAND_ERROR;
2815 rval = qla28xx_extract_sfub_and_verify(vha, (__le32 *)dwptr,
2816 dwords, buf_size_without_sfub, (uint8_t *)sfub);
2818 if (rval != QLA_SUCCESS)
2821 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2822 "SFUB extract and verify successful\n");
2825 rest_addr = (ha->fdt_block_size >> 2) - 1;
2826 sec_mask = ~rest_addr;
2828 /* Lock semaphore */
2829 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK);
2830 if (rval != QLA_SUCCESS) {
2831 ql_log(ql_log_warn, vha, 0xffff,
2832 "Unable to lock flash semaphore.");
2836 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2837 "Unprotect flash...\n");
2838 rval = qla24xx_unprotect_flash(vha);
2840 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK);
2841 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n");
2845 for (liter = 0; liter < dwords; liter++, faddr++) {
2846 fdata = (faddr & sec_mask) << 2;
2848 /* If start of sector */
2849 if (!(faddr & rest_addr)) {
2850 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2851 "Erase sector %#x...\n", faddr);
2852 rval = qla24xx_erase_sector(vha, fdata);
2854 ql_dbg(ql_dbg_user, vha, 0x7007,
2855 "Failed erase sector %#x\n", faddr);
2861 if (ha->flags.secure_adapter) {
2863 * If adapter supports secure flash but FW doesn't,
2864 * disable write protect, release semaphore and reset
2865 * chip to execute ROM code in order to update region securely
2867 if (!ha->flags.secure_fw) {
2868 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2869 "Disable Write and Release Semaphore.");
2870 rval = qla24xx_protect_flash(vha);
2871 if (rval != QLA_SUCCESS) {
2872 qla81xx_fac_semaphore_access(vha,
2873 FAC_SEMAPHORE_UNLOCK);
2874 ql_log(ql_log_warn, vha, 0xffff,
2875 "Unable to protect flash.");
2879 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2880 "Reset chip to ROM.");
2881 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2882 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags);
2883 qla2xxx_wake_dpc(vha);
2884 rval = qla2x00_wait_for_chip_reset(vha);
2885 if (rval != QLA_SUCCESS) {
2886 ql_log(ql_log_warn, vha, 0xffff,
2887 "Unable to reset to ROM code.");
2890 reset_to_rom = true;
2891 ha->flags.fac_supported = 0;
2893 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2895 rval = qla2xxx_write_remote_register(vha,
2896 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002);
2897 if (rval != QLA_SUCCESS) {
2898 ql_log(ql_log_warn, vha, 0xffff,
2899 "Unable to lock flash semaphore.");
2903 /* Unprotect flash */
2904 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2906 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0);
2908 ql_log(ql_log_warn, vha, 0x7096,
2909 "Failed unprotect flash\n");
2914 /* If region is secure, send Secure Flash MB Cmd */
2915 if (region.attribute && buf_size_without_sfub) {
2916 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff,
2917 "Sending Secure Flash MB Cmd\n");
2918 rval = qla28xx_secure_flash_update(vha, 0,
2919 le16_to_cpu(region.code),
2920 buf_size_without_sfub, sfub_dma,
2921 sizeof(struct secure_flash_update_block) >> 2);
2922 if (rval != QLA_SUCCESS) {
2923 ql_log(ql_log_warn, vha, 0xffff,
2924 "Secure Flash MB Cmd failed %x.", rval);
2931 /* re-init flash offset */
2932 faddr = offset >> 2;
2934 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
2935 fdata = (faddr & sec_mask) << 2;
2937 /* If smaller than a burst remaining */
2938 if (dwords - liter < dburst)
2939 dburst = dwords - liter;
2941 /* Copy to dma buffer */
2942 memcpy(optrom, dwptr, dburst << 2);
2945 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2946 "Write burst (%#lx dwords)...\n", dburst);
2947 rval = qla2x00_load_ram(vha, optrom_dma,
2948 flash_data_addr(ha, faddr), dburst);
2949 if (rval != QLA_SUCCESS) {
2950 ql_log(ql_log_warn, vha, 0x7097,
2951 "Failed burst write at %x (%p/%#llx)...\n",
2952 flash_data_addr(ha, faddr), optrom,
2957 liter += dburst - 1;
2958 faddr += dburst - 1;
2959 dwptr += dburst - 1;
2963 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095,
2964 "Protect flash...\n");
2965 ret = qla24xx_protect_flash(vha);
2967 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK);
2968 ql_log(ql_log_warn, vha, 0x7099,
2969 "Failed protect flash\n");
2970 rval = QLA_COMMAND_ERROR;
2973 if (reset_to_rom == true) {
2974 /* Schedule DPC to restart the RISC */
2975 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2976 qla2xxx_wake_dpc(vha);
2978 ret = qla2x00_wait_for_hba_online(vha);
2979 if (ret != QLA_SUCCESS) {
2980 ql_log(ql_log_warn, vha, 0xffff,
2981 "Adapter did not come out of reset\n");
2982 rval = QLA_COMMAND_ERROR;
2988 dma_free_coherent(&ha->pdev->dev,
2989 OPTROM_BURST_SIZE, optrom, optrom_dma);
2995 qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2996 uint32_t offset, uint32_t length)
2999 struct qla_hw_data *ha = vha->hw;
3002 scsi_block_requests(vha->host);
3003 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
3005 /* Go with write. */
3007 rval = qla28xx_write_flash_data(vha, buf, offset >> 2,
3010 rval = qla24xx_write_flash_data(vha, buf, offset >> 2,
3013 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
3014 scsi_unblock_requests(vha->host);
3020 qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
3021 uint32_t offset, uint32_t length)
3024 dma_addr_t optrom_dma;
3027 uint32_t faddr, left, burst;
3028 struct qla_hw_data *ha = vha->hw;
3030 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
3031 IS_QLA27XX(ha) || IS_QLA28XX(ha))
3035 if (length < OPTROM_BURST_SIZE)
3041 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
3042 &optrom_dma, GFP_KERNEL);
3044 ql_log(ql_log_warn, vha, 0x00cc,
3045 "Unable to allocate memory for optrom burst read (%x KB).\n",
3046 OPTROM_BURST_SIZE / 1024);
3051 faddr = offset >> 2;
3053 burst = OPTROM_BURST_DWORDS;
3058 rval = qla2x00_dump_ram(vha, optrom_dma,
3059 flash_data_addr(ha, faddr), burst);
3061 ql_log(ql_log_warn, vha, 0x00f5,
3062 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
3063 rval, flash_data_addr(ha, faddr),
3064 (unsigned long long)optrom_dma);
3065 ql_log(ql_log_warn, vha, 0x00f6,
3066 "Reverting to slow-read.\n");
3068 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
3069 optrom, optrom_dma);
3073 memcpy(pbuf, optrom, burst * 4);
3080 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
3086 return qla24xx_read_optrom_data(vha, buf, offset, length);
3090 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
3092 * @pcids: Pointer to the FCODE PCI data structure
3094 * The process of retrieving the FCODE version information is at best
3095 * described as interesting.
3097 * Within the first 100h bytes of the image an ASCII string is present
3098 * which contains several pieces of information including the FCODE
3099 * version. Unfortunately it seems the only reliable way to retrieve
3100 * the version is by scanning for another sentinel within the string,
3101 * the FCODE build date:
3103 * ... 2.00.02 10/17/02 ...
3105 * Returns QLA_SUCCESS on successful retrieval of version.
3108 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
3110 int ret = QLA_FUNCTION_FAILED;
3111 uint32_t istart, iend, iter, vend;
3112 uint8_t do_next, rbyte, *vbyte;
3114 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3116 /* Skip the PCI data structure. */
3118 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
3119 qla2x00_read_flash_byte(ha, pcids + 0x0A));
3120 iend = istart + 0x100;
3122 /* Scan for the sentinel date string...eeewww. */
3125 while ((iter < iend) && !do_next) {
3127 if (qla2x00_read_flash_byte(ha, iter) == '/') {
3128 if (qla2x00_read_flash_byte(ha, iter + 2) ==
3131 else if (qla2x00_read_flash_byte(ha,
3139 /* Backtrack to previous ' ' (space). */
3141 while ((iter > istart) && !do_next) {
3143 if (qla2x00_read_flash_byte(ha, iter) == ' ')
3150 * Mark end of version tag, and find previous ' ' (space) or
3151 * string length (recent FCODE images -- major hack ahead!!!).
3155 while ((iter > istart) && !do_next) {
3157 rbyte = qla2x00_read_flash_byte(ha, iter);
3158 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
3164 /* Mark beginning of version tag, and copy data. */
3166 if ((vend - iter) &&
3167 ((vend - iter) < sizeof(ha->fcode_revision))) {
3168 vbyte = ha->fcode_revision;
3169 while (iter <= vend) {
3170 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
3177 if (ret != QLA_SUCCESS)
3178 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3182 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3184 int ret = QLA_SUCCESS;
3185 uint8_t code_type, last_image;
3186 uint32_t pcihdr, pcids;
3189 struct qla_hw_data *ha = vha->hw;
3191 if (!ha->pio_address || !mbuf)
3192 return QLA_FUNCTION_FAILED;
3194 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3195 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3196 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3197 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3199 qla2x00_flash_enable(ha);
3201 /* Begin with first PCI expansion ROM header. */
3205 /* Verify PCI expansion ROM header. */
3206 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
3207 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
3209 ql_log(ql_log_fatal, vha, 0x0050,
3210 "No matching ROM signature.\n");
3211 ret = QLA_FUNCTION_FAILED;
3215 /* Locate PCI data structure. */
3217 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
3218 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
3220 /* Validate signature of PCI data structure. */
3221 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
3222 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
3223 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
3224 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
3225 /* Incorrect header. */
3226 ql_log(ql_log_fatal, vha, 0x0051,
3227 "PCI data struct not found pcir_adr=%x.\n", pcids);
3228 ret = QLA_FUNCTION_FAILED;
3233 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
3234 switch (code_type) {
3235 case ROM_CODE_TYPE_BIOS:
3236 /* Intel x86, PC-AT compatible. */
3237 ha->bios_revision[0] =
3238 qla2x00_read_flash_byte(ha, pcids + 0x12);
3239 ha->bios_revision[1] =
3240 qla2x00_read_flash_byte(ha, pcids + 0x13);
3241 ql_dbg(ql_dbg_init, vha, 0x0052,
3242 "Read BIOS %d.%d.\n",
3243 ha->bios_revision[1], ha->bios_revision[0]);
3245 case ROM_CODE_TYPE_FCODE:
3246 /* Open Firmware standard for PCI (FCode). */
3248 qla2x00_get_fcode_version(ha, pcids);
3250 case ROM_CODE_TYPE_EFI:
3251 /* Extensible Firmware Interface (EFI). */
3252 ha->efi_revision[0] =
3253 qla2x00_read_flash_byte(ha, pcids + 0x12);
3254 ha->efi_revision[1] =
3255 qla2x00_read_flash_byte(ha, pcids + 0x13);
3256 ql_dbg(ql_dbg_init, vha, 0x0053,
3257 "Read EFI %d.%d.\n",
3258 ha->efi_revision[1], ha->efi_revision[0]);
3261 ql_log(ql_log_warn, vha, 0x0054,
3262 "Unrecognized code type %x at pcids %x.\n",
3267 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
3269 /* Locate next PCI expansion ROM. */
3270 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
3271 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
3272 } while (!last_image);
3274 if (IS_QLA2322(ha)) {
3275 /* Read firmware image information. */
3276 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3278 memset(dbyte, 0, 8);
3279 dcode = (uint16_t *)dbyte;
3281 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
3283 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
3285 "ver from flash:.\n");
3286 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
3289 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
3290 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
3291 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
3293 ql_log(ql_log_warn, vha, 0x0057,
3294 "Unrecognized fw revision at %x.\n",
3295 ha->flt_region_fw * 4);
3297 /* values are in big endian */
3298 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
3299 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
3300 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
3301 ql_dbg(ql_dbg_init, vha, 0x0058,
3303 "%d.%d.%d.\n", ha->fw_revision[0],
3304 ha->fw_revision[1], ha->fw_revision[2]);
3308 qla2x00_flash_disable(ha);
3314 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3316 int ret = QLA_SUCCESS;
3317 uint32_t pcihdr, pcids;
3318 uint32_t *dcode = mbuf;
3319 uint8_t *bcode = mbuf;
3320 uint8_t code_type, last_image;
3321 struct qla_hw_data *ha = vha->hw;
3324 return QLA_FUNCTION_FAILED;
3326 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3327 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3328 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3329 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3331 /* Begin with first PCI expansion ROM header. */
3332 pcihdr = ha->flt_region_boot << 2;
3335 /* Verify PCI expansion ROM header. */
3336 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4);
3337 bcode = mbuf + (pcihdr % 4);
3338 if (memcmp(bcode, "\x55\xaa", 2)) {
3340 ql_log(ql_log_fatal, vha, 0x0154,
3341 "No matching ROM signature.\n");
3342 ret = QLA_FUNCTION_FAILED;
3346 /* Locate PCI data structure. */
3347 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
3349 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4);
3350 bcode = mbuf + (pcihdr % 4);
3352 /* Validate signature of PCI data structure. */
3353 if (memcmp(bcode, "PCIR", 4)) {
3354 /* Incorrect header. */
3355 ql_log(ql_log_fatal, vha, 0x0155,
3356 "PCI data struct not found pcir_adr=%x.\n", pcids);
3357 ret = QLA_FUNCTION_FAILED;
3362 code_type = bcode[0x14];
3363 switch (code_type) {
3364 case ROM_CODE_TYPE_BIOS:
3365 /* Intel x86, PC-AT compatible. */
3366 ha->bios_revision[0] = bcode[0x12];
3367 ha->bios_revision[1] = bcode[0x13];
3368 ql_dbg(ql_dbg_init, vha, 0x0156,
3369 "Read BIOS %d.%d.\n",
3370 ha->bios_revision[1], ha->bios_revision[0]);
3372 case ROM_CODE_TYPE_FCODE:
3373 /* Open Firmware standard for PCI (FCode). */
3374 ha->fcode_revision[0] = bcode[0x12];
3375 ha->fcode_revision[1] = bcode[0x13];
3376 ql_dbg(ql_dbg_init, vha, 0x0157,
3377 "Read FCODE %d.%d.\n",
3378 ha->fcode_revision[1], ha->fcode_revision[0]);
3380 case ROM_CODE_TYPE_EFI:
3381 /* Extensible Firmware Interface (EFI). */
3382 ha->efi_revision[0] = bcode[0x12];
3383 ha->efi_revision[1] = bcode[0x13];
3384 ql_dbg(ql_dbg_init, vha, 0x0158,
3385 "Read EFI %d.%d.\n",
3386 ha->efi_revision[1], ha->efi_revision[0]);
3389 ql_log(ql_log_warn, vha, 0x0159,
3390 "Unrecognized code type %x at pcids %x.\n",
3395 last_image = bcode[0x15] & BIT_7;
3397 /* Locate next PCI expansion ROM. */
3398 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3399 } while (!last_image);
3401 /* Read firmware image information. */
3402 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3404 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20);
3405 bcode = mbuf + (pcihdr % 4);
3407 /* Validate signature of PCI data structure. */
3408 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 &&
3409 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) {
3410 ha->fw_revision[0] = bcode[0x4];
3411 ha->fw_revision[1] = bcode[0x5];
3412 ha->fw_revision[2] = bcode[0x6];
3413 ql_dbg(ql_dbg_init, vha, 0x0153,
3414 "Firmware revision %d.%d.%d\n",
3415 ha->fw_revision[0], ha->fw_revision[1],
3416 ha->fw_revision[2]);
3423 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
3425 int ret = QLA_SUCCESS;
3426 uint32_t pcihdr = 0, pcids = 0;
3427 uint32_t *dcode = mbuf;
3428 uint8_t *bcode = mbuf;
3429 uint8_t code_type, last_image;
3431 struct qla_hw_data *ha = vha->hw;
3433 struct active_regions active_regions = { };
3435 if (IS_P3P_TYPE(ha))
3439 return QLA_FUNCTION_FAILED;
3441 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
3442 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
3443 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
3444 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3446 pcihdr = ha->flt_region_boot << 2;
3447 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3448 qla27xx_get_active_image(vha, &active_regions);
3449 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) {
3450 pcihdr = ha->flt_region_boot_sec << 2;
3455 /* Verify PCI expansion ROM header. */
3456 ret = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
3458 ql_log(ql_log_info, vha, 0x017d,
3459 "Unable to read PCI EXP Rom Header(%x).\n", ret);
3460 return QLA_FUNCTION_FAILED;
3463 bcode = mbuf + (pcihdr % 4);
3464 if (memcmp(bcode, "\x55\xaa", 2)) {
3466 ql_log(ql_log_fatal, vha, 0x0059,
3467 "No matching ROM signature.\n");
3468 return QLA_FUNCTION_FAILED;
3471 /* Locate PCI data structure. */
3472 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
3474 ret = qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
3476 ql_log(ql_log_info, vha, 0x018e,
3477 "Unable to read PCI Data Structure (%x).\n", ret);
3478 return QLA_FUNCTION_FAILED;
3481 bcode = mbuf + (pcihdr % 4);
3483 /* Validate signature of PCI data structure. */
3484 if (memcmp(bcode, "PCIR", 4)) {
3485 /* Incorrect header. */
3486 ql_log(ql_log_fatal, vha, 0x005a,
3487 "PCI data struct not found pcir_adr=%x.\n", pcids);
3488 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32);
3489 return QLA_FUNCTION_FAILED;
3493 code_type = bcode[0x14];
3494 switch (code_type) {
3495 case ROM_CODE_TYPE_BIOS:
3496 /* Intel x86, PC-AT compatible. */
3497 ha->bios_revision[0] = bcode[0x12];
3498 ha->bios_revision[1] = bcode[0x13];
3499 ql_dbg(ql_dbg_init, vha, 0x005b,
3500 "Read BIOS %d.%d.\n",
3501 ha->bios_revision[1], ha->bios_revision[0]);
3503 case ROM_CODE_TYPE_FCODE:
3504 /* Open Firmware standard for PCI (FCode). */
3505 ha->fcode_revision[0] = bcode[0x12];
3506 ha->fcode_revision[1] = bcode[0x13];
3507 ql_dbg(ql_dbg_init, vha, 0x005c,
3508 "Read FCODE %d.%d.\n",
3509 ha->fcode_revision[1], ha->fcode_revision[0]);
3511 case ROM_CODE_TYPE_EFI:
3512 /* Extensible Firmware Interface (EFI). */
3513 ha->efi_revision[0] = bcode[0x12];
3514 ha->efi_revision[1] = bcode[0x13];
3515 ql_dbg(ql_dbg_init, vha, 0x005d,
3516 "Read EFI %d.%d.\n",
3517 ha->efi_revision[1], ha->efi_revision[0]);
3520 ql_log(ql_log_warn, vha, 0x005e,
3521 "Unrecognized code type %x at pcids %x.\n",
3526 last_image = bcode[0x15] & BIT_7;
3528 /* Locate next PCI expansion ROM. */
3529 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
3530 } while (!last_image);
3532 /* Read firmware image information. */
3533 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
3534 faddr = ha->flt_region_fw;
3535 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3536 qla27xx_get_active_image(vha, &active_regions);
3537 if (active_regions.global == QLA27XX_SECONDARY_IMAGE)
3538 faddr = ha->flt_region_fw_sec;
3541 ret = qla24xx_read_flash_data(vha, dcode, faddr, 8);
3543 ql_log(ql_log_info, vha, 0x019e,
3544 "Unable to read FW version (%x).\n", ret);
3547 if (qla24xx_risc_firmware_invalid(dcode)) {
3548 ql_log(ql_log_warn, vha, 0x005f,
3549 "Unrecognized fw revision at %x.\n",
3550 ha->flt_region_fw * 4);
3551 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32);
3553 for (i = 0; i < 4; i++)
3554 ha->fw_revision[i] =
3555 be32_to_cpu((__force __be32)dcode[4+i]);
3556 ql_dbg(ql_dbg_init, vha, 0x0060,
3557 "Firmware revision (flash) %u.%u.%u (%x).\n",
3558 ha->fw_revision[0], ha->fw_revision[1],
3559 ha->fw_revision[2], ha->fw_revision[3]);
3563 /* Check for golden firmware and get version if available */
3564 if (!IS_QLA81XX(ha)) {
3565 /* Golden firmware is not present in non 81XX adapters */
3569 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
3570 faddr = ha->flt_region_gold_fw;
3571 ret = qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8);
3573 ql_log(ql_log_info, vha, 0x019f,
3574 "Unable to read Gold FW version (%x).\n", ret);
3577 if (qla24xx_risc_firmware_invalid(dcode)) {
3578 ql_log(ql_log_warn, vha, 0x0056,
3579 "Unrecognized golden fw at %#x.\n", faddr);
3580 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32);
3581 return QLA_FUNCTION_FAILED;
3584 for (i = 0; i < 4; i++)
3585 ha->gold_fw_version[i] =
3586 be32_to_cpu((__force __be32)dcode[4+i]);
3592 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
3594 if (pos >= end || *pos != 0x82)
3598 if (pos >= end || *pos != 0x90)
3602 if (pos >= end || *pos != 0x78)
3609 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
3611 struct qla_hw_data *ha = vha->hw;
3612 uint8_t *pos = ha->vpd;
3613 uint8_t *end = pos + ha->vpd_size;
3616 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
3619 while (pos < end && *pos != 0x78) {
3620 len = (*pos == 0x82) ? pos[1] : pos[2];
3622 if (!strncmp(pos, key, strlen(key)))
3625 if (*pos != 0x90 && *pos != 0x91)
3631 if (pos < end - len && *pos != 0x78)
3632 return scnprintf(str, size, "%.*s", len, pos + 3);
3638 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3641 uint32_t fcp_prio_addr;
3642 struct qla_hw_data *ha = vha->hw;
3644 if (!ha->fcp_prio_cfg) {
3645 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3646 if (!ha->fcp_prio_cfg) {
3647 ql_log(ql_log_warn, vha, 0x00d5,
3648 "Unable to allocate memory for fcp priority data (%x).\n",
3650 return QLA_FUNCTION_FAILED;
3653 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3655 fcp_prio_addr = ha->flt_region_fcp_prio;
3657 /* first read the fcp priority data header from flash */
3658 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg,
3659 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3661 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3664 /* read remaining FCP CMD config data from flash */
3665 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3666 len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry);
3667 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3669 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0],
3670 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3672 /* revalidate the entire FCP priority config data, including entries */
3673 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3676 ha->flags.fcp_prio_enabled = 1;
3679 vfree(ha->fcp_prio_cfg);
3680 ha->fcp_prio_cfg = NULL;
3681 return QLA_FUNCTION_FAILED;