drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 103 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 104 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 105 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 106 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 107 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 108 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 109 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 110 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 111 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 112 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 113 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 114 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 115 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 116 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 117 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 118 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 119 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 120 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 121 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 122
 123 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 124 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 125 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 126 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 127 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 128 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 129 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 130 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 131 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 132 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 133 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 134 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 135
 136 #define mmCPG_PSP_DEBUG                         0x5c10
 137 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 138 #define mmCPC_PSP_DEBUG                         0x5c11
 139 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 140 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 141 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 142
 143 //CC_GC_SA_UNIT_DISABLE
 144 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 145 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 146 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 147 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 148 //GC_USER_SA_UNIT_DISABLE
 149 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 150 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 151 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 152 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 153 //PA_SC_ENHANCE_3
 154 #define mmPA_SC_ENHANCE_3                       0x1085
 155 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 156 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 157 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 158
 159 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 160 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 161
 162 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 163 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 164 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 165 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 166
 167 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 168 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 169 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 170 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 171 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 172 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 173
 174 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 175 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 176 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 177 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 178 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 179 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 180 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 181 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 182 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 183 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 184 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 185
 186 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 187 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 188 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 189 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 190 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 191 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 192
 193 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 194 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 195 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 196 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 197 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 198 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 199
 200 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 201 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 202 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 203 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 204 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 205 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 206
 207 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 208 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 209 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 210 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 211 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 212 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 213
 214 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 215 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 216 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 217 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 218 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 219 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 220
 221 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 222 {
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 263 };
 264
 265 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 266 {
 267         /* Pending on emulation bring up */
 268 };
 269
 270 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 271 {
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1324 };
1325
1326 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1327 {
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1366 };
1367
1368 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1369 {
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1410 };
1411
1412 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1413 {
1414         static void *scratch_reg0;
1415         static void *scratch_reg1;
1416         static void *spare_int;
1417         uint32_t i = 0;
1418         uint32_t retries = 50000;
1419
1420         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1421         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1422         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1423
1424         if (amdgpu_sriov_runtime(adev)) {
1425                 pr_err("shouldn't call rlcg write register during runtime\n");
1426                 return;
1427         }
1428
1429         writel(v, scratch_reg0);
1430         writel(offset | 0x80000000, scratch_reg1);
1431         writel(1, spare_int);
1432         for (i = 0; i < retries; i++) {
1433                 u32 tmp;
1434
1435                 tmp = readl(scratch_reg1);
1436                 if (!(tmp & 0x80000000))
1437                         break;
1438
1439                 udelay(10);
1440         }
1441
1442         if (i >= retries)
1443                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1444 }
1445
1446 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1447 {
1448         /* Pending on emulation bring up */
1449 };
1450
1451 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1452 {
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2073 };
2074
2075 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2076 {
2077         /* Pending on emulation bring up */
2078 };
2079
2080 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2081 {
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3134 };
3135
3136 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3137 {
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3180 };
3181
3182 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3183 {
3184         /* Pending on emulation bring up */
3185 };
3186
3187 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3188 {
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3230
3231         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3233 };
3234
3235 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3236 {
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3260
3261         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3263 };
3264
3265 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3266 {
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3302 };
3303
3304 #define DEFAULT_SH_MEM_CONFIG \
3305         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3306          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3307          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3308          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3309
3310
3311 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3312 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3313 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3314 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3315 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3316                                  struct amdgpu_cu_info *cu_info);
3317 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3318 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3319                                    u32 sh_num, u32 instance);
3320 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3321
3322 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3323 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3324 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3325 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3326 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3327 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3328 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3329 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3330 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3331
3332 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3333 {
3334         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3335         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3336                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3337         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3338         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3339         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3340         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3341         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3342         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3343 }
3344
3345 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3346                                  struct amdgpu_ring *ring)
3347 {
3348         struct amdgpu_device *adev = kiq_ring->adev;
3349         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3350         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3351         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3352
3353         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3354         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3355         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3356                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3357                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3358                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3359                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3360                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3361                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3362                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3363                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3364                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3365         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3366         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3367         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3368         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3369         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3370 }
3371
3372 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3373                                    struct amdgpu_ring *ring,
3374                                    enum amdgpu_unmap_queues_action action,
3375                                    u64 gpu_addr, u64 seq)
3376 {
3377         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3378
3379         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3380         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3381                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3382                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3383                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3384                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3385         amdgpu_ring_write(kiq_ring,
3386                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3387
3388         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3389                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3390                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3391                 amdgpu_ring_write(kiq_ring, seq);
3392         } else {
3393                 amdgpu_ring_write(kiq_ring, 0);
3394                 amdgpu_ring_write(kiq_ring, 0);
3395                 amdgpu_ring_write(kiq_ring, 0);
3396         }
3397 }
3398
3399 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3400                                    struct amdgpu_ring *ring,
3401                                    u64 addr,
3402                                    u64 seq)
3403 {
3404         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3405
3406         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3407         amdgpu_ring_write(kiq_ring,
3408                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3409                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3410                           PACKET3_QUERY_STATUS_COMMAND(2));
3411         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3412                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3413                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3414         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3415         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3416         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3417         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3418 }
3419
3420 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3421                                 uint16_t pasid, uint32_t flush_type,
3422                                 bool all_hub)
3423 {
3424         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3425         amdgpu_ring_write(kiq_ring,
3426                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3427                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3428                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3429                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3430 }
3431
3432 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3433         .kiq_set_resources = gfx10_kiq_set_resources,
3434         .kiq_map_queues = gfx10_kiq_map_queues,
3435         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3436         .kiq_query_status = gfx10_kiq_query_status,
3437         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3438         .set_resources_size = 8,
3439         .map_queues_size = 7,
3440         .unmap_queues_size = 6,
3441         .query_status_size = 7,
3442         .invalidate_tlbs_size = 2,
3443 };
3444
3445 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3446 {
3447         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3448 }
3449
3450 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3451 {
3452         switch (adev->asic_type) {
3453         case CHIP_NAVI10:
3454                 soc15_program_register_sequence(adev,
3455                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3456                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3457                 break;
3458         case CHIP_NAVI14:
3459                 soc15_program_register_sequence(adev,
3460                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3461                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3462                 break;
3463         case CHIP_NAVI12:
3464                 soc15_program_register_sequence(adev,
3465                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3466                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3467                 break;
3468         default:
3469                 break;
3470         }
3471 }
3472
3473 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3474 {
3475         switch (adev->asic_type) {
3476         case CHIP_NAVI10:
3477                 soc15_program_register_sequence(adev,
3478                                                 golden_settings_gc_10_1,
3479                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3480                 soc15_program_register_sequence(adev,
3481                                                 golden_settings_gc_10_0_nv10,
3482                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3483                 break;
3484         case CHIP_NAVI14:
3485                 soc15_program_register_sequence(adev,
3486                                                 golden_settings_gc_10_1_1,
3487                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3488                 soc15_program_register_sequence(adev,
3489                                                 golden_settings_gc_10_1_nv14,
3490                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3491                 break;
3492         case CHIP_NAVI12:
3493                 soc15_program_register_sequence(adev,
3494                                                 golden_settings_gc_10_1_2,
3495                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3496                 soc15_program_register_sequence(adev,
3497                                                 golden_settings_gc_10_1_2_nv12,
3498                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3499                 break;
3500         case CHIP_SIENNA_CICHLID:
3501                 soc15_program_register_sequence(adev,
3502                                                 golden_settings_gc_10_3,
3503                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3504                 soc15_program_register_sequence(adev,
3505                                                 golden_settings_gc_10_3_sienna_cichlid,
3506                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3507                 break;
3508         case CHIP_NAVY_FLOUNDER:
3509                 soc15_program_register_sequence(adev,
3510                                                 golden_settings_gc_10_3_2,
3511                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3512                 break;
3513         case CHIP_VANGOGH:
3514                 soc15_program_register_sequence(adev,
3515                                                 golden_settings_gc_10_3_vangogh,
3516                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3517                 break;
3518         case CHIP_DIMGREY_CAVEFISH:
3519                 soc15_program_register_sequence(adev,
3520                                                 golden_settings_gc_10_3_4,
3521                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3522                 break;
3523         default:
3524                 break;
3525         }
3526         gfx_v10_0_init_spm_golden_registers(adev);
3527 }
3528
3529 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3530 {
3531         adev->gfx.scratch.num_reg = 8;
3532         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3533         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3534 }
3535
3536 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3537                                        bool wc, uint32_t reg, uint32_t val)
3538 {
3539         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3540         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3541                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3542         amdgpu_ring_write(ring, reg);
3543         amdgpu_ring_write(ring, 0);
3544         amdgpu_ring_write(ring, val);
3545 }
3546
3547 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3548                                   int mem_space, int opt, uint32_t addr0,
3549                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3550                                   uint32_t inv)
3551 {
3552         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3553         amdgpu_ring_write(ring,
3554                           /* memory (1) or register (0) */
3555                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3556                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3557                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3558                            WAIT_REG_MEM_ENGINE(eng_sel)));
3559
3560         if (mem_space)
3561                 BUG_ON(addr0 & 0x3); /* Dword align */
3562         amdgpu_ring_write(ring, addr0);
3563         amdgpu_ring_write(ring, addr1);
3564         amdgpu_ring_write(ring, ref);
3565         amdgpu_ring_write(ring, mask);
3566         amdgpu_ring_write(ring, inv); /* poll interval */
3567 }
3568
3569 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3570 {
3571         struct amdgpu_device *adev = ring->adev;
3572         uint32_t scratch;
3573         uint32_t tmp = 0;
3574         unsigned i;
3575         int r;
3576
3577         r = amdgpu_gfx_scratch_get(adev, &scratch);
3578         if (r) {
3579                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3580                 return r;
3581         }
3582
3583         WREG32(scratch, 0xCAFEDEAD);
3584
3585         r = amdgpu_ring_alloc(ring, 3);
3586         if (r) {
3587                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3588                           ring->idx, r);
3589                 amdgpu_gfx_scratch_free(adev, scratch);
3590                 return r;
3591         }
3592
3593         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3594         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3595         amdgpu_ring_write(ring, 0xDEADBEEF);
3596         amdgpu_ring_commit(ring);
3597
3598         for (i = 0; i < adev->usec_timeout; i++) {
3599                 tmp = RREG32(scratch);
3600                 if (tmp == 0xDEADBEEF)
3601                         break;
3602                 if (amdgpu_emu_mode == 1)
3603                         msleep(1);
3604                 else
3605                         udelay(1);
3606         }
3607
3608         if (i >= adev->usec_timeout)
3609                 r = -ETIMEDOUT;
3610
3611         amdgpu_gfx_scratch_free(adev, scratch);
3612
3613         return r;
3614 }
3615
3616 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3617 {
3618         struct amdgpu_device *adev = ring->adev;
3619         struct amdgpu_ib ib;
3620         struct dma_fence *f = NULL;
3621         unsigned index;
3622         uint64_t gpu_addr;
3623         uint32_t tmp;
3624         long r;
3625
3626         r = amdgpu_device_wb_get(adev, &index);
3627         if (r)
3628                 return r;
3629
3630         gpu_addr = adev->wb.gpu_addr + (index * 4);
3631         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3632         memset(&ib, 0, sizeof(ib));
3633         r = amdgpu_ib_get(adev, NULL, 16,
3634                                         AMDGPU_IB_POOL_DIRECT, &ib);
3635         if (r)
3636                 goto err1;
3637
3638         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3639         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3640         ib.ptr[2] = lower_32_bits(gpu_addr);
3641         ib.ptr[3] = upper_32_bits(gpu_addr);
3642         ib.ptr[4] = 0xDEADBEEF;
3643         ib.length_dw = 5;
3644
3645         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3646         if (r)
3647                 goto err2;
3648
3649         r = dma_fence_wait_timeout(f, false, timeout);
3650         if (r == 0) {
3651                 r = -ETIMEDOUT;
3652                 goto err2;
3653         } else if (r < 0) {
3654                 goto err2;
3655         }
3656
3657         tmp = adev->wb.wb[index];
3658         if (tmp == 0xDEADBEEF)
3659                 r = 0;
3660         else
3661                 r = -EINVAL;
3662 err2:
3663         amdgpu_ib_free(adev, &ib, NULL);
3664         dma_fence_put(f);
3665 err1:
3666         amdgpu_device_wb_free(adev, index);
3667         return r;
3668 }
3669
3670 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3671 {
3672         release_firmware(adev->gfx.pfp_fw);
3673         adev->gfx.pfp_fw = NULL;
3674         release_firmware(adev->gfx.me_fw);
3675         adev->gfx.me_fw = NULL;
3676         release_firmware(adev->gfx.ce_fw);
3677         adev->gfx.ce_fw = NULL;
3678         release_firmware(adev->gfx.rlc_fw);
3679         adev->gfx.rlc_fw = NULL;
3680         release_firmware(adev->gfx.mec_fw);
3681         adev->gfx.mec_fw = NULL;
3682         release_firmware(adev->gfx.mec2_fw);
3683         adev->gfx.mec2_fw = NULL;
3684
3685         kfree(adev->gfx.rlc.register_list_format);
3686 }
3687
3688 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3689 {
3690         adev->gfx.cp_fw_write_wait = false;
3691
3692         switch (adev->asic_type) {
3693         case CHIP_NAVI10:
3694         case CHIP_NAVI12:
3695         case CHIP_NAVI14:
3696                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3697                     (adev->gfx.me_feature_version >= 27) &&
3698                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3699                     (adev->gfx.pfp_feature_version >= 27) &&
3700                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3701                     (adev->gfx.mec_feature_version >= 27))
3702                         adev->gfx.cp_fw_write_wait = true;
3703                 break;
3704         case CHIP_SIENNA_CICHLID:
3705         case CHIP_NAVY_FLOUNDER:
3706         case CHIP_VANGOGH:
3707         case CHIP_DIMGREY_CAVEFISH:
3708                 adev->gfx.cp_fw_write_wait = true;
3709                 break;
3710         default:
3711                 break;
3712         }
3713
3714         if (!adev->gfx.cp_fw_write_wait)
3715                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3716 }
3717
3718
3719 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3720 {
3721         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3722
3723         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3724         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3725         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3726         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3727         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3728         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3729         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3730         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3731         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3732         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3733         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3734         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3735         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3736         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3737                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3738 }
3739
3740 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3741 {
3742         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3743
3744         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3745         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3746         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3747         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3748         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3749 }
3750
3751 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3752 {
3753         bool ret = false;
3754
3755         switch (adev->pdev->revision) {
3756         case 0xc2:
3757         case 0xc3:
3758                 ret = true;
3759                 break;
3760         default:
3761                 ret = false;
3762                 break;
3763         }
3764
3765         return ret ;
3766 }
3767
3768 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3769 {
3770         switch (adev->asic_type) {
3771         case CHIP_NAVI10:
3772                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3773                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3774                 break;
3775         case CHIP_VANGOGH:
3776                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3777                 break;
3778         default:
3779                 break;
3780         }
3781 }
3782
3783 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3784 {
3785         const char *chip_name;
3786         char fw_name[40];
3787         char wks[10];
3788         int err;
3789         struct amdgpu_firmware_info *info = NULL;
3790         const struct common_firmware_header *header = NULL;
3791         const struct gfx_firmware_header_v1_0 *cp_hdr;
3792         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3793         unsigned int *tmp = NULL;
3794         unsigned int i = 0;
3795         uint16_t version_major;
3796         uint16_t version_minor;
3797
3798         DRM_DEBUG("\n");
3799
3800         memset(wks, 0, sizeof(wks));
3801         switch (adev->asic_type) {
3802         case CHIP_NAVI10:
3803                 chip_name = "navi10";
3804                 break;
3805         case CHIP_NAVI14:
3806                 chip_name = "navi14";
3807                 if (!(adev->pdev->device == 0x7340 &&
3808                       adev->pdev->revision != 0x00))
3809                         snprintf(wks, sizeof(wks), "_wks");
3810                 break;
3811         case CHIP_NAVI12:
3812                 chip_name = "navi12";
3813                 break;
3814         case CHIP_SIENNA_CICHLID:
3815                 chip_name = "sienna_cichlid";
3816                 break;
3817         case CHIP_NAVY_FLOUNDER:
3818                 chip_name = "navy_flounder";
3819                 break;
3820         case CHIP_VANGOGH:
3821                 chip_name = "vangogh";
3822                 break;
3823         case CHIP_DIMGREY_CAVEFISH:
3824                 chip_name = "dimgrey_cavefish";
3825                 break;
3826         default:
3827                 BUG();
3828         }
3829
3830         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3831         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3832         if (err)
3833                 goto out;
3834         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3835         if (err)
3836                 goto out;
3837         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3838         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3839         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3840
3841         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3842         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3843         if (err)
3844                 goto out;
3845         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3846         if (err)
3847                 goto out;
3848         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3849         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3850         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3851
3852         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3853         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3854         if (err)
3855                 goto out;
3856         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3857         if (err)
3858                 goto out;
3859         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3860         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3861         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3862
3863         if (!amdgpu_sriov_vf(adev)) {
3864                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3865                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3866                 if (err)
3867                         goto out;
3868                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3869                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3870                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3871                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3872
3873                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3874                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3875                 adev->gfx.rlc.save_and_restore_offset =
3876                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3877                 adev->gfx.rlc.clear_state_descriptor_offset =
3878                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3879                 adev->gfx.rlc.avail_scratch_ram_locations =
3880                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3881                 adev->gfx.rlc.reg_restore_list_size =
3882                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3883                 adev->gfx.rlc.reg_list_format_start =
3884                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3885                 adev->gfx.rlc.reg_list_format_separate_start =
3886                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3887                 adev->gfx.rlc.starting_offsets_start =
3888                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3889                 adev->gfx.rlc.reg_list_format_size_bytes =
3890                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3891                 adev->gfx.rlc.reg_list_size_bytes =
3892                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3893                 adev->gfx.rlc.register_list_format =
3894                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3895                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3896                 if (!adev->gfx.rlc.register_list_format) {
3897                         err = -ENOMEM;
3898                         goto out;
3899                 }
3900
3901                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3902                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3903                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3904                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3905
3906                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3907
3908                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3909                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3910                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3911                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3912
3913                 if (version_major == 2) {
3914                         if (version_minor >= 1)
3915                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3916                         if (version_minor == 2)
3917                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3918                 }
3919         }
3920
3921         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3922         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3923         if (err)
3924                 goto out;
3925         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3926         if (err)
3927                 goto out;
3928         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3929         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3930         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3931
3932         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3933         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3934         if (!err) {
3935                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3936                 if (err)
3937                         goto out;
3938                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3939                 adev->gfx.mec2_fw->data;
3940                 adev->gfx.mec2_fw_version =
3941                 le32_to_cpu(cp_hdr->header.ucode_version);
3942                 adev->gfx.mec2_feature_version =
3943                 le32_to_cpu(cp_hdr->ucode_feature_version);
3944         } else {
3945                 err = 0;
3946                 adev->gfx.mec2_fw = NULL;
3947         }
3948
3949         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3950                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3951                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3952                 info->fw = adev->gfx.pfp_fw;
3953                 header = (const struct common_firmware_header *)info->fw->data;
3954                 adev->firmware.fw_size +=
3955                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3956
3957                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3958                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3959                 info->fw = adev->gfx.me_fw;
3960                 header = (const struct common_firmware_header *)info->fw->data;
3961                 adev->firmware.fw_size +=
3962                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3963
3964                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3965                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3966                 info->fw = adev->gfx.ce_fw;
3967                 header = (const struct common_firmware_header *)info->fw->data;
3968                 adev->firmware.fw_size +=
3969                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3970
3971                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3972                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3973                 info->fw = adev->gfx.rlc_fw;
3974                 if (info->fw) {
3975                         header = (const struct common_firmware_header *)info->fw->data;
3976                         adev->firmware.fw_size +=
3977                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3978                 }
3979                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3980                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3981                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3982                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3983                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3984                         info->fw = adev->gfx.rlc_fw;
3985                         adev->firmware.fw_size +=
3986                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3987
3988                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3989                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3990                         info->fw = adev->gfx.rlc_fw;
3991                         adev->firmware.fw_size +=
3992                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3993
3994                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3995                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3996                         info->fw = adev->gfx.rlc_fw;
3997                         adev->firmware.fw_size +=
3998                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3999
4000                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4001                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4002                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4003                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4004                                 info->fw = adev->gfx.rlc_fw;
4005                                 adev->firmware.fw_size +=
4006                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4007
4008                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4009                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4010                                 info->fw = adev->gfx.rlc_fw;
4011                                 adev->firmware.fw_size +=
4012                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4013                         }
4014                 }
4015
4016                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4017                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4018                 info->fw = adev->gfx.mec_fw;
4019                 header = (const struct common_firmware_header *)info->fw->data;
4020                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4021                 adev->firmware.fw_size +=
4022                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4023                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4024
4025                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4026                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4027                 info->fw = adev->gfx.mec_fw;
4028                 adev->firmware.fw_size +=
4029                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4030
4031                 if (adev->gfx.mec2_fw) {
4032                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4033                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4034                         info->fw = adev->gfx.mec2_fw;
4035                         header = (const struct common_firmware_header *)info->fw->data;
4036                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4037                         adev->firmware.fw_size +=
4038                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4039                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4040                                       PAGE_SIZE);
4041                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4042                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4043                         info->fw = adev->gfx.mec2_fw;
4044                         adev->firmware.fw_size +=
4045                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4046                                       PAGE_SIZE);
4047                 }
4048         }
4049
4050         gfx_v10_0_check_fw_write_wait(adev);
4051 out:
4052         if (err) {
4053                 dev_err(adev->dev,
4054                         "gfx10: Failed to load firmware \"%s\"\n",
4055                         fw_name);
4056                 release_firmware(adev->gfx.pfp_fw);
4057                 adev->gfx.pfp_fw = NULL;
4058                 release_firmware(adev->gfx.me_fw);
4059                 adev->gfx.me_fw = NULL;
4060                 release_firmware(adev->gfx.ce_fw);
4061                 adev->gfx.ce_fw = NULL;
4062                 release_firmware(adev->gfx.rlc_fw);
4063                 adev->gfx.rlc_fw = NULL;
4064                 release_firmware(adev->gfx.mec_fw);
4065                 adev->gfx.mec_fw = NULL;
4066                 release_firmware(adev->gfx.mec2_fw);
4067                 adev->gfx.mec2_fw = NULL;
4068         }
4069
4070         gfx_v10_0_check_gfxoff_flag(adev);
4071
4072         return err;
4073 }
4074
4075 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4076 {
4077         u32 count = 0;
4078         const struct cs_section_def *sect = NULL;
4079         const struct cs_extent_def *ext = NULL;
4080
4081         /* begin clear state */
4082         count += 2;
4083         /* context control state */
4084         count += 3;
4085
4086         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4087                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4088                         if (sect->id == SECT_CONTEXT)
4089                                 count += 2 + ext->reg_count;
4090                         else
4091                                 return 0;
4092                 }
4093         }
4094
4095         /* set PA_SC_TILE_STEERING_OVERRIDE */
4096         count += 3;
4097         /* end clear state */
4098         count += 2;
4099         /* clear state */
4100         count += 2;
4101
4102         return count;
4103 }
4104
4105 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4106                                     volatile u32 *buffer)
4107 {
4108         u32 count = 0, i;
4109         const struct cs_section_def *sect = NULL;
4110         const struct cs_extent_def *ext = NULL;
4111         int ctx_reg_offset;
4112
4113         if (adev->gfx.rlc.cs_data == NULL)
4114                 return;
4115         if (buffer == NULL)
4116                 return;
4117
4118         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4119         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4120
4121         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4122         buffer[count++] = cpu_to_le32(0x80000000);
4123         buffer[count++] = cpu_to_le32(0x80000000);
4124
4125         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4126                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4127                         if (sect->id == SECT_CONTEXT) {
4128                                 buffer[count++] =
4129                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4130                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4131                                                 PACKET3_SET_CONTEXT_REG_START);
4132                                 for (i = 0; i < ext->reg_count; i++)
4133                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4134                         } else {
4135                                 return;
4136                         }
4137                 }
4138         }
4139
4140         ctx_reg_offset =
4141                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4142         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4143         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4144         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4145
4146         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4147         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4148
4149         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4150         buffer[count++] = cpu_to_le32(0);
4151 }
4152
4153 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4154 {
4155         /* clear state block */
4156         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4157                         &adev->gfx.rlc.clear_state_gpu_addr,
4158                         (void **)&adev->gfx.rlc.cs_ptr);
4159
4160         /* jump table block */
4161         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4162                         &adev->gfx.rlc.cp_table_gpu_addr,
4163                         (void **)&adev->gfx.rlc.cp_table_ptr);
4164 }
4165
4166 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4167 {
4168         const struct cs_section_def *cs_data;
4169         int r;
4170
4171         adev->gfx.rlc.cs_data = gfx10_cs_data;
4172
4173         cs_data = adev->gfx.rlc.cs_data;
4174
4175         if (cs_data) {
4176                 /* init clear state block */
4177                 r = amdgpu_gfx_rlc_init_csb(adev);
4178                 if (r)
4179                         return r;
4180         }
4181
4182         /* init spm vmid with 0xf */
4183         if (adev->gfx.rlc.funcs->update_spm_vmid)
4184                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4185
4186         return 0;
4187 }
4188
4189 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4190 {
4191         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4192         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4193 }
4194
4195 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4196 {
4197         int r;
4198
4199         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4200
4201         amdgpu_gfx_graphics_queue_acquire(adev);
4202
4203         r = gfx_v10_0_init_microcode(adev);
4204         if (r)
4205                 DRM_ERROR("Failed to load gfx firmware!\n");
4206
4207         return r;
4208 }
4209
4210 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4211 {
4212         int r;
4213         u32 *hpd;
4214         const __le32 *fw_data = NULL;
4215         unsigned fw_size;
4216         u32 *fw = NULL;
4217         size_t mec_hpd_size;
4218
4219         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4220
4221         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4222
4223         /* take ownership of the relevant compute queues */
4224         amdgpu_gfx_compute_queue_acquire(adev);
4225         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4226
4227         if (mec_hpd_size) {
4228                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4229                                               AMDGPU_GEM_DOMAIN_GTT,
4230                                               &adev->gfx.mec.hpd_eop_obj,
4231                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4232                                               (void **)&hpd);
4233                 if (r) {
4234                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4235                         gfx_v10_0_mec_fini(adev);
4236                         return r;
4237                 }
4238
4239                 memset(hpd, 0, mec_hpd_size);
4240
4241                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4242                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4243         }
4244
4245         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4246                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4247
4248                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4249                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4250                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4251
4252                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4253                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4254                                               &adev->gfx.mec.mec_fw_obj,
4255                                               &adev->gfx.mec.mec_fw_gpu_addr,
4256                                               (void **)&fw);
4257                 if (r) {
4258                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4259                         gfx_v10_0_mec_fini(adev);
4260                         return r;
4261                 }
4262
4263                 memcpy(fw, fw_data, fw_size);
4264
4265                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4266                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4267         }
4268
4269         return 0;
4270 }
4271
4272 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4273 {
4274         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4275                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4276                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4277         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4278 }
4279
4280 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4281                            uint32_t thread, uint32_t regno,
4282                            uint32_t num, uint32_t *out)
4283 {
4284         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4285                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4286                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4287                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4288                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4289         while (num--)
4290                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4291 }
4292
4293 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4294 {
4295         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4296          * field when performing a select_se_sh so it should be
4297          * zero here */
4298         WARN_ON(simd != 0);
4299
4300         /* type 2 wave data */
4301         dst[(*no_fields)++] = 2;
4302         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4303         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4304         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4305         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4306         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4307         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4308         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4309         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4310         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4311         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4312         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4313         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4314         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4315         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4316         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4317 }
4318
4319 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4320                                      uint32_t wave, uint32_t start,
4321                                      uint32_t size, uint32_t *dst)
4322 {
4323         WARN_ON(simd != 0);
4324
4325         wave_read_regs(
4326                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4327                 dst);
4328 }
4329
4330 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4331                                       uint32_t wave, uint32_t thread,
4332                                       uint32_t start, uint32_t size,
4333                                       uint32_t *dst)
4334 {
4335         wave_read_regs(
4336                 adev, wave, thread,
4337                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4338 }
4339
4340 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4341                                        u32 me, u32 pipe, u32 q, u32 vm)
4342 {
4343         nv_grbm_select(adev, me, pipe, q, vm);
4344 }
4345
4346 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4347                                           bool enable)
4348 {
4349         uint32_t data, def;
4350
4351         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4352
4353         if (enable)
4354                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4355         else
4356                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4357
4358         if (data != def)
4359                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4360 }
4361
4362 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4363         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4364         .select_se_sh = &gfx_v10_0_select_se_sh,
4365         .read_wave_data = &gfx_v10_0_read_wave_data,
4366         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4367         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4368         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4369         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4370         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4371 };
4372
4373 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4374 {
4375         u32 gb_addr_config;
4376
4377         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4378
4379         switch (adev->asic_type) {
4380         case CHIP_NAVI10:
4381         case CHIP_NAVI14:
4382         case CHIP_NAVI12:
4383                 adev->gfx.config.max_hw_contexts = 8;
4384                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4385                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4386                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4387                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4388                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4389                 break;
4390         case CHIP_SIENNA_CICHLID:
4391         case CHIP_NAVY_FLOUNDER:
4392         case CHIP_VANGOGH:
4393         case CHIP_DIMGREY_CAVEFISH:
4394                 adev->gfx.config.max_hw_contexts = 8;
4395                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4396                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4397                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4398                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4399                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4400                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4401                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4402                 break;
4403         default:
4404                 BUG();
4405                 break;
4406         }
4407
4408         adev->gfx.config.gb_addr_config = gb_addr_config;
4409
4410         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4411                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4412                                       GB_ADDR_CONFIG, NUM_PIPES);
4413
4414         adev->gfx.config.max_tile_pipes =
4415                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4416
4417         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4418                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4419                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4420         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4421                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4422                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4423         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4424                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4425                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4426         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4427                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4428                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4429 }
4430
4431 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4432                                    int me, int pipe, int queue)
4433 {
4434         int r;
4435         struct amdgpu_ring *ring;
4436         unsigned int irq_type;
4437
4438         ring = &adev->gfx.gfx_ring[ring_id];
4439
4440         ring->me = me;
4441         ring->pipe = pipe;
4442         ring->queue = queue;
4443
4444         ring->ring_obj = NULL;
4445         ring->use_doorbell = true;
4446
4447         if (!ring_id)
4448                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4449         else
4450                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4451         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4452
4453         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4454         r = amdgpu_ring_init(adev, ring, 1024,
4455                              &adev->gfx.eop_irq, irq_type,
4456                              AMDGPU_RING_PRIO_DEFAULT);
4457         if (r)
4458                 return r;
4459         return 0;
4460 }
4461
4462 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4463                                        int mec, int pipe, int queue)
4464 {
4465         int r;
4466         unsigned irq_type;
4467         struct amdgpu_ring *ring;
4468         unsigned int hw_prio;
4469
4470         ring = &adev->gfx.compute_ring[ring_id];
4471
4472         /* mec0 is me1 */
4473         ring->me = mec + 1;
4474         ring->pipe = pipe;
4475         ring->queue = queue;
4476
4477         ring->ring_obj = NULL;
4478         ring->use_doorbell = true;
4479         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4480         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4481                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4482         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4483
4484         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4485                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4486                 + ring->pipe;
4487         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
4488                                                             ring->queue) ?
4489                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4490         /* type-2 packets are deprecated on MEC, use type-3 instead */
4491         r = amdgpu_ring_init(adev, ring, 1024,
4492                              &adev->gfx.eop_irq, irq_type, hw_prio);
4493         if (r)
4494                 return r;
4495
4496         return 0;
4497 }
4498
4499 static int gfx_v10_0_sw_init(void *handle)
4500 {
4501         int i, j, k, r, ring_id = 0;
4502         struct amdgpu_kiq *kiq;
4503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4504
4505         switch (adev->asic_type) {
4506         case CHIP_NAVI10:
4507         case CHIP_NAVI14:
4508         case CHIP_NAVI12:
4509                 adev->gfx.me.num_me = 1;
4510                 adev->gfx.me.num_pipe_per_me = 1;
4511                 adev->gfx.me.num_queue_per_pipe = 1;
4512                 adev->gfx.mec.num_mec = 2;
4513                 adev->gfx.mec.num_pipe_per_mec = 4;
4514                 adev->gfx.mec.num_queue_per_pipe = 8;
4515                 break;
4516         case CHIP_SIENNA_CICHLID:
4517         case CHIP_NAVY_FLOUNDER:
4518         case CHIP_VANGOGH:
4519         case CHIP_DIMGREY_CAVEFISH:
4520                 adev->gfx.me.num_me = 1;
4521                 adev->gfx.me.num_pipe_per_me = 1;
4522                 adev->gfx.me.num_queue_per_pipe = 1;
4523                 adev->gfx.mec.num_mec = 2;
4524                 adev->gfx.mec.num_pipe_per_mec = 4;
4525                 adev->gfx.mec.num_queue_per_pipe = 4;
4526                 break;
4527         default:
4528                 adev->gfx.me.num_me = 1;
4529                 adev->gfx.me.num_pipe_per_me = 1;
4530                 adev->gfx.me.num_queue_per_pipe = 1;
4531                 adev->gfx.mec.num_mec = 1;
4532                 adev->gfx.mec.num_pipe_per_mec = 4;
4533                 adev->gfx.mec.num_queue_per_pipe = 8;
4534                 break;
4535         }
4536
4537         /* KIQ event */
4538         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4539                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4540                               &adev->gfx.kiq.irq);
4541         if (r)
4542                 return r;
4543
4544         /* EOP Event */
4545         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4546                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4547                               &adev->gfx.eop_irq);
4548         if (r)
4549                 return r;
4550
4551         /* Privileged reg */
4552         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4553                               &adev->gfx.priv_reg_irq);
4554         if (r)
4555                 return r;
4556
4557         /* Privileged inst */
4558         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4559                               &adev->gfx.priv_inst_irq);
4560         if (r)
4561                 return r;
4562
4563         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4564
4565         gfx_v10_0_scratch_init(adev);
4566
4567         r = gfx_v10_0_me_init(adev);
4568         if (r)
4569                 return r;
4570
4571         r = gfx_v10_0_rlc_init(adev);
4572         if (r) {
4573                 DRM_ERROR("Failed to init rlc BOs!\n");
4574                 return r;
4575         }
4576
4577         r = gfx_v10_0_mec_init(adev);
4578         if (r) {
4579                 DRM_ERROR("Failed to init MEC BOs!\n");
4580                 return r;
4581         }
4582
4583         /* set up the gfx ring */
4584         for (i = 0; i < adev->gfx.me.num_me; i++) {
4585                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4586                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4587                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4588                                         continue;
4589
4590                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4591                                                             i, k, j);
4592                                 if (r)
4593                                         return r;
4594                                 ring_id++;
4595                         }
4596                 }
4597         }
4598
4599         ring_id = 0;
4600         /* set up the compute queues - allocate horizontally across pipes */
4601         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4602                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4603                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4604                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4605                                                                      j))
4606                                         continue;
4607
4608                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4609                                                                 i, k, j);
4610                                 if (r)
4611                                         return r;
4612
4613                                 ring_id++;
4614                         }
4615                 }
4616         }
4617
4618         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4619         if (r) {
4620                 DRM_ERROR("Failed to init KIQ BOs!\n");
4621                 return r;
4622         }
4623
4624         kiq = &adev->gfx.kiq;
4625         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4626         if (r)
4627                 return r;
4628
4629         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4630         if (r)
4631                 return r;
4632
4633         /* allocate visible FB for rlc auto-loading fw */
4634         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4635                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4636                 if (r)
4637                         return r;
4638         }
4639
4640         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4641
4642         gfx_v10_0_gpu_early_init(adev);
4643
4644         return 0;
4645 }
4646
4647 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4648 {
4649         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4650                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4651                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4652 }
4653
4654 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4655 {
4656         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4657                               &adev->gfx.ce.ce_fw_gpu_addr,
4658                               (void **)&adev->gfx.ce.ce_fw_ptr);
4659 }
4660
4661 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4662 {
4663         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4664                               &adev->gfx.me.me_fw_gpu_addr,
4665                               (void **)&adev->gfx.me.me_fw_ptr);
4666 }
4667
4668 static int gfx_v10_0_sw_fini(void *handle)
4669 {
4670         int i;
4671         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4672
4673         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4674                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4675         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4676                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4677
4678         amdgpu_gfx_mqd_sw_fini(adev);
4679         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4680         amdgpu_gfx_kiq_fini(adev);
4681
4682         gfx_v10_0_pfp_fini(adev);
4683         gfx_v10_0_ce_fini(adev);
4684         gfx_v10_0_me_fini(adev);
4685         gfx_v10_0_rlc_fini(adev);
4686         gfx_v10_0_mec_fini(adev);
4687
4688         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4689                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4690
4691         gfx_v10_0_free_microcode(adev);
4692
4693         return 0;
4694 }
4695
4696 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4697                                    u32 sh_num, u32 instance)
4698 {
4699         u32 data;
4700
4701         if (instance == 0xffffffff)
4702                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4703                                      INSTANCE_BROADCAST_WRITES, 1);
4704         else
4705                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4706                                      instance);
4707
4708         if (se_num == 0xffffffff)
4709                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4710                                      1);
4711         else
4712                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4713
4714         if (sh_num == 0xffffffff)
4715                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4716                                      1);
4717         else
4718                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4719
4720         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4721 }
4722
4723 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4724 {
4725         u32 data, mask;
4726
4727         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4728         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4729
4730         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4731         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4732
4733         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4734                                          adev->gfx.config.max_sh_per_se);
4735
4736         return (~data) & mask;
4737 }
4738
4739 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4740 {
4741         int i, j;
4742         u32 data;
4743         u32 active_rbs = 0;
4744         u32 bitmap;
4745         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4746                                         adev->gfx.config.max_sh_per_se;
4747
4748         mutex_lock(&adev->grbm_idx_mutex);
4749         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4750                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4751                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4752                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4753                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4754                                 continue;
4755                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4756                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4757                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4758                                                rb_bitmap_width_per_sh);
4759                 }
4760         }
4761         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4762         mutex_unlock(&adev->grbm_idx_mutex);
4763
4764         adev->gfx.config.backend_enable_mask = active_rbs;
4765         adev->gfx.config.num_rbs = hweight32(active_rbs);
4766 }
4767
4768 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4769 {
4770         uint32_t num_sc;
4771         uint32_t enabled_rb_per_sh;
4772         uint32_t active_rb_bitmap;
4773         uint32_t num_rb_per_sc;
4774         uint32_t num_packer_per_sc;
4775         uint32_t pa_sc_tile_steering_override;
4776
4777         /* for ASICs that integrates GFX v10.3
4778          * pa_sc_tile_steering_override should be set to 0 */
4779         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4780                 return 0;
4781
4782         /* init num_sc */
4783         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4784                         adev->gfx.config.num_sc_per_sh;
4785         /* init num_rb_per_sc */
4786         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4787         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4788         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4789         /* init num_packer_per_sc */
4790         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4791
4792         pa_sc_tile_steering_override = 0;
4793         pa_sc_tile_steering_override |=
4794                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4795                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4796         pa_sc_tile_steering_override |=
4797                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4798                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4799         pa_sc_tile_steering_override |=
4800                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4801                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4802
4803         return pa_sc_tile_steering_override;
4804 }
4805
4806 #define DEFAULT_SH_MEM_BASES    (0x6000)
4807
4808 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4809 {
4810         int i;
4811         uint32_t sh_mem_bases;
4812
4813         /*
4814          * Configure apertures:
4815          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4816          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4817          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4818          */
4819         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4820
4821         mutex_lock(&adev->srbm_mutex);
4822         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4823                 nv_grbm_select(adev, 0, 0, 0, i);
4824                 /* CP and shaders */
4825                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4826                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4827         }
4828         nv_grbm_select(adev, 0, 0, 0, 0);
4829         mutex_unlock(&adev->srbm_mutex);
4830
4831         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4832            acccess. These should be enabled by FW for target VMIDs. */
4833         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4834                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4835                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4836                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4837                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4838         }
4839 }
4840
4841 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4842 {
4843         int vmid;
4844
4845         /*
4846          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4847          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4848          * the driver can enable them for graphics. VMID0 should maintain
4849          * access so that HWS firmware can save/restore entries.
4850          */
4851         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4852                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4853                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4854                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4855                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4856         }
4857 }
4858
4859
4860 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4861 {
4862         int i, j, k;
4863         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4864         u32 tmp, wgp_active_bitmap = 0;
4865         u32 gcrd_targets_disable_tcp = 0;
4866         u32 utcl_invreq_disable = 0;
4867         /*
4868          * GCRD_TARGETS_DISABLE field contains
4869          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4870          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4871          */
4872         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4873                 2 * max_wgp_per_sh + /* TCP */
4874                 max_wgp_per_sh + /* SQC */
4875                 4); /* GL1C */
4876         /*
4877          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4878          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4879          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4880          */
4881         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4882                 2 * max_wgp_per_sh + /* TCP */
4883                 2 * max_wgp_per_sh + /* SQC */
4884                 4 + /* RMI */
4885                 1); /* SQG */
4886
4887         if (adev->asic_type == CHIP_NAVI10 ||
4888             adev->asic_type == CHIP_NAVI14 ||
4889             adev->asic_type == CHIP_NAVI12) {
4890                 mutex_lock(&adev->grbm_idx_mutex);
4891                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4892                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4893                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4894                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4895                                 /*
4896                                  * Set corresponding TCP bits for the inactive WGPs in
4897                                  * GCRD_SA_TARGETS_DISABLE
4898                                  */
4899                                 gcrd_targets_disable_tcp = 0;
4900                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4901                                 utcl_invreq_disable = 0;
4902
4903                                 for (k = 0; k < max_wgp_per_sh; k++) {
4904                                         if (!(wgp_active_bitmap & (1 << k))) {
4905                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4906                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4907                                                         (3 << (2 * (max_wgp_per_sh + k)));
4908                                         }
4909                                 }
4910
4911                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4912                                 /* only override TCP & SQC bits */
4913                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4914                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4915                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4916
4917                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4918                                 /* only override TCP bits */
4919                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4920                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4921                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4922                         }
4923                 }
4924
4925                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4926                 mutex_unlock(&adev->grbm_idx_mutex);
4927         }
4928 }
4929
4930 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4931 {
4932         /* TCCs are global (not instanced). */
4933         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4934                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4935
4936         adev->gfx.config.tcc_disabled_mask =
4937                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4938                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4939 }
4940
4941 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4942 {
4943         u32 tmp;
4944         int i;
4945
4946         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4947
4948         gfx_v10_0_setup_rb(adev);
4949         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4950         gfx_v10_0_get_tcc_info(adev);
4951         adev->gfx.config.pa_sc_tile_steering_override =
4952                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4953
4954         /* XXX SH_MEM regs */
4955         /* where to put LDS, scratch, GPUVM in FSA64 space */
4956         mutex_lock(&adev->srbm_mutex);
4957         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4958                 nv_grbm_select(adev, 0, 0, 0, i);
4959                 /* CP and shaders */
4960                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4961                 if (i != 0) {
4962                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4963                                 (adev->gmc.private_aperture_start >> 48));
4964                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4965                                 (adev->gmc.shared_aperture_start >> 48));
4966                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4967                 }
4968         }
4969         nv_grbm_select(adev, 0, 0, 0, 0);
4970
4971         mutex_unlock(&adev->srbm_mutex);
4972
4973         gfx_v10_0_init_compute_vmid(adev);
4974         gfx_v10_0_init_gds_vmid(adev);
4975
4976 }
4977
4978 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4979                                                bool enable)
4980 {
4981         u32 tmp;
4982
4983         if (amdgpu_sriov_vf(adev))
4984                 return;
4985
4986         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4987
4988         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4989                             enable ? 1 : 0);
4990         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4991                             enable ? 1 : 0);
4992         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4993                             enable ? 1 : 0);
4994         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4995                             enable ? 1 : 0);
4996
4997         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4998 }
4999
5000 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5001 {
5002         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5003
5004         /* csib */
5005         if (adev->asic_type == CHIP_NAVI12) {
5006                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5007                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5008                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5009                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5010                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5011         } else {
5012                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5013                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5014                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5015                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5016                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5017         }
5018         return 0;
5019 }
5020
5021 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5022 {
5023         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5024
5025         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5026         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5027 }
5028
5029 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5030 {
5031         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5032         udelay(50);
5033         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5034         udelay(50);
5035 }
5036
5037 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5038                                              bool enable)
5039 {
5040         uint32_t rlc_pg_cntl;
5041
5042         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5043
5044         if (!enable) {
5045                 /* RLC_PG_CNTL[23] = 0 (default)
5046                  * RLC will wait for handshake acks with SMU
5047                  * GFXOFF will be enabled
5048                  * RLC_PG_CNTL[23] = 1
5049                  * RLC will not issue any message to SMU
5050                  * hence no handshake between SMU & RLC
5051                  * GFXOFF will be disabled
5052                  */
5053                 rlc_pg_cntl |= 0x800000;
5054         } else
5055                 rlc_pg_cntl &= ~0x800000;
5056         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5057 }
5058
5059 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5060 {
5061         /* TODO: enable rlc & smu handshake until smu
5062          * and gfxoff feature works as expected */
5063         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5064                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5065
5066         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5067         udelay(50);
5068 }
5069
5070 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5071 {
5072         uint32_t tmp;
5073
5074         /* enable Save Restore Machine */
5075         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5076         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5077         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5078         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5079 }
5080
5081 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5082 {
5083         const struct rlc_firmware_header_v2_0 *hdr;
5084         const __le32 *fw_data;
5085         unsigned i, fw_size;
5086
5087         if (!adev->gfx.rlc_fw)
5088                 return -EINVAL;
5089
5090         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5091         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5092
5093         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5094                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5095         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5096
5097         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5098                      RLCG_UCODE_LOADING_START_ADDRESS);
5099
5100         for (i = 0; i < fw_size; i++)
5101                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5102                              le32_to_cpup(fw_data++));
5103
5104         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5105
5106         return 0;
5107 }
5108
5109 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5110 {
5111         int r;
5112
5113         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5114
5115                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5116                 if (r)
5117                         return r;
5118
5119                 gfx_v10_0_init_csb(adev);
5120
5121                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5122                         gfx_v10_0_rlc_enable_srm(adev);
5123         } else {
5124                 if (amdgpu_sriov_vf(adev)) {
5125                         gfx_v10_0_init_csb(adev);
5126                         return 0;
5127                 }
5128
5129                 adev->gfx.rlc.funcs->stop(adev);
5130
5131                 /* disable CG */
5132                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5133
5134                 /* disable PG */
5135                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5136
5137                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5138                         /* legacy rlc firmware loading */
5139                         r = gfx_v10_0_rlc_load_microcode(adev);
5140                         if (r)
5141                                 return r;
5142                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5143                         /* rlc backdoor autoload firmware */
5144                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5145                         if (r)
5146                                 return r;
5147                 }
5148
5149                 gfx_v10_0_init_csb(adev);
5150
5151                 adev->gfx.rlc.funcs->start(adev);
5152
5153                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5154                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5155                         if (r)
5156                                 return r;
5157                 }
5158         }
5159         return 0;
5160 }
5161
5162 static struct {
5163         FIRMWARE_ID     id;
5164         unsigned int    offset;
5165         unsigned int    size;
5166 } rlc_autoload_info[FIRMWARE_ID_MAX];
5167
5168 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5169 {
5170         int ret;
5171         RLC_TABLE_OF_CONTENT *rlc_toc;
5172
5173         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5174                                         AMDGPU_GEM_DOMAIN_GTT,
5175                                         &adev->gfx.rlc.rlc_toc_bo,
5176                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5177                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5178         if (ret) {
5179                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5180                 return ret;
5181         }
5182
5183         /* Copy toc from psp sos fw to rlc toc buffer */
5184         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5185
5186         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5187         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5188                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5189                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5190                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5191                         /* Offset needs 4KB alignment */
5192                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5193                 }
5194
5195                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5196                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5197                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5198
5199                 rlc_toc++;
5200         }
5201
5202         return 0;
5203 }
5204
5205 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5206 {
5207         uint32_t total_size = 0;
5208         FIRMWARE_ID id;
5209         int ret;
5210
5211         ret = gfx_v10_0_parse_rlc_toc(adev);
5212         if (ret) {
5213                 dev_err(adev->dev, "failed to parse rlc toc\n");
5214                 return 0;
5215         }
5216
5217         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5218                 total_size += rlc_autoload_info[id].size;
5219
5220         /* In case the offset in rlc toc ucode is aligned */
5221         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5222                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5223                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5224
5225         return total_size;
5226 }
5227
5228 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5229 {
5230         int r;
5231         uint32_t total_size;
5232
5233         total_size = gfx_v10_0_calc_toc_total_size(adev);
5234
5235         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5236                                       AMDGPU_GEM_DOMAIN_GTT,
5237                                       &adev->gfx.rlc.rlc_autoload_bo,
5238                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5239                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5240         if (r) {
5241                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5242                 return r;
5243         }
5244
5245         return 0;
5246 }
5247
5248 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5249 {
5250         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5251                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5252                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5253         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5254                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5255                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5256 }
5257
5258 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5259                                                        FIRMWARE_ID id,
5260                                                        const void *fw_data,
5261                                                        uint32_t fw_size)
5262 {
5263         uint32_t toc_offset;
5264         uint32_t toc_fw_size;
5265         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5266
5267         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5268                 return;
5269
5270         toc_offset = rlc_autoload_info[id].offset;
5271         toc_fw_size = rlc_autoload_info[id].size;
5272
5273         if (fw_size == 0)
5274                 fw_size = toc_fw_size;
5275
5276         if (fw_size > toc_fw_size)
5277                 fw_size = toc_fw_size;
5278
5279         memcpy(ptr + toc_offset, fw_data, fw_size);
5280
5281         if (fw_size < toc_fw_size)
5282                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5283 }
5284
5285 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5286 {
5287         void *data;
5288         uint32_t size;
5289
5290         data = adev->gfx.rlc.rlc_toc_buf;
5291         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5292
5293         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5294                                                    FIRMWARE_ID_RLC_TOC,
5295                                                    data, size);
5296 }
5297
5298 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5299 {
5300         const __le32 *fw_data;
5301         uint32_t fw_size;
5302         const struct gfx_firmware_header_v1_0 *cp_hdr;
5303         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5304
5305         /* pfp ucode */
5306         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5307                 adev->gfx.pfp_fw->data;
5308         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5309                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5310         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5311         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5312                                                    FIRMWARE_ID_CP_PFP,
5313                                                    fw_data, fw_size);
5314
5315         /* ce ucode */
5316         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5317                 adev->gfx.ce_fw->data;
5318         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5319                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5320         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5321         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5322                                                    FIRMWARE_ID_CP_CE,
5323                                                    fw_data, fw_size);
5324
5325         /* me ucode */
5326         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5327                 adev->gfx.me_fw->data;
5328         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5329                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5330         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5331         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5332                                                    FIRMWARE_ID_CP_ME,
5333                                                    fw_data, fw_size);
5334
5335         /* rlc ucode */
5336         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5337                 adev->gfx.rlc_fw->data;
5338         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5339                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5340         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5341         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5342                                                    FIRMWARE_ID_RLC_G_UCODE,
5343                                                    fw_data, fw_size);
5344
5345         /* mec1 ucode */
5346         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5347                 adev->gfx.mec_fw->data;
5348         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5349                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5350         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5351                 cp_hdr->jt_size * 4;
5352         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5353                                                    FIRMWARE_ID_CP_MEC,
5354                                                    fw_data, fw_size);
5355         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5356 }
5357
5358 /* Temporarily put sdma part here */
5359 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5360 {
5361         const __le32 *fw_data;
5362         uint32_t fw_size;
5363         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5364         int i;
5365
5366         for (i = 0; i < adev->sdma.num_instances; i++) {
5367                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5368                         adev->sdma.instance[i].fw->data;
5369                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5370                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5371                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5372
5373                 if (i == 0) {
5374                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5375                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5376                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5377                                 FIRMWARE_ID_SDMA0_JT,
5378                                 (uint32_t *)fw_data +
5379                                 sdma_hdr->jt_offset,
5380                                 sdma_hdr->jt_size * 4);
5381                 } else if (i == 1) {
5382                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5383                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5384                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5385                                 FIRMWARE_ID_SDMA1_JT,
5386                                 (uint32_t *)fw_data +
5387                                 sdma_hdr->jt_offset,
5388                                 sdma_hdr->jt_size * 4);
5389                 }
5390         }
5391 }
5392
5393 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5394 {
5395         uint32_t rlc_g_offset, rlc_g_size, tmp;
5396         uint64_t gpu_addr;
5397
5398         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5399         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5400         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5401
5402         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5403         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5404         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5405
5406         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5407         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5408         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5409
5410         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5411         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5412                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5413                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5414                 return -EINVAL;
5415         }
5416
5417         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5418         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5419                 DRM_ERROR("RLC ROM should halt itself\n");
5420                 return -EINVAL;
5421         }
5422
5423         return 0;
5424 }
5425
5426 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5427 {
5428         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5429         uint32_t tmp;
5430         int i;
5431         uint64_t addr;
5432
5433         /* Trigger an invalidation of the L1 instruction caches */
5434         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5435         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5436         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5437
5438         /* Wait for invalidation complete */
5439         for (i = 0; i < usec_timeout; i++) {
5440                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5441                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5442                         INVALIDATE_CACHE_COMPLETE))
5443                         break;
5444                 udelay(1);
5445         }
5446
5447         if (i >= usec_timeout) {
5448                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5449                 return -EINVAL;
5450         }
5451
5452         /* Program me ucode address into intruction cache address register */
5453         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5454                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5455         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5456                         lower_32_bits(addr) & 0xFFFFF000);
5457         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5458                         upper_32_bits(addr));
5459
5460         return 0;
5461 }
5462
5463 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5464 {
5465         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5466         uint32_t tmp;
5467         int i;
5468         uint64_t addr;
5469
5470         /* Trigger an invalidation of the L1 instruction caches */
5471         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5472         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5473         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5474
5475         /* Wait for invalidation complete */
5476         for (i = 0; i < usec_timeout; i++) {
5477                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5478                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5479                         INVALIDATE_CACHE_COMPLETE))
5480                         break;
5481                 udelay(1);
5482         }
5483
5484         if (i >= usec_timeout) {
5485                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5486                 return -EINVAL;
5487         }
5488
5489         /* Program ce ucode address into intruction cache address register */
5490         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5491                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5492         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5493                         lower_32_bits(addr) & 0xFFFFF000);
5494         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5495                         upper_32_bits(addr));
5496
5497         return 0;
5498 }
5499
5500 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5501 {
5502         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5503         uint32_t tmp;
5504         int i;
5505         uint64_t addr;
5506
5507         /* Trigger an invalidation of the L1 instruction caches */
5508         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5509         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5510         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5511
5512         /* Wait for invalidation complete */
5513         for (i = 0; i < usec_timeout; i++) {
5514                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5515                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5516                         INVALIDATE_CACHE_COMPLETE))
5517                         break;
5518                 udelay(1);
5519         }
5520
5521         if (i >= usec_timeout) {
5522                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5523                 return -EINVAL;
5524         }
5525
5526         /* Program pfp ucode address into intruction cache address register */
5527         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5528                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5529         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5530                         lower_32_bits(addr) & 0xFFFFF000);
5531         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5532                         upper_32_bits(addr));
5533
5534         return 0;
5535 }
5536
5537 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5538 {
5539         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5540         uint32_t tmp;
5541         int i;
5542         uint64_t addr;
5543
5544         /* Trigger an invalidation of the L1 instruction caches */
5545         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5546         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5547         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5548
5549         /* Wait for invalidation complete */
5550         for (i = 0; i < usec_timeout; i++) {
5551                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5552                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5553                         INVALIDATE_CACHE_COMPLETE))
5554                         break;
5555                 udelay(1);
5556         }
5557
5558         if (i >= usec_timeout) {
5559                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5560                 return -EINVAL;
5561         }
5562
5563         /* Program mec1 ucode address into intruction cache address register */
5564         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5565                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5566         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5567                         lower_32_bits(addr) & 0xFFFFF000);
5568         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5569                         upper_32_bits(addr));
5570
5571         return 0;
5572 }
5573
5574 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5575 {
5576         uint32_t cp_status;
5577         uint32_t bootload_status;
5578         int i, r;
5579
5580         for (i = 0; i < adev->usec_timeout; i++) {
5581                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5582                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5583                 if ((cp_status == 0) &&
5584                     (REG_GET_FIELD(bootload_status,
5585                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5586                         break;
5587                 }
5588                 udelay(1);
5589         }
5590
5591         if (i >= adev->usec_timeout) {
5592                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5593                 return -ETIMEDOUT;
5594         }
5595
5596         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5597                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5598                 if (r)
5599                         return r;
5600
5601                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5602                 if (r)
5603                         return r;
5604
5605                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5606                 if (r)
5607                         return r;
5608
5609                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5610                 if (r)
5611                         return r;
5612         }
5613
5614         return 0;
5615 }
5616
5617 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5618 {
5619         int i;
5620         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5621
5622         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5623         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5624         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5625
5626         if (adev->asic_type == CHIP_NAVI12) {
5627                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5628         } else {
5629                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5630         }
5631
5632         for (i = 0; i < adev->usec_timeout; i++) {
5633                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5634                         break;
5635                 udelay(1);
5636         }
5637
5638         if (i >= adev->usec_timeout)
5639                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5640
5641         return 0;
5642 }
5643
5644 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5645 {
5646         int r;
5647         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5648         const __le32 *fw_data;
5649         unsigned i, fw_size;
5650         uint32_t tmp;
5651         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5652
5653         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5654                 adev->gfx.pfp_fw->data;
5655
5656         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5657
5658         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5659                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5660         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5661
5662         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5663                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5664                                       &adev->gfx.pfp.pfp_fw_obj,
5665                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5666                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5667         if (r) {
5668                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5669                 gfx_v10_0_pfp_fini(adev);
5670                 return r;
5671         }
5672
5673         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5674
5675         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5676         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5677
5678         /* Trigger an invalidation of the L1 instruction caches */
5679         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5680         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5681         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5682
5683         /* Wait for invalidation complete */
5684         for (i = 0; i < usec_timeout; i++) {
5685                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5686                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5687                         INVALIDATE_CACHE_COMPLETE))
5688                         break;
5689                 udelay(1);
5690         }
5691
5692         if (i >= usec_timeout) {
5693                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5694                 return -EINVAL;
5695         }
5696
5697         if (amdgpu_emu_mode == 1)
5698                 adev->nbio.funcs->hdp_flush(adev, NULL);
5699
5700         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5701         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5702         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5703         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5704         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5705         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5706         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5707                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5708         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5709                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5710
5711         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5712
5713         for (i = 0; i < pfp_hdr->jt_size; i++)
5714                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5715                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5716
5717         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5718
5719         return 0;
5720 }
5721
5722 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5723 {
5724         int r;
5725         const struct gfx_firmware_header_v1_0 *ce_hdr;
5726         const __le32 *fw_data;
5727         unsigned i, fw_size;
5728         uint32_t tmp;
5729         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5730
5731         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5732                 adev->gfx.ce_fw->data;
5733
5734         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5735
5736         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5737                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5738         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5739
5740         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5741                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5742                                       &adev->gfx.ce.ce_fw_obj,
5743                                       &adev->gfx.ce.ce_fw_gpu_addr,
5744                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5745         if (r) {
5746                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5747                 gfx_v10_0_ce_fini(adev);
5748                 return r;
5749         }
5750
5751         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5752
5753         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5754         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5755
5756         /* Trigger an invalidation of the L1 instruction caches */
5757         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5758         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5759         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5760
5761         /* Wait for invalidation complete */
5762         for (i = 0; i < usec_timeout; i++) {
5763                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5764                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5765                         INVALIDATE_CACHE_COMPLETE))
5766                         break;
5767                 udelay(1);
5768         }
5769
5770         if (i >= usec_timeout) {
5771                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5772                 return -EINVAL;
5773         }
5774
5775         if (amdgpu_emu_mode == 1)
5776                 adev->nbio.funcs->hdp_flush(adev, NULL);
5777
5778         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5779         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5780         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5781         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5782         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5783         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5784                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5785         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5786                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5787
5788         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5789
5790         for (i = 0; i < ce_hdr->jt_size; i++)
5791                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5792                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5793
5794         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5795
5796         return 0;
5797 }
5798
5799 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5800 {
5801         int r;
5802         const struct gfx_firmware_header_v1_0 *me_hdr;
5803         const __le32 *fw_data;
5804         unsigned i, fw_size;
5805         uint32_t tmp;
5806         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5807
5808         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5809                 adev->gfx.me_fw->data;
5810
5811         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5812
5813         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5814                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5815         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5816
5817         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5818                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5819                                       &adev->gfx.me.me_fw_obj,
5820                                       &adev->gfx.me.me_fw_gpu_addr,
5821                                       (void **)&adev->gfx.me.me_fw_ptr);
5822         if (r) {
5823                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5824                 gfx_v10_0_me_fini(adev);
5825                 return r;
5826         }
5827
5828         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5829
5830         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5831         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5832
5833         /* Trigger an invalidation of the L1 instruction caches */
5834         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5835         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5836         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5837
5838         /* Wait for invalidation complete */
5839         for (i = 0; i < usec_timeout; i++) {
5840                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5841                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5842                         INVALIDATE_CACHE_COMPLETE))
5843                         break;
5844                 udelay(1);
5845         }
5846
5847         if (i >= usec_timeout) {
5848                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5849                 return -EINVAL;
5850         }
5851
5852         if (amdgpu_emu_mode == 1)
5853                 adev->nbio.funcs->hdp_flush(adev, NULL);
5854
5855         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5856         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5857         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5858         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5859         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5860         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5861                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5862         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5863                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5864
5865         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5866
5867         for (i = 0; i < me_hdr->jt_size; i++)
5868                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5869                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5870
5871         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5872
5873         return 0;
5874 }
5875
5876 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5877 {
5878         int r;
5879
5880         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5881                 return -EINVAL;
5882
5883         gfx_v10_0_cp_gfx_enable(adev, false);
5884
5885         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5886         if (r) {
5887                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5888                 return r;
5889         }
5890
5891         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5892         if (r) {
5893                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5894                 return r;
5895         }
5896
5897         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5898         if (r) {
5899                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5900                 return r;
5901         }
5902
5903         return 0;
5904 }
5905
5906 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5907 {
5908         struct amdgpu_ring *ring;
5909         const struct cs_section_def *sect = NULL;
5910         const struct cs_extent_def *ext = NULL;
5911         int r, i;
5912         int ctx_reg_offset;
5913
5914         /* init the CP */
5915         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5916                      adev->gfx.config.max_hw_contexts - 1);
5917         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5918
5919         gfx_v10_0_cp_gfx_enable(adev, true);
5920
5921         ring = &adev->gfx.gfx_ring[0];
5922         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5923         if (r) {
5924                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5925                 return r;
5926         }
5927
5928         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5929         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5930
5931         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5932         amdgpu_ring_write(ring, 0x80000000);
5933         amdgpu_ring_write(ring, 0x80000000);
5934
5935         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5936                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5937                         if (sect->id == SECT_CONTEXT) {
5938                                 amdgpu_ring_write(ring,
5939                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5940                                                           ext->reg_count));
5941                                 amdgpu_ring_write(ring, ext->reg_index -
5942                                                   PACKET3_SET_CONTEXT_REG_START);
5943                                 for (i = 0; i < ext->reg_count; i++)
5944                                         amdgpu_ring_write(ring, ext->extent[i]);
5945                         }
5946                 }
5947         }
5948
5949         ctx_reg_offset =
5950                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5951         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5952         amdgpu_ring_write(ring, ctx_reg_offset);
5953         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5954
5955         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5956         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5957
5958         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5959         amdgpu_ring_write(ring, 0);
5960
5961         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5962         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5963         amdgpu_ring_write(ring, 0x8000);
5964         amdgpu_ring_write(ring, 0x8000);
5965
5966         amdgpu_ring_commit(ring);
5967
5968         /* submit cs packet to copy state 0 to next available state */
5969         if (adev->gfx.num_gfx_rings > 1) {
5970                 /* maximum supported gfx ring is 2 */
5971                 ring = &adev->gfx.gfx_ring[1];
5972                 r = amdgpu_ring_alloc(ring, 2);
5973                 if (r) {
5974                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5975                         return r;
5976                 }
5977
5978                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5979                 amdgpu_ring_write(ring, 0);
5980
5981                 amdgpu_ring_commit(ring);
5982         }
5983         return 0;
5984 }
5985
5986 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5987                                          CP_PIPE_ID pipe)
5988 {
5989         u32 tmp;
5990
5991         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5992         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5993
5994         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5995 }
5996
5997 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5998                                           struct amdgpu_ring *ring)
5999 {
6000         u32 tmp;
6001
6002         if (!amdgpu_async_gfx_ring) {
6003                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6004                 if (ring->use_doorbell) {
6005                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6006                                                 DOORBELL_OFFSET, ring->doorbell_index);
6007                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6008                                                 DOORBELL_EN, 1);
6009                 } else {
6010                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6011                                                 DOORBELL_EN, 0);
6012                 }
6013                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6014         }
6015         switch (adev->asic_type) {
6016         case CHIP_SIENNA_CICHLID:
6017         case CHIP_NAVY_FLOUNDER:
6018         case CHIP_VANGOGH:
6019         case CHIP_DIMGREY_CAVEFISH:
6020                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6021                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6022                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6023
6024                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6025                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6026                 break;
6027         default:
6028                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6029                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6030                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6031
6032                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6033                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6034                 break;
6035         }
6036 }
6037
6038 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6039 {
6040         struct amdgpu_ring *ring;
6041         u32 tmp;
6042         u32 rb_bufsz;
6043         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6044         u32 i;
6045
6046         /* Set the write pointer delay */
6047         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6048
6049         /* set the RB to use vmid 0 */
6050         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6051
6052         /* Init gfx ring 0 for pipe 0 */
6053         mutex_lock(&adev->srbm_mutex);
6054         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6055
6056         /* Set ring buffer size */
6057         ring = &adev->gfx.gfx_ring[0];
6058         rb_bufsz = order_base_2(ring->ring_size / 8);
6059         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6060         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6061 #ifdef __BIG_ENDIAN
6062         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6063 #endif
6064         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6065
6066         /* Initialize the ring buffer's write pointers */
6067         ring->wptr = 0;
6068         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6069         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6070
6071         /* set the wb address wether it's enabled or not */
6072         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6073         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6074         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6075                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6076
6077         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6078         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6079                      lower_32_bits(wptr_gpu_addr));
6080         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6081                      upper_32_bits(wptr_gpu_addr));
6082
6083         mdelay(1);
6084         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6085
6086         rb_addr = ring->gpu_addr >> 8;
6087         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6088         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6089
6090         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6091
6092         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6093         mutex_unlock(&adev->srbm_mutex);
6094
6095         /* Init gfx ring 1 for pipe 1 */
6096         if (adev->gfx.num_gfx_rings > 1) {
6097                 mutex_lock(&adev->srbm_mutex);
6098                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6099                 /* maximum supported gfx ring is 2 */
6100                 ring = &adev->gfx.gfx_ring[1];
6101                 rb_bufsz = order_base_2(ring->ring_size / 8);
6102                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6103                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6104                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6105                 /* Initialize the ring buffer's write pointers */
6106                 ring->wptr = 0;
6107                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6108                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6109                 /* Set the wb address wether it's enabled or not */
6110                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6111                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6112                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6113                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6114                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6115                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6116                              lower_32_bits(wptr_gpu_addr));
6117                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6118                              upper_32_bits(wptr_gpu_addr));
6119
6120                 mdelay(1);
6121                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6122
6123                 rb_addr = ring->gpu_addr >> 8;
6124                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6125                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6126                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6127
6128                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6129                 mutex_unlock(&adev->srbm_mutex);
6130         }
6131         /* Switch to pipe 0 */
6132         mutex_lock(&adev->srbm_mutex);
6133         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6134         mutex_unlock(&adev->srbm_mutex);
6135
6136         /* start the ring */
6137         gfx_v10_0_cp_gfx_start(adev);
6138
6139         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6140                 ring = &adev->gfx.gfx_ring[i];
6141                 ring->sched.ready = true;
6142         }
6143
6144         return 0;
6145 }
6146
6147 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6148 {
6149         if (enable) {
6150                 switch (adev->asic_type) {
6151                 case CHIP_SIENNA_CICHLID:
6152                 case CHIP_NAVY_FLOUNDER:
6153                 case CHIP_VANGOGH:
6154                 case CHIP_DIMGREY_CAVEFISH:
6155                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6156                         break;
6157                 default:
6158                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6159                         break;
6160                 }
6161         } else {
6162                 switch (adev->asic_type) {
6163                 case CHIP_SIENNA_CICHLID:
6164                 case CHIP_NAVY_FLOUNDER:
6165                 case CHIP_VANGOGH:
6166                 case CHIP_DIMGREY_CAVEFISH:
6167                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6168                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6169                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6170                         break;
6171                 default:
6172                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6173                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6174                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6175                         break;
6176                 }
6177                 adev->gfx.kiq.ring.sched.ready = false;
6178         }
6179         udelay(50);
6180 }
6181
6182 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6183 {
6184         const struct gfx_firmware_header_v1_0 *mec_hdr;
6185         const __le32 *fw_data;
6186         unsigned i;
6187         u32 tmp;
6188         u32 usec_timeout = 50000; /* Wait for 50 ms */
6189
6190         if (!adev->gfx.mec_fw)
6191                 return -EINVAL;
6192
6193         gfx_v10_0_cp_compute_enable(adev, false);
6194
6195         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6196         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6197
6198         fw_data = (const __le32 *)
6199                 (adev->gfx.mec_fw->data +
6200                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6201
6202         /* Trigger an invalidation of the L1 instruction caches */
6203         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6204         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6205         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6206
6207         /* Wait for invalidation complete */
6208         for (i = 0; i < usec_timeout; i++) {
6209                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6210                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6211                                        INVALIDATE_CACHE_COMPLETE))
6212                         break;
6213                 udelay(1);
6214         }
6215
6216         if (i >= usec_timeout) {
6217                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6218                 return -EINVAL;
6219         }
6220
6221         if (amdgpu_emu_mode == 1)
6222                 adev->nbio.funcs->hdp_flush(adev, NULL);
6223
6224         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6225         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6226         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6227         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6228         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6229
6230         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6231                      0xFFFFF000);
6232         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6233                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6234
6235         /* MEC1 */
6236         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6237
6238         for (i = 0; i < mec_hdr->jt_size; i++)
6239                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6240                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6241
6242         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6243
6244         /*
6245          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6246          * different microcode than MEC1.
6247          */
6248
6249         return 0;
6250 }
6251
6252 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6253 {
6254         uint32_t tmp;
6255         struct amdgpu_device *adev = ring->adev;
6256
6257         /* tell RLC which is KIQ queue */
6258         switch (adev->asic_type) {
6259         case CHIP_SIENNA_CICHLID:
6260         case CHIP_NAVY_FLOUNDER:
6261         case CHIP_VANGOGH:
6262         case CHIP_DIMGREY_CAVEFISH:
6263                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6264                 tmp &= 0xffffff00;
6265                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6266                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6267                 tmp |= 0x80;
6268                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6269                 break;
6270         default:
6271                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6272                 tmp &= 0xffffff00;
6273                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6274                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6275                 tmp |= 0x80;
6276                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6277                 break;
6278         }
6279 }
6280
6281 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6282 {
6283         struct amdgpu_device *adev = ring->adev;
6284         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6285         uint64_t hqd_gpu_addr, wb_gpu_addr;
6286         uint32_t tmp;
6287         uint32_t rb_bufsz;
6288
6289         /* set up gfx hqd wptr */
6290         mqd->cp_gfx_hqd_wptr = 0;
6291         mqd->cp_gfx_hqd_wptr_hi = 0;
6292
6293         /* set the pointer to the MQD */
6294         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6295         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6296
6297         /* set up mqd control */
6298         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6299         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6300         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6301         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6302         mqd->cp_gfx_mqd_control = tmp;
6303
6304         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6305         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6306         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6307         mqd->cp_gfx_hqd_vmid = 0;
6308
6309         /* set up default queue priority level
6310          * 0x0 = low priority, 0x1 = high priority */
6311         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6312         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6313         mqd->cp_gfx_hqd_queue_priority = tmp;
6314
6315         /* set up time quantum */
6316         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6317         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6318         mqd->cp_gfx_hqd_quantum = tmp;
6319
6320         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6321         hqd_gpu_addr = ring->gpu_addr >> 8;
6322         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6323         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6324
6325         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6326         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6327         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6328         mqd->cp_gfx_hqd_rptr_addr_hi =
6329                 upper_32_bits(wb_gpu_addr) & 0xffff;
6330
6331         /* set up rb_wptr_poll addr */
6332         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6333         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6334         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6335
6336         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6337         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6338         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6339         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6340         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6341 #ifdef __BIG_ENDIAN
6342         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6343 #endif
6344         mqd->cp_gfx_hqd_cntl = tmp;
6345
6346         /* set up cp_doorbell_control */
6347         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6348         if (ring->use_doorbell) {
6349                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6350                                     DOORBELL_OFFSET, ring->doorbell_index);
6351                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6352                                     DOORBELL_EN, 1);
6353         } else
6354                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6355                                     DOORBELL_EN, 0);
6356         mqd->cp_rb_doorbell_control = tmp;
6357
6358         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6359          *otherwise the range of the second ring will override the first ring */
6360         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6361                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6362
6363         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6364         ring->wptr = 0;
6365         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6366
6367         /* active the queue */
6368         mqd->cp_gfx_hqd_active = 1;
6369
6370         return 0;
6371 }
6372
6373 #ifdef BRING_UP_DEBUG
6374 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6375 {
6376         struct amdgpu_device *adev = ring->adev;
6377         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6378
6379         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6380         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6381         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6382
6383         /* set GFX_MQD_BASE */
6384         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6385         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6386
6387         /* set GFX_MQD_CONTROL */
6388         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6389
6390         /* set GFX_HQD_VMID to 0 */
6391         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6392
6393         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6394                         mqd->cp_gfx_hqd_queue_priority);
6395         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6396
6397         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6398         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6399         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6400
6401         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6402         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6403         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6404
6405         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6406         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6407
6408         /* set RB_WPTR_POLL_ADDR */
6409         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6410         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6411
6412         /* set RB_DOORBELL_CONTROL */
6413         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6414
6415         /* active the queue */
6416         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6417
6418         return 0;
6419 }
6420 #endif
6421
6422 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6423 {
6424         struct amdgpu_device *adev = ring->adev;
6425         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6426         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6427
6428         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6429                 memset((void *)mqd, 0, sizeof(*mqd));
6430                 mutex_lock(&adev->srbm_mutex);
6431                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6432                 gfx_v10_0_gfx_mqd_init(ring);
6433 #ifdef BRING_UP_DEBUG
6434                 gfx_v10_0_gfx_queue_init_register(ring);
6435 #endif
6436                 nv_grbm_select(adev, 0, 0, 0, 0);
6437                 mutex_unlock(&adev->srbm_mutex);
6438                 if (adev->gfx.me.mqd_backup[mqd_idx])
6439                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6440         } else if (amdgpu_in_reset(adev)) {
6441                 /* reset mqd with the backup copy */
6442                 if (adev->gfx.me.mqd_backup[mqd_idx])
6443                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6444                 /* reset the ring */
6445                 ring->wptr = 0;
6446                 adev->wb.wb[ring->wptr_offs] = 0;
6447                 amdgpu_ring_clear_ring(ring);
6448 #ifdef BRING_UP_DEBUG
6449                 mutex_lock(&adev->srbm_mutex);
6450                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6451                 gfx_v10_0_gfx_queue_init_register(ring);
6452                 nv_grbm_select(adev, 0, 0, 0, 0);
6453                 mutex_unlock(&adev->srbm_mutex);
6454 #endif
6455         } else {
6456                 amdgpu_ring_clear_ring(ring);
6457         }
6458
6459         return 0;
6460 }
6461
6462 #ifndef BRING_UP_DEBUG
6463 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6464 {
6465         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6466         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6467         int r, i;
6468
6469         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6470                 return -EINVAL;
6471
6472         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6473                                         adev->gfx.num_gfx_rings);
6474         if (r) {
6475                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6476                 return r;
6477         }
6478
6479         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6480                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6481
6482         return amdgpu_ring_test_helper(kiq_ring);
6483 }
6484 #endif
6485
6486 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6487 {
6488         int r, i;
6489         struct amdgpu_ring *ring;
6490
6491         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6492                 ring = &adev->gfx.gfx_ring[i];
6493
6494                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6495                 if (unlikely(r != 0))
6496                         goto done;
6497
6498                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6499                 if (!r) {
6500                         r = gfx_v10_0_gfx_init_queue(ring);
6501                         amdgpu_bo_kunmap(ring->mqd_obj);
6502                         ring->mqd_ptr = NULL;
6503                 }
6504                 amdgpu_bo_unreserve(ring->mqd_obj);
6505                 if (r)
6506                         goto done;
6507         }
6508 #ifndef BRING_UP_DEBUG
6509         r = gfx_v10_0_kiq_enable_kgq(adev);
6510         if (r)
6511                 goto done;
6512 #endif
6513         r = gfx_v10_0_cp_gfx_start(adev);
6514         if (r)
6515                 goto done;
6516
6517         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6518                 ring = &adev->gfx.gfx_ring[i];
6519                 ring->sched.ready = true;
6520         }
6521 done:
6522         return r;
6523 }
6524
6525 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6526 {
6527         struct amdgpu_device *adev = ring->adev;
6528
6529         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6530                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
6531                                                               ring->queue)) {
6532                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6533                         mqd->cp_hqd_queue_priority =
6534                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6535                 }
6536         }
6537 }
6538
6539 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6540 {
6541         struct amdgpu_device *adev = ring->adev;
6542         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6543         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6544         uint32_t tmp;
6545
6546         mqd->header = 0xC0310800;
6547         mqd->compute_pipelinestat_enable = 0x00000001;
6548         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6549         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6550         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6551         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6552         mqd->compute_misc_reserved = 0x00000003;
6553
6554         eop_base_addr = ring->eop_gpu_addr >> 8;
6555         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6556         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6557
6558         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6559         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6560         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6561                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6562
6563         mqd->cp_hqd_eop_control = tmp;
6564
6565         /* enable doorbell? */
6566         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6567
6568         if (ring->use_doorbell) {
6569                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6570                                     DOORBELL_OFFSET, ring->doorbell_index);
6571                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6572                                     DOORBELL_EN, 1);
6573                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6574                                     DOORBELL_SOURCE, 0);
6575                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6576                                     DOORBELL_HIT, 0);
6577         } else {
6578                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6579                                     DOORBELL_EN, 0);
6580         }
6581
6582         mqd->cp_hqd_pq_doorbell_control = tmp;
6583
6584         /* disable the queue if it's active */
6585         ring->wptr = 0;
6586         mqd->cp_hqd_dequeue_request = 0;
6587         mqd->cp_hqd_pq_rptr = 0;
6588         mqd->cp_hqd_pq_wptr_lo = 0;
6589         mqd->cp_hqd_pq_wptr_hi = 0;
6590
6591         /* set the pointer to the MQD */
6592         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6593         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6594
6595         /* set MQD vmid to 0 */
6596         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6597         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6598         mqd->cp_mqd_control = tmp;
6599
6600         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6601         hqd_gpu_addr = ring->gpu_addr >> 8;
6602         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6603         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6604
6605         /* set up the HQD, this is similar to CP_RB0_CNTL */
6606         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6607         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6608                             (order_base_2(ring->ring_size / 4) - 1));
6609         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6610                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6611 #ifdef __BIG_ENDIAN
6612         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6613 #endif
6614         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6615         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6616         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6617         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6618         mqd->cp_hqd_pq_control = tmp;
6619
6620         /* set the wb address whether it's enabled or not */
6621         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6622         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6623         mqd->cp_hqd_pq_rptr_report_addr_hi =
6624                 upper_32_bits(wb_gpu_addr) & 0xffff;
6625
6626         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6627         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6628         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6629         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6630
6631         tmp = 0;
6632         /* enable the doorbell if requested */
6633         if (ring->use_doorbell) {
6634                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6635                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6636                                 DOORBELL_OFFSET, ring->doorbell_index);
6637
6638                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6639                                     DOORBELL_EN, 1);
6640                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6641                                     DOORBELL_SOURCE, 0);
6642                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6643                                     DOORBELL_HIT, 0);
6644         }
6645
6646         mqd->cp_hqd_pq_doorbell_control = tmp;
6647
6648         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6649         ring->wptr = 0;
6650         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6651
6652         /* set the vmid for the queue */
6653         mqd->cp_hqd_vmid = 0;
6654
6655         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6656         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6657         mqd->cp_hqd_persistent_state = tmp;
6658
6659         /* set MIN_IB_AVAIL_SIZE */
6660         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6661         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6662         mqd->cp_hqd_ib_control = tmp;
6663
6664         /* set static priority for a compute queue/ring */
6665         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6666
6667         /* map_queues packet doesn't need activate the queue,
6668          * so only kiq need set this field.
6669          */
6670         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6671                 mqd->cp_hqd_active = 1;
6672
6673         return 0;
6674 }
6675
6676 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6677 {
6678         struct amdgpu_device *adev = ring->adev;
6679         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6680         int j;
6681
6682         /* inactivate the queue */
6683         if (amdgpu_sriov_vf(adev))
6684                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6685
6686         /* disable wptr polling */
6687         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6688
6689         /* write the EOP addr */
6690         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6691                mqd->cp_hqd_eop_base_addr_lo);
6692         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6693                mqd->cp_hqd_eop_base_addr_hi);
6694
6695         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6696         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6697                mqd->cp_hqd_eop_control);
6698
6699         /* enable doorbell? */
6700         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6701                mqd->cp_hqd_pq_doorbell_control);
6702
6703         /* disable the queue if it's active */
6704         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6705                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6706                 for (j = 0; j < adev->usec_timeout; j++) {
6707                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6708                                 break;
6709                         udelay(1);
6710                 }
6711                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6712                        mqd->cp_hqd_dequeue_request);
6713                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6714                        mqd->cp_hqd_pq_rptr);
6715                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6716                        mqd->cp_hqd_pq_wptr_lo);
6717                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6718                        mqd->cp_hqd_pq_wptr_hi);
6719         }
6720
6721         /* set the pointer to the MQD */
6722         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6723                mqd->cp_mqd_base_addr_lo);
6724         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6725                mqd->cp_mqd_base_addr_hi);
6726
6727         /* set MQD vmid to 0 */
6728         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6729                mqd->cp_mqd_control);
6730
6731         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6732         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6733                mqd->cp_hqd_pq_base_lo);
6734         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6735                mqd->cp_hqd_pq_base_hi);
6736
6737         /* set up the HQD, this is similar to CP_RB0_CNTL */
6738         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6739                mqd->cp_hqd_pq_control);
6740
6741         /* set the wb address whether it's enabled or not */
6742         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6743                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6744         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6745                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6746
6747         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6748         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6749                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6750         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6751                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6752
6753         /* enable the doorbell if requested */
6754         if (ring->use_doorbell) {
6755                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6756                         (adev->doorbell_index.kiq * 2) << 2);
6757                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6758                         (adev->doorbell_index.userqueue_end * 2) << 2);
6759         }
6760
6761         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6762                mqd->cp_hqd_pq_doorbell_control);
6763
6764         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6765         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6766                mqd->cp_hqd_pq_wptr_lo);
6767         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6768                mqd->cp_hqd_pq_wptr_hi);
6769
6770         /* set the vmid for the queue */
6771         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6772
6773         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6774                mqd->cp_hqd_persistent_state);
6775
6776         /* activate the queue */
6777         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6778                mqd->cp_hqd_active);
6779
6780         if (ring->use_doorbell)
6781                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6782
6783         return 0;
6784 }
6785
6786 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6787 {
6788         struct amdgpu_device *adev = ring->adev;
6789         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6790         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6791
6792         gfx_v10_0_kiq_setting(ring);
6793
6794         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6795                 /* reset MQD to a clean status */
6796                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6797                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6798
6799                 /* reset ring buffer */
6800                 ring->wptr = 0;
6801                 amdgpu_ring_clear_ring(ring);
6802
6803                 mutex_lock(&adev->srbm_mutex);
6804                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6805                 gfx_v10_0_kiq_init_register(ring);
6806                 nv_grbm_select(adev, 0, 0, 0, 0);
6807                 mutex_unlock(&adev->srbm_mutex);
6808         } else {
6809                 memset((void *)mqd, 0, sizeof(*mqd));
6810                 mutex_lock(&adev->srbm_mutex);
6811                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6812                 gfx_v10_0_compute_mqd_init(ring);
6813                 gfx_v10_0_kiq_init_register(ring);
6814                 nv_grbm_select(adev, 0, 0, 0, 0);
6815                 mutex_unlock(&adev->srbm_mutex);
6816
6817                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6818                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6819         }
6820
6821         return 0;
6822 }
6823
6824 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6825 {
6826         struct amdgpu_device *adev = ring->adev;
6827         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6828         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6829
6830         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6831                 memset((void *)mqd, 0, sizeof(*mqd));
6832                 mutex_lock(&adev->srbm_mutex);
6833                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6834                 gfx_v10_0_compute_mqd_init(ring);
6835                 nv_grbm_select(adev, 0, 0, 0, 0);
6836                 mutex_unlock(&adev->srbm_mutex);
6837
6838                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6839                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6840         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6841                 /* reset MQD to a clean status */
6842                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6843                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6844
6845                 /* reset ring buffer */
6846                 ring->wptr = 0;
6847                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6848                 amdgpu_ring_clear_ring(ring);
6849         } else {
6850                 amdgpu_ring_clear_ring(ring);
6851         }
6852
6853         return 0;
6854 }
6855
6856 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6857 {
6858         struct amdgpu_ring *ring;
6859         int r;
6860
6861         ring = &adev->gfx.kiq.ring;
6862
6863         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6864         if (unlikely(r != 0))
6865                 return r;
6866
6867         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6868         if (unlikely(r != 0))
6869                 return r;
6870
6871         gfx_v10_0_kiq_init_queue(ring);
6872         amdgpu_bo_kunmap(ring->mqd_obj);
6873         ring->mqd_ptr = NULL;
6874         amdgpu_bo_unreserve(ring->mqd_obj);
6875         ring->sched.ready = true;
6876         return 0;
6877 }
6878
6879 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6880 {
6881         struct amdgpu_ring *ring = NULL;
6882         int r = 0, i;
6883
6884         gfx_v10_0_cp_compute_enable(adev, true);
6885
6886         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6887                 ring = &adev->gfx.compute_ring[i];
6888
6889                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6890                 if (unlikely(r != 0))
6891                         goto done;
6892                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6893                 if (!r) {
6894                         r = gfx_v10_0_kcq_init_queue(ring);
6895                         amdgpu_bo_kunmap(ring->mqd_obj);
6896                         ring->mqd_ptr = NULL;
6897                 }
6898                 amdgpu_bo_unreserve(ring->mqd_obj);
6899                 if (r)
6900                         goto done;
6901         }
6902
6903         r = amdgpu_gfx_enable_kcq(adev);
6904 done:
6905         return r;
6906 }
6907
6908 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6909 {
6910         int r, i;
6911         struct amdgpu_ring *ring;
6912
6913         if (!(adev->flags & AMD_IS_APU))
6914                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6915
6916         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6917                 /* legacy firmware loading */
6918                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6919                 if (r)
6920                         return r;
6921
6922                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6923                 if (r)
6924                         return r;
6925         }
6926
6927         r = gfx_v10_0_kiq_resume(adev);
6928         if (r)
6929                 return r;
6930
6931         r = gfx_v10_0_kcq_resume(adev);
6932         if (r)
6933                 return r;
6934
6935         if (!amdgpu_async_gfx_ring) {
6936                 r = gfx_v10_0_cp_gfx_resume(adev);
6937                 if (r)
6938                         return r;
6939         } else {
6940                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6941                 if (r)
6942                         return r;
6943         }
6944
6945         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6946                 ring = &adev->gfx.gfx_ring[i];
6947                 r = amdgpu_ring_test_helper(ring);
6948                 if (r)
6949                         return r;
6950         }
6951
6952         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6953                 ring = &adev->gfx.compute_ring[i];
6954                 r = amdgpu_ring_test_helper(ring);
6955                 if (r)
6956                         return r;
6957         }
6958
6959         return 0;
6960 }
6961
6962 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6963 {
6964         gfx_v10_0_cp_gfx_enable(adev, enable);
6965         gfx_v10_0_cp_compute_enable(adev, enable);
6966 }
6967
6968 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6969 {
6970         uint32_t data, pattern = 0xDEADBEEF;
6971
6972         /* check if mmVGT_ESGS_RING_SIZE_UMD
6973          * has been remapped to mmVGT_ESGS_RING_SIZE */
6974         switch (adev->asic_type) {
6975         case CHIP_SIENNA_CICHLID:
6976         case CHIP_NAVY_FLOUNDER:
6977         case CHIP_DIMGREY_CAVEFISH:
6978                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6979                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6980                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6981
6982                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6983                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6984                         return true;
6985                 } else {
6986                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6987                         return false;
6988                 }
6989                 break;
6990         case CHIP_VANGOGH:
6991                 return true;
6992         default:
6993                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6994                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6995                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6996
6997                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6998                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6999                         return true;
7000                 } else {
7001                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7002                         return false;
7003                 }
7004                 break;
7005         }
7006 }
7007
7008 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7009 {
7010         uint32_t data;
7011
7012         /* initialize cam_index to 0
7013          * index will auto-inc after each data writting */
7014         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7015
7016         switch (adev->asic_type) {
7017         case CHIP_SIENNA_CICHLID:
7018         case CHIP_NAVY_FLOUNDER:
7019         case CHIP_VANGOGH:
7020         case CHIP_DIMGREY_CAVEFISH:
7021                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7022                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7023                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7024                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7025                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7026                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7027                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7028
7029                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7030                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7031                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7032                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7033                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7034                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7035                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7036
7037                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7038                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7039                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7040                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7041                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7042                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7043                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7044
7045                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7046                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7047                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7048                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7049                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7050                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7051                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7052
7053                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7054                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7055                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7056                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7057                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7058                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7059                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7060
7061                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7062                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7063                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7064                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7065                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7066                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7067                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7068
7069                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7070                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7071                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7072                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7073                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7074                 break;
7075         default:
7076                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7077                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7078                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7079                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7080                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7081                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7082                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7083
7084                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7085                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7086                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7087                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7088                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7089                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7090                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7091
7092                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7093                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7094                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7095                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7096                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7097                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7098                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7099
7100                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7101                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7102                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7103                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7104                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7105                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7106                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7107
7108                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7109                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7110                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7111                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7112                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7113                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7114                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7115
7116                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7117                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7118                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7119                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7120                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7121                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7122                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7123
7124                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7125                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7126                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7127                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7128                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7129                 break;
7130         }
7131
7132         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7133         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7134 }
7135
7136 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7137 {
7138         uint32_t data;
7139         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7140         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7141         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7142
7143         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7144         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7145         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7146 }
7147
7148 static int gfx_v10_0_hw_init(void *handle)
7149 {
7150         int r;
7151         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7152
7153         if (!amdgpu_emu_mode)
7154                 gfx_v10_0_init_golden_registers(adev);
7155
7156         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7157                 /**
7158                  * For gfx 10, rlc firmware loading relies on smu firmware is
7159                  * loaded firstly, so in direct type, it has to load smc ucode
7160                  * here before rlc.
7161                  */
7162                 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) {
7163                         r = smu_load_microcode(&adev->smu);
7164                         if (r)
7165                                 return r;
7166
7167                         r = smu_check_fw_status(&adev->smu);
7168                         if (r) {
7169                                 pr_err("SMC firmware status is not correct\n");
7170                                 return r;
7171                         }
7172                 }
7173                 gfx_v10_0_disable_gpa_mode(adev);
7174         }
7175
7176         /* if GRBM CAM not remapped, set up the remapping */
7177         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7178                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7179
7180         gfx_v10_0_constants_init(adev);
7181
7182         r = gfx_v10_0_rlc_resume(adev);
7183         if (r)
7184                 return r;
7185
7186         /*
7187          * init golden registers and rlc resume may override some registers,
7188          * reconfig them here
7189          */
7190         gfx_v10_0_tcp_harvest(adev);
7191
7192         r = gfx_v10_0_cp_resume(adev);
7193         if (r)
7194                 return r;
7195
7196         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7197                 gfx_v10_3_program_pbb_mode(adev);
7198
7199         return r;
7200 }
7201
7202 #ifndef BRING_UP_DEBUG
7203 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7204 {
7205         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7206         struct amdgpu_ring *kiq_ring = &kiq->ring;
7207         int i;
7208
7209         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7210                 return -EINVAL;
7211
7212         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7213                                         adev->gfx.num_gfx_rings))
7214                 return -ENOMEM;
7215
7216         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7217                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7218                                            PREEMPT_QUEUES, 0, 0);
7219
7220         return amdgpu_ring_test_helper(kiq_ring);
7221 }
7222 #endif
7223
7224 static int gfx_v10_0_hw_fini(void *handle)
7225 {
7226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7227         int r;
7228         uint32_t tmp;
7229
7230         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7231         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7232
7233         if (!adev->in_pci_err_recovery) {
7234 #ifndef BRING_UP_DEBUG
7235                 if (amdgpu_async_gfx_ring) {
7236                         r = gfx_v10_0_kiq_disable_kgq(adev);
7237                         if (r)
7238                                 DRM_ERROR("KGQ disable failed\n");
7239                 }
7240 #endif
7241                 if (amdgpu_gfx_disable_kcq(adev))
7242                         DRM_ERROR("KCQ disable failed\n");
7243         }
7244
7245         if (amdgpu_sriov_vf(adev)) {
7246                 gfx_v10_0_cp_gfx_enable(adev, false);
7247                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7248                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7249                 tmp &= 0xffffff00;
7250                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7251
7252                 return 0;
7253         }
7254         gfx_v10_0_cp_enable(adev, false);
7255         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7256
7257         return 0;
7258 }
7259
7260 static int gfx_v10_0_suspend(void *handle)
7261 {
7262         return gfx_v10_0_hw_fini(handle);
7263 }
7264
7265 static int gfx_v10_0_resume(void *handle)
7266 {
7267         return gfx_v10_0_hw_init(handle);
7268 }
7269
7270 static bool gfx_v10_0_is_idle(void *handle)
7271 {
7272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7273
7274         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7275                                 GRBM_STATUS, GUI_ACTIVE))
7276                 return false;
7277         else
7278                 return true;
7279 }
7280
7281 static int gfx_v10_0_wait_for_idle(void *handle)
7282 {
7283         unsigned i;
7284         u32 tmp;
7285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7286
7287         for (i = 0; i < adev->usec_timeout; i++) {
7288                 /* read MC_STATUS */
7289                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7290                         GRBM_STATUS__GUI_ACTIVE_MASK;
7291
7292                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7293                         return 0;
7294                 udelay(1);
7295         }
7296         return -ETIMEDOUT;
7297 }
7298
7299 static int gfx_v10_0_soft_reset(void *handle)
7300 {
7301         u32 grbm_soft_reset = 0;
7302         u32 tmp;
7303         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7304
7305         /* GRBM_STATUS */
7306         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7307         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7308                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7309                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7310                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7311                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7312                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7313                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7314                                                 1);
7315                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7316                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7317                                                 1);
7318         }
7319
7320         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7321                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7322                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7323                                                 1);
7324         }
7325
7326         /* GRBM_STATUS2 */
7327         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7328         switch (adev->asic_type) {
7329         case CHIP_SIENNA_CICHLID:
7330         case CHIP_NAVY_FLOUNDER:
7331         case CHIP_VANGOGH:
7332         case CHIP_DIMGREY_CAVEFISH:
7333                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7334                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7335                                                         GRBM_SOFT_RESET,
7336                                                         SOFT_RESET_RLC,
7337                                                         1);
7338                 break;
7339         default:
7340                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7341                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7342                                                         GRBM_SOFT_RESET,
7343                                                         SOFT_RESET_RLC,
7344                                                         1);
7345                 break;
7346         }
7347
7348         if (grbm_soft_reset) {
7349                 /* stop the rlc */
7350                 gfx_v10_0_rlc_stop(adev);
7351
7352                 /* Disable GFX parsing/prefetching */
7353                 gfx_v10_0_cp_gfx_enable(adev, false);
7354
7355                 /* Disable MEC parsing/prefetching */
7356                 gfx_v10_0_cp_compute_enable(adev, false);
7357
7358                 if (grbm_soft_reset) {
7359                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7360                         tmp |= grbm_soft_reset;
7361                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7362                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7363                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7364
7365                         udelay(50);
7366
7367                         tmp &= ~grbm_soft_reset;
7368                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7369                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7370                 }
7371
7372                 /* Wait a little for things to settle down */
7373                 udelay(50);
7374         }
7375         return 0;
7376 }
7377
7378 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7379 {
7380         uint64_t clock;
7381
7382         amdgpu_gfx_off_ctrl(adev, false);
7383         mutex_lock(&adev->gfx.gpu_clock_mutex);
7384         switch (adev->asic_type) {
7385         case CHIP_VANGOGH:
7386                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7387                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7388                 break;
7389         default:
7390                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7391                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7392                 break;
7393         }
7394         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7395         amdgpu_gfx_off_ctrl(adev, true);
7396         return clock;
7397 }
7398
7399 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7400                                            uint32_t vmid,
7401                                            uint32_t gds_base, uint32_t gds_size,
7402                                            uint32_t gws_base, uint32_t gws_size,
7403                                            uint32_t oa_base, uint32_t oa_size)
7404 {
7405         struct amdgpu_device *adev = ring->adev;
7406
7407         /* GDS Base */
7408         gfx_v10_0_write_data_to_reg(ring, 0, false,
7409                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7410                                     gds_base);
7411
7412         /* GDS Size */
7413         gfx_v10_0_write_data_to_reg(ring, 0, false,
7414                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7415                                     gds_size);
7416
7417         /* GWS */
7418         gfx_v10_0_write_data_to_reg(ring, 0, false,
7419                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7420                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7421
7422         /* OA */
7423         gfx_v10_0_write_data_to_reg(ring, 0, false,
7424                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7425                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7426 }
7427
7428 static int gfx_v10_0_early_init(void *handle)
7429 {
7430         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7431
7432         switch (adev->asic_type) {
7433         case CHIP_NAVI10:
7434         case CHIP_NAVI14:
7435         case CHIP_NAVI12:
7436                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7437                 break;
7438         case CHIP_SIENNA_CICHLID:
7439         case CHIP_NAVY_FLOUNDER:
7440         case CHIP_VANGOGH:
7441         case CHIP_DIMGREY_CAVEFISH:
7442                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7443                 break;
7444         default:
7445                 break;
7446         }
7447
7448         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7449                                           AMDGPU_MAX_COMPUTE_RINGS);
7450
7451         gfx_v10_0_set_kiq_pm4_funcs(adev);
7452         gfx_v10_0_set_ring_funcs(adev);
7453         gfx_v10_0_set_irq_funcs(adev);
7454         gfx_v10_0_set_gds_init(adev);
7455         gfx_v10_0_set_rlc_funcs(adev);
7456
7457         return 0;
7458 }
7459
7460 static int gfx_v10_0_late_init(void *handle)
7461 {
7462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7463         int r;
7464
7465         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7466         if (r)
7467                 return r;
7468
7469         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7470         if (r)
7471                 return r;
7472
7473         return 0;
7474 }
7475
7476 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7477 {
7478         uint32_t rlc_cntl;
7479
7480         /* if RLC is not enabled, do nothing */
7481         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7482         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7483 }
7484
7485 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7486 {
7487         uint32_t data;
7488         unsigned i;
7489
7490         data = RLC_SAFE_MODE__CMD_MASK;
7491         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7492
7493         switch (adev->asic_type) {
7494         case CHIP_SIENNA_CICHLID:
7495         case CHIP_NAVY_FLOUNDER:
7496         case CHIP_VANGOGH:
7497         case CHIP_DIMGREY_CAVEFISH:
7498                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7499
7500                 /* wait for RLC_SAFE_MODE */
7501                 for (i = 0; i < adev->usec_timeout; i++) {
7502                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7503                                            RLC_SAFE_MODE, CMD))
7504                                 break;
7505                         udelay(1);
7506                 }
7507                 break;
7508         default:
7509                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7510
7511                 /* wait for RLC_SAFE_MODE */
7512                 for (i = 0; i < adev->usec_timeout; i++) {
7513                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7514                                            RLC_SAFE_MODE, CMD))
7515                                 break;
7516                         udelay(1);
7517                 }
7518                 break;
7519         }
7520 }
7521
7522 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7523 {
7524         uint32_t data;
7525
7526         data = RLC_SAFE_MODE__CMD_MASK;
7527         switch (adev->asic_type) {
7528         case CHIP_SIENNA_CICHLID:
7529         case CHIP_NAVY_FLOUNDER:
7530         case CHIP_VANGOGH:
7531         case CHIP_DIMGREY_CAVEFISH:
7532                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7533                 break;
7534         default:
7535                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7536                 break;
7537         }
7538 }
7539
7540 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7541                                                       bool enable)
7542 {
7543         uint32_t data, def;
7544
7545         /* It is disabled by HW by default */
7546         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7547                 /* 0 - Disable some blocks' MGCG */
7548                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7549                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7550                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7551                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7552
7553                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7554                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7555                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7556                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7557                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7558                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7559                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7560
7561                 if (def != data)
7562                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7563
7564                 /* MGLS is a global flag to control all MGLS in GFX */
7565                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7566                         /* 2 - RLC memory Light sleep */
7567                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7568                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7569                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7570                                 if (def != data)
7571                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7572                         }
7573                         /* 3 - CP memory Light sleep */
7574                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7575                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7576                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7577                                 if (def != data)
7578                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7579                         }
7580                 }
7581         } else {
7582                 /* 1 - MGCG_OVERRIDE */
7583                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7584                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7585                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7586                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7587                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7588                 if (def != data)
7589                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7590
7591                 /* 2 - disable MGLS in CP */
7592                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7593                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7594                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7595                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7596                 }
7597
7598                 /* 3 - disable MGLS in RLC */
7599                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7600                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7601                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7602                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7603                 }
7604
7605         }
7606 }
7607
7608 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7609                                            bool enable)
7610 {
7611         uint32_t data, def;
7612
7613         /* Enable 3D CGCG/CGLS */
7614         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7615                 /* write cmd to clear cgcg/cgls ov */
7616                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7617                 /* unset CGCG override */
7618                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7619                 /* update CGCG and CGLS override bits */
7620                 if (def != data)
7621                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7622                 /* enable 3Dcgcg FSM(0x0000363f) */
7623                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7624                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7625                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7626                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7627                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7628                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7629                 if (def != data)
7630                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7631
7632                 /* set IDLE_POLL_COUNT(0x00900100) */
7633                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7634                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7635                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7636                 if (def != data)
7637                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7638         } else {
7639                 /* Disable CGCG/CGLS */
7640                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7641                 /* disable cgcg, cgls should be disabled */
7642                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7643                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7644                 /* disable cgcg and cgls in FSM */
7645                 if (def != data)
7646                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7647         }
7648 }
7649
7650 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7651                                                       bool enable)
7652 {
7653         uint32_t def, data;
7654
7655         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7656                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7657                 /* unset CGCG override */
7658                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7659                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7660                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7661                 else
7662                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7663                 /* update CGCG and CGLS override bits */
7664                 if (def != data)
7665                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7666
7667                 /* enable cgcg FSM(0x0000363F) */
7668                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7669                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7670                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7671                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7672                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7673                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7674                 if (def != data)
7675                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7676
7677                 /* set IDLE_POLL_COUNT(0x00900100) */
7678                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7679                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7680                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7681                 if (def != data)
7682                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7683         } else {
7684                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7685                 /* reset CGCG/CGLS bits */
7686                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7687                 /* disable cgcg and cgls in FSM */
7688                 if (def != data)
7689                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7690         }
7691 }
7692
7693 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7694                                                       bool enable)
7695 {
7696         uint32_t def, data;
7697
7698         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7699                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7700                 /* unset FGCG override */
7701                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7702                 /* update FGCG override bits */
7703                 if (def != data)
7704                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7705
7706                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7707                 /* unset RLC SRAM CLK GATER override */
7708                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7709                 /* update RLC SRAM CLK GATER override bits */
7710                 if (def != data)
7711                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7712         } else {
7713                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7714                 /* reset FGCG bits */
7715                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7716                 /* disable FGCG*/
7717                 if (def != data)
7718                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7719
7720                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7721                 /* reset RLC SRAM CLK GATER bits */
7722                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7723                 /* disable RLC SRAM CLK*/
7724                 if (def != data)
7725                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7726         }
7727 }
7728
7729 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7730                                             bool enable)
7731 {
7732         amdgpu_gfx_rlc_enter_safe_mode(adev);
7733
7734         if (enable) {
7735                 /* enable FGCG firstly*/
7736                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7737                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7738                  * ===  MGCG + MGLS ===
7739                  */
7740                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7741                 /* ===  CGCG /CGLS for GFX 3D Only === */
7742                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7743                 /* ===  CGCG + CGLS === */
7744                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7745         } else {
7746                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7747                  * ===  CGCG + CGLS ===
7748                  */
7749                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7750                 /* ===  CGCG /CGLS for GFX 3D Only === */
7751                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7752                 /* ===  MGCG + MGLS === */
7753                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7754                 /* disable fgcg at last*/
7755                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7756         }
7757
7758         if (adev->cg_flags &
7759             (AMD_CG_SUPPORT_GFX_MGCG |
7760              AMD_CG_SUPPORT_GFX_CGLS |
7761              AMD_CG_SUPPORT_GFX_CGCG |
7762              AMD_CG_SUPPORT_GFX_3D_CGCG |
7763              AMD_CG_SUPPORT_GFX_3D_CGLS))
7764                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7765
7766         amdgpu_gfx_rlc_exit_safe_mode(adev);
7767
7768         return 0;
7769 }
7770
7771 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7772 {
7773         u32 reg, data;
7774
7775         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7776         if (amdgpu_sriov_is_pp_one_vf(adev))
7777                 data = RREG32_NO_KIQ(reg);
7778         else
7779                 data = RREG32(reg);
7780
7781         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7782         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7783
7784         if (amdgpu_sriov_is_pp_one_vf(adev))
7785                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7786         else
7787                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7788 }
7789
7790 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7791                                         uint32_t offset,
7792                                         struct soc15_reg_rlcg *entries, int arr_size)
7793 {
7794         int i;
7795         uint32_t reg;
7796
7797         if (!entries)
7798                 return false;
7799
7800         for (i = 0; i < arr_size; i++) {
7801                 const struct soc15_reg_rlcg *entry;
7802
7803                 entry = &entries[i];
7804                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7805                 if (offset == reg)
7806                         return true;
7807         }
7808
7809         return false;
7810 }
7811
7812 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7813 {
7814         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7815 }
7816
7817 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7818 {
7819         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7820
7821         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7822                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7823         else
7824                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7825
7826         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7827 }
7828
7829 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7830 {
7831         amdgpu_gfx_rlc_enter_safe_mode(adev);
7832
7833         gfx_v10_cntl_power_gating(adev, enable);
7834
7835         amdgpu_gfx_rlc_exit_safe_mode(adev);
7836 }
7837
7838 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7839         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7840         .set_safe_mode = gfx_v10_0_set_safe_mode,
7841         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7842         .init = gfx_v10_0_rlc_init,
7843         .get_csb_size = gfx_v10_0_get_csb_size,
7844         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7845         .resume = gfx_v10_0_rlc_resume,
7846         .stop = gfx_v10_0_rlc_stop,
7847         .reset = gfx_v10_0_rlc_reset,
7848         .start = gfx_v10_0_rlc_start,
7849         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7850 };
7851
7852 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7853         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7854         .set_safe_mode = gfx_v10_0_set_safe_mode,
7855         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7856         .init = gfx_v10_0_rlc_init,
7857         .get_csb_size = gfx_v10_0_get_csb_size,
7858         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7859         .resume = gfx_v10_0_rlc_resume,
7860         .stop = gfx_v10_0_rlc_stop,
7861         .reset = gfx_v10_0_rlc_reset,
7862         .start = gfx_v10_0_rlc_start,
7863         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7864         .rlcg_wreg = gfx_v10_rlcg_wreg,
7865         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7866 };
7867
7868 static int gfx_v10_0_set_powergating_state(void *handle,
7869                                           enum amd_powergating_state state)
7870 {
7871         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7872         bool enable = (state == AMD_PG_STATE_GATE);
7873
7874         if (amdgpu_sriov_vf(adev))
7875                 return 0;
7876
7877         switch (adev->asic_type) {
7878         case CHIP_NAVI10:
7879         case CHIP_NAVI14:
7880         case CHIP_NAVI12:
7881         case CHIP_SIENNA_CICHLID:
7882         case CHIP_NAVY_FLOUNDER:
7883         case CHIP_DIMGREY_CAVEFISH:
7884                 amdgpu_gfx_off_ctrl(adev, enable);
7885                 break;
7886         case CHIP_VANGOGH:
7887                 gfx_v10_cntl_pg(adev, enable);
7888                 break;
7889         default:
7890                 break;
7891         }
7892         return 0;
7893 }
7894
7895 static int gfx_v10_0_set_clockgating_state(void *handle,
7896                                           enum amd_clockgating_state state)
7897 {
7898         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7899
7900         if (amdgpu_sriov_vf(adev))
7901                 return 0;
7902
7903         switch (adev->asic_type) {
7904         case CHIP_NAVI10:
7905         case CHIP_NAVI14:
7906         case CHIP_NAVI12:
7907         case CHIP_SIENNA_CICHLID:
7908         case CHIP_NAVY_FLOUNDER:
7909         case CHIP_VANGOGH:
7910         case CHIP_DIMGREY_CAVEFISH:
7911                 gfx_v10_0_update_gfx_clock_gating(adev,
7912                                                  state == AMD_CG_STATE_GATE);
7913                 break;
7914         default:
7915                 break;
7916         }
7917         return 0;
7918 }
7919
7920 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7921 {
7922         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7923         int data;
7924
7925         /* AMD_CG_SUPPORT_GFX_FGCG */
7926         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7927         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
7928                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
7929
7930         /* AMD_CG_SUPPORT_GFX_MGCG */
7931         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7932         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7933                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7934
7935         /* AMD_CG_SUPPORT_GFX_CGCG */
7936         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7937         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7938                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7939
7940         /* AMD_CG_SUPPORT_GFX_CGLS */
7941         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7942                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7943
7944         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7945         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7946         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7947                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7948
7949         /* AMD_CG_SUPPORT_GFX_CP_LS */
7950         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7951         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7952                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7953
7954         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7955         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7956         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7957                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7958
7959         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7960         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7961                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7962 }
7963
7964 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7965 {
7966         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7967 }
7968
7969 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7970 {
7971         struct amdgpu_device *adev = ring->adev;
7972         u64 wptr;
7973
7974         /* XXX check if swapping is necessary on BE */
7975         if (ring->use_doorbell) {
7976                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7977         } else {
7978                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7979                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7980         }
7981
7982         return wptr;
7983 }
7984
7985 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7986 {
7987         struct amdgpu_device *adev = ring->adev;
7988
7989         if (ring->use_doorbell) {
7990                 /* XXX check if swapping is necessary on BE */
7991                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7992                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7993         } else {
7994                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7995                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7996         }
7997 }
7998
7999 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8000 {
8001         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8002 }
8003
8004 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8005 {
8006         u64 wptr;
8007
8008         /* XXX check if swapping is necessary on BE */
8009         if (ring->use_doorbell)
8010                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8011         else
8012                 BUG();
8013         return wptr;
8014 }
8015
8016 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8017 {
8018         struct amdgpu_device *adev = ring->adev;
8019
8020         /* XXX check if swapping is necessary on BE */
8021         if (ring->use_doorbell) {
8022                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8023                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8024         } else {
8025                 BUG(); /* only DOORBELL method supported on gfx10 now */
8026         }
8027 }
8028
8029 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8030 {
8031         struct amdgpu_device *adev = ring->adev;
8032         u32 ref_and_mask, reg_mem_engine;
8033         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8034
8035         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8036                 switch (ring->me) {
8037                 case 1:
8038                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8039                         break;
8040                 case 2:
8041                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8042                         break;
8043                 default:
8044                         return;
8045                 }
8046                 reg_mem_engine = 0;
8047         } else {
8048                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8049                 reg_mem_engine = 1; /* pfp */
8050         }
8051
8052         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8053                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8054                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8055                                ref_and_mask, ref_and_mask, 0x20);
8056 }
8057
8058 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8059                                        struct amdgpu_job *job,
8060                                        struct amdgpu_ib *ib,
8061                                        uint32_t flags)
8062 {
8063         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8064         u32 header, control = 0;
8065
8066         if (ib->flags & AMDGPU_IB_FLAG_CE)
8067                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8068         else
8069                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8070
8071         control |= ib->length_dw | (vmid << 24);
8072
8073         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8074                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8075
8076                 if (flags & AMDGPU_IB_PREEMPTED)
8077                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8078
8079                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8080                         gfx_v10_0_ring_emit_de_meta(ring,
8081                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8082         }
8083
8084         amdgpu_ring_write(ring, header);
8085         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8086         amdgpu_ring_write(ring,
8087 #ifdef __BIG_ENDIAN
8088                 (2 << 0) |
8089 #endif
8090                 lower_32_bits(ib->gpu_addr));
8091         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8092         amdgpu_ring_write(ring, control);
8093 }
8094
8095 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8096                                            struct amdgpu_job *job,
8097                                            struct amdgpu_ib *ib,
8098                                            uint32_t flags)
8099 {
8100         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8101         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8102
8103         /* Currently, there is a high possibility to get wave ID mismatch
8104          * between ME and GDS, leading to a hw deadlock, because ME generates
8105          * different wave IDs than the GDS expects. This situation happens
8106          * randomly when at least 5 compute pipes use GDS ordered append.
8107          * The wave IDs generated by ME are also wrong after suspend/resume.
8108          * Those are probably bugs somewhere else in the kernel driver.
8109          *
8110          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8111          * GDS to 0 for this ring (me/pipe).
8112          */
8113         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8114                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8115                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8116                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8117         }
8118
8119         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8120         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8121         amdgpu_ring_write(ring,
8122 #ifdef __BIG_ENDIAN
8123                                 (2 << 0) |
8124 #endif
8125                                 lower_32_bits(ib->gpu_addr));
8126         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8127         amdgpu_ring_write(ring, control);
8128 }
8129
8130 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8131                                      u64 seq, unsigned flags)
8132 {
8133         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8134         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8135
8136         /* RELEASE_MEM - flush caches, send int */
8137         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8138         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8139                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8140                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8141                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8142                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8143                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8144                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8145         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8146                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8147
8148         /*
8149          * the address should be Qword aligned if 64bit write, Dword
8150          * aligned if only send 32bit data low (discard data high)
8151          */
8152         if (write64bit)
8153                 BUG_ON(addr & 0x7);
8154         else
8155                 BUG_ON(addr & 0x3);
8156         amdgpu_ring_write(ring, lower_32_bits(addr));
8157         amdgpu_ring_write(ring, upper_32_bits(addr));
8158         amdgpu_ring_write(ring, lower_32_bits(seq));
8159         amdgpu_ring_write(ring, upper_32_bits(seq));
8160         amdgpu_ring_write(ring, 0);
8161 }
8162
8163 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8164 {
8165         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8166         uint32_t seq = ring->fence_drv.sync_seq;
8167         uint64_t addr = ring->fence_drv.gpu_addr;
8168
8169         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8170                                upper_32_bits(addr), seq, 0xffffffff, 4);
8171 }
8172
8173 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8174                                          unsigned vmid, uint64_t pd_addr)
8175 {
8176         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8177
8178         /* compute doesn't have PFP */
8179         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8180                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8181                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8182                 amdgpu_ring_write(ring, 0x0);
8183         }
8184 }
8185
8186 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8187                                           u64 seq, unsigned int flags)
8188 {
8189         struct amdgpu_device *adev = ring->adev;
8190
8191         /* we only allocate 32bit for each seq wb address */
8192         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8193
8194         /* write fence seq to the "addr" */
8195         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8196         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8197                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8198         amdgpu_ring_write(ring, lower_32_bits(addr));
8199         amdgpu_ring_write(ring, upper_32_bits(addr));
8200         amdgpu_ring_write(ring, lower_32_bits(seq));
8201
8202         if (flags & AMDGPU_FENCE_FLAG_INT) {
8203                 /* set register to trigger INT */
8204                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8205                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8206                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8207                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8208                 amdgpu_ring_write(ring, 0);
8209                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8210         }
8211 }
8212
8213 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8214 {
8215         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8216         amdgpu_ring_write(ring, 0);
8217 }
8218
8219 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8220                                          uint32_t flags)
8221 {
8222         uint32_t dw2 = 0;
8223
8224         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8225                 gfx_v10_0_ring_emit_ce_meta(ring,
8226                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8227
8228         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8229         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8230                 /* set load_global_config & load_global_uconfig */
8231                 dw2 |= 0x8001;
8232                 /* set load_cs_sh_regs */
8233                 dw2 |= 0x01000000;
8234                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8235                 dw2 |= 0x10002;
8236
8237                 /* set load_ce_ram if preamble presented */
8238                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8239                         dw2 |= 0x10000000;
8240         } else {
8241                 /* still load_ce_ram if this is the first time preamble presented
8242                  * although there is no context switch happens.
8243                  */
8244                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8245                         dw2 |= 0x10000000;
8246         }
8247
8248         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8249         amdgpu_ring_write(ring, dw2);
8250         amdgpu_ring_write(ring, 0);
8251 }
8252
8253 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8254 {
8255         unsigned ret;
8256
8257         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8258         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8259         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8260         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8261         ret = ring->wptr & ring->buf_mask;
8262         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8263
8264         return ret;
8265 }
8266
8267 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8268 {
8269         unsigned cur;
8270         BUG_ON(offset > ring->buf_mask);
8271         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8272
8273         cur = (ring->wptr - 1) & ring->buf_mask;
8274         if (likely(cur > offset))
8275                 ring->ring[offset] = cur - offset;
8276         else
8277                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8278 }
8279
8280 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8281 {
8282         int i, r = 0;
8283         struct amdgpu_device *adev = ring->adev;
8284         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8285         struct amdgpu_ring *kiq_ring = &kiq->ring;
8286         unsigned long flags;
8287
8288         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8289                 return -EINVAL;
8290
8291         spin_lock_irqsave(&kiq->ring_lock, flags);
8292
8293         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8294                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8295                 return -ENOMEM;
8296         }
8297
8298         /* assert preemption condition */
8299         amdgpu_ring_set_preempt_cond_exec(ring, false);
8300
8301         /* assert IB preemption, emit the trailing fence */
8302         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8303                                    ring->trail_fence_gpu_addr,
8304                                    ++ring->trail_seq);
8305         amdgpu_ring_commit(kiq_ring);
8306
8307         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8308
8309         /* poll the trailing fence */
8310         for (i = 0; i < adev->usec_timeout; i++) {
8311                 if (ring->trail_seq ==
8312                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8313                         break;
8314                 udelay(1);
8315         }
8316
8317         if (i >= adev->usec_timeout) {
8318                 r = -EINVAL;
8319                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8320         }
8321
8322         /* deassert preemption condition */
8323         amdgpu_ring_set_preempt_cond_exec(ring, true);
8324         return r;
8325 }
8326
8327 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8328 {
8329         struct amdgpu_device *adev = ring->adev;
8330         struct v10_ce_ib_state ce_payload = {0};
8331         uint64_t csa_addr;
8332         int cnt;
8333
8334         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8335         csa_addr = amdgpu_csa_vaddr(ring->adev);
8336
8337         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8338         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8339                                  WRITE_DATA_DST_SEL(8) |
8340                                  WR_CONFIRM) |
8341                                  WRITE_DATA_CACHE_POLICY(0));
8342         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8343                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8344         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8345                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8346
8347         if (resume)
8348                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8349                                            offsetof(struct v10_gfx_meta_data,
8350                                                     ce_payload),
8351                                            sizeof(ce_payload) >> 2);
8352         else
8353                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8354                                            sizeof(ce_payload) >> 2);
8355 }
8356
8357 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8358 {
8359         struct amdgpu_device *adev = ring->adev;
8360         struct v10_de_ib_state de_payload = {0};
8361         uint64_t csa_addr, gds_addr;
8362         int cnt;
8363
8364         csa_addr = amdgpu_csa_vaddr(ring->adev);
8365         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8366                          PAGE_SIZE);
8367         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8368         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8369
8370         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8371         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8372         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8373                                  WRITE_DATA_DST_SEL(8) |
8374                                  WR_CONFIRM) |
8375                                  WRITE_DATA_CACHE_POLICY(0));
8376         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8377                               offsetof(struct v10_gfx_meta_data, de_payload)));
8378         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8379                               offsetof(struct v10_gfx_meta_data, de_payload)));
8380
8381         if (resume)
8382                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8383                                            offsetof(struct v10_gfx_meta_data,
8384                                                     de_payload),
8385                                            sizeof(de_payload) >> 2);
8386         else
8387                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8388                                            sizeof(de_payload) >> 2);
8389 }
8390
8391 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8392                                     bool secure)
8393 {
8394         uint32_t v = secure ? FRAME_TMZ : 0;
8395
8396         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8397         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8398 }
8399
8400 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8401                                      uint32_t reg_val_offs)
8402 {
8403         struct amdgpu_device *adev = ring->adev;
8404
8405         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8406         amdgpu_ring_write(ring, 0 |     /* src: register*/
8407                                 (5 << 8) |      /* dst: memory */
8408                                 (1 << 20));     /* write confirm */
8409         amdgpu_ring_write(ring, reg);
8410         amdgpu_ring_write(ring, 0);
8411         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8412                                 reg_val_offs * 4));
8413         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8414                                 reg_val_offs * 4));
8415 }
8416
8417 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8418                                    uint32_t val)
8419 {
8420         uint32_t cmd = 0;
8421
8422         switch (ring->funcs->type) {
8423         case AMDGPU_RING_TYPE_GFX:
8424                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8425                 break;
8426         case AMDGPU_RING_TYPE_KIQ:
8427                 cmd = (1 << 16); /* no inc addr */
8428                 break;
8429         default:
8430                 cmd = WR_CONFIRM;
8431                 break;
8432         }
8433         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8434         amdgpu_ring_write(ring, cmd);
8435         amdgpu_ring_write(ring, reg);
8436         amdgpu_ring_write(ring, 0);
8437         amdgpu_ring_write(ring, val);
8438 }
8439
8440 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8441                                         uint32_t val, uint32_t mask)
8442 {
8443         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8444 }
8445
8446 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8447                                                    uint32_t reg0, uint32_t reg1,
8448                                                    uint32_t ref, uint32_t mask)
8449 {
8450         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8451         struct amdgpu_device *adev = ring->adev;
8452         bool fw_version_ok = false;
8453
8454         fw_version_ok = adev->gfx.cp_fw_write_wait;
8455
8456         if (fw_version_ok)
8457                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8458                                        ref, mask, 0x20);
8459         else
8460                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8461                                                            ref, mask);
8462 }
8463
8464 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8465                                          unsigned vmid)
8466 {
8467         struct amdgpu_device *adev = ring->adev;
8468         uint32_t value = 0;
8469
8470         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8471         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8472         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8473         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8474         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8475 }
8476
8477 static void
8478 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8479                                       uint32_t me, uint32_t pipe,
8480                                       enum amdgpu_interrupt_state state)
8481 {
8482         uint32_t cp_int_cntl, cp_int_cntl_reg;
8483
8484         if (!me) {
8485                 switch (pipe) {
8486                 case 0:
8487                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8488                         break;
8489                 case 1:
8490                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8491                         break;
8492                 default:
8493                         DRM_DEBUG("invalid pipe %d\n", pipe);
8494                         return;
8495                 }
8496         } else {
8497                 DRM_DEBUG("invalid me %d\n", me);
8498                 return;
8499         }
8500
8501         switch (state) {
8502         case AMDGPU_IRQ_STATE_DISABLE:
8503                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8504                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8505                                             TIME_STAMP_INT_ENABLE, 0);
8506                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8507                 break;
8508         case AMDGPU_IRQ_STATE_ENABLE:
8509                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8510                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8511                                             TIME_STAMP_INT_ENABLE, 1);
8512                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8513                 break;
8514         default:
8515                 break;
8516         }
8517 }
8518
8519 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8520                                                      int me, int pipe,
8521                                                      enum amdgpu_interrupt_state state)
8522 {
8523         u32 mec_int_cntl, mec_int_cntl_reg;
8524
8525         /*
8526          * amdgpu controls only the first MEC. That's why this function only
8527          * handles the setting of interrupts for this specific MEC. All other
8528          * pipes' interrupts are set by amdkfd.
8529          */
8530
8531         if (me == 1) {
8532                 switch (pipe) {
8533                 case 0:
8534                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8535                         break;
8536                 case 1:
8537                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8538                         break;
8539                 case 2:
8540                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8541                         break;
8542                 case 3:
8543                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8544                         break;
8545                 default:
8546                         DRM_DEBUG("invalid pipe %d\n", pipe);
8547                         return;
8548                 }
8549         } else {
8550                 DRM_DEBUG("invalid me %d\n", me);
8551                 return;
8552         }
8553
8554         switch (state) {
8555         case AMDGPU_IRQ_STATE_DISABLE:
8556                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8557                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8558                                              TIME_STAMP_INT_ENABLE, 0);
8559                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8560                 break;
8561         case AMDGPU_IRQ_STATE_ENABLE:
8562                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8563                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8564                                              TIME_STAMP_INT_ENABLE, 1);
8565                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8566                 break;
8567         default:
8568                 break;
8569         }
8570 }
8571
8572 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8573                                             struct amdgpu_irq_src *src,
8574                                             unsigned type,
8575                                             enum amdgpu_interrupt_state state)
8576 {
8577         switch (type) {
8578         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8579                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8580                 break;
8581         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8582                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8583                 break;
8584         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8585                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8586                 break;
8587         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8588                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8589                 break;
8590         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8591                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8592                 break;
8593         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8594                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8595                 break;
8596         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8597                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8598                 break;
8599         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8600                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8601                 break;
8602         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8603                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8604                 break;
8605         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8606                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8607                 break;
8608         default:
8609                 break;
8610         }
8611         return 0;
8612 }
8613
8614 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8615                              struct amdgpu_irq_src *source,
8616                              struct amdgpu_iv_entry *entry)
8617 {
8618         int i;
8619         u8 me_id, pipe_id, queue_id;
8620         struct amdgpu_ring *ring;
8621
8622         DRM_DEBUG("IH: CP EOP\n");
8623         me_id = (entry->ring_id & 0x0c) >> 2;
8624         pipe_id = (entry->ring_id & 0x03) >> 0;
8625         queue_id = (entry->ring_id & 0x70) >> 4;
8626
8627         switch (me_id) {
8628         case 0:
8629                 if (pipe_id == 0)
8630                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8631                 else
8632                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8633                 break;
8634         case 1:
8635         case 2:
8636                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8637                         ring = &adev->gfx.compute_ring[i];
8638                         /* Per-queue interrupt is supported for MEC starting from VI.
8639                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8640                           */
8641                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8642                                 amdgpu_fence_process(ring);
8643                 }
8644                 break;
8645         }
8646         return 0;
8647 }
8648
8649 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8650                                               struct amdgpu_irq_src *source,
8651                                               unsigned type,
8652                                               enum amdgpu_interrupt_state state)
8653 {
8654         switch (state) {
8655         case AMDGPU_IRQ_STATE_DISABLE:
8656         case AMDGPU_IRQ_STATE_ENABLE:
8657                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8658                                PRIV_REG_INT_ENABLE,
8659                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8660                 break;
8661         default:
8662                 break;
8663         }
8664
8665         return 0;
8666 }
8667
8668 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8669                                                struct amdgpu_irq_src *source,
8670                                                unsigned type,
8671                                                enum amdgpu_interrupt_state state)
8672 {
8673         switch (state) {
8674         case AMDGPU_IRQ_STATE_DISABLE:
8675         case AMDGPU_IRQ_STATE_ENABLE:
8676                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8677                                PRIV_INSTR_INT_ENABLE,
8678                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8679                 break;
8680         default:
8681                 break;
8682         }
8683
8684         return 0;
8685 }
8686
8687 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8688                                         struct amdgpu_iv_entry *entry)
8689 {
8690         u8 me_id, pipe_id, queue_id;
8691         struct amdgpu_ring *ring;
8692         int i;
8693
8694         me_id = (entry->ring_id & 0x0c) >> 2;
8695         pipe_id = (entry->ring_id & 0x03) >> 0;
8696         queue_id = (entry->ring_id & 0x70) >> 4;
8697
8698         switch (me_id) {
8699         case 0:
8700                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8701                         ring = &adev->gfx.gfx_ring[i];
8702                         /* we only enabled 1 gfx queue per pipe for now */
8703                         if (ring->me == me_id && ring->pipe == pipe_id)
8704                                 drm_sched_fault(&ring->sched);
8705                 }
8706                 break;
8707         case 1:
8708         case 2:
8709                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8710                         ring = &adev->gfx.compute_ring[i];
8711                         if (ring->me == me_id && ring->pipe == pipe_id &&
8712                             ring->queue == queue_id)
8713                                 drm_sched_fault(&ring->sched);
8714                 }
8715                 break;
8716         default:
8717                 BUG();
8718         }
8719 }
8720
8721 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8722                                   struct amdgpu_irq_src *source,
8723                                   struct amdgpu_iv_entry *entry)
8724 {
8725         DRM_ERROR("Illegal register access in command stream\n");
8726         gfx_v10_0_handle_priv_fault(adev, entry);
8727         return 0;
8728 }
8729
8730 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8731                                    struct amdgpu_irq_src *source,
8732                                    struct amdgpu_iv_entry *entry)
8733 {
8734         DRM_ERROR("Illegal instruction in command stream\n");
8735         gfx_v10_0_handle_priv_fault(adev, entry);
8736         return 0;
8737 }
8738
8739 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8740                                              struct amdgpu_irq_src *src,
8741                                              unsigned int type,
8742                                              enum amdgpu_interrupt_state state)
8743 {
8744         uint32_t tmp, target;
8745         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8746
8747         if (ring->me == 1)
8748                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8749         else
8750                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8751         target += ring->pipe;
8752
8753         switch (type) {
8754         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8755                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8756                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8757                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8758                                             GENERIC2_INT_ENABLE, 0);
8759                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8760
8761                         tmp = RREG32(target);
8762                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8763                                             GENERIC2_INT_ENABLE, 0);
8764                         WREG32(target, tmp);
8765                 } else {
8766                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8767                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8768                                             GENERIC2_INT_ENABLE, 1);
8769                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8770
8771                         tmp = RREG32(target);
8772                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8773                                             GENERIC2_INT_ENABLE, 1);
8774                         WREG32(target, tmp);
8775                 }
8776                 break;
8777         default:
8778                 BUG(); /* kiq only support GENERIC2_INT now */
8779                 break;
8780         }
8781         return 0;
8782 }
8783
8784 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8785                              struct amdgpu_irq_src *source,
8786                              struct amdgpu_iv_entry *entry)
8787 {
8788         u8 me_id, pipe_id, queue_id;
8789         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8790
8791         me_id = (entry->ring_id & 0x0c) >> 2;
8792         pipe_id = (entry->ring_id & 0x03) >> 0;
8793         queue_id = (entry->ring_id & 0x70) >> 4;
8794         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8795                    me_id, pipe_id, queue_id);
8796
8797         amdgpu_fence_process(ring);
8798         return 0;
8799 }
8800
8801 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8802 {
8803         const unsigned int gcr_cntl =
8804                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8805                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8806                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8807                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8808                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8809                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8810                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8811                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8812
8813         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8814         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8815         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8816         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8817         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8818         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8819         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8820         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8821         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8822 }
8823
8824 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8825         .name = "gfx_v10_0",
8826         .early_init = gfx_v10_0_early_init,
8827         .late_init = gfx_v10_0_late_init,
8828         .sw_init = gfx_v10_0_sw_init,
8829         .sw_fini = gfx_v10_0_sw_fini,
8830         .hw_init = gfx_v10_0_hw_init,
8831         .hw_fini = gfx_v10_0_hw_fini,
8832         .suspend = gfx_v10_0_suspend,
8833         .resume = gfx_v10_0_resume,
8834         .is_idle = gfx_v10_0_is_idle,
8835         .wait_for_idle = gfx_v10_0_wait_for_idle,
8836         .soft_reset = gfx_v10_0_soft_reset,
8837         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8838         .set_powergating_state = gfx_v10_0_set_powergating_state,
8839         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8840 };
8841
8842 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8843         .type = AMDGPU_RING_TYPE_GFX,
8844         .align_mask = 0xff,
8845         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8846         .support_64bit_ptrs = true,
8847         .vmhub = AMDGPU_GFXHUB_0,
8848         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8849         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8850         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8851         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8852                 5 + /* COND_EXEC */
8853                 7 + /* PIPELINE_SYNC */
8854                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8855                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8856                 2 + /* VM_FLUSH */
8857                 8 + /* FENCE for VM_FLUSH */
8858                 20 + /* GDS switch */
8859                 4 + /* double SWITCH_BUFFER,
8860                      * the first COND_EXEC jump to the place
8861                      * just prior to this double SWITCH_BUFFER
8862                      */
8863                 5 + /* COND_EXEC */
8864                 7 + /* HDP_flush */
8865                 4 + /* VGT_flush */
8866                 14 + /* CE_META */
8867                 31 + /* DE_META */
8868                 3 + /* CNTX_CTRL */
8869                 5 + /* HDP_INVL */
8870                 8 + 8 + /* FENCE x2 */
8871                 2 + /* SWITCH_BUFFER */
8872                 8, /* gfx_v10_0_emit_mem_sync */
8873         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8874         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8875         .emit_fence = gfx_v10_0_ring_emit_fence,
8876         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8877         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8878         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8879         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8880         .test_ring = gfx_v10_0_ring_test_ring,
8881         .test_ib = gfx_v10_0_ring_test_ib,
8882         .insert_nop = amdgpu_ring_insert_nop,
8883         .pad_ib = amdgpu_ring_generic_pad_ib,
8884         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8885         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8886         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8887         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8888         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8889         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8890         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8891         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8892         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8893         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8894         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8895 };
8896
8897 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8898         .type = AMDGPU_RING_TYPE_COMPUTE,
8899         .align_mask = 0xff,
8900         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8901         .support_64bit_ptrs = true,
8902         .vmhub = AMDGPU_GFXHUB_0,
8903         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8904         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8905         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8906         .emit_frame_size =
8907                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8908                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8909                 5 + /* hdp invalidate */
8910                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8911                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8912                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8913                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8914                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8915                 8, /* gfx_v10_0_emit_mem_sync */
8916         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8917         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8918         .emit_fence = gfx_v10_0_ring_emit_fence,
8919         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8920         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8921         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8922         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8923         .test_ring = gfx_v10_0_ring_test_ring,
8924         .test_ib = gfx_v10_0_ring_test_ib,
8925         .insert_nop = amdgpu_ring_insert_nop,
8926         .pad_ib = amdgpu_ring_generic_pad_ib,
8927         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8928         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8929         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8930         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8931 };
8932
8933 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8934         .type = AMDGPU_RING_TYPE_KIQ,
8935         .align_mask = 0xff,
8936         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8937         .support_64bit_ptrs = true,
8938         .vmhub = AMDGPU_GFXHUB_0,
8939         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8940         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8941         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8942         .emit_frame_size =
8943                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8944                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8945                 5 + /*hdp invalidate */
8946                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8947                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8948                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8949                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8950                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8951         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8952         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8953         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8954         .test_ring = gfx_v10_0_ring_test_ring,
8955         .test_ib = gfx_v10_0_ring_test_ib,
8956         .insert_nop = amdgpu_ring_insert_nop,
8957         .pad_ib = amdgpu_ring_generic_pad_ib,
8958         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8959         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8960         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8961         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8962 };
8963
8964 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8965 {
8966         int i;
8967
8968         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8969
8970         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8971                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8972
8973         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8974                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8975 }
8976
8977 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8978         .set = gfx_v10_0_set_eop_interrupt_state,
8979         .process = gfx_v10_0_eop_irq,
8980 };
8981
8982 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8983         .set = gfx_v10_0_set_priv_reg_fault_state,
8984         .process = gfx_v10_0_priv_reg_irq,
8985 };
8986
8987 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8988         .set = gfx_v10_0_set_priv_inst_fault_state,
8989         .process = gfx_v10_0_priv_inst_irq,
8990 };
8991
8992 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8993         .set = gfx_v10_0_kiq_set_interrupt_state,
8994         .process = gfx_v10_0_kiq_irq,
8995 };
8996
8997 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8998 {
8999         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9000         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9001
9002         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9003         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9004
9005         adev->gfx.priv_reg_irq.num_types = 1;
9006         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9007
9008         adev->gfx.priv_inst_irq.num_types = 1;
9009         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9010 }
9011
9012 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9013 {
9014         switch (adev->asic_type) {
9015         case CHIP_NAVI10:
9016         case CHIP_NAVI14:
9017         case CHIP_SIENNA_CICHLID:
9018         case CHIP_NAVY_FLOUNDER:
9019         case CHIP_VANGOGH:
9020         case CHIP_DIMGREY_CAVEFISH:
9021                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9022                 break;
9023         case CHIP_NAVI12:
9024                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9025                 break;
9026         default:
9027                 break;
9028         }
9029 }
9030
9031 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9032 {
9033         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9034                             adev->gfx.config.max_sh_per_se *
9035                             adev->gfx.config.max_shader_engines;
9036
9037         adev->gds.gds_size = 0x10000;
9038         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9039         adev->gds.gws_size = 64;
9040         adev->gds.oa_size = 16;
9041 }
9042
9043 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9044                                                           u32 bitmap)
9045 {
9046         u32 data;
9047
9048         if (!bitmap)
9049                 return;
9050
9051         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9052         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9053
9054         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9055 }
9056
9057 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9058 {
9059         u32 data, wgp_bitmask;
9060         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9061         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9062
9063         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9064         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9065
9066         wgp_bitmask =
9067                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9068
9069         return (~data) & wgp_bitmask;
9070 }
9071
9072 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9073 {
9074         u32 wgp_idx, wgp_active_bitmap;
9075         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9076
9077         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9078         cu_active_bitmap = 0;
9079
9080         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9081                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9082                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9083                 if (wgp_active_bitmap & (1 << wgp_idx))
9084                         cu_active_bitmap |= cu_bitmap_per_wgp;
9085         }
9086
9087         return cu_active_bitmap;
9088 }
9089
9090 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9091                                  struct amdgpu_cu_info *cu_info)
9092 {
9093         int i, j, k, counter, active_cu_number = 0;
9094         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9095         unsigned disable_masks[4 * 2];
9096
9097         if (!adev || !cu_info)
9098                 return -EINVAL;
9099
9100         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9101
9102         mutex_lock(&adev->grbm_idx_mutex);
9103         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9104                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9105                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9106                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9107                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9108                                 continue;
9109                         mask = 1;
9110                         ao_bitmap = 0;
9111                         counter = 0;
9112                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9113                         if (i < 4 && j < 2)
9114                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9115                                         adev, disable_masks[i * 2 + j]);
9116                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9117                         cu_info->bitmap[i][j] = bitmap;
9118
9119                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9120                                 if (bitmap & mask) {
9121                                         if (counter < adev->gfx.config.max_cu_per_sh)
9122                                                 ao_bitmap |= mask;
9123                                         counter++;
9124                                 }
9125                                 mask <<= 1;
9126                         }
9127                         active_cu_number += counter;
9128                         if (i < 2 && j < 2)
9129                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9130                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9131                 }
9132         }
9133         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9134         mutex_unlock(&adev->grbm_idx_mutex);
9135
9136         cu_info->number = active_cu_number;
9137         cu_info->ao_cu_mask = ao_cu_mask;
9138         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9139
9140         return 0;
9141 }
9142
9143 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9144 {
9145         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9146
9147         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9148         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9149         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9150
9151         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9152         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9153         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9154
9155         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9156                                                 adev->gfx.config.max_shader_engines);
9157         disabled_sa = efuse_setting | vbios_setting;
9158         disabled_sa &= max_sa_mask;
9159
9160         return disabled_sa;
9161 }
9162
9163 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9164 {
9165         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9166         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9167
9168         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9169
9170         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9171         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9172         max_shader_engines = adev->gfx.config.max_shader_engines;
9173
9174         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9175                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9176                 disabled_sa_per_se &= max_sa_per_se_mask;
9177                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9178                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9179                         break;
9180                 }
9181         }
9182 }
9183
9184 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9185 {
9186         .type = AMD_IP_BLOCK_TYPE_GFX,
9187         .major = 10,
9188         .minor = 0,
9189         .rev = 0,
9190         .funcs = &gfx_v10_0_ip_funcs,
9191 };