drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31 #include "mmsch_v1_0.h"
  32
  33 #include "uvd/uvd_7_0_offset.h"
  34 #include "uvd/uvd_7_0_sh_mask.h"
  35 #include "vce/vce_4_0_offset.h"
  36 #include "vce/vce_4_0_default.h"
  37 #include "vce/vce_4_0_sh_mask.h"
  38 #include "nbif/nbif_6_1_offset.h"
  39 #include "hdp/hdp_4_0_offset.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "mmhub/mmhub_1_0_sh_mask.h"
  42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
  43
  44 #define mmUVD_PG0_CC_UVD_HARVESTING                                                                    0x00c7
  45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX                                                           1
  46 //UVD_PG0_CC_UVD_HARVESTING
  47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                         0x1
  48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                           0x00000002L
  49
  50 #define UVD7_MAX_HW_INSTANCES_VEGA20                    2
  51
  52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static int uvd_v7_0_start(struct amdgpu_device *adev);
  56 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  58
  59 static int amdgpu_ih_clientid_uvds[] = {
  60         SOC15_IH_CLIENTID_UVD,
  61         SOC15_IH_CLIENTID_UVD1
  62 };
  63
  64 /**
  65  * uvd_v7_0_ring_get_rptr - get read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware read pointer
  70  */
  71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
  76 }
  77
  78 /**
  79  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Returns the current hardware enc read pointer
  84  */
  85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
  90                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
  91         else
  92                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
  93 }
  94
  95 /**
  96  * uvd_v7_0_ring_get_wptr - get write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware write pointer
 101  */
 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
 107 }
 108
 109 /**
 110  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
 111  *
 112  * @ring: amdgpu_ring pointer
 113  *
 114  * Returns the current hardware enc write pointer
 115  */
 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119
 120         if (ring->use_doorbell)
 121                 return adev->wb.wb[ring->wptr_offs];
 122
 123         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 124                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
 125         else
 126                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 127 }
 128
 129 /**
 130  * uvd_v7_0_ring_set_wptr - set write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the write pointer to the hardware
 135  */
 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 141 }
 142
 143 /**
 144  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 145  *
 146  * @ring: amdgpu_ring pointer
 147  *
 148  * Commits the enc write pointer to the hardware
 149  */
 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 151 {
 152         struct amdgpu_device *adev = ring->adev;
 153
 154         if (ring->use_doorbell) {
 155                 /* XXX check if swapping is necessary on BE */
 156                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 157                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 158                 return;
 159         }
 160
 161         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 162                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
 163                         lower_32_bits(ring->wptr));
 164         else
 165                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
 166                         lower_32_bits(ring->wptr));
 167 }
 168
 169 /**
 170  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 171  *
 172  * @ring: the engine to test on
 173  *
 174  */
 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 179         unsigned i;
 180         int r;
 181
 182         if (amdgpu_sriov_vf(adev))
 183                 return 0;
 184
 185         r = amdgpu_ring_alloc(ring, 16);
 186         if (r) {
 187                 DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n",
 188                           ring->me, ring->idx, r);
 189                 return r;
 190         }
 191         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 192         amdgpu_ring_commit(ring);
 193
 194         for (i = 0; i < adev->usec_timeout; i++) {
 195                 if (amdgpu_ring_get_rptr(ring) != rptr)
 196                         break;
 197                 DRM_UDELAY(1);
 198         }
 199
 200         if (i < adev->usec_timeout) {
 201                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
 202                          ring->me, ring->idx, i);
 203         } else {
 204                 DRM_ERROR("amdgpu: (%d)ring %d test failed\n",
 205                           ring->me, ring->idx);
 206                 r = -ETIMEDOUT;
 207         }
 208
 209         return r;
 210 }
 211
 212 /**
 213  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 214  *
 215  * @adev: amdgpu_device pointer
 216  * @ring: ring we should submit the msg to
 217  * @handle: session handle to use
 218  * @fence: optional fence to return
 219  *
 220  * Open up a stream for HW test
 221  */
 222 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 223                                        struct dma_fence **fence)
 224 {
 225         const unsigned ib_size_dw = 16;
 226         struct amdgpu_job *job;
 227         struct amdgpu_ib *ib;
 228         struct dma_fence *f = NULL;
 229         uint64_t dummy;
 230         int i, r;
 231
 232         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 233         if (r)
 234                 return r;
 235
 236         ib = &job->ibs[0];
 237         dummy = ib->gpu_addr + 1024;
 238
 239         ib->length_dw = 0;
 240         ib->ptr[ib->length_dw++] = 0x00000018;
 241         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 242         ib->ptr[ib->length_dw++] = handle;
 243         ib->ptr[ib->length_dw++] = 0x00000000;
 244         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 245         ib->ptr[ib->length_dw++] = dummy;
 246
 247         ib->ptr[ib->length_dw++] = 0x00000014;
 248         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 249         ib->ptr[ib->length_dw++] = 0x0000001c;
 250         ib->ptr[ib->length_dw++] = 0x00000000;
 251         ib->ptr[ib->length_dw++] = 0x00000000;
 252
 253         ib->ptr[ib->length_dw++] = 0x00000008;
 254         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 255
 256         for (i = ib->length_dw; i < ib_size_dw; ++i)
 257                 ib->ptr[i] = 0x0;
 258
 259         r = amdgpu_job_submit_direct(job, ring, &f);
 260         if (r)
 261                 goto err;
 262
 263         if (fence)
 264                 *fence = dma_fence_get(f);
 265         dma_fence_put(f);
 266         return 0;
 267
 268 err:
 269         amdgpu_job_free(job);
 270         return r;
 271 }
 272
 273 /**
 274  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 275  *
 276  * @adev: amdgpu_device pointer
 277  * @ring: ring we should submit the msg to
 278  * @handle: session handle to use
 279  * @fence: optional fence to return
 280  *
 281  * Close up a stream for HW test or if userspace failed to do so
 282  */
 283 int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 284                                  bool direct, struct dma_fence **fence)
 285 {
 286         const unsigned ib_size_dw = 16;
 287         struct amdgpu_job *job;
 288         struct amdgpu_ib *ib;
 289         struct dma_fence *f = NULL;
 290         uint64_t dummy;
 291         int i, r;
 292
 293         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 294         if (r)
 295                 return r;
 296
 297         ib = &job->ibs[0];
 298         dummy = ib->gpu_addr + 1024;
 299
 300         ib->length_dw = 0;
 301         ib->ptr[ib->length_dw++] = 0x00000018;
 302         ib->ptr[ib->length_dw++] = 0x00000001;
 303         ib->ptr[ib->length_dw++] = handle;
 304         ib->ptr[ib->length_dw++] = 0x00000000;
 305         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 306         ib->ptr[ib->length_dw++] = dummy;
 307
 308         ib->ptr[ib->length_dw++] = 0x00000014;
 309         ib->ptr[ib->length_dw++] = 0x00000002;
 310         ib->ptr[ib->length_dw++] = 0x0000001c;
 311         ib->ptr[ib->length_dw++] = 0x00000000;
 312         ib->ptr[ib->length_dw++] = 0x00000000;
 313
 314         ib->ptr[ib->length_dw++] = 0x00000008;
 315         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 316
 317         for (i = ib->length_dw; i < ib_size_dw; ++i)
 318                 ib->ptr[i] = 0x0;
 319
 320         if (direct)
 321                 r = amdgpu_job_submit_direct(job, ring, &f);
 322         else
 323                 r = amdgpu_job_submit(job, &ring->adev->vce.entity,
 324                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 325         if (r)
 326                 goto err;
 327
 328         if (fence)
 329                 *fence = dma_fence_get(f);
 330         dma_fence_put(f);
 331         return 0;
 332
 333 err:
 334         amdgpu_job_free(job);
 335         return r;
 336 }
 337
 338 /**
 339  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 340  *
 341  * @ring: the engine to test on
 342  *
 343  */
 344 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 345 {
 346         struct dma_fence *fence = NULL;
 347         long r;
 348
 349         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 350         if (r) {
 351                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r);
 352                 goto error;
 353         }
 354
 355         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, true, &fence);
 356         if (r) {
 357                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r);
 358                 goto error;
 359         }
 360
 361         r = dma_fence_wait_timeout(fence, false, timeout);
 362         if (r == 0) {
 363                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me);
 364                 r = -ETIMEDOUT;
 365         } else if (r < 0) {
 366                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r);
 367         } else {
 368                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx);
 369                 r = 0;
 370         }
 371 error:
 372         dma_fence_put(fence);
 373         return r;
 374 }
 375
 376 static int uvd_v7_0_early_init(void *handle)
 377 {
 378         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 379
 380         if (adev->asic_type == CHIP_VEGA20) {
 381                 u32 harvest;
 382                 int i;
 383
 384                 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
 385                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 386                         harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);
 387                         if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) {
 388                                 adev->uvd.harvest_config |= 1 << i;
 389                         }
 390                 }
 391                 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |
 392                                                  AMDGPU_UVD_HARVEST_UVD1))
 393                         /* both instances are harvested, disable the block */
 394                         return -ENOENT;
 395         } else {
 396                 adev->uvd.num_uvd_inst = 1;
 397         }
 398
 399         if (amdgpu_sriov_vf(adev))
 400                 adev->uvd.num_enc_rings = 1;
 401         else
 402                 adev->uvd.num_enc_rings = 2;
 403         uvd_v7_0_set_ring_funcs(adev);
 404         uvd_v7_0_set_enc_ring_funcs(adev);
 405         uvd_v7_0_set_irq_funcs(adev);
 406
 407         return 0;
 408 }
 409
 410 static int uvd_v7_0_sw_init(void *handle)
 411 {
 412         struct amdgpu_ring *ring;
 413         int i, j, r;
 414         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 415
 416         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 417                 if (adev->uvd.harvest_config & (1 << j))
 418                         continue;
 419                 /* UVD TRAP */
 420                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
 421                 if (r)
 422                         return r;
 423
 424                 /* UVD ENC TRAP */
 425                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 426                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
 427                         if (r)
 428                                 return r;
 429                 }
 430         }
 431
 432         r = amdgpu_uvd_sw_init(adev);
 433         if (r)
 434                 return r;
 435
 436         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 437                 const struct common_firmware_header *hdr;
 438                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 439                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 440                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 441                 adev->firmware.fw_size +=
 442                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 443                 DRM_INFO("PSP loading UVD firmware\n");
 444         }
 445
 446         r = amdgpu_uvd_resume(adev);
 447         if (r)
 448                 return r;
 449
 450         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 451                 if (adev->uvd.harvest_config & (1 << j))
 452                         continue;
 453                 if (!amdgpu_sriov_vf(adev)) {
 454                         ring = &adev->uvd.inst[j].ring;
 455                         sprintf(ring->name, "uvd<%d>", j);
 456                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 457                         if (r)
 458                                 return r;
 459                 }
 460
 461                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 462                         ring = &adev->uvd.inst[j].ring_enc[i];
 463                         sprintf(ring->name, "uvd_enc%d<%d>", i, j);
 464                         if (amdgpu_sriov_vf(adev)) {
 465                                 ring->use_doorbell = true;
 466
 467                                 /* currently only use the first enconding ring for
 468                                  * sriov, so set unused location for other unused rings.
 469                                  */
 470                                 if (i == 0)
 471                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 472                                 else
 473                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
 474                         }
 475                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 476                         if (r)
 477                                 return r;
 478                 }
 479         }
 480
 481         r = amdgpu_virt_alloc_mm_table(adev);
 482         if (r)
 483                 return r;
 484
 485         return r;
 486 }
 487
 488 static int uvd_v7_0_sw_fini(void *handle)
 489 {
 490         int i, j, r;
 491         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 492
 493         amdgpu_virt_free_mm_table(adev);
 494
 495         r = amdgpu_uvd_suspend(adev);
 496         if (r)
 497                 return r;
 498
 499         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 500                 if (adev->uvd.harvest_config & (1 << j))
 501                         continue;
 502                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 503                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 504         }
 505         return amdgpu_uvd_sw_fini(adev);
 506 }
 507
 508 /**
 509  * uvd_v7_0_hw_init - start and test UVD block
 510  *
 511  * @adev: amdgpu_device pointer
 512  *
 513  * Initialize the hardware, boot up the VCPU and do some testing
 514  */
 515 static int uvd_v7_0_hw_init(void *handle)
 516 {
 517         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 518         struct amdgpu_ring *ring;
 519         uint32_t tmp;
 520         int i, j, r;
 521
 522         if (amdgpu_sriov_vf(adev))
 523                 r = uvd_v7_0_sriov_start(adev);
 524         else
 525                 r = uvd_v7_0_start(adev);
 526         if (r)
 527                 goto done;
 528
 529         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 530                 if (adev->uvd.harvest_config & (1 << j))
 531                         continue;
 532                 ring = &adev->uvd.inst[j].ring;
 533
 534                 if (!amdgpu_sriov_vf(adev)) {
 535                         ring->ready = true;
 536                         r = amdgpu_ring_test_ring(ring);
 537                         if (r) {
 538                                 ring->ready = false;
 539                                 goto done;
 540                         }
 541
 542                         r = amdgpu_ring_alloc(ring, 10);
 543                         if (r) {
 544                                 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
 545                                 goto done;
 546                         }
 547
 548                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 549                                 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 550                         amdgpu_ring_write(ring, tmp);
 551                         amdgpu_ring_write(ring, 0xFFFFF);
 552
 553                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 554                                 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 555                         amdgpu_ring_write(ring, tmp);
 556                         amdgpu_ring_write(ring, 0xFFFFF);
 557
 558                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 559                                 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 560                         amdgpu_ring_write(ring, tmp);
 561                         amdgpu_ring_write(ring, 0xFFFFF);
 562
 563                         /* Clear timeout status bits */
 564                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 565                                 mmUVD_SEMA_TIMEOUT_STATUS), 0));
 566                         amdgpu_ring_write(ring, 0x8);
 567
 568                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 569                                 mmUVD_SEMA_CNTL), 0));
 570                         amdgpu_ring_write(ring, 3);
 571
 572                         amdgpu_ring_commit(ring);
 573                 }
 574
 575                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 576                         ring = &adev->uvd.inst[j].ring_enc[i];
 577                         ring->ready = true;
 578                         r = amdgpu_ring_test_ring(ring);
 579                         if (r) {
 580                                 ring->ready = false;
 581                                 goto done;
 582                         }
 583                 }
 584         }
 585 done:
 586         if (!r)
 587                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 588
 589         return r;
 590 }
 591
 592 /**
 593  * uvd_v7_0_hw_fini - stop the hardware block
 594  *
 595  * @adev: amdgpu_device pointer
 596  *
 597  * Stop the UVD block, mark ring as not ready any more
 598  */
 599 static int uvd_v7_0_hw_fini(void *handle)
 600 {
 601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 602         int i;
 603
 604         if (!amdgpu_sriov_vf(adev))
 605                 uvd_v7_0_stop(adev);
 606         else {
 607                 /* full access mode, so don't touch any UVD register */
 608                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 609         }
 610
 611         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 612                 if (adev->uvd.harvest_config & (1 << i))
 613                         continue;
 614                 adev->uvd.inst[i].ring.ready = false;
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int uvd_v7_0_suspend(void *handle)
 621 {
 622         int r;
 623         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 624
 625         r = uvd_v7_0_hw_fini(adev);
 626         if (r)
 627                 return r;
 628
 629         return amdgpu_uvd_suspend(adev);
 630 }
 631
 632 static int uvd_v7_0_resume(void *handle)
 633 {
 634         int r;
 635         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 636
 637         r = amdgpu_uvd_resume(adev);
 638         if (r)
 639                 return r;
 640
 641         return uvd_v7_0_hw_init(adev);
 642 }
 643
 644 /**
 645  * uvd_v7_0_mc_resume - memory controller programming
 646  *
 647  * @adev: amdgpu_device pointer
 648  *
 649  * Let the UVD memory controller know it's offsets
 650  */
 651 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 652 {
 653         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 654         uint32_t offset;
 655         int i;
 656
 657         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 658                 if (adev->uvd.harvest_config & (1 << i))
 659                         continue;
 660                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 661                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 662                                 lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 663                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 664                                 upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 665                         offset = 0;
 666                 } else {
 667                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 668                                 lower_32_bits(adev->uvd.inst[i].gpu_addr));
 669                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 670                                 upper_32_bits(adev->uvd.inst[i].gpu_addr));
 671                         offset = size;
 672                 }
 673
 674                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 675                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 676                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 677
 678                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 679                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 680                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 681                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 682                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 683                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 684
 685                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 686                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 687                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 688                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 689                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 690                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
 691                                 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 692
 693                 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
 694                                 adev->gfx.config.gb_addr_config);
 695                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
 696                                 adev->gfx.config.gb_addr_config);
 697                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
 698                                 adev->gfx.config.gb_addr_config);
 699
 700                 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 701         }
 702 }
 703
 704 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 705                                 struct amdgpu_mm_table *table)
 706 {
 707         uint32_t data = 0, loop;
 708         uint64_t addr = table->gpu_addr;
 709         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 710         uint32_t size;
 711         int i;
 712
 713         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 714
 715         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 716         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 717         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 718
 719         /* 2, update vmid of descriptor */
 720         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 721         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 722         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 723         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 724
 725         /* 3, notify mmsch about the size of this descriptor */
 726         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 727
 728         /* 4, set resp to zero */
 729         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 730
 731         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 732                 if (adev->uvd.harvest_config & (1 << i))
 733                         continue;
 734                 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
 735                 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
 736                 adev->uvd.inst[i].ring_enc[0].wptr = 0;
 737                 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
 738         }
 739         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 740         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 741
 742         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 743         loop = 1000;
 744         while ((data & 0x10000002) != 0x10000002) {
 745                 udelay(10);
 746                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 747                 loop--;
 748                 if (!loop)
 749                         break;
 750         }
 751
 752         if (!loop) {
 753                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 754                 return -EBUSY;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 761 {
 762         struct amdgpu_ring *ring;
 763         uint32_t offset, size, tmp;
 764         uint32_t table_size = 0;
 765         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 766         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 767         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 768         struct mmsch_v1_0_cmd_end end = { {0} };
 769         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 770         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 771         uint8_t i = 0;
 772
 773         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 774         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 775         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 776         end.cmd_header.command_type = MMSCH_COMMAND__END;
 777
 778         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 779                 header->version = MMSCH_VERSION;
 780                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 781
 782                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 783                         header->uvd_table_offset = header->header_size;
 784                 else
 785                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 786
 787                 init_table += header->uvd_table_offset;
 788
 789                 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 790                         if (adev->uvd.harvest_config & (1 << i))
 791                                 continue;
 792                         ring = &adev->uvd.inst[i].ring;
 793                         ring->wptr = 0;
 794                         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 795
 796                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 797                                                            0xFFFFFFFF, 0x00000004);
 798                         /* mc resume*/
 799                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 800                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 801                                                             lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 802                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 803                                                             upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 804                                 offset = 0;
 805                         } else {
 806                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 807                                                             lower_32_bits(adev->uvd.inst[i].gpu_addr));
 808                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 809                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
 810                                 offset = size;
 811                         }
 812
 813                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
 814                                                     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 815                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 816
 817                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 818                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 819                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 820                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 821                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 822                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 823
 824                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 825                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 826                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 827                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 828                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 829                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
 830                                                     AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 831
 832                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 833                         /* mc resume end*/
 834
 835                         /* disable clock gating */
 836                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
 837                                                            ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 838
 839                         /* disable interupt */
 840                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 841                                                            ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 842
 843                         /* stall UMC and register bus before resetting VCPU */
 844                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 845                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 846                                                            UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 847
 848                         /* put LMI, VCPU, RBC etc... into reset */
 849                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 850                                                     (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 851                                                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 852                                                                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 853                                                                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 854                                                                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 855                                                                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 856                                                                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 857                                                                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 858
 859                         /* initialize UVD memory controller */
 860                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
 861                                                     (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 862                                                                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 863                                                                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 864                                                                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 865                                                                UVD_LMI_CTRL__REQ_MODE_MASK |
 866                                                                0x00100000L));
 867
 868                         /* take all subblocks out of reset, except VCPU */
 869                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 870                                                     UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 871
 872                         /* enable VCPU clock */
 873                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 874                                                     UVD_VCPU_CNTL__CLK_EN_MASK);
 875
 876                         /* enable master interrupt */
 877                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 878                                                            ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 879                                                            (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 880
 881                         /* clear the bit 4 of UVD_STATUS */
 882                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 883                                                            ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 884
 885                         /* force RBC into idle state */
 886                         size = order_base_2(ring->ring_size);
 887                         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 888                         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 889                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
 890
 891                         ring = &adev->uvd.inst[i].ring_enc[0];
 892                         ring->wptr = 0;
 893                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
 894                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 895                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
 896
 897                         /* boot up the VCPU */
 898                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
 899
 900                         /* enable UMC */
 901                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 902                                                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 903
 904                         MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
 905                 }
 906                 /* add end packet */
 907                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 908                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 909                 header->uvd_table_size = table_size;
 910
 911         }
 912         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 913 }
 914
 915 /**
 916  * uvd_v7_0_start - start UVD block
 917  *
 918  * @adev: amdgpu_device pointer
 919  *
 920  * Setup and start the UVD block
 921  */
 922 static int uvd_v7_0_start(struct amdgpu_device *adev)
 923 {
 924         struct amdgpu_ring *ring;
 925         uint32_t rb_bufsz, tmp;
 926         uint32_t lmi_swap_cntl;
 927         uint32_t mp_swap_cntl;
 928         int i, j, k, r;
 929
 930         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 931                 if (adev->uvd.harvest_config & (1 << k))
 932                         continue;
 933                 /* disable DPG */
 934                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
 935                                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 936         }
 937
 938         /* disable byte swapping */
 939         lmi_swap_cntl = 0;
 940         mp_swap_cntl = 0;
 941
 942         uvd_v7_0_mc_resume(adev);
 943
 944         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 945                 if (adev->uvd.harvest_config & (1 << k))
 946                         continue;
 947                 ring = &adev->uvd.inst[k].ring;
 948                 /* disable clock gating */
 949                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
 950                                 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 951
 952                 /* disable interupt */
 953                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
 954                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 955
 956                 /* stall UMC and register bus before resetting VCPU */
 957                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
 958                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 959                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 960                 mdelay(1);
 961
 962                 /* put LMI, VCPU, RBC etc... into reset */
 963                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 964                         UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 965                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 966                         UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 967                         UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 968                         UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 969                         UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 970                         UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 971                         UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 972                 mdelay(5);
 973
 974                 /* initialize UVD memory controller */
 975                 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
 976                         (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 977                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 978                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 979                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 980                         UVD_LMI_CTRL__REQ_MODE_MASK |
 981                         0x00100000L);
 982
 983 #ifdef __BIG_ENDIAN
 984                 /* swap (8 in 32) RB and IB */
 985                 lmi_swap_cntl = 0xa;
 986                 mp_swap_cntl = 0;
 987 #endif
 988                 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 989                 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 990
 991                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 992                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
 993                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
 994                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
 995                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
 996                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
 997
 998                 /* take all subblocks out of reset, except VCPU */
 999                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
1000                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1001                 mdelay(5);
1002
1003                 /* enable VCPU clock */
1004                 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
1005                                 UVD_VCPU_CNTL__CLK_EN_MASK);
1006
1007                 /* enable UMC */
1008                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
1009                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1010
1011                 /* boot up the VCPU */
1012                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
1013                 mdelay(10);
1014
1015                 for (i = 0; i < 10; ++i) {
1016                         uint32_t status;
1017
1018                         for (j = 0; j < 100; ++j) {
1019                                 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
1020                                 if (status & 2)
1021                                         break;
1022                                 mdelay(10);
1023                         }
1024                         r = 0;
1025                         if (status & 2)
1026                                 break;
1027
1028                         DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
1029                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
1030                                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1031                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1032                         mdelay(10);
1033                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1034                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1035                         mdelay(10);
1036                         r = -1;
1037                 }
1038
1039                 if (r) {
1040                         DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1041                         return r;
1042                 }
1043                 /* enable master interrupt */
1044                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1045                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1046                         ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1047
1048                 /* clear the bit 4 of UVD_STATUS */
1049                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1050                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1051
1052                 /* force RBC into idle state */
1053                 rb_bufsz = order_base_2(ring->ring_size);
1054                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1055                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1056                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1057                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1058                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1059                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1060                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1061
1062                 /* set the write pointer delay */
1063                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1064
1065                 /* set the wb address */
1066                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1067                                 (upper_32_bits(ring->gpu_addr) >> 2));
1068
1069                 /* programm the RB_BASE for ring buffer */
1070                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1071                                 lower_32_bits(ring->gpu_addr));
1072                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1073                                 upper_32_bits(ring->gpu_addr));
1074
1075                 /* Initialize the ring buffer's read and write pointers */
1076                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1077
1078                 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1079                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1080                                 lower_32_bits(ring->wptr));
1081
1082                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1083                                 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1084
1085                 ring = &adev->uvd.inst[k].ring_enc[0];
1086                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1087                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1088                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1089                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1090                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1091
1092                 ring = &adev->uvd.inst[k].ring_enc[1];
1093                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1094                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1095                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1096                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1097                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1098         }
1099         return 0;
1100 }
1101
1102 /**
1103  * uvd_v7_0_stop - stop UVD block
1104  *
1105  * @adev: amdgpu_device pointer
1106  *
1107  * stop the UVD block
1108  */
1109 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1110 {
1111         uint8_t i = 0;
1112
1113         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1114                 if (adev->uvd.harvest_config & (1 << i))
1115                         continue;
1116                 /* force RBC into idle state */
1117                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1118
1119                 /* Stall UMC and register bus before resetting VCPU */
1120                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1121                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1122                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1123                 mdelay(1);
1124
1125                 /* put VCPU into reset */
1126                 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1127                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1128                 mdelay(5);
1129
1130                 /* disable VCPU clock */
1131                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1132
1133                 /* Unstall UMC and register bus */
1134                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1135                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1136         }
1137 }
1138
1139 /**
1140  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1141  *
1142  * @ring: amdgpu_ring pointer
1143  * @fence: fence to emit
1144  *
1145  * Write a fence and a trap command to the ring.
1146  */
1147 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1148                                      unsigned flags)
1149 {
1150         struct amdgpu_device *adev = ring->adev;
1151
1152         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1153
1154         amdgpu_ring_write(ring,
1155                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1156         amdgpu_ring_write(ring, seq);
1157         amdgpu_ring_write(ring,
1158                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1159         amdgpu_ring_write(ring, addr & 0xffffffff);
1160         amdgpu_ring_write(ring,
1161                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1162         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1163         amdgpu_ring_write(ring,
1164                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1165         amdgpu_ring_write(ring, 0);
1166
1167         amdgpu_ring_write(ring,
1168                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1169         amdgpu_ring_write(ring, 0);
1170         amdgpu_ring_write(ring,
1171                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1172         amdgpu_ring_write(ring, 0);
1173         amdgpu_ring_write(ring,
1174                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1175         amdgpu_ring_write(ring, 2);
1176 }
1177
1178 /**
1179  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1180  *
1181  * @ring: amdgpu_ring pointer
1182  * @fence: fence to emit
1183  *
1184  * Write enc a fence and a trap command to the ring.
1185  */
1186 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1187                         u64 seq, unsigned flags)
1188 {
1189
1190         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1191
1192         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1193         amdgpu_ring_write(ring, addr);
1194         amdgpu_ring_write(ring, upper_32_bits(addr));
1195         amdgpu_ring_write(ring, seq);
1196         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1197 }
1198
1199 /**
1200  * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1201  *
1202  * @ring: amdgpu_ring pointer
1203  */
1204 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1205 {
1206         /* The firmware doesn't seem to like touching registers at this point. */
1207 }
1208
1209 /**
1210  * uvd_v7_0_ring_test_ring - register write test
1211  *
1212  * @ring: amdgpu_ring pointer
1213  *
1214  * Test if we can successfully write to the context register
1215  */
1216 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1217 {
1218         struct amdgpu_device *adev = ring->adev;
1219         uint32_t tmp = 0;
1220         unsigned i;
1221         int r;
1222
1223         WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1224         r = amdgpu_ring_alloc(ring, 3);
1225         if (r) {
1226                 DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n",
1227                           ring->me, ring->idx, r);
1228                 return r;
1229         }
1230         amdgpu_ring_write(ring,
1231                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1232         amdgpu_ring_write(ring, 0xDEADBEEF);
1233         amdgpu_ring_commit(ring);
1234         for (i = 0; i < adev->usec_timeout; i++) {
1235                 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1236                 if (tmp == 0xDEADBEEF)
1237                         break;
1238                 DRM_UDELAY(1);
1239         }
1240
1241         if (i < adev->usec_timeout) {
1242                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
1243                          ring->me, ring->idx, i);
1244         } else {
1245                 DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n",
1246                           ring->me, ring->idx, tmp);
1247                 r = -EINVAL;
1248         }
1249         return r;
1250 }
1251
1252 /**
1253  * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.
1254  *
1255  * @p: the CS parser with the IBs
1256  * @ib_idx: which IB to patch
1257  *
1258  */
1259 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1260                                            uint32_t ib_idx)
1261 {
1262         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1263         unsigned i;
1264
1265         /* No patching necessary for the first instance */
1266         if (!p->ring->me)
1267                 return 0;
1268
1269         for (i = 0; i < ib->length_dw; i += 2) {
1270                 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1271
1272                 reg -= p->adev->reg_offset[UVD_HWIP][0][1];
1273                 reg += p->adev->reg_offset[UVD_HWIP][1][1];
1274
1275                 amdgpu_set_ib_value(p, ib_idx, i, reg);
1276         }
1277         return 0;
1278 }
1279
1280 /**
1281  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1282  *
1283  * @ring: amdgpu_ring pointer
1284  * @ib: indirect buffer to execute
1285  *
1286  * Write ring commands to execute the indirect buffer
1287  */
1288 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1289                                   struct amdgpu_ib *ib,
1290                                   unsigned vmid, bool ctx_switch)
1291 {
1292         struct amdgpu_device *adev = ring->adev;
1293
1294         amdgpu_ring_write(ring,
1295                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1296         amdgpu_ring_write(ring, vmid);
1297
1298         amdgpu_ring_write(ring,
1299                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1300         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1301         amdgpu_ring_write(ring,
1302                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1303         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1304         amdgpu_ring_write(ring,
1305                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1306         amdgpu_ring_write(ring, ib->length_dw);
1307 }
1308
1309 /**
1310  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1311  *
1312  * @ring: amdgpu_ring pointer
1313  * @ib: indirect buffer to execute
1314  *
1315  * Write enc ring commands to execute the indirect buffer
1316  */
1317 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1318                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1319 {
1320         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1321         amdgpu_ring_write(ring, vmid);
1322         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1323         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1324         amdgpu_ring_write(ring, ib->length_dw);
1325 }
1326
1327 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1328                                     uint32_t reg, uint32_t val)
1329 {
1330         struct amdgpu_device *adev = ring->adev;
1331
1332         amdgpu_ring_write(ring,
1333                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1334         amdgpu_ring_write(ring, reg << 2);
1335         amdgpu_ring_write(ring,
1336                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1337         amdgpu_ring_write(ring, val);
1338         amdgpu_ring_write(ring,
1339                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1340         amdgpu_ring_write(ring, 8);
1341 }
1342
1343 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1344                                         uint32_t val, uint32_t mask)
1345 {
1346         struct amdgpu_device *adev = ring->adev;
1347
1348         amdgpu_ring_write(ring,
1349                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1350         amdgpu_ring_write(ring, reg << 2);
1351         amdgpu_ring_write(ring,
1352                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1353         amdgpu_ring_write(ring, val);
1354         amdgpu_ring_write(ring,
1355                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1356         amdgpu_ring_write(ring, mask);
1357         amdgpu_ring_write(ring,
1358                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1359         amdgpu_ring_write(ring, 12);
1360 }
1361
1362 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1363                                         unsigned vmid, uint64_t pd_addr)
1364 {
1365         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1366         uint32_t data0, data1, mask;
1367
1368         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1369
1370         /* wait for reg writes */
1371         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1372         data1 = lower_32_bits(pd_addr);
1373         mask = 0xffffffff;
1374         uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1375 }
1376
1377 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1378 {
1379         struct amdgpu_device *adev = ring->adev;
1380         int i;
1381
1382         WARN_ON(ring->wptr % 2 || count % 2);
1383
1384         for (i = 0; i < count / 2; i++) {
1385                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1386                 amdgpu_ring_write(ring, 0);
1387         }
1388 }
1389
1390 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1391 {
1392         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1393 }
1394
1395 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1396                                             uint32_t reg, uint32_t val,
1397                                             uint32_t mask)
1398 {
1399         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1400         amdgpu_ring_write(ring, reg << 2);
1401         amdgpu_ring_write(ring, mask);
1402         amdgpu_ring_write(ring, val);
1403 }
1404
1405 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1406                                             unsigned int vmid, uint64_t pd_addr)
1407 {
1408         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1409
1410         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1411
1412         /* wait for reg writes */
1413         uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1414                                         lower_32_bits(pd_addr), 0xffffffff);
1415 }
1416
1417 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1418                                         uint32_t reg, uint32_t val)
1419 {
1420         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1421         amdgpu_ring_write(ring, reg << 2);
1422         amdgpu_ring_write(ring, val);
1423 }
1424
1425 #if 0
1426 static bool uvd_v7_0_is_idle(void *handle)
1427 {
1428         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1429
1430         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1431 }
1432
1433 static int uvd_v7_0_wait_for_idle(void *handle)
1434 {
1435         unsigned i;
1436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1437
1438         for (i = 0; i < adev->usec_timeout; i++) {
1439                 if (uvd_v7_0_is_idle(handle))
1440                         return 0;
1441         }
1442         return -ETIMEDOUT;
1443 }
1444
1445 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1446 static bool uvd_v7_0_check_soft_reset(void *handle)
1447 {
1448         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1449         u32 srbm_soft_reset = 0;
1450         u32 tmp = RREG32(mmSRBM_STATUS);
1451
1452         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1453             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1454             (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1455                     AMDGPU_UVD_STATUS_BUSY_MASK))
1456                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1457                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1458
1459         if (srbm_soft_reset) {
1460                 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1461                 return true;
1462         } else {
1463                 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1464                 return false;
1465         }
1466 }
1467
1468 static int uvd_v7_0_pre_soft_reset(void *handle)
1469 {
1470         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1471
1472         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1473                 return 0;
1474
1475         uvd_v7_0_stop(adev);
1476         return 0;
1477 }
1478
1479 static int uvd_v7_0_soft_reset(void *handle)
1480 {
1481         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1482         u32 srbm_soft_reset;
1483
1484         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1485                 return 0;
1486         srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1487
1488         if (srbm_soft_reset) {
1489                 u32 tmp;
1490
1491                 tmp = RREG32(mmSRBM_SOFT_RESET);
1492                 tmp |= srbm_soft_reset;
1493                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1494                 WREG32(mmSRBM_SOFT_RESET, tmp);
1495                 tmp = RREG32(mmSRBM_SOFT_RESET);
1496
1497                 udelay(50);
1498
1499                 tmp &= ~srbm_soft_reset;
1500                 WREG32(mmSRBM_SOFT_RESET, tmp);
1501                 tmp = RREG32(mmSRBM_SOFT_RESET);
1502
1503                 /* Wait a little for things to settle down */
1504                 udelay(50);
1505         }
1506
1507         return 0;
1508 }
1509
1510 static int uvd_v7_0_post_soft_reset(void *handle)
1511 {
1512         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1513
1514         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1515                 return 0;
1516
1517         mdelay(5);
1518
1519         return uvd_v7_0_start(adev);
1520 }
1521 #endif
1522
1523 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1524                                         struct amdgpu_irq_src *source,
1525                                         unsigned type,
1526                                         enum amdgpu_interrupt_state state)
1527 {
1528         // TODO
1529         return 0;
1530 }
1531
1532 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1533                                       struct amdgpu_irq_src *source,
1534                                       struct amdgpu_iv_entry *entry)
1535 {
1536         uint32_t ip_instance;
1537
1538         switch (entry->client_id) {
1539         case SOC15_IH_CLIENTID_UVD:
1540                 ip_instance = 0;
1541                 break;
1542         case SOC15_IH_CLIENTID_UVD1:
1543                 ip_instance = 1;
1544                 break;
1545         default:
1546                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1547                 return 0;
1548         }
1549
1550         DRM_DEBUG("IH: UVD TRAP\n");
1551
1552         switch (entry->src_id) {
1553         case 124:
1554                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1555                 break;
1556         case 119:
1557                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1558                 break;
1559         case 120:
1560                 if (!amdgpu_sriov_vf(adev))
1561                         amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1562                 break;
1563         default:
1564                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1565                           entry->src_id, entry->src_data[0]);
1566                 break;
1567         }
1568
1569         return 0;
1570 }
1571
1572 #if 0
1573 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1574 {
1575         uint32_t data, data1, data2, suvd_flags;
1576
1577         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1578         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1579         data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1580
1581         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1582                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1583
1584         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1585                      UVD_SUVD_CGC_GATE__SIT_MASK |
1586                      UVD_SUVD_CGC_GATE__SMP_MASK |
1587                      UVD_SUVD_CGC_GATE__SCM_MASK |
1588                      UVD_SUVD_CGC_GATE__SDB_MASK;
1589
1590         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1591                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1592                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1593
1594         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1595                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1596                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1597                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1598                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1599                         UVD_CGC_CTRL__SYS_MODE_MASK |
1600                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1601                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1602                         UVD_CGC_CTRL__REGS_MODE_MASK |
1603                         UVD_CGC_CTRL__RBC_MODE_MASK |
1604                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1605                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1606                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1607                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1608                         UVD_CGC_CTRL__MPC_MODE_MASK |
1609                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1610                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1611                         UVD_CGC_CTRL__WCB_MODE_MASK |
1612                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1613                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1614                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1615                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1616         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1617                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1618                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1619                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1620                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1621         data1 |= suvd_flags;
1622
1623         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1624         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1625         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1626         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1627 }
1628
1629 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1630 {
1631         uint32_t data, data1, cgc_flags, suvd_flags;
1632
1633         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1634         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1635
1636         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1637                 UVD_CGC_GATE__UDEC_MASK |
1638                 UVD_CGC_GATE__MPEG2_MASK |
1639                 UVD_CGC_GATE__RBC_MASK |
1640                 UVD_CGC_GATE__LMI_MC_MASK |
1641                 UVD_CGC_GATE__IDCT_MASK |
1642                 UVD_CGC_GATE__MPRD_MASK |
1643                 UVD_CGC_GATE__MPC_MASK |
1644                 UVD_CGC_GATE__LBSI_MASK |
1645                 UVD_CGC_GATE__LRBBM_MASK |
1646                 UVD_CGC_GATE__UDEC_RE_MASK |
1647                 UVD_CGC_GATE__UDEC_CM_MASK |
1648                 UVD_CGC_GATE__UDEC_IT_MASK |
1649                 UVD_CGC_GATE__UDEC_DB_MASK |
1650                 UVD_CGC_GATE__UDEC_MP_MASK |
1651                 UVD_CGC_GATE__WCB_MASK |
1652                 UVD_CGC_GATE__VCPU_MASK |
1653                 UVD_CGC_GATE__SCPU_MASK |
1654                 UVD_CGC_GATE__JPEG_MASK |
1655                 UVD_CGC_GATE__JPEG2_MASK;
1656
1657         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1658                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1659                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1660                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1661                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1662
1663         data |= cgc_flags;
1664         data1 |= suvd_flags;
1665
1666         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1667         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1668 }
1669
1670 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1671 {
1672         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1673
1674         if (enable)
1675                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1676                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1677         else
1678                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1679                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1680
1681         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1682 }
1683
1684
1685 static int uvd_v7_0_set_clockgating_state(void *handle,
1686                                           enum amd_clockgating_state state)
1687 {
1688         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1689         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1690
1691         uvd_v7_0_set_bypass_mode(adev, enable);
1692
1693         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1694                 return 0;
1695
1696         if (enable) {
1697                 /* disable HW gating and enable Sw gating */
1698                 uvd_v7_0_set_sw_clock_gating(adev);
1699         } else {
1700                 /* wait for STATUS to clear */
1701                 if (uvd_v7_0_wait_for_idle(handle))
1702                         return -EBUSY;
1703
1704                 /* enable HW gates because UVD is idle */
1705                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1706         }
1707
1708         return 0;
1709 }
1710
1711 static int uvd_v7_0_set_powergating_state(void *handle,
1712                                           enum amd_powergating_state state)
1713 {
1714         /* This doesn't actually powergate the UVD block.
1715          * That's done in the dpm code via the SMC.  This
1716          * just re-inits the block as necessary.  The actual
1717          * gating still happens in the dpm code.  We should
1718          * revisit this when there is a cleaner line between
1719          * the smc and the hw blocks
1720          */
1721         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1722
1723         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1724                 return 0;
1725
1726         WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1727
1728         if (state == AMD_PG_STATE_GATE) {
1729                 uvd_v7_0_stop(adev);
1730                 return 0;
1731         } else {
1732                 return uvd_v7_0_start(adev);
1733         }
1734 }
1735 #endif
1736
1737 static int uvd_v7_0_set_clockgating_state(void *handle,
1738                                           enum amd_clockgating_state state)
1739 {
1740         /* needed for driver unload*/
1741         return 0;
1742 }
1743
1744 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1745         .name = "uvd_v7_0",
1746         .early_init = uvd_v7_0_early_init,
1747         .late_init = NULL,
1748         .sw_init = uvd_v7_0_sw_init,
1749         .sw_fini = uvd_v7_0_sw_fini,
1750         .hw_init = uvd_v7_0_hw_init,
1751         .hw_fini = uvd_v7_0_hw_fini,
1752         .suspend = uvd_v7_0_suspend,
1753         .resume = uvd_v7_0_resume,
1754         .is_idle = NULL /* uvd_v7_0_is_idle */,
1755         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1756         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1757         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1758         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1759         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1760         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1761         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1762 };
1763
1764 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1765         .type = AMDGPU_RING_TYPE_UVD,
1766         .align_mask = 0xf,
1767         .support_64bit_ptrs = false,
1768         .vmhub = AMDGPU_MMHUB,
1769         .get_rptr = uvd_v7_0_ring_get_rptr,
1770         .get_wptr = uvd_v7_0_ring_get_wptr,
1771         .set_wptr = uvd_v7_0_ring_set_wptr,
1772         .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,
1773         .emit_frame_size =
1774                 6 + /* hdp invalidate */
1775                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1776                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1777                 8 + /* uvd_v7_0_ring_emit_vm_flush */
1778                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1779         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1780         .emit_ib = uvd_v7_0_ring_emit_ib,
1781         .emit_fence = uvd_v7_0_ring_emit_fence,
1782         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1783         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1784         .test_ring = uvd_v7_0_ring_test_ring,
1785         .test_ib = amdgpu_uvd_ring_test_ib,
1786         .insert_nop = uvd_v7_0_ring_insert_nop,
1787         .pad_ib = amdgpu_ring_generic_pad_ib,
1788         .begin_use = amdgpu_uvd_ring_begin_use,
1789         .end_use = amdgpu_uvd_ring_end_use,
1790         .emit_wreg = uvd_v7_0_ring_emit_wreg,
1791         .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1792         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1793 };
1794
1795 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1796         .type = AMDGPU_RING_TYPE_UVD_ENC,
1797         .align_mask = 0x3f,
1798         .nop = HEVC_ENC_CMD_NO_OP,
1799         .support_64bit_ptrs = false,
1800         .vmhub = AMDGPU_MMHUB,
1801         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1802         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1803         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1804         .emit_frame_size =
1805                 3 + 3 + /* hdp flush / invalidate */
1806                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1807                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1808                 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1809                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1810                 1, /* uvd_v7_0_enc_ring_insert_end */
1811         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1812         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1813         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1814         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1815         .test_ring = uvd_v7_0_enc_ring_test_ring,
1816         .test_ib = uvd_v7_0_enc_ring_test_ib,
1817         .insert_nop = amdgpu_ring_insert_nop,
1818         .insert_end = uvd_v7_0_enc_ring_insert_end,
1819         .pad_ib = amdgpu_ring_generic_pad_ib,
1820         .begin_use = amdgpu_uvd_ring_begin_use,
1821         .end_use = amdgpu_uvd_ring_end_use,
1822         .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1823         .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1824         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1825 };
1826
1827 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1828 {
1829         int i;
1830
1831         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1832                 if (adev->uvd.harvest_config & (1 << i))
1833                         continue;
1834                 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1835                 adev->uvd.inst[i].ring.me = i;
1836                 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1837         }
1838 }
1839
1840 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1841 {
1842         int i, j;
1843
1844         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1845                 if (adev->uvd.harvest_config & (1 << j))
1846                         continue;
1847                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1848                         adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1849                         adev->uvd.inst[j].ring_enc[i].me = j;
1850                 }
1851
1852                 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1853         }
1854 }
1855
1856 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1857         .set = uvd_v7_0_set_interrupt_state,
1858         .process = uvd_v7_0_process_interrupt,
1859 };
1860
1861 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1862 {
1863         int i;
1864
1865         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1866                 if (adev->uvd.harvest_config & (1 << i))
1867                         continue;
1868                 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1869                 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1870         }
1871 }
1872
1873 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1874 {
1875                 .type = AMD_IP_BLOCK_TYPE_UVD,
1876                 .major = 7,
1877                 .minor = 0,
1878                 .rev = 0,
1879                 .funcs = &uvd_v7_0_ip_funcs,
1880 };