drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/kthread.h>
  27 #include <linux/pci.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include <drm/drm_debugfs.h>
  32
  33 #include "amdgpu.h"
  34 #include "amdgpu_pm.h"
  35 #include "amdgpu_dm_debugfs.h"
  36
  37 /**
  38  * amdgpu_debugfs_add_files - Add simple debugfs entries
  39  *
  40  * @adev:  Device to attach debugfs entries to
  41  * @files:  Array of function callbacks that respond to reads
  42  * @nfiles: Number of callbacks to register
  43  *
  44  */
  45 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
  46                              const struct drm_info_list *files,
  47                              unsigned nfiles)
  48 {
  49         unsigned i;
  50
  51         for (i = 0; i < adev->debugfs_count; i++) {
  52                 if (adev->debugfs[i].files == files) {
  53                         /* Already registered */
  54                         return 0;
  55                 }
  56         }
  57
  58         i = adev->debugfs_count + 1;
  59         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
  60                 DRM_ERROR("Reached maximum number of debugfs components.\n");
  61                 DRM_ERROR("Report so we increase "
  62                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
  63                 return -EINVAL;
  64         }
  65         adev->debugfs[adev->debugfs_count].files = files;
  66         adev->debugfs[adev->debugfs_count].num_files = nfiles;
  67         adev->debugfs_count = i;
  68 #if defined(CONFIG_DEBUG_FS)
  69         drm_debugfs_create_files(files, nfiles,
  70                                  adev->ddev->primary->debugfs_root,
  71                                  adev->ddev->primary);
  72 #endif
  73         return 0;
  74 }
  75
  76 #if defined(CONFIG_DEBUG_FS)
  77
  78 /**
  79  * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
  80  *
  81  * @read: True if reading
  82  * @f: open file handle
  83  * @buf: User buffer to write/read to
  84  * @size: Number of bytes to write/read
  85  * @pos:  Offset to seek to
  86  *
  87  * This debugfs entry has special meaning on the offset being sought.
  88  * Various bits have different meanings:
  89  *
  90  * Bit 62:  Indicates a GRBM bank switch is needed
  91  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
  92  *                      zero)
  93  * Bits 24..33: The SE or ME selector if needed
  94  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  95  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  96  *
  97  * Bit 23:  Indicates that the PM power gating lock should be held
  98  *                      This is necessary to read registers that might be
  99  *                      unreliable during a power gating transistion.
 100  *
 101  * The lower bits are the BYTE offset of the register to read.  This
 102  * allows reading multiple registers in a single call and having
 103  * the returned size reflect that.
 104  */
 105 static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
 106                 char __user *buf, size_t size, loff_t *pos)
 107 {
 108         struct amdgpu_device *adev = file_inode(f)->i_private;
 109         ssize_t result = 0;
 110         int r;
 111         bool pm_pg_lock, use_bank, use_ring;
 112         unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
 113
 114         pm_pg_lock = use_bank = use_ring = false;
 115         instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
 116
 117         if (size & 0x3 || *pos & 0x3 ||
 118                         ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
 119                 return -EINVAL;
 120
 121         /* are we reading registers for which a PG lock is necessary? */
 122         pm_pg_lock = (*pos >> 23) & 1;
 123
 124         if (*pos & (1ULL << 62)) {
 125                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
 126                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
 127                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
 128
 129                 if (se_bank == 0x3FF)
 130                         se_bank = 0xFFFFFFFF;
 131                 if (sh_bank == 0x3FF)
 132                         sh_bank = 0xFFFFFFFF;
 133                 if (instance_bank == 0x3FF)
 134                         instance_bank = 0xFFFFFFFF;
 135                 use_bank = true;
 136         } else if (*pos & (1ULL << 61)) {
 137
 138                 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
 139                 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
 140                 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
 141                 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
 142
 143                 use_ring = true;
 144         } else {
 145                 use_bank = use_ring = false;
 146         }
 147
 148         *pos &= (1UL << 22) - 1;
 149
 150         r = pm_runtime_get_sync(adev->ddev->dev);
 151         if (r < 0)
 152                 return r;
 153
 154         if (use_bank) {
 155                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
 156                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
 157                         pm_runtime_mark_last_busy(adev->ddev->dev);
 158                         pm_runtime_put_autosuspend(adev->ddev->dev);
 159                         return -EINVAL;
 160                 }
 161                 mutex_lock(&adev->grbm_idx_mutex);
 162                 amdgpu_gfx_select_se_sh(adev, se_bank,
 163                                         sh_bank, instance_bank);
 164         } else if (use_ring) {
 165                 mutex_lock(&adev->srbm_mutex);
 166                 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
 167         }
 168
 169         if (pm_pg_lock)
 170                 mutex_lock(&adev->pm.mutex);
 171
 172         while (size) {
 173                 uint32_t value;
 174
 175                 if (read) {
 176                         value = RREG32(*pos >> 2);
 177                         r = put_user(value, (uint32_t *)buf);
 178                 } else {
 179                         r = get_user(value, (uint32_t *)buf);
 180                         if (!r)
 181                                 WREG32(*pos >> 2, value);
 182                 }
 183                 if (r) {
 184                         result = r;
 185                         goto end;
 186                 }
 187
 188                 result += 4;
 189                 buf += 4;
 190                 *pos += 4;
 191                 size -= 4;
 192         }
 193
 194 end:
 195         if (use_bank) {
 196                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 197                 mutex_unlock(&adev->grbm_idx_mutex);
 198         } else if (use_ring) {
 199                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
 200                 mutex_unlock(&adev->srbm_mutex);
 201         }
 202
 203         if (pm_pg_lock)
 204                 mutex_unlock(&adev->pm.mutex);
 205
 206         pm_runtime_mark_last_busy(adev->ddev->dev);
 207         pm_runtime_put_autosuspend(adev->ddev->dev);
 208
 209         return result;
 210 }
 211
 212 /**
 213  * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
 214  */
 215 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 216                                         size_t size, loff_t *pos)
 217 {
 218         return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
 219 }
 220
 221 /**
 222  * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
 223  */
 224 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
 225                                          size_t size, loff_t *pos)
 226 {
 227         return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
 228 }
 229
 230
 231 /**
 232  * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
 233  *
 234  * @f: open file handle
 235  * @buf: User buffer to store read data in
 236  * @size: Number of bytes to read
 237  * @pos:  Offset to seek to
 238  *
 239  * The lower bits are the BYTE offset of the register to read.  This
 240  * allows reading multiple registers in a single call and having
 241  * the returned size reflect that.
 242  */
 243 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
 244                                         size_t size, loff_t *pos)
 245 {
 246         struct amdgpu_device *adev = file_inode(f)->i_private;
 247         ssize_t result = 0;
 248         int r;
 249
 250         if (size & 0x3 || *pos & 0x3)
 251                 return -EINVAL;
 252
 253         r = pm_runtime_get_sync(adev->ddev->dev);
 254         if (r < 0)
 255                 return r;
 256
 257         while (size) {
 258                 uint32_t value;
 259
 260                 value = RREG32_PCIE(*pos >> 2);
 261                 r = put_user(value, (uint32_t *)buf);
 262                 if (r) {
 263                         pm_runtime_mark_last_busy(adev->ddev->dev);
 264                         pm_runtime_put_autosuspend(adev->ddev->dev);
 265                         return r;
 266                 }
 267
 268                 result += 4;
 269                 buf += 4;
 270                 *pos += 4;
 271                 size -= 4;
 272         }
 273
 274         pm_runtime_mark_last_busy(adev->ddev->dev);
 275         pm_runtime_put_autosuspend(adev->ddev->dev);
 276
 277         return result;
 278 }
 279
 280 /**
 281  * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
 282  *
 283  * @f: open file handle
 284  * @buf: User buffer to write data from
 285  * @size: Number of bytes to write
 286  * @pos:  Offset to seek to
 287  *
 288  * The lower bits are the BYTE offset of the register to write.  This
 289  * allows writing multiple registers in a single call and having
 290  * the returned size reflect that.
 291  */
 292 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
 293                                          size_t size, loff_t *pos)
 294 {
 295         struct amdgpu_device *adev = file_inode(f)->i_private;
 296         ssize_t result = 0;
 297         int r;
 298
 299         if (size & 0x3 || *pos & 0x3)
 300                 return -EINVAL;
 301
 302         r = pm_runtime_get_sync(adev->ddev->dev);
 303         if (r < 0)
 304                 return r;
 305
 306         while (size) {
 307                 uint32_t value;
 308
 309                 r = get_user(value, (uint32_t *)buf);
 310                 if (r) {
 311                         pm_runtime_mark_last_busy(adev->ddev->dev);
 312                         pm_runtime_put_autosuspend(adev->ddev->dev);
 313                         return r;
 314                 }
 315
 316                 WREG32_PCIE(*pos >> 2, value);
 317
 318                 result += 4;
 319                 buf += 4;
 320                 *pos += 4;
 321                 size -= 4;
 322         }
 323
 324         pm_runtime_mark_last_busy(adev->ddev->dev);
 325         pm_runtime_put_autosuspend(adev->ddev->dev);
 326
 327         return result;
 328 }
 329
 330 /**
 331  * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
 332  *
 333  * @f: open file handle
 334  * @buf: User buffer to store read data in
 335  * @size: Number of bytes to read
 336  * @pos:  Offset to seek to
 337  *
 338  * The lower bits are the BYTE offset of the register to read.  This
 339  * allows reading multiple registers in a single call and having
 340  * the returned size reflect that.
 341  */
 342 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
 343                                         size_t size, loff_t *pos)
 344 {
 345         struct amdgpu_device *adev = file_inode(f)->i_private;
 346         ssize_t result = 0;
 347         int r;
 348
 349         if (size & 0x3 || *pos & 0x3)
 350                 return -EINVAL;
 351
 352         r = pm_runtime_get_sync(adev->ddev->dev);
 353         if (r < 0)
 354                 return r;
 355
 356         while (size) {
 357                 uint32_t value;
 358
 359                 value = RREG32_DIDT(*pos >> 2);
 360                 r = put_user(value, (uint32_t *)buf);
 361                 if (r) {
 362                         pm_runtime_mark_last_busy(adev->ddev->dev);
 363                         pm_runtime_put_autosuspend(adev->ddev->dev);
 364                         return r;
 365                 }
 366
 367                 result += 4;
 368                 buf += 4;
 369                 *pos += 4;
 370                 size -= 4;
 371         }
 372
 373         pm_runtime_mark_last_busy(adev->ddev->dev);
 374         pm_runtime_put_autosuspend(adev->ddev->dev);
 375
 376         return result;
 377 }
 378
 379 /**
 380  * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
 381  *
 382  * @f: open file handle
 383  * @buf: User buffer to write data from
 384  * @size: Number of bytes to write
 385  * @pos:  Offset to seek to
 386  *
 387  * The lower bits are the BYTE offset of the register to write.  This
 388  * allows writing multiple registers in a single call and having
 389  * the returned size reflect that.
 390  */
 391 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
 392                                          size_t size, loff_t *pos)
 393 {
 394         struct amdgpu_device *adev = file_inode(f)->i_private;
 395         ssize_t result = 0;
 396         int r;
 397
 398         if (size & 0x3 || *pos & 0x3)
 399                 return -EINVAL;
 400
 401         r = pm_runtime_get_sync(adev->ddev->dev);
 402         if (r < 0)
 403                 return r;
 404
 405         while (size) {
 406                 uint32_t value;
 407
 408                 r = get_user(value, (uint32_t *)buf);
 409                 if (r) {
 410                         pm_runtime_mark_last_busy(adev->ddev->dev);
 411                         pm_runtime_put_autosuspend(adev->ddev->dev);
 412                         return r;
 413                 }
 414
 415                 WREG32_DIDT(*pos >> 2, value);
 416
 417                 result += 4;
 418                 buf += 4;
 419                 *pos += 4;
 420                 size -= 4;
 421         }
 422
 423         pm_runtime_mark_last_busy(adev->ddev->dev);
 424         pm_runtime_put_autosuspend(adev->ddev->dev);
 425
 426         return result;
 427 }
 428
 429 /**
 430  * amdgpu_debugfs_regs_smc_read - Read from a SMC register
 431  *
 432  * @f: open file handle
 433  * @buf: User buffer to store read data in
 434  * @size: Number of bytes to read
 435  * @pos:  Offset to seek to
 436  *
 437  * The lower bits are the BYTE offset of the register to read.  This
 438  * allows reading multiple registers in a single call and having
 439  * the returned size reflect that.
 440  */
 441 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
 442                                         size_t size, loff_t *pos)
 443 {
 444         struct amdgpu_device *adev = file_inode(f)->i_private;
 445         ssize_t result = 0;
 446         int r;
 447
 448         if (size & 0x3 || *pos & 0x3)
 449                 return -EINVAL;
 450
 451         r = pm_runtime_get_sync(adev->ddev->dev);
 452         if (r < 0)
 453                 return r;
 454
 455         while (size) {
 456                 uint32_t value;
 457
 458                 value = RREG32_SMC(*pos);
 459                 r = put_user(value, (uint32_t *)buf);
 460                 if (r) {
 461                         pm_runtime_mark_last_busy(adev->ddev->dev);
 462                         pm_runtime_put_autosuspend(adev->ddev->dev);
 463                         return r;
 464                 }
 465
 466                 result += 4;
 467                 buf += 4;
 468                 *pos += 4;
 469                 size -= 4;
 470         }
 471
 472         pm_runtime_mark_last_busy(adev->ddev->dev);
 473         pm_runtime_put_autosuspend(adev->ddev->dev);
 474
 475         return result;
 476 }
 477
 478 /**
 479  * amdgpu_debugfs_regs_smc_write - Write to a SMC register
 480  *
 481  * @f: open file handle
 482  * @buf: User buffer to write data from
 483  * @size: Number of bytes to write
 484  * @pos:  Offset to seek to
 485  *
 486  * The lower bits are the BYTE offset of the register to write.  This
 487  * allows writing multiple registers in a single call and having
 488  * the returned size reflect that.
 489  */
 490 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
 491                                          size_t size, loff_t *pos)
 492 {
 493         struct amdgpu_device *adev = file_inode(f)->i_private;
 494         ssize_t result = 0;
 495         int r;
 496
 497         if (size & 0x3 || *pos & 0x3)
 498                 return -EINVAL;
 499
 500         r = pm_runtime_get_sync(adev->ddev->dev);
 501         if (r < 0)
 502                 return r;
 503
 504         while (size) {
 505                 uint32_t value;
 506
 507                 r = get_user(value, (uint32_t *)buf);
 508                 if (r) {
 509                         pm_runtime_mark_last_busy(adev->ddev->dev);
 510                         pm_runtime_put_autosuspend(adev->ddev->dev);
 511                         return r;
 512                 }
 513
 514                 WREG32_SMC(*pos, value);
 515
 516                 result += 4;
 517                 buf += 4;
 518                 *pos += 4;
 519                 size -= 4;
 520         }
 521
 522         pm_runtime_mark_last_busy(adev->ddev->dev);
 523         pm_runtime_put_autosuspend(adev->ddev->dev);
 524
 525         return result;
 526 }
 527
 528 /**
 529  * amdgpu_debugfs_gca_config_read - Read from gfx config data
 530  *
 531  * @f: open file handle
 532  * @buf: User buffer to store read data in
 533  * @size: Number of bytes to read
 534  * @pos:  Offset to seek to
 535  *
 536  * This file is used to access configuration data in a somewhat
 537  * stable fashion.  The format is a series of DWORDs with the first
 538  * indicating which revision it is.  New content is appended to the
 539  * end so that older software can still read the data.
 540  */
 541
 542 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
 543                                         size_t size, loff_t *pos)
 544 {
 545         struct amdgpu_device *adev = file_inode(f)->i_private;
 546         ssize_t result = 0;
 547         int r;
 548         uint32_t *config, no_regs = 0;
 549
 550         if (size & 0x3 || *pos & 0x3)
 551                 return -EINVAL;
 552
 553         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
 554         if (!config)
 555                 return -ENOMEM;
 556
 557         /* version, increment each time something is added */
 558         config[no_regs++] = 3;
 559         config[no_regs++] = adev->gfx.config.max_shader_engines;
 560         config[no_regs++] = adev->gfx.config.max_tile_pipes;
 561         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
 562         config[no_regs++] = adev->gfx.config.max_sh_per_se;
 563         config[no_regs++] = adev->gfx.config.max_backends_per_se;
 564         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
 565         config[no_regs++] = adev->gfx.config.max_gprs;
 566         config[no_regs++] = adev->gfx.config.max_gs_threads;
 567         config[no_regs++] = adev->gfx.config.max_hw_contexts;
 568         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
 569         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
 570         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
 571         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
 572         config[no_regs++] = adev->gfx.config.num_tile_pipes;
 573         config[no_regs++] = adev->gfx.config.backend_enable_mask;
 574         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
 575         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
 576         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
 577         config[no_regs++] = adev->gfx.config.num_gpus;
 578         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
 579         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
 580         config[no_regs++] = adev->gfx.config.gb_addr_config;
 581         config[no_regs++] = adev->gfx.config.num_rbs;
 582
 583         /* rev==1 */
 584         config[no_regs++] = adev->rev_id;
 585         config[no_regs++] = adev->pg_flags;
 586         config[no_regs++] = adev->cg_flags;
 587
 588         /* rev==2 */
 589         config[no_regs++] = adev->family;
 590         config[no_regs++] = adev->external_rev_id;
 591
 592         /* rev==3 */
 593         config[no_regs++] = adev->pdev->device;
 594         config[no_regs++] = adev->pdev->revision;
 595         config[no_regs++] = adev->pdev->subsystem_device;
 596         config[no_regs++] = adev->pdev->subsystem_vendor;
 597
 598         while (size && (*pos < no_regs * 4)) {
 599                 uint32_t value;
 600
 601                 value = config[*pos >> 2];
 602                 r = put_user(value, (uint32_t *)buf);
 603                 if (r) {
 604                         kfree(config);
 605                         return r;
 606                 }
 607
 608                 result += 4;
 609                 buf += 4;
 610                 *pos += 4;
 611                 size -= 4;
 612         }
 613
 614         kfree(config);
 615         return result;
 616 }
 617
 618 /**
 619  * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
 620  *
 621  * @f: open file handle
 622  * @buf: User buffer to store read data in
 623  * @size: Number of bytes to read
 624  * @pos:  Offset to seek to
 625  *
 626  * The offset is treated as the BYTE address of one of the sensors
 627  * enumerated in amd/include/kgd_pp_interface.h under the
 628  * 'amd_pp_sensors' enumeration.  For instance to read the UVD VCLK
 629  * you would use the offset 3 * 4 = 12.
 630  */
 631 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
 632                                         size_t size, loff_t *pos)
 633 {
 634         struct amdgpu_device *adev = file_inode(f)->i_private;
 635         int idx, x, outsize, r, valuesize;
 636         uint32_t values[16];
 637
 638         if (size & 3 || *pos & 0x3)
 639                 return -EINVAL;
 640
 641         if (!adev->pm.dpm_enabled)
 642                 return -EINVAL;
 643
 644         /* convert offset to sensor number */
 645         idx = *pos >> 2;
 646
 647         valuesize = sizeof(values);
 648
 649         r = pm_runtime_get_sync(adev->ddev->dev);
 650         if (r < 0)
 651                 return r;
 652
 653         r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
 654
 655         pm_runtime_mark_last_busy(adev->ddev->dev);
 656         pm_runtime_put_autosuspend(adev->ddev->dev);
 657
 658         if (r)
 659                 return r;
 660
 661         if (size > valuesize)
 662                 return -EINVAL;
 663
 664         outsize = 0;
 665         x = 0;
 666         if (!r) {
 667                 while (size) {
 668                         r = put_user(values[x++], (int32_t *)buf);
 669                         buf += 4;
 670                         size -= 4;
 671                         outsize += 4;
 672                 }
 673         }
 674
 675         return !r ? outsize : r;
 676 }
 677
 678 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
 679  *
 680  * @f: open file handle
 681  * @buf: User buffer to store read data in
 682  * @size: Number of bytes to read
 683  * @pos:  Offset to seek to
 684  *
 685  * The offset being sought changes which wave that the status data
 686  * will be returned for.  The bits are used as follows:
 687  *
 688  * Bits 0..6:   Byte offset into data
 689  * Bits 7..14:  SE selector
 690  * Bits 15..22: SH/SA selector
 691  * Bits 23..30: CU/{WGP+SIMD} selector
 692  * Bits 31..36: WAVE ID selector
 693  * Bits 37..44: SIMD ID selector
 694  *
 695  * The returned data begins with one DWORD of version information
 696  * Followed by WAVE STATUS registers relevant to the GFX IP version
 697  * being used.  See gfx_v8_0_read_wave_data() for an example output.
 698  */
 699 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
 700                                         size_t size, loff_t *pos)
 701 {
 702         struct amdgpu_device *adev = f->f_inode->i_private;
 703         int r, x;
 704         ssize_t result=0;
 705         uint32_t offset, se, sh, cu, wave, simd, data[32];
 706
 707         if (size & 3 || *pos & 3)
 708                 return -EINVAL;
 709
 710         /* decode offset */
 711         offset = (*pos & GENMASK_ULL(6, 0));
 712         se = (*pos & GENMASK_ULL(14, 7)) >> 7;
 713         sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
 714         cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
 715         wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
 716         simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
 717
 718         r = pm_runtime_get_sync(adev->ddev->dev);
 719         if (r < 0)
 720                 return r;
 721
 722         /* switch to the specific se/sh/cu */
 723         mutex_lock(&adev->grbm_idx_mutex);
 724         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
 725
 726         x = 0;
 727         if (adev->gfx.funcs->read_wave_data)
 728                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
 729
 730         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
 731         mutex_unlock(&adev->grbm_idx_mutex);
 732
 733         pm_runtime_mark_last_busy(adev->ddev->dev);
 734         pm_runtime_put_autosuspend(adev->ddev->dev);
 735
 736         if (!x)
 737                 return -EINVAL;
 738
 739         while (size && (offset < x * 4)) {
 740                 uint32_t value;
 741
 742                 value = data[offset >> 2];
 743                 r = put_user(value, (uint32_t *)buf);
 744                 if (r)
 745                         return r;
 746
 747                 result += 4;
 748                 buf += 4;
 749                 offset += 4;
 750                 size -= 4;
 751         }
 752
 753         return result;
 754 }
 755
 756 /** amdgpu_debugfs_gpr_read - Read wave gprs
 757  *
 758  * @f: open file handle
 759  * @buf: User buffer to store read data in
 760  * @size: Number of bytes to read
 761  * @pos:  Offset to seek to
 762  *
 763  * The offset being sought changes which wave that the status data
 764  * will be returned for.  The bits are used as follows:
 765  *
 766  * Bits 0..11:  Byte offset into data
 767  * Bits 12..19: SE selector
 768  * Bits 20..27: SH/SA selector
 769  * Bits 28..35: CU/{WGP+SIMD} selector
 770  * Bits 36..43: WAVE ID selector
 771  * Bits 37..44: SIMD ID selector
 772  * Bits 52..59: Thread selector
 773  * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
 774  *
 775  * The return data comes from the SGPR or VGPR register bank for
 776  * the selected operational unit.
 777  */
 778 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
 779                                         size_t size, loff_t *pos)
 780 {
 781         struct amdgpu_device *adev = f->f_inode->i_private;
 782         int r;
 783         ssize_t result = 0;
 784         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
 785
 786         if (size & 3 || *pos & 3)
 787                 return -EINVAL;
 788
 789         /* decode offset */
 790         offset = *pos & GENMASK_ULL(11, 0);
 791         se = (*pos & GENMASK_ULL(19, 12)) >> 12;
 792         sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
 793         cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
 794         wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
 795         simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
 796         thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
 797         bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
 798
 799         data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
 800         if (!data)
 801                 return -ENOMEM;
 802
 803         r = pm_runtime_get_sync(adev->ddev->dev);
 804         if (r < 0)
 805                 return r;
 806
 807         /* switch to the specific se/sh/cu */
 808         mutex_lock(&adev->grbm_idx_mutex);
 809         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
 810
 811         if (bank == 0) {
 812                 if (adev->gfx.funcs->read_wave_vgprs)
 813                         adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
 814         } else {
 815                 if (adev->gfx.funcs->read_wave_sgprs)
 816                         adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
 817         }
 818
 819         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
 820         mutex_unlock(&adev->grbm_idx_mutex);
 821
 822         pm_runtime_mark_last_busy(adev->ddev->dev);
 823         pm_runtime_put_autosuspend(adev->ddev->dev);
 824
 825         while (size) {
 826                 uint32_t value;
 827
 828                 value = data[offset++];
 829                 r = put_user(value, (uint32_t *)buf);
 830                 if (r) {
 831                         result = r;
 832                         goto err;
 833                 }
 834
 835                 result += 4;
 836                 buf += 4;
 837                 size -= 4;
 838         }
 839
 840 err:
 841         kfree(data);
 842         return result;
 843 }
 844
 845 /**
 846  * amdgpu_debugfs_regs_gfxoff_write - Enable/disable GFXOFF
 847  *
 848  * @f: open file handle
 849  * @buf: User buffer to write data from
 850  * @size: Number of bytes to write
 851  * @pos:  Offset to seek to
 852  *
 853  * Write a 32-bit zero to disable or a 32-bit non-zero to enable
 854  */
 855 static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
 856                                          size_t size, loff_t *pos)
 857 {
 858         struct amdgpu_device *adev = file_inode(f)->i_private;
 859         ssize_t result = 0;
 860         int r;
 861
 862         if (size & 0x3 || *pos & 0x3)
 863                 return -EINVAL;
 864
 865         r = pm_runtime_get_sync(adev->ddev->dev);
 866         if (r < 0)
 867                 return r;
 868
 869         while (size) {
 870                 uint32_t value;
 871
 872                 r = get_user(value, (uint32_t *)buf);
 873                 if (r) {
 874                         pm_runtime_mark_last_busy(adev->ddev->dev);
 875                         pm_runtime_put_autosuspend(adev->ddev->dev);
 876                         return r;
 877                 }
 878
 879                 amdgpu_gfx_off_ctrl(adev, value ? true : false);
 880
 881                 result += 4;
 882                 buf += 4;
 883                 *pos += 4;
 884                 size -= 4;
 885         }
 886
 887         pm_runtime_mark_last_busy(adev->ddev->dev);
 888         pm_runtime_put_autosuspend(adev->ddev->dev);
 889
 890         return result;
 891 }
 892
 893
 894 static const struct file_operations amdgpu_debugfs_regs_fops = {
 895         .owner = THIS_MODULE,
 896         .read = amdgpu_debugfs_regs_read,
 897         .write = amdgpu_debugfs_regs_write,
 898         .llseek = default_llseek
 899 };
 900 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
 901         .owner = THIS_MODULE,
 902         .read = amdgpu_debugfs_regs_didt_read,
 903         .write = amdgpu_debugfs_regs_didt_write,
 904         .llseek = default_llseek
 905 };
 906 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
 907         .owner = THIS_MODULE,
 908         .read = amdgpu_debugfs_regs_pcie_read,
 909         .write = amdgpu_debugfs_regs_pcie_write,
 910         .llseek = default_llseek
 911 };
 912 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
 913         .owner = THIS_MODULE,
 914         .read = amdgpu_debugfs_regs_smc_read,
 915         .write = amdgpu_debugfs_regs_smc_write,
 916         .llseek = default_llseek
 917 };
 918
 919 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
 920         .owner = THIS_MODULE,
 921         .read = amdgpu_debugfs_gca_config_read,
 922         .llseek = default_llseek
 923 };
 924
 925 static const struct file_operations amdgpu_debugfs_sensors_fops = {
 926         .owner = THIS_MODULE,
 927         .read = amdgpu_debugfs_sensor_read,
 928         .llseek = default_llseek
 929 };
 930
 931 static const struct file_operations amdgpu_debugfs_wave_fops = {
 932         .owner = THIS_MODULE,
 933         .read = amdgpu_debugfs_wave_read,
 934         .llseek = default_llseek
 935 };
 936 static const struct file_operations amdgpu_debugfs_gpr_fops = {
 937         .owner = THIS_MODULE,
 938         .read = amdgpu_debugfs_gpr_read,
 939         .llseek = default_llseek
 940 };
 941
 942 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
 943         .owner = THIS_MODULE,
 944         .write = amdgpu_debugfs_gfxoff_write,
 945 };
 946
 947 static const struct file_operations *debugfs_regs[] = {
 948         &amdgpu_debugfs_regs_fops,
 949         &amdgpu_debugfs_regs_didt_fops,
 950         &amdgpu_debugfs_regs_pcie_fops,
 951         &amdgpu_debugfs_regs_smc_fops,
 952         &amdgpu_debugfs_gca_config_fops,
 953         &amdgpu_debugfs_sensors_fops,
 954         &amdgpu_debugfs_wave_fops,
 955         &amdgpu_debugfs_gpr_fops,
 956         &amdgpu_debugfs_gfxoff_fops,
 957 };
 958
 959 static const char *debugfs_regs_names[] = {
 960         "amdgpu_regs",
 961         "amdgpu_regs_didt",
 962         "amdgpu_regs_pcie",
 963         "amdgpu_regs_smc",
 964         "amdgpu_gca_config",
 965         "amdgpu_sensors",
 966         "amdgpu_wave",
 967         "amdgpu_gpr",
 968         "amdgpu_gfxoff",
 969 };
 970
 971 /**
 972  * amdgpu_debugfs_regs_init -   Initialize debugfs entries that provide
 973  *                                                              register access.
 974  *
 975  * @adev: The device to attach the debugfs entries to
 976  */
 977 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
 978 {
 979         struct drm_minor *minor = adev->ddev->primary;
 980         struct dentry *ent, *root = minor->debugfs_root;
 981         unsigned int i;
 982
 983         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
 984                 ent = debugfs_create_file(debugfs_regs_names[i],
 985                                           S_IFREG | S_IRUGO, root,
 986                                           adev, debugfs_regs[i]);
 987                 if (!i && !IS_ERR_OR_NULL(ent))
 988                         i_size_write(ent->d_inode, adev->rmmio_size);
 989                 adev->debugfs_regs[i] = ent;
 990         }
 991
 992         return 0;
 993 }
 994
 995 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
 996 {
 997         struct drm_info_node *node = (struct drm_info_node *) m->private;
 998         struct drm_device *dev = node->minor->dev;
 999         struct amdgpu_device *adev = dev->dev_private;
1000         int r = 0, i;
1001
1002         r = pm_runtime_get_sync(dev->dev);
1003         if (r < 0)
1004                 return r;
1005
1006         /* Avoid accidently unparking the sched thread during GPU reset */
1007         mutex_lock(&adev->lock_reset);
1008
1009         /* hold on the scheduler */
1010         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1011                 struct amdgpu_ring *ring = adev->rings[i];
1012
1013                 if (!ring || !ring->sched.thread)
1014                         continue;
1015                 kthread_park(ring->sched.thread);
1016         }
1017
1018         seq_printf(m, "run ib test:\n");
1019         r = amdgpu_ib_ring_tests(adev);
1020         if (r)
1021                 seq_printf(m, "ib ring tests failed (%d).\n", r);
1022         else
1023                 seq_printf(m, "ib ring tests passed.\n");
1024
1025         /* go on the scheduler */
1026         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1027                 struct amdgpu_ring *ring = adev->rings[i];
1028
1029                 if (!ring || !ring->sched.thread)
1030                         continue;
1031                 kthread_unpark(ring->sched.thread);
1032         }
1033
1034         mutex_unlock(&adev->lock_reset);
1035
1036         pm_runtime_mark_last_busy(dev->dev);
1037         pm_runtime_put_autosuspend(dev->dev);
1038
1039         return 0;
1040 }
1041
1042 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
1043 {
1044         struct drm_info_node *node = (struct drm_info_node *) m->private;
1045         struct drm_device *dev = node->minor->dev;
1046         struct amdgpu_device *adev = dev->dev_private;
1047
1048         seq_write(m, adev->bios, adev->bios_size);
1049         return 0;
1050 }
1051
1052 static int amdgpu_debugfs_evict_vram(struct seq_file *m, void *data)
1053 {
1054         struct drm_info_node *node = (struct drm_info_node *)m->private;
1055         struct drm_device *dev = node->minor->dev;
1056         struct amdgpu_device *adev = dev->dev_private;
1057         int r;
1058
1059         r = pm_runtime_get_sync(dev->dev);
1060         if (r < 0)
1061                 return r;
1062
1063         seq_printf(m, "(%d)\n", amdgpu_bo_evict_vram(adev));
1064
1065         pm_runtime_mark_last_busy(dev->dev);
1066         pm_runtime_put_autosuspend(dev->dev);
1067
1068         return 0;
1069 }
1070
1071 static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data)
1072 {
1073         struct drm_info_node *node = (struct drm_info_node *)m->private;
1074         struct drm_device *dev = node->minor->dev;
1075         struct amdgpu_device *adev = dev->dev_private;
1076         int r;
1077
1078         r = pm_runtime_get_sync(dev->dev);
1079         if (r < 0)
1080                 return r;
1081
1082         seq_printf(m, "(%d)\n", ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_TT));
1083
1084         pm_runtime_mark_last_busy(dev->dev);
1085         pm_runtime_put_autosuspend(dev->dev);
1086
1087         return 0;
1088 }
1089
1090 static const struct drm_info_list amdgpu_debugfs_list[] = {
1091         {"amdgpu_vbios", amdgpu_debugfs_get_vbios_dump},
1092         {"amdgpu_test_ib", &amdgpu_debugfs_test_ib},
1093         {"amdgpu_evict_vram", &amdgpu_debugfs_evict_vram},
1094         {"amdgpu_evict_gtt", &amdgpu_debugfs_evict_gtt},
1095 };
1096
1097 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1098                                           struct dma_fence **fences)
1099 {
1100         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1101         uint32_t sync_seq, last_seq;
1102
1103         last_seq = atomic_read(&ring->fence_drv.last_seq);
1104         sync_seq = ring->fence_drv.sync_seq;
1105
1106         last_seq &= drv->num_fences_mask;
1107         sync_seq &= drv->num_fences_mask;
1108
1109         do {
1110                 struct dma_fence *fence, **ptr;
1111
1112                 ++last_seq;
1113                 last_seq &= drv->num_fences_mask;
1114                 ptr = &drv->fences[last_seq];
1115
1116                 fence = rcu_dereference_protected(*ptr, 1);
1117                 RCU_INIT_POINTER(*ptr, NULL);
1118
1119                 if (!fence)
1120                         continue;
1121
1122                 fences[last_seq] = fence;
1123
1124         } while (last_seq != sync_seq);
1125 }
1126
1127 static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1128                                             int length)
1129 {
1130         int i;
1131         struct dma_fence *fence;
1132
1133         for (i = 0; i < length; i++) {
1134                 fence = fences[i];
1135                 if (!fence)
1136                         continue;
1137                 dma_fence_signal(fence);
1138                 dma_fence_put(fence);
1139         }
1140 }
1141
1142 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1143 {
1144         struct drm_sched_job *s_job;
1145         struct dma_fence *fence;
1146
1147         spin_lock(&sched->job_list_lock);
1148         list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
1149                 fence = sched->ops->run_job(s_job);
1150                 dma_fence_put(fence);
1151         }
1152         spin_unlock(&sched->job_list_lock);
1153 }
1154
1155 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1156 {
1157         struct amdgpu_job *job;
1158         struct drm_sched_job *s_job;
1159         uint32_t preempt_seq;
1160         struct dma_fence *fence, **ptr;
1161         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1162         struct drm_gpu_scheduler *sched = &ring->sched;
1163
1164         if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1165                 return;
1166
1167         preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1168         if (preempt_seq <= atomic_read(&drv->last_seq))
1169                 return;
1170
1171         preempt_seq &= drv->num_fences_mask;
1172         ptr = &drv->fences[preempt_seq];
1173         fence = rcu_dereference_protected(*ptr, 1);
1174
1175         spin_lock(&sched->job_list_lock);
1176         list_for_each_entry(s_job, &sched->ring_mirror_list, node) {
1177                 job = to_amdgpu_job(s_job);
1178                 if (job->fence == fence)
1179                         /* mark the job as preempted */
1180                         job->preemption_status |= AMDGPU_IB_PREEMPTED;
1181         }
1182         spin_unlock(&sched->job_list_lock);
1183 }
1184
1185 static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1186 {
1187         int r, resched, length;
1188         struct amdgpu_ring *ring;
1189         struct dma_fence **fences = NULL;
1190         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1191
1192         if (val >= AMDGPU_MAX_RINGS)
1193                 return -EINVAL;
1194
1195         ring = adev->rings[val];
1196
1197         if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1198                 return -EINVAL;
1199
1200         /* the last preemption failed */
1201         if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1202                 return -EBUSY;
1203
1204         length = ring->fence_drv.num_fences_mask + 1;
1205         fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1206         if (!fences)
1207                 return -ENOMEM;
1208
1209         /* Avoid accidently unparking the sched thread during GPU reset */
1210         mutex_lock(&adev->lock_reset);
1211
1212         /* stop the scheduler */
1213         kthread_park(ring->sched.thread);
1214
1215         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1216
1217         /* preempt the IB */
1218         r = amdgpu_ring_preempt_ib(ring);
1219         if (r) {
1220                 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1221                 goto failure;
1222         }
1223
1224         amdgpu_fence_process(ring);
1225
1226         if (atomic_read(&ring->fence_drv.last_seq) !=
1227             ring->fence_drv.sync_seq) {
1228                 DRM_INFO("ring %d was preempted\n", ring->idx);
1229
1230                 amdgpu_ib_preempt_mark_partial_job(ring);
1231
1232                 /* swap out the old fences */
1233                 amdgpu_ib_preempt_fences_swap(ring, fences);
1234
1235                 amdgpu_fence_driver_force_completion(ring);
1236
1237                 /* resubmit unfinished jobs */
1238                 amdgpu_ib_preempt_job_recovery(&ring->sched);
1239
1240                 /* wait for jobs finished */
1241                 amdgpu_fence_wait_empty(ring);
1242
1243                 /* signal the old fences */
1244                 amdgpu_ib_preempt_signal_fences(fences, length);
1245         }
1246
1247 failure:
1248         /* restart the scheduler */
1249         kthread_unpark(ring->sched.thread);
1250
1251         mutex_unlock(&adev->lock_reset);
1252
1253         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1254
1255         kfree(fences);
1256
1257         return 0;
1258 }
1259
1260 static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1261 {
1262         int ret = 0;
1263         uint32_t max_freq, min_freq;
1264         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1265
1266         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1267                 return -EINVAL;
1268
1269         ret = pm_runtime_get_sync(adev->ddev->dev);
1270         if (ret < 0)
1271                 return ret;
1272
1273         if (is_support_sw_smu(adev)) {
1274                 ret = smu_get_dpm_freq_range(&adev->smu, SMU_SCLK, &min_freq, &max_freq, true);
1275                 if (ret || val > max_freq || val < min_freq)
1276                         return -EINVAL;
1277                 ret = smu_set_soft_freq_range(&adev->smu, SMU_SCLK, (uint32_t)val, (uint32_t)val, true);
1278         } else {
1279                 return 0;
1280         }
1281
1282         pm_runtime_mark_last_busy(adev->ddev->dev);
1283         pm_runtime_put_autosuspend(adev->ddev->dev);
1284
1285         if (ret)
1286                 return -EINVAL;
1287
1288         return 0;
1289 }
1290
1291 DEFINE_SIMPLE_ATTRIBUTE(fops_ib_preempt, NULL,
1292                         amdgpu_debugfs_ib_preempt, "%llu\n");
1293
1294 DEFINE_SIMPLE_ATTRIBUTE(fops_sclk_set, NULL,
1295                         amdgpu_debugfs_sclk_set, "%llu\n");
1296
1297 extern void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
1298 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1299 {
1300         int r, i;
1301
1302         adev->debugfs_preempt =
1303                 debugfs_create_file("amdgpu_preempt_ib", 0600,
1304                                     adev->ddev->primary->debugfs_root, adev,
1305                                     &fops_ib_preempt);
1306         if (!(adev->debugfs_preempt)) {
1307                 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
1308                 return -EIO;
1309         }
1310
1311         adev->smu.debugfs_sclk =
1312                 debugfs_create_file("amdgpu_force_sclk", 0200,
1313                                     adev->ddev->primary->debugfs_root, adev,
1314                                     &fops_sclk_set);
1315         if (!(adev->smu.debugfs_sclk)) {
1316                 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
1317                 return -EIO;
1318         }
1319
1320         /* Register debugfs entries for amdgpu_ttm */
1321         r = amdgpu_ttm_debugfs_init(adev);
1322         if (r) {
1323                 DRM_ERROR("Failed to init debugfs\n");
1324                 return r;
1325         }
1326
1327         r = amdgpu_debugfs_pm_init(adev);
1328         if (r) {
1329                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1330                 return r;
1331         }
1332
1333         if (amdgpu_debugfs_sa_init(adev)) {
1334                 dev_err(adev->dev, "failed to register debugfs file for SA\n");
1335         }
1336
1337         if (amdgpu_debugfs_fence_init(adev))
1338                 dev_err(adev->dev, "fence debugfs file creation failed\n");
1339
1340         r = amdgpu_debugfs_gem_init(adev);
1341         if (r)
1342                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1343
1344         r = amdgpu_debugfs_regs_init(adev);
1345         if (r)
1346                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1347
1348         r = amdgpu_debugfs_firmware_init(adev);
1349         if (r)
1350                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
1351
1352 #if defined(CONFIG_DRM_AMD_DC)
1353         if (amdgpu_device_has_dc_support(adev)) {
1354                 if (dtn_debugfs_init(adev))
1355                         DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
1356         }
1357 #endif
1358
1359         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1360                 struct amdgpu_ring *ring = adev->rings[i];
1361
1362                 if (!ring)
1363                         continue;
1364
1365                 if (amdgpu_debugfs_ring_init(adev, ring)) {
1366                         DRM_ERROR("Failed to register debugfs file for rings !\n");
1367                 }
1368         }
1369
1370         amdgpu_ras_debugfs_create_all(adev);
1371
1372         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,
1373                                         ARRAY_SIZE(amdgpu_debugfs_list));
1374 }
1375
1376 #else
1377 int amdgpu_debugfs_init(struct amdgpu_device *adev)
1378 {
1379         return 0;
1380 }
1381 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1382 {
1383         return 0;
1384 }
1385 #endif