drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 103 {
 104         struct ras_err_data err_data = {0, 0, 0, NULL};
 105         struct eeprom_table_record err_rec;
 106
 107         if ((address >= adev->gmc.mc_vram_size) ||
 108             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 109                 dev_warn(adev->dev,
 110                          "RAS WARN: input address 0x%llx is invalid.\n",
 111                          address);
 112                 return -EINVAL;
 113         }
 114
 115         if (amdgpu_ras_check_bad_page(adev, address)) {
 116                 dev_warn(adev->dev,
 117                          "RAS WARN: 0x%llx has already been marked as bad page!\n",
 118                          address);
 119                 return 0;
 120         }
 121
 122         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 123
 124         err_rec.address = address;
 125         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 126         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 127         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 128
 129         err_data.err_addr = &err_rec;
 130         err_data.err_addr_cnt = 1;
 131
 132         if (amdgpu_bad_page_threshold != 0) {
 133                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 134                                          err_data.err_addr_cnt);
 135                 amdgpu_ras_save_bad_pages(adev);
 136         }
 137
 138         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 139         dev_warn(adev->dev, "Clear EEPROM:\n");
 140         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 141
 142         return 0;
 143 }
 144
 145 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 146                                         size_t size, loff_t *pos)
 147 {
 148         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 149         struct ras_query_if info = {
 150                 .head = obj->head,
 151         };
 152         ssize_t s;
 153         char val[128];
 154
 155         if (amdgpu_ras_query_error_status(obj->adev, &info))
 156                 return -EINVAL;
 157
 158         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 159                         "ue", info.ue_count,
 160                         "ce", info.ce_count);
 161         if (*pos >= s)
 162                 return 0;
 163
 164         s -= *pos;
 165         s = min_t(u64, s, size);
 166
 167
 168         if (copy_to_user(buf, &val[*pos], s))
 169                 return -EINVAL;
 170
 171         *pos += s;
 172
 173         return s;
 174 }
 175
 176 static const struct file_operations amdgpu_ras_debugfs_ops = {
 177         .owner = THIS_MODULE,
 178         .read = amdgpu_ras_debugfs_read,
 179         .write = NULL,
 180         .llseek = default_llseek
 181 };
 182
 183 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 184 {
 185         int i;
 186
 187         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 188                 *block_id = i;
 189                 if (strcmp(name, ras_block_str(i)) == 0)
 190                         return 0;
 191         }
 192         return -EINVAL;
 193 }
 194
 195 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 196                 const char __user *buf, size_t size,
 197                 loff_t *pos, struct ras_debug_if *data)
 198 {
 199         ssize_t s = min_t(u64, 64, size);
 200         char str[65];
 201         char block_name[33];
 202         char err[9] = "ue";
 203         int op = -1;
 204         int block_id;
 205         uint32_t sub_block;
 206         u64 address, value;
 207
 208         if (*pos)
 209                 return -EINVAL;
 210         *pos = size;
 211
 212         memset(str, 0, sizeof(str));
 213         memset(data, 0, sizeof(*data));
 214
 215         if (copy_from_user(str, buf, s))
 216                 return -EINVAL;
 217
 218         if (sscanf(str, "disable %32s", block_name) == 1)
 219                 op = 0;
 220         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 221                 op = 1;
 222         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 223                 op = 2;
 224         else if (strstr(str, "retire_page") != NULL)
 225                 op = 3;
 226         else if (str[0] && str[1] && str[2] && str[3])
 227                 /* ascii string, but commands are not matched. */
 228                 return -EINVAL;
 229
 230         if (op != -1) {
 231                 if (op == 3) {
 232                         if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
 233                             sscanf(str, "%*s %llu", &address) != 1)
 234                                 return -EINVAL;
 235
 236                         data->op = op;
 237                         data->inject.address = address;
 238
 239                         return 0;
 240                 }
 241
 242                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 243                         return -EINVAL;
 244
 245                 data->head.block = block_id;
 246                 /* only ue and ce errors are supported */
 247                 if (!memcmp("ue", err, 2))
 248                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 249                 else if (!memcmp("ce", err, 2))
 250                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 251                 else
 252                         return -EINVAL;
 253
 254                 data->op = op;
 255
 256                 if (op == 2) {
 257                         if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
 258                                    &sub_block, &address, &value) != 3 &&
 259                             sscanf(str, "%*s %*s %*s %u %llu %llu",
 260                                    &sub_block, &address, &value) != 3)
 261                                 return -EINVAL;
 262                         data->head.sub_block_index = sub_block;
 263                         data->inject.address = address;
 264                         data->inject.value = value;
 265                 }
 266         } else {
 267                 if (size < sizeof(*data))
 268                         return -EINVAL;
 269
 270                 if (copy_from_user(data, buf, sizeof(*data)))
 271                         return -EINVAL;
 272         }
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * DOC: AMDGPU RAS debugfs control interface
 279  *
 280  * The control interface accepts struct ras_debug_if which has two members.
 281  *
 282  * First member: ras_debug_if::head or ras_debug_if::inject.
 283  *
 284  * head is used to indicate which IP block will be under control.
 285  *
 286  * head has four members, they are block, type, sub_block_index, name.
 287  * block: which IP will be under control.
 288  * type: what kind of error will be enabled/disabled/injected.
 289  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 290  * name: the name of IP.
 291  *
 292  * inject has two more members than head, they are address, value.
 293  * As their names indicate, inject operation will write the
 294  * value to the address.
 295  *
 296  * The second member: struct ras_debug_if::op.
 297  * It has three kinds of operations.
 298  *
 299  * - 0: disable RAS on the block. Take ::head as its data.
 300  * - 1: enable RAS on the block. Take ::head as its data.
 301  * - 2: inject errors on the block. Take ::inject as its data.
 302  *
 303  * How to use the interface?
 304  *
 305  * In a program
 306  *
 307  * Copy the struct ras_debug_if in your code and initialize it.
 308  * Write the struct to the control interface.
 309  *
 310  * From shell
 311  *
 312  * .. code-block:: bash
 313  *
 314  *      echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 315  *      echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 316  *      echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
 317  *
 318  * Where N, is the card which you want to affect.
 319  *
 320  * "disable" requires only the block.
 321  * "enable" requires the block and error type.
 322  * "inject" requires the block, error type, address, and value.
 323  * The block is one of: umc, sdma, gfx, etc.
 324  *      see ras_block_string[] for details
 325  * The error type is one of: ue, ce, where,
 326  *      ue is multi-uncorrectable
 327  *      ce is single-correctable
 328  * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
 329  * The address and value are hexadecimal numbers, leading 0x is optional.
 330  *
 331  * For instance,
 332  *
 333  * .. code-block:: bash
 334  *
 335  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 336  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 337  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 338  *
 339  * How to check the result of the operation?
 340  *
 341  * To check disable/enable, see "ras" features at,
 342  * /sys/class/drm/card[0/1/2...]/device/ras/features
 343  *
 344  * To check inject, see the corresponding error count at,
 345  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
 346  *
 347  * .. note::
 348  *      Operations are only allowed on blocks which are supported.
 349  *      Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
 350  *      to see which blocks support RAS on a particular asic.
 351  *
 352  */
 353 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 354                 size_t size, loff_t *pos)
 355 {
 356         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 357         struct ras_debug_if data;
 358         int ret = 0;
 359
 360         if (!amdgpu_ras_get_error_query_ready(adev)) {
 361                 dev_warn(adev->dev, "RAS WARN: error injection "
 362                                 "currently inaccessible\n");
 363                 return size;
 364         }
 365
 366         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 367         if (ret)
 368                 return -EINVAL;
 369
 370         if (data.op == 3) {
 371                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 372                 if (!ret)
 373                         return size;
 374                 else
 375                         return ret;
 376         }
 377
 378         if (!amdgpu_ras_is_supported(adev, data.head.block))
 379                 return -EINVAL;
 380
 381         switch (data.op) {
 382         case 0:
 383                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 384                 break;
 385         case 1:
 386                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 387                 break;
 388         case 2:
 389                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 390                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 391                         dev_warn(adev->dev, "RAS WARN: input address "
 392                                         "0x%llx is invalid.",
 393                                         data.inject.address);
 394                         ret = -EINVAL;
 395                         break;
 396                 }
 397
 398                 /* umc ce/ue error injection for a bad page is not allowed */
 399                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 400                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 401                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 402                                         "as bad before error injection!\n",
 403                                         data.inject.address);
 404                         break;
 405                 }
 406
 407                 /* data.inject.address is offset instead of absolute gpu address */
 408                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 409                 break;
 410         default:
 411                 ret = -EINVAL;
 412                 break;
 413         }
 414
 415         if (ret)
 416                 return -EINVAL;
 417
 418         return size;
 419 }
 420
 421 /**
 422  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 423  *
 424  * Some boards contain an EEPROM which is used to persistently store a list of
 425  * bad pages which experiences ECC errors in vram.  This interface provides
 426  * a way to reset the EEPROM, e.g., after testing error injection.
 427  *
 428  * Usage:
 429  *
 430  * .. code-block:: bash
 431  *
 432  *      echo 1 > ../ras/ras_eeprom_reset
 433  *
 434  * will reset EEPROM table to 0 entries.
 435  *
 436  */
 437 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 438                 size_t size, loff_t *pos)
 439 {
 440         struct amdgpu_device *adev =
 441                 (struct amdgpu_device *)file_inode(f)->i_private;
 442         int ret;
 443
 444         ret = amdgpu_ras_eeprom_reset_table(
 445                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 446
 447         if (ret == 1) {
 448                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 449                 return size;
 450         } else {
 451                 return -EIO;
 452         }
 453 }
 454
 455 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 456         .owner = THIS_MODULE,
 457         .read = NULL,
 458         .write = amdgpu_ras_debugfs_ctrl_write,
 459         .llseek = default_llseek
 460 };
 461
 462 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 463         .owner = THIS_MODULE,
 464         .read = NULL,
 465         .write = amdgpu_ras_debugfs_eeprom_write,
 466         .llseek = default_llseek
 467 };
 468
 469 /**
 470  * DOC: AMDGPU RAS sysfs Error Count Interface
 471  *
 472  * It allows the user to read the error count for each IP block on the gpu through
 473  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 474  *
 475  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 476  * (ce) error counts.
 477  *
 478  * The format of one line is below,
 479  *
 480  * [ce|ue]: count
 481  *
 482  * Example:
 483  *
 484  * .. code-block:: bash
 485  *
 486  *      ue: 0
 487  *      ce: 1
 488  *
 489  */
 490 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 491                 struct device_attribute *attr, char *buf)
 492 {
 493         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 494         struct ras_query_if info = {
 495                 .head = obj->head,
 496         };
 497
 498         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 499                 return sysfs_emit(buf, "Query currently inaccessible\n");
 500
 501         if (amdgpu_ras_query_error_status(obj->adev, &info))
 502                 return -EINVAL;
 503
 504
 505         if (obj->adev->asic_type == CHIP_ALDEBARAN) {
 506                 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
 507                         DRM_WARN("Failed to reset error counter and error status");
 508         }
 509
 510         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 511                           "ce", info.ce_count);
 512 }
 513
 514 /* obj begin */
 515
 516 #define get_obj(obj) do { (obj)->use++; } while (0)
 517 #define alive_obj(obj) ((obj)->use)
 518
 519 static inline void put_obj(struct ras_manager *obj)
 520 {
 521         if (obj && (--obj->use == 0))
 522                 list_del(&obj->node);
 523         if (obj && (obj->use < 0))
 524                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 525 }
 526
 527 /* make one obj and return it. */
 528 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 529                 struct ras_common_if *head)
 530 {
 531         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 532         struct ras_manager *obj;
 533
 534         if (!adev->ras_features || !con)
 535                 return NULL;
 536
 537         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 538                 return NULL;
 539
 540         obj = &con->objs[head->block];
 541         /* already exist. return obj? */
 542         if (alive_obj(obj))
 543                 return NULL;
 544
 545         obj->head = *head;
 546         obj->adev = adev;
 547         list_add(&obj->node, &con->head);
 548         get_obj(obj);
 549
 550         return obj;
 551 }
 552
 553 /* return an obj equal to head, or the first when head is NULL */
 554 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 555                 struct ras_common_if *head)
 556 {
 557         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 558         struct ras_manager *obj;
 559         int i;
 560
 561         if (!adev->ras_features || !con)
 562                 return NULL;
 563
 564         if (head) {
 565                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 566                         return NULL;
 567
 568                 obj = &con->objs[head->block];
 569
 570                 if (alive_obj(obj)) {
 571                         WARN_ON(head->block != obj->head.block);
 572                         return obj;
 573                 }
 574         } else {
 575                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 576                         obj = &con->objs[i];
 577                         if (alive_obj(obj)) {
 578                                 WARN_ON(i != obj->head.block);
 579                                 return obj;
 580                         }
 581                 }
 582         }
 583
 584         return NULL;
 585 }
 586 /* obj end */
 587
 588 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 589                                          const char* invoke_type,
 590                                          const char* block_name,
 591                                          enum ta_ras_status ret)
 592 {
 593         switch (ret) {
 594         case TA_RAS_STATUS__SUCCESS:
 595                 return;
 596         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 597                 dev_warn(adev->dev,
 598                         "RAS WARN: %s %s currently unavailable\n",
 599                         invoke_type,
 600                         block_name);
 601                 break;
 602         default:
 603                 dev_err(adev->dev,
 604                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 605                         invoke_type,
 606                         block_name,
 607                         ret);
 608         }
 609 }
 610
 611 /* feature ctl begin */
 612 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 613                 struct ras_common_if *head)
 614 {
 615         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 616
 617         return con->hw_supported & BIT(head->block);
 618 }
 619
 620 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 621                 struct ras_common_if *head)
 622 {
 623         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 624
 625         return con->features & BIT(head->block);
 626 }
 627
 628 /*
 629  * if obj is not created, then create one.
 630  * set feature enable flag.
 631  */
 632 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 633                 struct ras_common_if *head, int enable)
 634 {
 635         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 636         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 637
 638         /* If hardware does not support ras, then do not create obj.
 639          * But if hardware support ras, we can create the obj.
 640          * Ras framework checks con->hw_supported to see if it need do
 641          * corresponding initialization.
 642          * IP checks con->support to see if it need disable ras.
 643          */
 644         if (!amdgpu_ras_is_feature_allowed(adev, head))
 645                 return 0;
 646         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 647                 return 0;
 648
 649         if (enable) {
 650                 if (!obj) {
 651                         obj = amdgpu_ras_create_obj(adev, head);
 652                         if (!obj)
 653                                 return -EINVAL;
 654                 } else {
 655                         /* In case we create obj somewhere else */
 656                         get_obj(obj);
 657                 }
 658                 con->features |= BIT(head->block);
 659         } else {
 660                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 661                         con->features &= ~BIT(head->block);
 662                         put_obj(obj);
 663                 }
 664         }
 665
 666         return 0;
 667 }
 668
 669 /* wrapper of psp_ras_enable_features */
 670 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 671                 struct ras_common_if *head, bool enable)
 672 {
 673         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 674         union ta_ras_cmd_input *info;
 675         int ret;
 676
 677         if (!con)
 678                 return -EINVAL;
 679
 680         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 681         if (!info)
 682                 return -ENOMEM;
 683
 684         if (!enable) {
 685                 info->disable_features = (struct ta_ras_disable_features_input) {
 686                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 687                         .error_type = amdgpu_ras_error_to_ta(head->type),
 688                 };
 689         } else {
 690                 info->enable_features = (struct ta_ras_enable_features_input) {
 691                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 692                         .error_type = amdgpu_ras_error_to_ta(head->type),
 693                 };
 694         }
 695
 696         /* Do not enable if it is not allowed. */
 697         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 698         /* Are we alerady in that state we are going to set? */
 699         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 700                 ret = 0;
 701                 goto out;
 702         }
 703
 704         if (!amdgpu_ras_intr_triggered()) {
 705                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 706                 if (ret) {
 707                         amdgpu_ras_parse_status_code(adev,
 708                                                      enable ? "enable":"disable",
 709                                                      ras_block_str(head->block),
 710                                                     (enum ta_ras_status)ret);
 711                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 712                                 ret = -EAGAIN;
 713                         else
 714                                 ret = -EINVAL;
 715
 716                         goto out;
 717                 }
 718         }
 719
 720         /* setup the obj */
 721         __amdgpu_ras_feature_enable(adev, head, enable);
 722         ret = 0;
 723 out:
 724         kfree(info);
 725         return ret;
 726 }
 727
 728 /* Only used in device probe stage and called only once. */
 729 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 730                 struct ras_common_if *head, bool enable)
 731 {
 732         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 733         int ret;
 734
 735         if (!con)
 736                 return -EINVAL;
 737
 738         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 739                 if (enable) {
 740                         /* There is no harm to issue a ras TA cmd regardless of
 741                          * the currecnt ras state.
 742                          * If current state == target state, it will do nothing
 743                          * But sometimes it requests driver to reset and repost
 744                          * with error code -EAGAIN.
 745                          */
 746                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 747                         /* With old ras TA, we might fail to enable ras.
 748                          * Log it and just setup the object.
 749                          * TODO need remove this WA in the future.
 750                          */
 751                         if (ret == -EINVAL) {
 752                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 753                                 if (!ret)
 754                                         dev_info(adev->dev,
 755                                                 "RAS INFO: %s setup object\n",
 756                                                 ras_block_str(head->block));
 757                         }
 758                 } else {
 759                         /* setup the object then issue a ras TA disable cmd.*/
 760                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 761                         if (ret)
 762                                 return ret;
 763
 764                         /* gfx block ras dsiable cmd must send to ras-ta */
 765                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 766                                 con->features |= BIT(head->block);
 767
 768                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 769
 770                         /* clean gfx block ras features flag */
 771                         if (adev->ras_features && head->block == AMDGPU_RAS_BLOCK__GFX)
 772                                 con->features &= ~BIT(head->block);
 773                 }
 774         } else
 775                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 776
 777         return ret;
 778 }
 779
 780 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 781                 bool bypass)
 782 {
 783         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 784         struct ras_manager *obj, *tmp;
 785
 786         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 787                 /* bypass psp.
 788                  * aka just release the obj and corresponding flags
 789                  */
 790                 if (bypass) {
 791                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 792                                 break;
 793                 } else {
 794                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 795                                 break;
 796                 }
 797         }
 798
 799         return con->features;
 800 }
 801
 802 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 803                 bool bypass)
 804 {
 805         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 806         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 807         int i;
 808         const enum amdgpu_ras_error_type default_ras_type =
 809                 AMDGPU_RAS_ERROR__NONE;
 810
 811         for (i = 0; i < ras_block_count; i++) {
 812                 struct ras_common_if head = {
 813                         .block = i,
 814                         .type = default_ras_type,
 815                         .sub_block_index = 0,
 816                 };
 817                 strcpy(head.name, ras_block_str(i));
 818                 if (bypass) {
 819                         /*
 820                          * bypass psp. vbios enable ras for us.
 821                          * so just create the obj
 822                          */
 823                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 824                                 break;
 825                 } else {
 826                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 827                                 break;
 828                 }
 829         }
 830
 831         return con->features;
 832 }
 833 /* feature ctl end */
 834
 835 /* query/inject/cure begin */
 836 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 837         struct ras_query_if *info)
 838 {
 839         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 840         struct ras_err_data err_data = {0, 0, 0, NULL};
 841         int i;
 842
 843         if (!obj)
 844                 return -EINVAL;
 845
 846         switch (info->head.block) {
 847         case AMDGPU_RAS_BLOCK__UMC:
 848                 if (adev->umc.ras_funcs &&
 849                     adev->umc.ras_funcs->query_ras_error_count)
 850                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 851                 /* umc query_ras_error_address is also responsible for clearing
 852                  * error status
 853                  */
 854                 if (adev->umc.ras_funcs &&
 855                     adev->umc.ras_funcs->query_ras_error_address)
 856                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 857                 break;
 858         case AMDGPU_RAS_BLOCK__SDMA:
 859                 if (adev->sdma.funcs->query_ras_error_count) {
 860                         for (i = 0; i < adev->sdma.num_instances; i++)
 861                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 862                                                                         &err_data);
 863                 }
 864                 break;
 865         case AMDGPU_RAS_BLOCK__GFX:
 866                 if (adev->gfx.ras_funcs &&
 867                     adev->gfx.ras_funcs->query_ras_error_count)
 868                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 869
 870                 if (adev->gfx.ras_funcs &&
 871                     adev->gfx.ras_funcs->query_ras_error_status)
 872                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 873                 break;
 874         case AMDGPU_RAS_BLOCK__MMHUB:
 875                 if (adev->mmhub.ras_funcs &&
 876                     adev->mmhub.ras_funcs->query_ras_error_count)
 877                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 878
 879                 if (adev->mmhub.ras_funcs &&
 880                     adev->mmhub.ras_funcs->query_ras_error_status)
 881                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 882                 break;
 883         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 884                 if (adev->nbio.ras_funcs &&
 885                     adev->nbio.ras_funcs->query_ras_error_count)
 886                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 887                 break;
 888         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 889                 if (adev->gmc.xgmi.ras_funcs &&
 890                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 891                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 892                 break;
 893         default:
 894                 break;
 895         }
 896
 897         obj->err_data.ue_count += err_data.ue_count;
 898         obj->err_data.ce_count += err_data.ce_count;
 899
 900         info->ue_count = obj->err_data.ue_count;
 901         info->ce_count = obj->err_data.ce_count;
 902
 903         if (err_data.ce_count) {
 904                 if (adev->smuio.funcs &&
 905                     adev->smuio.funcs->get_socket_id &&
 906                     adev->smuio.funcs->get_die_id) {
 907                         dev_info(adev->dev, "socket: %d, die: %d "
 908                                         "%ld correctable hardware errors "
 909                                         "detected in %s block, no user "
 910                                         "action is needed.\n",
 911                                         adev->smuio.funcs->get_socket_id(adev),
 912                                         adev->smuio.funcs->get_die_id(adev),
 913                                         obj->err_data.ce_count,
 914                                         ras_block_str(info->head.block));
 915                 } else {
 916                         dev_info(adev->dev, "%ld correctable hardware errors "
 917                                         "detected in %s block, no user "
 918                                         "action is needed.\n",
 919                                         obj->err_data.ce_count,
 920                                         ras_block_str(info->head.block));
 921                 }
 922         }
 923         if (err_data.ue_count) {
 924                 if (adev->smuio.funcs &&
 925                     adev->smuio.funcs->get_socket_id &&
 926                     adev->smuio.funcs->get_die_id) {
 927                         dev_info(adev->dev, "socket: %d, die: %d "
 928                                         "%ld uncorrectable hardware errors "
 929                                         "detected in %s block\n",
 930                                         adev->smuio.funcs->get_socket_id(adev),
 931                                         adev->smuio.funcs->get_die_id(adev),
 932                                         obj->err_data.ue_count,
 933                                         ras_block_str(info->head.block));
 934                 } else {
 935                         dev_info(adev->dev, "%ld uncorrectable hardware errors "
 936                                         "detected in %s block\n",
 937                                         obj->err_data.ue_count,
 938                                         ras_block_str(info->head.block));
 939                 }
 940         }
 941
 942         return 0;
 943 }
 944
 945 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 946                 enum amdgpu_ras_block block)
 947 {
 948         if (!amdgpu_ras_is_supported(adev, block))
 949                 return -EINVAL;
 950
 951         switch (block) {
 952         case AMDGPU_RAS_BLOCK__GFX:
 953                 if (adev->gfx.ras_funcs &&
 954                     adev->gfx.ras_funcs->reset_ras_error_count)
 955                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
 956
 957                 if (adev->gfx.ras_funcs &&
 958                     adev->gfx.ras_funcs->reset_ras_error_status)
 959                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
 960                 break;
 961         case AMDGPU_RAS_BLOCK__MMHUB:
 962                 if (adev->mmhub.ras_funcs &&
 963                     adev->mmhub.ras_funcs->reset_ras_error_count)
 964                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
 965                 break;
 966         case AMDGPU_RAS_BLOCK__SDMA:
 967                 if (adev->sdma.funcs->reset_ras_error_count)
 968                         adev->sdma.funcs->reset_ras_error_count(adev);
 969                 break;
 970         default:
 971                 break;
 972         }
 973
 974         return 0;
 975 }
 976
 977 /* Trigger XGMI/WAFL error */
 978 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 979                                  struct ta_ras_trigger_error_input *block_info)
 980 {
 981         int ret;
 982
 983         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 984                 dev_warn(adev->dev, "Failed to disallow df cstate");
 985
 986         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 987                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 988
 989         ret = psp_ras_trigger_error(&adev->psp, block_info);
 990
 991         if (amdgpu_ras_intr_triggered())
 992                 return ret;
 993
 994         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 995                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 996
 997         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 998                 dev_warn(adev->dev, "Failed to allow df cstate");
 999
1000         return ret;
1001 }
1002
1003 /* wrapper of psp_ras_trigger_error */
1004 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1005                 struct ras_inject_if *info)
1006 {
1007         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1008         struct ta_ras_trigger_error_input block_info = {
1009                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
1010                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
1011                 .sub_block_index = info->head.sub_block_index,
1012                 .address = info->address,
1013                 .value = info->value,
1014         };
1015         int ret = 0;
1016
1017         if (!obj)
1018                 return -EINVAL;
1019
1020         /* Calculate XGMI relative offset */
1021         if (adev->gmc.xgmi.num_physical_nodes > 1) {
1022                 block_info.address =
1023                         amdgpu_xgmi_get_relative_phy_addr(adev,
1024                                                           block_info.address);
1025         }
1026
1027         switch (info->head.block) {
1028         case AMDGPU_RAS_BLOCK__GFX:
1029                 if (adev->gfx.ras_funcs &&
1030                     adev->gfx.ras_funcs->ras_error_inject)
1031                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1032                 else
1033                         ret = -EINVAL;
1034                 break;
1035         case AMDGPU_RAS_BLOCK__UMC:
1036         case AMDGPU_RAS_BLOCK__SDMA:
1037         case AMDGPU_RAS_BLOCK__MMHUB:
1038         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1039                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1040                 break;
1041         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1042                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1043                 break;
1044         default:
1045                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1046                          ras_block_str(info->head.block));
1047                 ret = -EINVAL;
1048         }
1049
1050         amdgpu_ras_parse_status_code(adev,
1051                                      "inject",
1052                                      ras_block_str(info->head.block),
1053                                      (enum ta_ras_status)ret);
1054
1055         return ret;
1056 }
1057
1058 /* get the total error counts on all IPs */
1059 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1060                 bool is_ce)
1061 {
1062         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1063         struct ras_manager *obj;
1064         struct ras_err_data data = {0, 0};
1065
1066         if (!adev->ras_features || !con)
1067                 return 0;
1068
1069         list_for_each_entry(obj, &con->head, node) {
1070                 struct ras_query_if info = {
1071                         .head = obj->head,
1072                 };
1073
1074                 if (amdgpu_ras_query_error_status(adev, &info))
1075                         return 0;
1076
1077                 data.ce_count += info.ce_count;
1078                 data.ue_count += info.ue_count;
1079         }
1080
1081         return is_ce ? data.ce_count : data.ue_count;
1082 }
1083 /* query/inject/cure end */
1084
1085
1086 /* sysfs begin */
1087
1088 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1089                 struct ras_badpage **bps, unsigned int *count);
1090
1091 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1092 {
1093         switch (flags) {
1094         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1095                 return "R";
1096         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1097                 return "P";
1098         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1099         default:
1100                 return "F";
1101         }
1102 }
1103
1104 /**
1105  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1106  *
1107  * It allows user to read the bad pages of vram on the gpu through
1108  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1109  *
1110  * It outputs multiple lines, and each line stands for one gpu page.
1111  *
1112  * The format of one line is below,
1113  * gpu pfn : gpu page size : flags
1114  *
1115  * gpu pfn and gpu page size are printed in hex format.
1116  * flags can be one of below character,
1117  *
1118  * R: reserved, this gpu page is reserved and not able to use.
1119  *
1120  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1121  * in next window of page_reserve.
1122  *
1123  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1124  *
1125  * Examples:
1126  *
1127  * .. code-block:: bash
1128  *
1129  *      0x00000001 : 0x00001000 : R
1130  *      0x00000002 : 0x00001000 : P
1131  *
1132  */
1133
1134 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1135                 struct kobject *kobj, struct bin_attribute *attr,
1136                 char *buf, loff_t ppos, size_t count)
1137 {
1138         struct amdgpu_ras *con =
1139                 container_of(attr, struct amdgpu_ras, badpages_attr);
1140         struct amdgpu_device *adev = con->adev;
1141         const unsigned int element_size =
1142                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1143         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1144         unsigned int end = div64_ul(ppos + count - 1, element_size);
1145         ssize_t s = 0;
1146         struct ras_badpage *bps = NULL;
1147         unsigned int bps_count = 0;
1148
1149         memset(buf, 0, count);
1150
1151         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1152                 return 0;
1153
1154         for (; start < end && start < bps_count; start++)
1155                 s += scnprintf(&buf[s], element_size + 1,
1156                                 "0x%08x : 0x%08x : %1s\n",
1157                                 bps[start].bp,
1158                                 bps[start].size,
1159                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1160
1161         kfree(bps);
1162
1163         return s;
1164 }
1165
1166 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1167                 struct device_attribute *attr, char *buf)
1168 {
1169         struct amdgpu_ras *con =
1170                 container_of(attr, struct amdgpu_ras, features_attr);
1171
1172         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1173 }
1174
1175 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1176 {
1177         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1178
1179         sysfs_remove_file_from_group(&adev->dev->kobj,
1180                                 &con->badpages_attr.attr,
1181                                 RAS_FS_NAME);
1182 }
1183
1184 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1185 {
1186         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1187         struct attribute *attrs[] = {
1188                 &con->features_attr.attr,
1189                 NULL
1190         };
1191         struct attribute_group group = {
1192                 .name = RAS_FS_NAME,
1193                 .attrs = attrs,
1194         };
1195
1196         sysfs_remove_group(&adev->dev->kobj, &group);
1197
1198         return 0;
1199 }
1200
1201 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1202                 struct ras_fs_if *head)
1203 {
1204         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1205
1206         if (!obj || obj->attr_inuse)
1207                 return -EINVAL;
1208
1209         get_obj(obj);
1210
1211         memcpy(obj->fs_data.sysfs_name,
1212                         head->sysfs_name,
1213                         sizeof(obj->fs_data.sysfs_name));
1214
1215         obj->sysfs_attr = (struct device_attribute){
1216                 .attr = {
1217                         .name = obj->fs_data.sysfs_name,
1218                         .mode = S_IRUGO,
1219                 },
1220                         .show = amdgpu_ras_sysfs_read,
1221         };
1222         sysfs_attr_init(&obj->sysfs_attr.attr);
1223
1224         if (sysfs_add_file_to_group(&adev->dev->kobj,
1225                                 &obj->sysfs_attr.attr,
1226                                 RAS_FS_NAME)) {
1227                 put_obj(obj);
1228                 return -EINVAL;
1229         }
1230
1231         obj->attr_inuse = 1;
1232
1233         return 0;
1234 }
1235
1236 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1237                 struct ras_common_if *head)
1238 {
1239         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1240
1241         if (!obj || !obj->attr_inuse)
1242                 return -EINVAL;
1243
1244         sysfs_remove_file_from_group(&adev->dev->kobj,
1245                                 &obj->sysfs_attr.attr,
1246                                 RAS_FS_NAME);
1247         obj->attr_inuse = 0;
1248         put_obj(obj);
1249
1250         return 0;
1251 }
1252
1253 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1254 {
1255         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1256         struct ras_manager *obj, *tmp;
1257
1258         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1259                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1260         }
1261
1262         if (amdgpu_bad_page_threshold != 0)
1263                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1264
1265         amdgpu_ras_sysfs_remove_feature_node(adev);
1266
1267         return 0;
1268 }
1269 /* sysfs end */
1270
1271 /**
1272  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1273  *
1274  * Normally when there is an uncorrectable error, the driver will reset
1275  * the GPU to recover.  However, in the event of an unrecoverable error,
1276  * the driver provides an interface to reboot the system automatically
1277  * in that event.
1278  *
1279  * The following file in debugfs provides that interface:
1280  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1281  *
1282  * Usage:
1283  *
1284  * .. code-block:: bash
1285  *
1286  *      echo true > .../ras/auto_reboot
1287  *
1288  */
1289 /* debugfs begin */
1290 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1291 {
1292         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1293         struct dentry *dir;
1294         struct drm_minor *minor = adev_to_drm(adev)->primary;
1295
1296         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1297         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1298                             &amdgpu_ras_debugfs_ctrl_ops);
1299         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1300                             &amdgpu_ras_debugfs_eeprom_ops);
1301         debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1302                            &con->bad_page_cnt_threshold);
1303
1304         /*
1305          * After one uncorrectable error happens, usually GPU recovery will
1306          * be scheduled. But due to the known problem in GPU recovery failing
1307          * to bring GPU back, below interface provides one direct way to
1308          * user to reboot system automatically in such case within
1309          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1310          * will never be called.
1311          */
1312         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1313
1314         /*
1315          * User could set this not to clean up hardware's error count register
1316          * of RAS IPs during ras recovery.
1317          */
1318         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1319                             &con->disable_ras_err_cnt_harvest);
1320         return dir;
1321 }
1322
1323 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1324                                       struct ras_fs_if *head,
1325                                       struct dentry *dir)
1326 {
1327         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1328
1329         if (!obj || !dir)
1330                 return;
1331
1332         get_obj(obj);
1333
1334         memcpy(obj->fs_data.debugfs_name,
1335                         head->debugfs_name,
1336                         sizeof(obj->fs_data.debugfs_name));
1337
1338         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1339                             obj, &amdgpu_ras_debugfs_ops);
1340 }
1341
1342 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1343 {
1344         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1345         struct dentry *dir;
1346         struct ras_manager *obj;
1347         struct ras_fs_if fs_info;
1348
1349         /*
1350          * it won't be called in resume path, no need to check
1351          * suspend and gpu reset status
1352          */
1353         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1354                 return;
1355
1356         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1357
1358         list_for_each_entry(obj, &con->head, node) {
1359                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1360                         (obj->attr_inuse == 1)) {
1361                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1362                                         ras_block_str(obj->head.block));
1363                         fs_info.head = obj->head;
1364                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1365                 }
1366         }
1367 }
1368
1369 /* debugfs end */
1370
1371 /* ras fs */
1372 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1373                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1374 static DEVICE_ATTR(features, S_IRUGO,
1375                 amdgpu_ras_sysfs_features_read, NULL);
1376 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1377 {
1378         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1379         struct attribute_group group = {
1380                 .name = RAS_FS_NAME,
1381         };
1382         struct attribute *attrs[] = {
1383                 &con->features_attr.attr,
1384                 NULL
1385         };
1386         struct bin_attribute *bin_attrs[] = {
1387                 NULL,
1388                 NULL,
1389         };
1390         int r;
1391
1392         /* add features entry */
1393         con->features_attr = dev_attr_features;
1394         group.attrs = attrs;
1395         sysfs_attr_init(attrs[0]);
1396
1397         if (amdgpu_bad_page_threshold != 0) {
1398                 /* add bad_page_features entry */
1399                 bin_attr_gpu_vram_bad_pages.private = NULL;
1400                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1401                 bin_attrs[0] = &con->badpages_attr;
1402                 group.bin_attrs = bin_attrs;
1403                 sysfs_bin_attr_init(bin_attrs[0]);
1404         }
1405
1406         r = sysfs_create_group(&adev->dev->kobj, &group);
1407         if (r)
1408                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1409
1410         return 0;
1411 }
1412
1413 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1414 {
1415         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1416         struct ras_manager *con_obj, *ip_obj, *tmp;
1417
1418         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1419                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1420                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1421                         if (ip_obj)
1422                                 put_obj(ip_obj);
1423                 }
1424         }
1425
1426         amdgpu_ras_sysfs_remove_all(adev);
1427         return 0;
1428 }
1429 /* ras fs end */
1430
1431 /* ih begin */
1432 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1433 {
1434         struct ras_ih_data *data = &obj->ih_data;
1435         struct amdgpu_iv_entry entry;
1436         int ret;
1437         struct ras_err_data err_data = {0, 0, 0, NULL};
1438
1439         while (data->rptr != data->wptr) {
1440                 rmb();
1441                 memcpy(&entry, &data->ring[data->rptr],
1442                                 data->element_size);
1443
1444                 wmb();
1445                 data->rptr = (data->aligned_element_size +
1446                                 data->rptr) % data->ring_size;
1447
1448                 /* Let IP handle its data, maybe we need get the output
1449                  * from the callback to udpate the error type/count, etc
1450                  */
1451                 if (data->cb) {
1452                         ret = data->cb(obj->adev, &err_data, &entry);
1453                         /* ue will trigger an interrupt, and in that case
1454                          * we need do a reset to recovery the whole system.
1455                          * But leave IP do that recovery, here we just dispatch
1456                          * the error.
1457                          */
1458                         if (ret == AMDGPU_RAS_SUCCESS) {
1459                                 /* these counts could be left as 0 if
1460                                  * some blocks do not count error number
1461                                  */
1462                                 obj->err_data.ue_count += err_data.ue_count;
1463                                 obj->err_data.ce_count += err_data.ce_count;
1464                         }
1465                 }
1466         }
1467 }
1468
1469 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1470 {
1471         struct ras_ih_data *data =
1472                 container_of(work, struct ras_ih_data, ih_work);
1473         struct ras_manager *obj =
1474                 container_of(data, struct ras_manager, ih_data);
1475
1476         amdgpu_ras_interrupt_handler(obj);
1477 }
1478
1479 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1480                 struct ras_dispatch_if *info)
1481 {
1482         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1483         struct ras_ih_data *data = &obj->ih_data;
1484
1485         if (!obj)
1486                 return -EINVAL;
1487
1488         if (data->inuse == 0)
1489                 return 0;
1490
1491         /* Might be overflow... */
1492         memcpy(&data->ring[data->wptr], info->entry,
1493                         data->element_size);
1494
1495         wmb();
1496         data->wptr = (data->aligned_element_size +
1497                         data->wptr) % data->ring_size;
1498
1499         schedule_work(&data->ih_work);
1500
1501         return 0;
1502 }
1503
1504 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1505                 struct ras_ih_if *info)
1506 {
1507         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1508         struct ras_ih_data *data;
1509
1510         if (!obj)
1511                 return -EINVAL;
1512
1513         data = &obj->ih_data;
1514         if (data->inuse == 0)
1515                 return 0;
1516
1517         cancel_work_sync(&data->ih_work);
1518
1519         kfree(data->ring);
1520         memset(data, 0, sizeof(*data));
1521         put_obj(obj);
1522
1523         return 0;
1524 }
1525
1526 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1527                 struct ras_ih_if *info)
1528 {
1529         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1530         struct ras_ih_data *data;
1531
1532         if (!obj) {
1533                 /* in case we registe the IH before enable ras feature */
1534                 obj = amdgpu_ras_create_obj(adev, &info->head);
1535                 if (!obj)
1536                         return -EINVAL;
1537         } else
1538                 get_obj(obj);
1539
1540         data = &obj->ih_data;
1541         /* add the callback.etc */
1542         *data = (struct ras_ih_data) {
1543                 .inuse = 0,
1544                 .cb = info->cb,
1545                 .element_size = sizeof(struct amdgpu_iv_entry),
1546                 .rptr = 0,
1547                 .wptr = 0,
1548         };
1549
1550         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1551
1552         data->aligned_element_size = ALIGN(data->element_size, 8);
1553         /* the ring can store 64 iv entries. */
1554         data->ring_size = 64 * data->aligned_element_size;
1555         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1556         if (!data->ring) {
1557                 put_obj(obj);
1558                 return -ENOMEM;
1559         }
1560
1561         /* IH is ready */
1562         data->inuse = 1;
1563
1564         return 0;
1565 }
1566
1567 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1568 {
1569         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1570         struct ras_manager *obj, *tmp;
1571
1572         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1573                 struct ras_ih_if info = {
1574                         .head = obj->head,
1575                 };
1576                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1577         }
1578
1579         return 0;
1580 }
1581 /* ih end */
1582
1583 /* traversal all IPs except NBIO to query error counter */
1584 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1585 {
1586         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1587         struct ras_manager *obj;
1588
1589         if (!adev->ras_features || !con)
1590                 return;
1591
1592         list_for_each_entry(obj, &con->head, node) {
1593                 struct ras_query_if info = {
1594                         .head = obj->head,
1595                 };
1596
1597                 /*
1598                  * PCIE_BIF IP has one different isr by ras controller
1599                  * interrupt, the specific ras counter query will be
1600                  * done in that isr. So skip such block from common
1601                  * sync flood interrupt isr calling.
1602                  */
1603                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1604                         continue;
1605
1606                 amdgpu_ras_query_error_status(adev, &info);
1607         }
1608 }
1609
1610 /* Parse RdRspStatus and WrRspStatus */
1611 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1612                                           struct ras_query_if *info)
1613 {
1614         /*
1615          * Only two block need to query read/write
1616          * RspStatus at current state
1617          */
1618         switch (info->head.block) {
1619         case AMDGPU_RAS_BLOCK__GFX:
1620                 if (adev->gfx.ras_funcs &&
1621                     adev->gfx.ras_funcs->query_ras_error_status)
1622                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1623                 break;
1624         case AMDGPU_RAS_BLOCK__MMHUB:
1625                 if (adev->mmhub.ras_funcs &&
1626                     adev->mmhub.ras_funcs->query_ras_error_status)
1627                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1628                 break;
1629         default:
1630                 break;
1631         }
1632 }
1633
1634 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1635 {
1636         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1637         struct ras_manager *obj;
1638
1639         if (!adev->ras_features || !con)
1640                 return;
1641
1642         list_for_each_entry(obj, &con->head, node) {
1643                 struct ras_query_if info = {
1644                         .head = obj->head,
1645                 };
1646
1647                 amdgpu_ras_error_status_query(adev, &info);
1648         }
1649 }
1650
1651 /* recovery begin */
1652
1653 /* return 0 on success.
1654  * caller need free bps.
1655  */
1656 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1657                 struct ras_badpage **bps, unsigned int *count)
1658 {
1659         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1660         struct ras_err_handler_data *data;
1661         int i = 0;
1662         int ret = 0, status;
1663
1664         if (!con || !con->eh_data || !bps || !count)
1665                 return -EINVAL;
1666
1667         mutex_lock(&con->recovery_lock);
1668         data = con->eh_data;
1669         if (!data || data->count == 0) {
1670                 *bps = NULL;
1671                 ret = -EINVAL;
1672                 goto out;
1673         }
1674
1675         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1676         if (!*bps) {
1677                 ret = -ENOMEM;
1678                 goto out;
1679         }
1680
1681         for (; i < data->count; i++) {
1682                 (*bps)[i] = (struct ras_badpage){
1683                         .bp = data->bps[i].retired_page,
1684                         .size = AMDGPU_GPU_PAGE_SIZE,
1685                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1686                 };
1687                 status = amdgpu_vram_mgr_query_page_status(
1688                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1689                                 data->bps[i].retired_page);
1690                 if (status == -EBUSY)
1691                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1692                 else if (status == -ENOENT)
1693                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1694         }
1695
1696         *count = data->count;
1697 out:
1698         mutex_unlock(&con->recovery_lock);
1699         return ret;
1700 }
1701
1702 static void amdgpu_ras_do_recovery(struct work_struct *work)
1703 {
1704         struct amdgpu_ras *ras =
1705                 container_of(work, struct amdgpu_ras, recovery_work);
1706         struct amdgpu_device *remote_adev = NULL;
1707         struct amdgpu_device *adev = ras->adev;
1708         struct list_head device_list, *device_list_handle =  NULL;
1709
1710         if (!ras->disable_ras_err_cnt_harvest) {
1711                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1712
1713                 /* Build list of devices to query RAS related errors */
1714                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1715                         device_list_handle = &hive->device_list;
1716                 } else {
1717                         INIT_LIST_HEAD(&device_list);
1718                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1719                         device_list_handle = &device_list;
1720                 }
1721
1722                 list_for_each_entry(remote_adev,
1723                                 device_list_handle, gmc.xgmi.head) {
1724                         amdgpu_ras_query_err_status(remote_adev);
1725                         amdgpu_ras_log_on_err_counter(remote_adev);
1726                 }
1727
1728                 amdgpu_put_xgmi_hive(hive);
1729         }
1730
1731         if (amdgpu_device_should_recover_gpu(ras->adev))
1732                 amdgpu_device_gpu_recover(ras->adev, NULL);
1733         atomic_set(&ras->in_recovery, 0);
1734 }
1735
1736 /* alloc/realloc bps array */
1737 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1738                 struct ras_err_handler_data *data, int pages)
1739 {
1740         unsigned int old_space = data->count + data->space_left;
1741         unsigned int new_space = old_space + pages;
1742         unsigned int align_space = ALIGN(new_space, 512);
1743         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1744
1745         if (!bps) {
1746                 kfree(bps);
1747                 return -ENOMEM;
1748         }
1749
1750         if (data->bps) {
1751                 memcpy(bps, data->bps,
1752                                 data->count * sizeof(*data->bps));
1753                 kfree(data->bps);
1754         }
1755
1756         data->bps = bps;
1757         data->space_left += align_space - old_space;
1758         return 0;
1759 }
1760
1761 /* it deal with vram only. */
1762 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1763                 struct eeprom_table_record *bps, int pages)
1764 {
1765         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1766         struct ras_err_handler_data *data;
1767         int ret = 0;
1768         uint32_t i;
1769
1770         if (!con || !con->eh_data || !bps || pages <= 0)
1771                 return 0;
1772
1773         mutex_lock(&con->recovery_lock);
1774         data = con->eh_data;
1775         if (!data)
1776                 goto out;
1777
1778         for (i = 0; i < pages; i++) {
1779                 if (amdgpu_ras_check_bad_page_unlock(con,
1780                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1781                         continue;
1782
1783                 if (!data->space_left &&
1784                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1785                         ret = -ENOMEM;
1786                         goto out;
1787                 }
1788
1789                 amdgpu_vram_mgr_reserve_range(
1790                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1791                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1792                         AMDGPU_GPU_PAGE_SIZE);
1793
1794                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1795                 data->count++;
1796                 data->space_left--;
1797         }
1798 out:
1799         mutex_unlock(&con->recovery_lock);
1800
1801         return ret;
1802 }
1803
1804 /*
1805  * write error record array to eeprom, the function should be
1806  * protected by recovery_lock
1807  */
1808 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1809 {
1810         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1811         struct ras_err_handler_data *data;
1812         struct amdgpu_ras_eeprom_control *control;
1813         int save_count;
1814
1815         if (!con || !con->eh_data)
1816                 return 0;
1817
1818         control = &con->eeprom_control;
1819         data = con->eh_data;
1820         save_count = data->count - control->num_recs;
1821         /* only new entries are saved */
1822         if (save_count > 0) {
1823                 if (amdgpu_ras_eeprom_process_recods(control,
1824                                                         &data->bps[control->num_recs],
1825                                                         true,
1826                                                         save_count)) {
1827                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1828                         return -EIO;
1829                 }
1830
1831                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1832         }
1833
1834         return 0;
1835 }
1836
1837 /*
1838  * read error record array in eeprom and reserve enough space for
1839  * storing new bad pages
1840  */
1841 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1842 {
1843         struct amdgpu_ras_eeprom_control *control =
1844                                         &adev->psp.ras.ras->eeprom_control;
1845         struct eeprom_table_record *bps = NULL;
1846         int ret = 0;
1847
1848         /* no bad page record, skip eeprom access */
1849         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1850                 return ret;
1851
1852         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1853         if (!bps)
1854                 return -ENOMEM;
1855
1856         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1857                 control->num_recs)) {
1858                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1859                 ret = -EIO;
1860                 goto out;
1861         }
1862
1863         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1864
1865 out:
1866         kfree(bps);
1867         return ret;
1868 }
1869
1870 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1871                                 uint64_t addr)
1872 {
1873         struct ras_err_handler_data *data = con->eh_data;
1874         int i;
1875
1876         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1877         for (i = 0; i < data->count; i++)
1878                 if (addr == data->bps[i].retired_page)
1879                         return true;
1880
1881         return false;
1882 }
1883
1884 /*
1885  * check if an address belongs to bad page
1886  *
1887  * Note: this check is only for umc block
1888  */
1889 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1890                                 uint64_t addr)
1891 {
1892         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1893         bool ret = false;
1894
1895         if (!con || !con->eh_data)
1896                 return ret;
1897
1898         mutex_lock(&con->recovery_lock);
1899         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1900         mutex_unlock(&con->recovery_lock);
1901         return ret;
1902 }
1903
1904 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1905                                         uint32_t max_length)
1906 {
1907         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1908         int tmp_threshold = amdgpu_bad_page_threshold;
1909         u64 val;
1910
1911         /*
1912          * Justification of value bad_page_cnt_threshold in ras structure
1913          *
1914          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1915          * in eeprom, and introduce two scenarios accordingly.
1916          *
1917          * Bad page retirement enablement:
1918          *    - If amdgpu_bad_page_threshold = -1,
1919          *      bad_page_cnt_threshold = typical value by formula.
1920          *
1921          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1922          *      max record length in eeprom, use it directly.
1923          *
1924          * Bad page retirement disablement:
1925          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1926          *      functionality is disabled, and bad_page_cnt_threshold will
1927          *      take no effect.
1928          */
1929
1930         if (tmp_threshold < -1)
1931                 tmp_threshold = -1;
1932         else if (tmp_threshold > max_length)
1933                 tmp_threshold = max_length;
1934
1935         if (tmp_threshold == -1) {
1936                 val = adev->gmc.mc_vram_size;
1937                 do_div(val, RAS_BAD_PAGE_RATE);
1938                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1939                                                 max_length);
1940         } else {
1941                 con->bad_page_cnt_threshold = tmp_threshold;
1942         }
1943 }
1944
1945 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1946 {
1947         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1948         struct ras_err_handler_data **data;
1949         uint32_t max_eeprom_records_len = 0;
1950         bool exc_err_limit = false;
1951         int ret;
1952
1953         if (adev->ras_features && con)
1954                 data = &con->eh_data;
1955         else
1956                 return 0;
1957
1958         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1959         if (!*data) {
1960                 ret = -ENOMEM;
1961                 goto out;
1962         }
1963
1964         mutex_init(&con->recovery_lock);
1965         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1966         atomic_set(&con->in_recovery, 0);
1967         con->adev = adev;
1968
1969         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1970         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1971
1972         /* Todo: During test the SMU might fail to read the eeprom through I2C
1973          * when the GPU is pending on XGMI reset during probe time
1974          * (Mostly after second bus reset), skip it now
1975          */
1976         if (adev->gmc.xgmi.pending_reset)
1977                 return 0;
1978         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1979         /*
1980          * This calling fails when exc_err_limit is true or
1981          * ret != 0.
1982          */
1983         if (exc_err_limit || ret)
1984                 goto free;
1985
1986         if (con->eeprom_control.num_recs) {
1987                 ret = amdgpu_ras_load_bad_pages(adev);
1988                 if (ret)
1989                         goto free;
1990         }
1991
1992         return 0;
1993
1994 free:
1995         kfree((*data)->bps);
1996         kfree(*data);
1997         con->eh_data = NULL;
1998 out:
1999         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
2000
2001         /*
2002          * Except error threshold exceeding case, other failure cases in this
2003          * function would not fail amdgpu driver init.
2004          */
2005         if (!exc_err_limit)
2006                 ret = 0;
2007         else
2008                 ret = -EINVAL;
2009
2010         return ret;
2011 }
2012
2013 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2014 {
2015         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2016         struct ras_err_handler_data *data = con->eh_data;
2017
2018         /* recovery_init failed to init it, fini is useless */
2019         if (!data)
2020                 return 0;
2021
2022         cancel_work_sync(&con->recovery_work);
2023
2024         mutex_lock(&con->recovery_lock);
2025         con->eh_data = NULL;
2026         kfree(data->bps);
2027         kfree(data);
2028         mutex_unlock(&con->recovery_lock);
2029
2030         return 0;
2031 }
2032 /* recovery end */
2033
2034 /* return 0 if ras will reset gpu and repost.*/
2035 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2036                 unsigned int block)
2037 {
2038         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2039
2040         if (!ras)
2041                 return -EINVAL;
2042
2043         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2044         return 0;
2045 }
2046
2047 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2048 {
2049         return adev->asic_type == CHIP_VEGA10 ||
2050                 adev->asic_type == CHIP_VEGA20 ||
2051                 adev->asic_type == CHIP_ARCTURUS ||
2052                 adev->asic_type == CHIP_ALDEBARAN ||
2053                 adev->asic_type == CHIP_SIENNA_CICHLID;
2054 }
2055
2056 /*
2057  * check hardware's ras ability which will be saved in hw_supported.
2058  * if hardware does not support ras, we can skip some ras initializtion and
2059  * forbid some ras operations from IP.
2060  * if software itself, say boot parameter, limit the ras ability. We still
2061  * need allow IP do some limited operations, like disable. In such case,
2062  * we have to initialize ras as normal. but need check if operation is
2063  * allowed or not in each function.
2064  */
2065 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
2066                 uint32_t *hw_supported, uint32_t *supported)
2067 {
2068         *hw_supported = 0;
2069         *supported = 0;
2070
2071         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2072             !amdgpu_ras_asic_supported(adev))
2073                 return;
2074
2075         if (!adev->gmc.xgmi.connected_to_cpu) {
2076                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2077                         dev_info(adev->dev, "MEM ECC is active.\n");
2078                         *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
2079                                         1 << AMDGPU_RAS_BLOCK__DF);
2080                 } else {
2081                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2082                 }
2083
2084                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2085                         dev_info(adev->dev, "SRAM ECC is active.\n");
2086                         *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2087                                         1 << AMDGPU_RAS_BLOCK__DF);
2088                 } else {
2089                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2090                 }
2091         } else {
2092                 /* driver only manages a few IP blocks RAS feature
2093                  * when GPU is connected cpu through XGMI */
2094                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__SDMA |
2095                                 1 << AMDGPU_RAS_BLOCK__MMHUB);
2096         }
2097
2098         /* hw_supported needs to be aligned with RAS block mask. */
2099         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
2100
2101         *supported = amdgpu_ras_enable == 0 ?
2102                         0 : *hw_supported & amdgpu_ras_mask;
2103         adev->ras_features = *supported;
2104 }
2105
2106 int amdgpu_ras_init(struct amdgpu_device *adev)
2107 {
2108         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2109         int r;
2110
2111         if (con)
2112                 return 0;
2113
2114         con = kmalloc(sizeof(struct amdgpu_ras) +
2115                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2116                         GFP_KERNEL|__GFP_ZERO);
2117         if (!con)
2118                 return -ENOMEM;
2119
2120         con->objs = (struct ras_manager *)(con + 1);
2121
2122         amdgpu_ras_set_context(adev, con);
2123
2124         amdgpu_ras_check_supported(adev, &con->hw_supported,
2125                         &con->supported);
2126         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2127                 /* set gfx block ras context feature for VEGA20 Gaming
2128                  * send ras disable cmd to ras ta during ras late init.
2129                  */
2130                 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2131                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2132
2133                         return 0;
2134                 }
2135
2136                 r = 0;
2137                 goto release_con;
2138         }
2139
2140         con->features = 0;
2141         INIT_LIST_HEAD(&con->head);
2142         /* Might need get this flag from vbios. */
2143         con->flags = RAS_DEFAULT_FLAGS;
2144
2145         /* initialize nbio ras function ahead of any other
2146          * ras functions so hardware fatal error interrupt
2147          * can be enabled as early as possible */
2148         switch (adev->asic_type) {
2149         case CHIP_VEGA20:
2150         case CHIP_ARCTURUS:
2151         case CHIP_ALDEBARAN:
2152                 if (!adev->gmc.xgmi.connected_to_cpu)
2153                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2154                 break;
2155         default:
2156                 /* nbio ras is not available */
2157                 break;
2158         }
2159
2160         if (adev->nbio.ras_funcs &&
2161             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2162                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2163                 if (r)
2164                         goto release_con;
2165         }
2166
2167         if (adev->nbio.ras_funcs &&
2168             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2169                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2170                 if (r)
2171                         goto release_con;
2172         }
2173
2174         if (amdgpu_ras_fs_init(adev)) {
2175                 r = -EINVAL;
2176                 goto release_con;
2177         }
2178
2179         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2180                         "hardware ability[%x] ras_mask[%x]\n",
2181                         con->hw_supported, con->supported);
2182         return 0;
2183 release_con:
2184         amdgpu_ras_set_context(adev, NULL);
2185         kfree(con);
2186
2187         return r;
2188 }
2189
2190 static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2191 {
2192         if (adev->gmc.xgmi.connected_to_cpu)
2193                 return 1;
2194         return 0;
2195 }
2196
2197 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2198                                         struct ras_common_if *ras_block)
2199 {
2200         struct ras_query_if info = {
2201                 .head = *ras_block,
2202         };
2203
2204         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2205                 return 0;
2206
2207         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2208                 DRM_WARN("RAS init harvest failure");
2209
2210         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2211                 DRM_WARN("RAS init harvest reset failure");
2212
2213         return 0;
2214 }
2215
2216 /* helper function to handle common stuff in ip late init phase */
2217 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2218                          struct ras_common_if *ras_block,
2219                          struct ras_fs_if *fs_info,
2220                          struct ras_ih_if *ih_info)
2221 {
2222         int r;
2223
2224         /* disable RAS feature per IP block if it is not supported */
2225         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2226                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2227                 return 0;
2228         }
2229
2230         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2231         if (r) {
2232                 if (r == -EAGAIN) {
2233                         /* request gpu reset. will run again */
2234                         amdgpu_ras_request_reset_on_boot(adev,
2235                                         ras_block->block);
2236                         return 0;
2237                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2238                         /* in resume phase, if fail to enable ras,
2239                          * clean up all ras fs nodes, and disable ras */
2240                         goto cleanup;
2241                 } else
2242                         return r;
2243         }
2244
2245         /* check for errors on warm reset edc persisant supported ASIC */
2246         amdgpu_persistent_edc_harvesting(adev, ras_block);
2247
2248         /* in resume phase, no need to create ras fs node */
2249         if (adev->in_suspend || amdgpu_in_reset(adev))
2250                 return 0;
2251
2252         if (ih_info->cb) {
2253                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2254                 if (r)
2255                         goto interrupt;
2256         }
2257
2258         r = amdgpu_ras_sysfs_create(adev, fs_info);
2259         if (r)
2260                 goto sysfs;
2261
2262         return 0;
2263 cleanup:
2264         amdgpu_ras_sysfs_remove(adev, ras_block);
2265 sysfs:
2266         if (ih_info->cb)
2267                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2268 interrupt:
2269         amdgpu_ras_feature_enable(adev, ras_block, 0);
2270         return r;
2271 }
2272
2273 /* helper function to remove ras fs node and interrupt handler */
2274 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2275                           struct ras_common_if *ras_block,
2276                           struct ras_ih_if *ih_info)
2277 {
2278         if (!ras_block || !ih_info)
2279                 return;
2280
2281         amdgpu_ras_sysfs_remove(adev, ras_block);
2282         if (ih_info->cb)
2283                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2284         amdgpu_ras_feature_enable(adev, ras_block, 0);
2285 }
2286
2287 /* do some init work after IP late init as dependence.
2288  * and it runs in resume/gpu reset/booting up cases.
2289  */
2290 void amdgpu_ras_resume(struct amdgpu_device *adev)
2291 {
2292         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2293         struct ras_manager *obj, *tmp;
2294
2295         if (!adev->ras_features || !con) {
2296                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2297                 amdgpu_release_ras_context(adev);
2298
2299                 return;
2300         }
2301
2302         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2303                 /* Set up all other IPs which are not implemented. There is a
2304                  * tricky thing that IP's actual ras error type should be
2305                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2306                  * ERROR_NONE make sense anyway.
2307                  */
2308                 amdgpu_ras_enable_all_features(adev, 1);
2309
2310                 /* We enable ras on all hw_supported block, but as boot
2311                  * parameter might disable some of them and one or more IP has
2312                  * not implemented yet. So we disable them on behalf.
2313                  */
2314                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2315                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2316                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2317                                 /* there should be no any reference. */
2318                                 WARN_ON(alive_obj(obj));
2319                         }
2320                 }
2321         }
2322
2323         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2324                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2325                 /* setup ras obj state as disabled.
2326                  * for init_by_vbios case.
2327                  * if we want to enable ras, just enable it in a normal way.
2328                  * If we want do disable it, need setup ras obj as enabled,
2329                  * then issue another TA disable cmd.
2330                  * See feature_enable_on_boot
2331                  */
2332                 amdgpu_ras_disable_all_features(adev, 1);
2333                 amdgpu_ras_reset_gpu(adev);
2334         }
2335 }
2336
2337 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2338 {
2339         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2340
2341         if (!adev->ras_features || !con)
2342                 return;
2343
2344         amdgpu_ras_disable_all_features(adev, 0);
2345         /* Make sure all ras objects are disabled. */
2346         if (con->features)
2347                 amdgpu_ras_disable_all_features(adev, 1);
2348 }
2349
2350 /* do some fini work before IP fini as dependence */
2351 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2352 {
2353         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2354
2355         if (!adev->ras_features || !con)
2356                 return 0;
2357
2358         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2359         amdgpu_ras_disable_all_features(adev, 0);
2360         amdgpu_ras_recovery_fini(adev);
2361         return 0;
2362 }
2363
2364 int amdgpu_ras_fini(struct amdgpu_device *adev)
2365 {
2366         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2367
2368         if (!adev->ras_features || !con)
2369                 return 0;
2370
2371         amdgpu_ras_fs_fini(adev);
2372         amdgpu_ras_interrupt_remove_all(adev);
2373
2374         WARN(con->features, "Feature mask is not cleared");
2375
2376         if (con->features)
2377                 amdgpu_ras_disable_all_features(adev, 1);
2378
2379         amdgpu_ras_set_context(adev, NULL);
2380         kfree(con);
2381
2382         return 0;
2383 }
2384
2385 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2386 {
2387         uint32_t hw_supported, supported;
2388
2389         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2390         if (!hw_supported)
2391                 return;
2392
2393         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2394                 dev_info(adev->dev, "uncorrectable hardware error"
2395                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2396
2397                 amdgpu_ras_reset_gpu(adev);
2398         }
2399 }
2400
2401 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2402 {
2403         if (adev->asic_type == CHIP_VEGA20 &&
2404             adev->pm.fw_version <= 0x283400) {
2405                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2406                                 amdgpu_ras_intr_triggered();
2407         }
2408
2409         return false;
2410 }
2411
2412 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2413 {
2414         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2415
2416         if (!con)
2417                 return;
2418
2419         if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2420                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2421                 amdgpu_ras_set_context(adev, NULL);
2422                 kfree(con);
2423         }
2424 }