drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22 #include "amdgpu.h"
  23 #include "amdgpu_amdkfd.h"
  24 #include "amdgpu_amdkfd_arcturus.h"
  25 #include "amdgpu_amdkfd_gfx_v9.h"
  26 #include "gc/gc_9_4_2_offset.h"
  27 #include "gc/gc_9_4_2_sh_mask.h"
  28 #include <uapi/linux/kfd_ioctl.h>
  29
  30 /*
  31  * Returns TRAP_EN, EXCP_EN and EXCP_REPLACE.
  32  *
  33  * restore_dbg_registers is ignored here but is a general interface requirement
  34  * for devices that support GFXOFF and where the RLC save/restore list
  35  * does not support hw registers for debugging i.e. the driver has to manually
  36  * initialize the debug mode registers after it has disabled GFX off during the
  37  * debug session.
  38  */
  39 static uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev,
  40                                             bool restore_dbg_registers,
  41                                             uint32_t vmid)
  42 {
  43         uint32_t data = 0;
  44
  45         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
  46         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
  47         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);
  48
  49         return data;
  50 }
  51
  52 /* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */
  53 static uint32_t kgd_aldebaran_disable_debug_trap(struct amdgpu_device *adev,
  54                                                 bool keep_trap_enabled,
  55                                                 uint32_t vmid)
  56 {
  57         uint32_t data = 0;
  58
  59         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, keep_trap_enabled);
  60         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
  61         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0);
  62
  63         return data;
  64 }
  65
  66 static int kgd_aldebaran_validate_trap_override_request(struct amdgpu_device *adev,
  67                                                         uint32_t trap_override,
  68                                                         uint32_t *trap_mask_supported)
  69 {
  70         *trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID |
  71                                 KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL |
  72                                 KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO |
  73                                 KFD_DBG_TRAP_MASK_FP_OVERFLOW |
  74                                 KFD_DBG_TRAP_MASK_FP_UNDERFLOW |
  75                                 KFD_DBG_TRAP_MASK_FP_INEXACT |
  76                                 KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO |
  77                                 KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH |
  78                                 KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION;
  79
  80         if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR &&
  81                         trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE)
  82                 return -EPERM;
  83
  84         return 0;
  85 }
  86
  87 /* returns TRAP_EN, EXCP_EN and EXCP_RPLACE. */
  88 static uint32_t kgd_aldebaran_set_wave_launch_trap_override(struct amdgpu_device *adev,
  89                                         uint32_t vmid,
  90                                         uint32_t trap_override,
  91                                         uint32_t trap_mask_bits,
  92                                         uint32_t trap_mask_request,
  93                                         uint32_t *trap_mask_prev,
  94                                         uint32_t kfd_dbg_trap_cntl_prev)
  95
  96 {
  97         uint32_t data = 0;
  98
  99         *trap_mask_prev = REG_GET_FIELD(kfd_dbg_trap_cntl_prev, SPI_GDBG_PER_VMID_CNTL, EXCP_EN);
 100         trap_mask_bits = (trap_mask_bits & trap_mask_request) |
 101                 (*trap_mask_prev & ~trap_mask_request);
 102
 103         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
 104         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, trap_mask_bits);
 105         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override);
 106
 107         return data;
 108 }
 109
 110 static uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev,
 111                                         uint8_t wave_launch_mode,
 112                                         uint32_t vmid)
 113 {
 114         uint32_t data = 0;
 115
 116         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, wave_launch_mode);
 117
 118         return data;
 119 }
 120
 121 #define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H)
 122 static uint32_t kgd_gfx_aldebaran_set_address_watch(
 123                                         struct amdgpu_device *adev,
 124                                         uint64_t watch_address,
 125                                         uint32_t watch_address_mask,
 126                                         uint32_t watch_id,
 127                                         uint32_t watch_mode,
 128                                         uint32_t debug_vmid)
 129 {
 130         uint32_t watch_address_high;
 131         uint32_t watch_address_low;
 132         uint32_t watch_address_cntl;
 133
 134         watch_address_cntl = 0;
 135         watch_address_low = lower_32_bits(watch_address);
 136         watch_address_high = upper_32_bits(watch_address) & 0xffff;
 137
 138         watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
 139                         TCP_WATCH0_CNTL,
 140                         MODE,
 141                         watch_mode);
 142
 143         watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
 144                         TCP_WATCH0_CNTL,
 145                         MASK,
 146                         watch_address_mask >> 6);
 147
 148         watch_address_cntl = REG_SET_FIELD(watch_address_cntl,
 149                         TCP_WATCH0_CNTL,
 150                         VALID,
 151                         1);
 152
 153         WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +
 154                         (watch_id * TCP_WATCH_STRIDE)),
 155                         watch_address_high);
 156
 157         WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +
 158                         (watch_id * TCP_WATCH_STRIDE)),
 159                         watch_address_low);
 160
 161         return watch_address_cntl;
 162 }
 163
 164 static uint32_t kgd_gfx_aldebaran_clear_address_watch(struct amdgpu_device *adev,
 165                                                       uint32_t watch_id)
 166 {
 167         return 0;
 168 }
 169
 170 const struct kfd2kgd_calls aldebaran_kfd2kgd = {
 171         .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings,
 172         .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping,
 173         .init_interrupts = kgd_gfx_v9_init_interrupts,
 174         .hqd_load = kgd_gfx_v9_hqd_load,
 175         .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load,
 176         .hqd_sdma_load = kgd_arcturus_hqd_sdma_load,
 177         .hqd_dump = kgd_gfx_v9_hqd_dump,
 178         .hqd_sdma_dump = kgd_arcturus_hqd_sdma_dump,
 179         .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied,
 180         .hqd_sdma_is_occupied = kgd_arcturus_hqd_sdma_is_occupied,
 181         .hqd_destroy = kgd_gfx_v9_hqd_destroy,
 182         .hqd_sdma_destroy = kgd_arcturus_hqd_sdma_destroy,
 183         .wave_control_execute = kgd_gfx_v9_wave_control_execute,
 184         .get_atc_vmid_pasid_mapping_info =
 185                                 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
 186         .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
 187         .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy,
 188         .enable_debug_trap = kgd_aldebaran_enable_debug_trap,
 189         .disable_debug_trap = kgd_aldebaran_disable_debug_trap,
 190         .validate_trap_override_request = kgd_aldebaran_validate_trap_override_request,
 191         .set_wave_launch_trap_override = kgd_aldebaran_set_wave_launch_trap_override,
 192         .set_wave_launch_mode = kgd_aldebaran_set_wave_launch_mode,
 193         .set_address_watch = kgd_gfx_aldebaran_set_address_watch,
 194         .clear_address_watch = kgd_gfx_aldebaran_clear_address_watch,
 195         .get_iq_wait_times = kgd_gfx_v9_get_iq_wait_times,
 196         .build_grace_period_packet_info = kgd_gfx_v9_build_grace_period_packet_info,
 197         .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings,
 198 };