drivers/net/phy/dp83640.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for the National Semiconductor DP83640 PHYTER
   4  *
   5  * Copyright (C) 2010 OMICRON electronics GmbH
   6  */
   7
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9
  10 #include <linux/crc32.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/kernel.h>
  13 #include <linux/list.h>
  14 #include <linux/mii.h>
  15 #include <linux/module.h>
  16 #include <linux/net_tstamp.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/phy.h>
  20 #include <linux/ptp_classify.h>
  21 #include <linux/ptp_clock_kernel.h>
  22
  23 #include "dp83640_reg.h"
  24
  25 #define DP83640_PHY_ID  0x20005ce1
  26 #define PAGESEL         0x13
  27 #define MAX_RXTS        64
  28 #define N_EXT_TS        6
  29 #define N_PER_OUT       7
  30 #define PSF_PTPVER      2
  31 #define PSF_EVNT        0x4000
  32 #define PSF_RX          0x2000
  33 #define PSF_TX          0x1000
  34 #define EXT_EVENT       1
  35 #define CAL_EVENT       7
  36 #define CAL_TRIGGER     1
  37 #define DP83640_N_PINS  12
  38
  39 #define MII_DP83640_MICR 0x11
  40 #define MII_DP83640_MISR 0x12
  41
  42 #define MII_DP83640_MICR_OE 0x1
  43 #define MII_DP83640_MICR_IE 0x2
  44
  45 #define MII_DP83640_MISR_RHF_INT_EN 0x01
  46 #define MII_DP83640_MISR_FHF_INT_EN 0x02
  47 #define MII_DP83640_MISR_ANC_INT_EN 0x04
  48 #define MII_DP83640_MISR_DUP_INT_EN 0x08
  49 #define MII_DP83640_MISR_SPD_INT_EN 0x10
  50 #define MII_DP83640_MISR_LINK_INT_EN 0x20
  51 #define MII_DP83640_MISR_ED_INT_EN 0x40
  52 #define MII_DP83640_MISR_LQ_INT_EN 0x80
  53
  54 /* phyter seems to miss the mark by 16 ns */
  55 #define ADJTIME_FIX     16
  56
  57 #define SKB_TIMESTAMP_TIMEOUT   2 /* jiffies */
  58
  59 #if defined(__BIG_ENDIAN)
  60 #define ENDIAN_FLAG     0
  61 #elif defined(__LITTLE_ENDIAN)
  62 #define ENDIAN_FLAG     PSF_ENDIAN
  63 #endif
  64
  65 struct dp83640_skb_info {
  66         int ptp_type;
  67         unsigned long tmo;
  68 };
  69
  70 struct phy_rxts {
  71         u16 ns_lo;   /* ns[15:0] */
  72         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  73         u16 sec_lo;  /* sec[15:0] */
  74         u16 sec_hi;  /* sec[31:16] */
  75         u16 seqid;   /* sequenceId[15:0] */
  76         u16 msgtype; /* messageType[3:0], hash[11:0] */
  77 };
  78
  79 struct phy_txts {
  80         u16 ns_lo;   /* ns[15:0] */
  81         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  82         u16 sec_lo;  /* sec[15:0] */
  83         u16 sec_hi;  /* sec[31:16] */
  84 };
  85
  86 struct rxts {
  87         struct list_head list;
  88         unsigned long tmo;
  89         u64 ns;
  90         u16 seqid;
  91         u8  msgtype;
  92         u16 hash;
  93 };
  94
  95 struct dp83640_clock;
  96
  97 struct dp83640_private {
  98         struct list_head list;
  99         struct dp83640_clock *clock;
 100         struct phy_device *phydev;
 101         struct delayed_work ts_work;
 102         int hwts_tx_en;
 103         int hwts_rx_en;
 104         int layer;
 105         int version;
 106         /* remember state of cfg0 during calibration */
 107         int cfg0;
 108         /* remember the last event time stamp */
 109         struct phy_txts edata;
 110         /* list of rx timestamps */
 111         struct list_head rxts;
 112         struct list_head rxpool;
 113         struct rxts rx_pool_data[MAX_RXTS];
 114         /* protects above three fields from concurrent access */
 115         spinlock_t rx_lock;
 116         /* queues of incoming and outgoing packets */
 117         struct sk_buff_head rx_queue;
 118         struct sk_buff_head tx_queue;
 119 };
 120
 121 struct dp83640_clock {
 122         /* keeps the instance in the 'phyter_clocks' list */
 123         struct list_head list;
 124         /* we create one clock instance per MII bus */
 125         struct mii_bus *bus;
 126         /* protects extended registers from concurrent access */
 127         struct mutex extreg_lock;
 128         /* remembers which page was last selected */
 129         int page;
 130         /* our advertised capabilities */
 131         struct ptp_clock_info caps;
 132         /* protects the three fields below from concurrent access */
 133         struct mutex clock_lock;
 134         /* the one phyter from which we shall read */
 135         struct dp83640_private *chosen;
 136         /* list of the other attached phyters, not chosen */
 137         struct list_head phylist;
 138         /* reference to our PTP hardware clock */
 139         struct ptp_clock *ptp_clock;
 140 };
 141
 142 /* globals */
 143
 144 enum {
 145         CALIBRATE_GPIO,
 146         PEROUT_GPIO,
 147         EXTTS0_GPIO,
 148         EXTTS1_GPIO,
 149         EXTTS2_GPIO,
 150         EXTTS3_GPIO,
 151         EXTTS4_GPIO,
 152         EXTTS5_GPIO,
 153         GPIO_TABLE_SIZE
 154 };
 155
 156 static int chosen_phy = -1;
 157 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
 158         1, 2, 3, 4, 8, 9, 10, 11
 159 };
 160
 161 module_param(chosen_phy, int, 0444);
 162 module_param_array(gpio_tab, ushort, NULL, 0444);
 163
 164 MODULE_PARM_DESC(chosen_phy, \
 165         "The address of the PHY to use for the ancillary clock features");
 166 MODULE_PARM_DESC(gpio_tab, \
 167         "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
 168
 169 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
 170 {
 171         int i, index;
 172
 173         for (i = 0; i < DP83640_N_PINS; i++) {
 174                 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
 175                 pd[i].index = i;
 176         }
 177
 178         for (i = 0; i < GPIO_TABLE_SIZE; i++) {
 179                 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
 180                         pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
 181                         return;
 182                 }
 183         }
 184
 185         index = gpio_tab[CALIBRATE_GPIO] - 1;
 186         pd[index].func = PTP_PF_PHYSYNC;
 187         pd[index].chan = 0;
 188
 189         index = gpio_tab[PEROUT_GPIO] - 1;
 190         pd[index].func = PTP_PF_PEROUT;
 191         pd[index].chan = 0;
 192
 193         for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
 194                 index = gpio_tab[i] - 1;
 195                 pd[index].func = PTP_PF_EXTTS;
 196                 pd[index].chan = i - EXTTS0_GPIO;
 197         }
 198 }
 199
 200 /* a list of clocks and a mutex to protect it */
 201 static LIST_HEAD(phyter_clocks);
 202 static DEFINE_MUTEX(phyter_clocks_lock);
 203
 204 static void rx_timestamp_work(struct work_struct *work);
 205
 206 /* extended register access functions */
 207
 208 #define BROADCAST_ADDR 31
 209
 210 static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
 211                                   u16 val)
 212 {
 213         return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
 214 }
 215
 216 /* Caller must hold extreg_lock. */
 217 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
 218 {
 219         struct dp83640_private *dp83640 = phydev->priv;
 220         int val;
 221
 222         if (dp83640->clock->page != page) {
 223                 broadcast_write(phydev, PAGESEL, page);
 224                 dp83640->clock->page = page;
 225         }
 226         val = phy_read(phydev, regnum);
 227
 228         return val;
 229 }
 230
 231 /* Caller must hold extreg_lock. */
 232 static void ext_write(int broadcast, struct phy_device *phydev,
 233                       int page, u32 regnum, u16 val)
 234 {
 235         struct dp83640_private *dp83640 = phydev->priv;
 236
 237         if (dp83640->clock->page != page) {
 238                 broadcast_write(phydev, PAGESEL, page);
 239                 dp83640->clock->page = page;
 240         }
 241         if (broadcast)
 242                 broadcast_write(phydev, regnum, val);
 243         else
 244                 phy_write(phydev, regnum, val);
 245 }
 246
 247 /* Caller must hold extreg_lock. */
 248 static int tdr_write(int bc, struct phy_device *dev,
 249                      const struct timespec64 *ts, u16 cmd)
 250 {
 251         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0]  */
 252         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);   /* ns[31:16] */
 253         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
 254         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);    /* sec[31:16]*/
 255
 256         ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
 257
 258         return 0;
 259 }
 260
 261 /* convert phy timestamps into driver timestamps */
 262
 263 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
 264 {
 265         u32 sec;
 266
 267         sec = p->sec_lo;
 268         sec |= p->sec_hi << 16;
 269
 270         rxts->ns = p->ns_lo;
 271         rxts->ns |= (p->ns_hi & 0x3fff) << 16;
 272         rxts->ns += ((u64)sec) * 1000000000ULL;
 273         rxts->seqid = p->seqid;
 274         rxts->msgtype = (p->msgtype >> 12) & 0xf;
 275         rxts->hash = p->msgtype & 0x0fff;
 276         rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
 277 }
 278
 279 static u64 phy2txts(struct phy_txts *p)
 280 {
 281         u64 ns;
 282         u32 sec;
 283
 284         sec = p->sec_lo;
 285         sec |= p->sec_hi << 16;
 286
 287         ns = p->ns_lo;
 288         ns |= (p->ns_hi & 0x3fff) << 16;
 289         ns += ((u64)sec) * 1000000000ULL;
 290
 291         return ns;
 292 }
 293
 294 static int periodic_output(struct dp83640_clock *clock,
 295                            struct ptp_clock_request *clkreq, bool on,
 296                            int trigger)
 297 {
 298         struct dp83640_private *dp83640 = clock->chosen;
 299         struct phy_device *phydev = dp83640->phydev;
 300         u32 sec, nsec, pwidth;
 301         u16 gpio, ptp_trig, val;
 302
 303         if (on) {
 304                 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
 305                                         trigger);
 306                 if (gpio < 1)
 307                         return -EINVAL;
 308         } else {
 309                 gpio = 0;
 310         }
 311
 312         ptp_trig = TRIG_WR |
 313                 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
 314                 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
 315                 TRIG_PER |
 316                 TRIG_PULSE;
 317
 318         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 319
 320         if (!on) {
 321                 val |= TRIG_DIS;
 322                 mutex_lock(&clock->extreg_lock);
 323                 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 324                 ext_write(0, phydev, PAGE4, PTP_CTL, val);
 325                 mutex_unlock(&clock->extreg_lock);
 326                 return 0;
 327         }
 328
 329         sec = clkreq->perout.start.sec;
 330         nsec = clkreq->perout.start.nsec;
 331         pwidth = clkreq->perout.period.sec * 1000000000UL;
 332         pwidth += clkreq->perout.period.nsec;
 333         pwidth /= 2;
 334
 335         mutex_lock(&clock->extreg_lock);
 336
 337         ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
 338
 339         /*load trigger*/
 340         val |= TRIG_LOAD;
 341         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 342         ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff);   /* ns[15:0] */
 343         ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16);      /* ns[31:16] */
 344         ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff);    /* sec[15:0] */
 345         ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16);       /* sec[31:16] */
 346         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
 347         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);    /* ns[31:16] */
 348         /* Triggers 0 and 1 has programmable pulsewidth2 */
 349         if (trigger < 2) {
 350                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
 351                 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
 352         }
 353
 354         /*enable trigger*/
 355         val &= ~TRIG_LOAD;
 356         val |= TRIG_EN;
 357         ext_write(0, phydev, PAGE4, PTP_CTL, val);
 358
 359         mutex_unlock(&clock->extreg_lock);
 360         return 0;
 361 }
 362
 363 /* ptp clock methods */
 364
 365 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
 366 {
 367         struct dp83640_clock *clock =
 368                 container_of(ptp, struct dp83640_clock, caps);
 369         struct phy_device *phydev = clock->chosen->phydev;
 370         u64 rate;
 371         int neg_adj = 0;
 372         u16 hi, lo;
 373
 374         if (scaled_ppm < 0) {
 375                 neg_adj = 1;
 376                 scaled_ppm = -scaled_ppm;
 377         }
 378         rate = scaled_ppm;
 379         rate <<= 13;
 380         rate = div_u64(rate, 15625);
 381
 382         hi = (rate >> 16) & PTP_RATE_HI_MASK;
 383         if (neg_adj)
 384                 hi |= PTP_RATE_DIR;
 385
 386         lo = rate & 0xffff;
 387
 388         mutex_lock(&clock->extreg_lock);
 389
 390         ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
 391         ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
 392
 393         mutex_unlock(&clock->extreg_lock);
 394
 395         return 0;
 396 }
 397
 398 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
 399 {
 400         struct dp83640_clock *clock =
 401                 container_of(ptp, struct dp83640_clock, caps);
 402         struct phy_device *phydev = clock->chosen->phydev;
 403         struct timespec64 ts;
 404         int err;
 405
 406         delta += ADJTIME_FIX;
 407
 408         ts = ns_to_timespec64(delta);
 409
 410         mutex_lock(&clock->extreg_lock);
 411
 412         err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
 413
 414         mutex_unlock(&clock->extreg_lock);
 415
 416         return err;
 417 }
 418
 419 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
 420                                struct timespec64 *ts)
 421 {
 422         struct dp83640_clock *clock =
 423                 container_of(ptp, struct dp83640_clock, caps);
 424         struct phy_device *phydev = clock->chosen->phydev;
 425         unsigned int val[4];
 426
 427         mutex_lock(&clock->extreg_lock);
 428
 429         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
 430
 431         val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
 432         val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
 433         val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
 434         val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
 435
 436         mutex_unlock(&clock->extreg_lock);
 437
 438         ts->tv_nsec = val[0] | (val[1] << 16);
 439         ts->tv_sec  = val[2] | (val[3] << 16);
 440
 441         return 0;
 442 }
 443
 444 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
 445                                const struct timespec64 *ts)
 446 {
 447         struct dp83640_clock *clock =
 448                 container_of(ptp, struct dp83640_clock, caps);
 449         struct phy_device *phydev = clock->chosen->phydev;
 450         int err;
 451
 452         mutex_lock(&clock->extreg_lock);
 453
 454         err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
 455
 456         mutex_unlock(&clock->extreg_lock);
 457
 458         return err;
 459 }
 460
 461 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
 462                               struct ptp_clock_request *rq, int on)
 463 {
 464         struct dp83640_clock *clock =
 465                 container_of(ptp, struct dp83640_clock, caps);
 466         struct phy_device *phydev = clock->chosen->phydev;
 467         unsigned int index;
 468         u16 evnt, event_num, gpio_num;
 469
 470         switch (rq->type) {
 471         case PTP_CLK_REQ_EXTTS:
 472                 index = rq->extts.index;
 473                 if (index >= N_EXT_TS)
 474                         return -EINVAL;
 475                 event_num = EXT_EVENT + index;
 476                 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 477                 if (on) {
 478                         gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
 479                                                     PTP_PF_EXTTS, index);
 480                         if (gpio_num < 1)
 481                                 return -EINVAL;
 482                         evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 483                         if (rq->extts.flags & PTP_FALLING_EDGE)
 484                                 evnt |= EVNT_FALL;
 485                         else
 486                                 evnt |= EVNT_RISE;
 487                 }
 488                 mutex_lock(&clock->extreg_lock);
 489                 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
 490                 mutex_unlock(&clock->extreg_lock);
 491                 return 0;
 492
 493         case PTP_CLK_REQ_PEROUT:
 494                 if (rq->perout.index >= N_PER_OUT)
 495                         return -EINVAL;
 496                 return periodic_output(clock, rq, on, rq->perout.index);
 497
 498         default:
 499                 break;
 500         }
 501
 502         return -EOPNOTSUPP;
 503 }
 504
 505 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
 506                               enum ptp_pin_function func, unsigned int chan)
 507 {
 508         struct dp83640_clock *clock =
 509                 container_of(ptp, struct dp83640_clock, caps);
 510
 511         if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
 512             !list_empty(&clock->phylist))
 513                 return 1;
 514
 515         if (func == PTP_PF_PHYSYNC)
 516                 return 1;
 517
 518         return 0;
 519 }
 520
 521 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
 522 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
 523
 524 static void enable_status_frames(struct phy_device *phydev, bool on)
 525 {
 526         struct dp83640_private *dp83640 = phydev->priv;
 527         struct dp83640_clock *clock = dp83640->clock;
 528         u16 cfg0 = 0, ver;
 529
 530         if (on)
 531                 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
 532
 533         ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
 534
 535         mutex_lock(&clock->extreg_lock);
 536
 537         ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
 538         ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
 539
 540         mutex_unlock(&clock->extreg_lock);
 541
 542         if (!phydev->attached_dev) {
 543                 phydev_warn(phydev,
 544                             "expected to find an attached netdevice\n");
 545                 return;
 546         }
 547
 548         if (on) {
 549                 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
 550                         phydev_warn(phydev, "failed to add mc address\n");
 551         } else {
 552                 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
 553                         phydev_warn(phydev, "failed to delete mc address\n");
 554         }
 555 }
 556
 557 static bool is_status_frame(struct sk_buff *skb, int type)
 558 {
 559         struct ethhdr *h = eth_hdr(skb);
 560
 561         if (PTP_CLASS_V2_L2 == type &&
 562             !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
 563                 return true;
 564         else
 565                 return false;
 566 }
 567
 568 static int expired(struct rxts *rxts)
 569 {
 570         return time_after(jiffies, rxts->tmo);
 571 }
 572
 573 /* Caller must hold rx_lock. */
 574 static void prune_rx_ts(struct dp83640_private *dp83640)
 575 {
 576         struct list_head *this, *next;
 577         struct rxts *rxts;
 578
 579         list_for_each_safe(this, next, &dp83640->rxts) {
 580                 rxts = list_entry(this, struct rxts, list);
 581                 if (expired(rxts)) {
 582                         list_del_init(&rxts->list);
 583                         list_add(&rxts->list, &dp83640->rxpool);
 584                 }
 585         }
 586 }
 587
 588 /* synchronize the phyters so they act as one clock */
 589
 590 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
 591 {
 592         int val;
 593         phy_write(phydev, PAGESEL, 0);
 594         val = phy_read(phydev, PHYCR2);
 595         if (on)
 596                 val |= BC_WRITE;
 597         else
 598                 val &= ~BC_WRITE;
 599         phy_write(phydev, PHYCR2, val);
 600         phy_write(phydev, PAGESEL, init_page);
 601 }
 602
 603 static void recalibrate(struct dp83640_clock *clock)
 604 {
 605         s64 now, diff;
 606         struct phy_txts event_ts;
 607         struct timespec64 ts;
 608         struct list_head *this;
 609         struct dp83640_private *tmp;
 610         struct phy_device *master = clock->chosen->phydev;
 611         u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
 612
 613         trigger = CAL_TRIGGER;
 614         cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
 615         if (cal_gpio < 1) {
 616                 pr_err("PHY calibration pin not available - PHY is not calibrated.");
 617                 return;
 618         }
 619
 620         mutex_lock(&clock->extreg_lock);
 621
 622         /*
 623          * enable broadcast, disable status frames, enable ptp clock
 624          */
 625         list_for_each(this, &clock->phylist) {
 626                 tmp = list_entry(this, struct dp83640_private, list);
 627                 enable_broadcast(tmp->phydev, clock->page, 1);
 628                 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
 629                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
 630                 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
 631         }
 632         enable_broadcast(master, clock->page, 1);
 633         cfg0 = ext_read(master, PAGE5, PSF_CFG0);
 634         ext_write(0, master, PAGE5, PSF_CFG0, 0);
 635         ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
 636
 637         /*
 638          * enable an event timestamp
 639          */
 640         evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
 641         evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 642         evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 643
 644         list_for_each(this, &clock->phylist) {
 645                 tmp = list_entry(this, struct dp83640_private, list);
 646                 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
 647         }
 648         ext_write(0, master, PAGE5, PTP_EVNT, evnt);
 649
 650         /*
 651          * configure a trigger
 652          */
 653         ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
 654         ptp_trig |= (trigger  & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
 655         ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
 656         ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
 657
 658         /* load trigger */
 659         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 660         val |= TRIG_LOAD;
 661         ext_write(0, master, PAGE4, PTP_CTL, val);
 662
 663         /* enable trigger */
 664         val &= ~TRIG_LOAD;
 665         val |= TRIG_EN;
 666         ext_write(0, master, PAGE4, PTP_CTL, val);
 667
 668         /* disable trigger */
 669         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 670         val |= TRIG_DIS;
 671         ext_write(0, master, PAGE4, PTP_CTL, val);
 672
 673         /*
 674          * read out and correct offsets
 675          */
 676         val = ext_read(master, PAGE4, PTP_STS);
 677         phydev_info(master, "master PTP_STS  0x%04hx\n", val);
 678         val = ext_read(master, PAGE4, PTP_ESTS);
 679         phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
 680         event_ts.ns_lo  = ext_read(master, PAGE4, PTP_EDATA);
 681         event_ts.ns_hi  = ext_read(master, PAGE4, PTP_EDATA);
 682         event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
 683         event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
 684         now = phy2txts(&event_ts);
 685
 686         list_for_each(this, &clock->phylist) {
 687                 tmp = list_entry(this, struct dp83640_private, list);
 688                 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
 689                 phydev_info(tmp->phydev, "slave  PTP_STS  0x%04hx\n", val);
 690                 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
 691                 phydev_info(tmp->phydev, "slave  PTP_ESTS 0x%04hx\n", val);
 692                 event_ts.ns_lo  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 693                 event_ts.ns_hi  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 694                 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 695                 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 696                 diff = now - (s64) phy2txts(&event_ts);
 697                 phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
 698                             diff);
 699                 diff += ADJTIME_FIX;
 700                 ts = ns_to_timespec64(diff);
 701                 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
 702         }
 703
 704         /*
 705          * restore status frames
 706          */
 707         list_for_each(this, &clock->phylist) {
 708                 tmp = list_entry(this, struct dp83640_private, list);
 709                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
 710         }
 711         ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
 712
 713         mutex_unlock(&clock->extreg_lock);
 714 }
 715
 716 /* time stamping methods */
 717
 718 static inline u16 exts_chan_to_edata(int ch)
 719 {
 720         return 1 << ((ch + EXT_EVENT) * 2);
 721 }
 722
 723 static int decode_evnt(struct dp83640_private *dp83640,
 724                        void *data, int len, u16 ests)
 725 {
 726         struct phy_txts *phy_txts;
 727         struct ptp_clock_event event;
 728         int i, parsed;
 729         int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
 730         u16 ext_status = 0;
 731
 732         /* calculate length of the event timestamp status message */
 733         if (ests & MULT_EVNT)
 734                 parsed = (words + 2) * sizeof(u16);
 735         else
 736                 parsed = (words + 1) * sizeof(u16);
 737
 738         /* check if enough data is available */
 739         if (len < parsed)
 740                 return len;
 741
 742         if (ests & MULT_EVNT) {
 743                 ext_status = *(u16 *) data;
 744                 data += sizeof(ext_status);
 745         }
 746
 747         phy_txts = data;
 748
 749         switch (words) {
 750         case 3:
 751                 dp83640->edata.sec_hi = phy_txts->sec_hi;
 752                 /* fall through */
 753         case 2:
 754                 dp83640->edata.sec_lo = phy_txts->sec_lo;
 755                 /* fall through */
 756         case 1:
 757                 dp83640->edata.ns_hi = phy_txts->ns_hi;
 758                 /* fall through */
 759         case 0:
 760                 dp83640->edata.ns_lo = phy_txts->ns_lo;
 761         }
 762
 763         if (!ext_status) {
 764                 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
 765                 ext_status = exts_chan_to_edata(i);
 766         }
 767
 768         event.type = PTP_CLOCK_EXTTS;
 769         event.timestamp = phy2txts(&dp83640->edata);
 770
 771         /* Compensate for input path and synchronization delays */
 772         event.timestamp -= 35;
 773
 774         for (i = 0; i < N_EXT_TS; i++) {
 775                 if (ext_status & exts_chan_to_edata(i)) {
 776                         event.index = i;
 777                         ptp_clock_event(dp83640->clock->ptp_clock, &event);
 778                 }
 779         }
 780
 781         return parsed;
 782 }
 783
 784 #define DP83640_PACKET_HASH_OFFSET      20
 785 #define DP83640_PACKET_HASH_LEN         10
 786
 787 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
 788 {
 789         u16 *seqid, hash;
 790         unsigned int offset = 0;
 791         u8 *msgtype, *data = skb_mac_header(skb);
 792
 793         /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
 794
 795         if (type & PTP_CLASS_VLAN)
 796                 offset += VLAN_HLEN;
 797
 798         switch (type & PTP_CLASS_PMASK) {
 799         case PTP_CLASS_IPV4:
 800                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 801                 break;
 802         case PTP_CLASS_IPV6:
 803                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 804                 break;
 805         case PTP_CLASS_L2:
 806                 offset += ETH_HLEN;
 807                 break;
 808         default:
 809                 return 0;
 810         }
 811
 812         if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
 813                 return 0;
 814
 815         if (unlikely(type & PTP_CLASS_V1))
 816                 msgtype = data + offset + OFF_PTP_CONTROL;
 817         else
 818                 msgtype = data + offset;
 819         if (rxts->msgtype != (*msgtype & 0xf))
 820                 return 0;
 821
 822         seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 823         if (rxts->seqid != ntohs(*seqid))
 824                 return 0;
 825
 826         hash = ether_crc(DP83640_PACKET_HASH_LEN,
 827                          data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
 828         if (rxts->hash != hash)
 829                 return 0;
 830
 831         return 1;
 832 }
 833
 834 static void decode_rxts(struct dp83640_private *dp83640,
 835                         struct phy_rxts *phy_rxts)
 836 {
 837         struct rxts *rxts;
 838         struct skb_shared_hwtstamps *shhwtstamps = NULL;
 839         struct sk_buff *skb;
 840         unsigned long flags;
 841         u8 overflow;
 842
 843         overflow = (phy_rxts->ns_hi >> 14) & 0x3;
 844         if (overflow)
 845                 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
 846
 847         spin_lock_irqsave(&dp83640->rx_lock, flags);
 848
 849         prune_rx_ts(dp83640);
 850
 851         if (list_empty(&dp83640->rxpool)) {
 852                 pr_debug("rx timestamp pool is empty\n");
 853                 goto out;
 854         }
 855         rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
 856         list_del_init(&rxts->list);
 857         phy2rxts(phy_rxts, rxts);
 858
 859         spin_lock(&dp83640->rx_queue.lock);
 860         skb_queue_walk(&dp83640->rx_queue, skb) {
 861                 struct dp83640_skb_info *skb_info;
 862
 863                 skb_info = (struct dp83640_skb_info *)skb->cb;
 864                 if (match(skb, skb_info->ptp_type, rxts)) {
 865                         __skb_unlink(skb, &dp83640->rx_queue);
 866                         shhwtstamps = skb_hwtstamps(skb);
 867                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 868                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
 869                         list_add(&rxts->list, &dp83640->rxpool);
 870                         break;
 871                 }
 872         }
 873         spin_unlock(&dp83640->rx_queue.lock);
 874
 875         if (!shhwtstamps)
 876                 list_add_tail(&rxts->list, &dp83640->rxts);
 877 out:
 878         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
 879
 880         if (shhwtstamps)
 881                 netif_rx_ni(skb);
 882 }
 883
 884 static void decode_txts(struct dp83640_private *dp83640,
 885                         struct phy_txts *phy_txts)
 886 {
 887         struct skb_shared_hwtstamps shhwtstamps;
 888         struct dp83640_skb_info *skb_info;
 889         struct sk_buff *skb;
 890         u8 overflow;
 891         u64 ns;
 892
 893         /* We must already have the skb that triggered this. */
 894 again:
 895         skb = skb_dequeue(&dp83640->tx_queue);
 896         if (!skb) {
 897                 pr_debug("have timestamp but tx_queue empty\n");
 898                 return;
 899         }
 900
 901         overflow = (phy_txts->ns_hi >> 14) & 0x3;
 902         if (overflow) {
 903                 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
 904                 while (skb) {
 905                         kfree_skb(skb);
 906                         skb = skb_dequeue(&dp83640->tx_queue);
 907                 }
 908                 return;
 909         }
 910         skb_info = (struct dp83640_skb_info *)skb->cb;
 911         if (time_after(jiffies, skb_info->tmo)) {
 912                 kfree_skb(skb);
 913                 goto again;
 914         }
 915
 916         ns = phy2txts(phy_txts);
 917         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 918         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 919         skb_complete_tx_timestamp(skb, &shhwtstamps);
 920 }
 921
 922 static void decode_status_frame(struct dp83640_private *dp83640,
 923                                 struct sk_buff *skb)
 924 {
 925         struct phy_rxts *phy_rxts;
 926         struct phy_txts *phy_txts;
 927         u8 *ptr;
 928         int len, size;
 929         u16 ests, type;
 930
 931         ptr = skb->data + 2;
 932
 933         for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
 934
 935                 type = *(u16 *)ptr;
 936                 ests = type & 0x0fff;
 937                 type = type & 0xf000;
 938                 len -= sizeof(type);
 939                 ptr += sizeof(type);
 940
 941                 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
 942
 943                         phy_rxts = (struct phy_rxts *) ptr;
 944                         decode_rxts(dp83640, phy_rxts);
 945                         size = sizeof(*phy_rxts);
 946
 947                 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
 948
 949                         phy_txts = (struct phy_txts *) ptr;
 950                         decode_txts(dp83640, phy_txts);
 951                         size = sizeof(*phy_txts);
 952
 953                 } else if (PSF_EVNT == type) {
 954
 955                         size = decode_evnt(dp83640, ptr, len, ests);
 956
 957                 } else {
 958                         size = 0;
 959                         break;
 960                 }
 961                 ptr += size;
 962         }
 963 }
 964
 965 static int is_sync(struct sk_buff *skb, int type)
 966 {
 967         u8 *data = skb->data, *msgtype;
 968         unsigned int offset = 0;
 969
 970         if (type & PTP_CLASS_VLAN)
 971                 offset += VLAN_HLEN;
 972
 973         switch (type & PTP_CLASS_PMASK) {
 974         case PTP_CLASS_IPV4:
 975                 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
 976                 break;
 977         case PTP_CLASS_IPV6:
 978                 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
 979                 break;
 980         case PTP_CLASS_L2:
 981                 offset += ETH_HLEN;
 982                 break;
 983         default:
 984                 return 0;
 985         }
 986
 987         if (type & PTP_CLASS_V1)
 988                 offset += OFF_PTP_CONTROL;
 989
 990         if (skb->len < offset + 1)
 991                 return 0;
 992
 993         msgtype = data + offset;
 994
 995         return (*msgtype & 0xf) == 0;
 996 }
 997
 998 static void dp83640_free_clocks(void)
 999 {
1000         struct dp83640_clock *clock;
1001         struct list_head *this, *next;
1002
1003         mutex_lock(&phyter_clocks_lock);
1004
1005         list_for_each_safe(this, next, &phyter_clocks) {
1006                 clock = list_entry(this, struct dp83640_clock, list);
1007                 if (!list_empty(&clock->phylist)) {
1008                         pr_warn("phy list non-empty while unloading\n");
1009                         BUG();
1010                 }
1011                 list_del(&clock->list);
1012                 mutex_destroy(&clock->extreg_lock);
1013                 mutex_destroy(&clock->clock_lock);
1014                 put_device(&clock->bus->dev);
1015                 kfree(clock->caps.pin_config);
1016                 kfree(clock);
1017         }
1018
1019         mutex_unlock(&phyter_clocks_lock);
1020 }
1021
1022 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1023 {
1024         INIT_LIST_HEAD(&clock->list);
1025         clock->bus = bus;
1026         mutex_init(&clock->extreg_lock);
1027         mutex_init(&clock->clock_lock);
1028         INIT_LIST_HEAD(&clock->phylist);
1029         clock->caps.owner = THIS_MODULE;
1030         sprintf(clock->caps.name, "dp83640 timer");
1031         clock->caps.max_adj     = 1953124;
1032         clock->caps.n_alarm     = 0;
1033         clock->caps.n_ext_ts    = N_EXT_TS;
1034         clock->caps.n_per_out   = N_PER_OUT;
1035         clock->caps.n_pins      = DP83640_N_PINS;
1036         clock->caps.pps         = 0;
1037         clock->caps.adjfine     = ptp_dp83640_adjfine;
1038         clock->caps.adjtime     = ptp_dp83640_adjtime;
1039         clock->caps.gettime64   = ptp_dp83640_gettime;
1040         clock->caps.settime64   = ptp_dp83640_settime;
1041         clock->caps.enable      = ptp_dp83640_enable;
1042         clock->caps.verify      = ptp_dp83640_verify;
1043         /*
1044          * Convert the module param defaults into a dynamic pin configuration.
1045          */
1046         dp83640_gpio_defaults(clock->caps.pin_config);
1047         /*
1048          * Get a reference to this bus instance.
1049          */
1050         get_device(&bus->dev);
1051 }
1052
1053 static int choose_this_phy(struct dp83640_clock *clock,
1054                            struct phy_device *phydev)
1055 {
1056         if (chosen_phy == -1 && !clock->chosen)
1057                 return 1;
1058
1059         if (chosen_phy == phydev->mdio.addr)
1060                 return 1;
1061
1062         return 0;
1063 }
1064
1065 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1066 {
1067         if (clock)
1068                 mutex_lock(&clock->clock_lock);
1069         return clock;
1070 }
1071
1072 /*
1073  * Look up and lock a clock by bus instance.
1074  * If there is no clock for this bus, then create it first.
1075  */
1076 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1077 {
1078         struct dp83640_clock *clock = NULL, *tmp;
1079         struct list_head *this;
1080
1081         mutex_lock(&phyter_clocks_lock);
1082
1083         list_for_each(this, &phyter_clocks) {
1084                 tmp = list_entry(this, struct dp83640_clock, list);
1085                 if (tmp->bus == bus) {
1086                         clock = tmp;
1087                         break;
1088                 }
1089         }
1090         if (clock)
1091                 goto out;
1092
1093         clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1094         if (!clock)
1095                 goto out;
1096
1097         clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1098                                          sizeof(struct ptp_pin_desc),
1099                                          GFP_KERNEL);
1100         if (!clock->caps.pin_config) {
1101                 kfree(clock);
1102                 clock = NULL;
1103                 goto out;
1104         }
1105         dp83640_clock_init(clock, bus);
1106         list_add_tail(&phyter_clocks, &clock->list);
1107 out:
1108         mutex_unlock(&phyter_clocks_lock);
1109
1110         return dp83640_clock_get(clock);
1111 }
1112
1113 static void dp83640_clock_put(struct dp83640_clock *clock)
1114 {
1115         mutex_unlock(&clock->clock_lock);
1116 }
1117
1118 static int dp83640_probe(struct phy_device *phydev)
1119 {
1120         struct dp83640_clock *clock;
1121         struct dp83640_private *dp83640;
1122         int err = -ENOMEM, i;
1123
1124         if (phydev->mdio.addr == BROADCAST_ADDR)
1125                 return 0;
1126
1127         clock = dp83640_clock_get_bus(phydev->mdio.bus);
1128         if (!clock)
1129                 goto no_clock;
1130
1131         dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1132         if (!dp83640)
1133                 goto no_memory;
1134
1135         dp83640->phydev = phydev;
1136         INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1137
1138         INIT_LIST_HEAD(&dp83640->rxts);
1139         INIT_LIST_HEAD(&dp83640->rxpool);
1140         for (i = 0; i < MAX_RXTS; i++)
1141                 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1142
1143         phydev->priv = dp83640;
1144
1145         spin_lock_init(&dp83640->rx_lock);
1146         skb_queue_head_init(&dp83640->rx_queue);
1147         skb_queue_head_init(&dp83640->tx_queue);
1148
1149         dp83640->clock = clock;
1150
1151         if (choose_this_phy(clock, phydev)) {
1152                 clock->chosen = dp83640;
1153                 clock->ptp_clock = ptp_clock_register(&clock->caps,
1154                                                       &phydev->mdio.dev);
1155                 if (IS_ERR(clock->ptp_clock)) {
1156                         err = PTR_ERR(clock->ptp_clock);
1157                         goto no_register;
1158                 }
1159         } else
1160                 list_add_tail(&dp83640->list, &clock->phylist);
1161
1162         dp83640_clock_put(clock);
1163         return 0;
1164
1165 no_register:
1166         clock->chosen = NULL;
1167         kfree(dp83640);
1168 no_memory:
1169         dp83640_clock_put(clock);
1170 no_clock:
1171         return err;
1172 }
1173
1174 static void dp83640_remove(struct phy_device *phydev)
1175 {
1176         struct dp83640_clock *clock;
1177         struct list_head *this, *next;
1178         struct dp83640_private *tmp, *dp83640 = phydev->priv;
1179
1180         if (phydev->mdio.addr == BROADCAST_ADDR)
1181                 return;
1182
1183         enable_status_frames(phydev, false);
1184         cancel_delayed_work_sync(&dp83640->ts_work);
1185
1186         skb_queue_purge(&dp83640->rx_queue);
1187         skb_queue_purge(&dp83640->tx_queue);
1188
1189         clock = dp83640_clock_get(dp83640->clock);
1190
1191         if (dp83640 == clock->chosen) {
1192                 ptp_clock_unregister(clock->ptp_clock);
1193                 clock->chosen = NULL;
1194         } else {
1195                 list_for_each_safe(this, next, &clock->phylist) {
1196                         tmp = list_entry(this, struct dp83640_private, list);
1197                         if (tmp == dp83640) {
1198                                 list_del_init(&tmp->list);
1199                                 break;
1200                         }
1201                 }
1202         }
1203
1204         dp83640_clock_put(clock);
1205         kfree(dp83640);
1206 }
1207
1208 static int dp83640_soft_reset(struct phy_device *phydev)
1209 {
1210         int ret;
1211
1212         ret = genphy_soft_reset(phydev);
1213         if (ret < 0)
1214                 return ret;
1215
1216         /* From DP83640 datasheet: "Software driver code must wait 3 us
1217          * following a software reset before allowing further serial MII
1218          * operations with the DP83640."
1219          */
1220         udelay(10);             /* Taking udelay inaccuracy into account */
1221
1222         return 0;
1223 }
1224
1225 static int dp83640_config_init(struct phy_device *phydev)
1226 {
1227         struct dp83640_private *dp83640 = phydev->priv;
1228         struct dp83640_clock *clock = dp83640->clock;
1229
1230         if (clock->chosen && !list_empty(&clock->phylist))
1231                 recalibrate(clock);
1232         else {
1233                 mutex_lock(&clock->extreg_lock);
1234                 enable_broadcast(phydev, clock->page, 1);
1235                 mutex_unlock(&clock->extreg_lock);
1236         }
1237
1238         enable_status_frames(phydev, true);
1239
1240         mutex_lock(&clock->extreg_lock);
1241         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1242         mutex_unlock(&clock->extreg_lock);
1243
1244         return 0;
1245 }
1246
1247 static int dp83640_ack_interrupt(struct phy_device *phydev)
1248 {
1249         int err = phy_read(phydev, MII_DP83640_MISR);
1250
1251         if (err < 0)
1252                 return err;
1253
1254         return 0;
1255 }
1256
1257 static int dp83640_config_intr(struct phy_device *phydev)
1258 {
1259         int micr;
1260         int misr;
1261         int err;
1262
1263         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1264                 misr = phy_read(phydev, MII_DP83640_MISR);
1265                 if (misr < 0)
1266                         return misr;
1267                 misr |=
1268                         (MII_DP83640_MISR_ANC_INT_EN |
1269                         MII_DP83640_MISR_DUP_INT_EN |
1270                         MII_DP83640_MISR_SPD_INT_EN |
1271                         MII_DP83640_MISR_LINK_INT_EN);
1272                 err = phy_write(phydev, MII_DP83640_MISR, misr);
1273                 if (err < 0)
1274                         return err;
1275
1276                 micr = phy_read(phydev, MII_DP83640_MICR);
1277                 if (micr < 0)
1278                         return micr;
1279                 micr |=
1280                         (MII_DP83640_MICR_OE |
1281                         MII_DP83640_MICR_IE);
1282                 return phy_write(phydev, MII_DP83640_MICR, micr);
1283         } else {
1284                 micr = phy_read(phydev, MII_DP83640_MICR);
1285                 if (micr < 0)
1286                         return micr;
1287                 micr &=
1288                         ~(MII_DP83640_MICR_OE |
1289                         MII_DP83640_MICR_IE);
1290                 err = phy_write(phydev, MII_DP83640_MICR, micr);
1291                 if (err < 0)
1292                         return err;
1293
1294                 misr = phy_read(phydev, MII_DP83640_MISR);
1295                 if (misr < 0)
1296                         return misr;
1297                 misr &=
1298                         ~(MII_DP83640_MISR_ANC_INT_EN |
1299                         MII_DP83640_MISR_DUP_INT_EN |
1300                         MII_DP83640_MISR_SPD_INT_EN |
1301                         MII_DP83640_MISR_LINK_INT_EN);
1302                 return phy_write(phydev, MII_DP83640_MISR, misr);
1303         }
1304 }
1305
1306 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1307 {
1308         struct dp83640_private *dp83640 = phydev->priv;
1309         struct hwtstamp_config cfg;
1310         u16 txcfg0, rxcfg0;
1311
1312         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1313                 return -EFAULT;
1314
1315         if (cfg.flags) /* reserved for future extensions */
1316                 return -EINVAL;
1317
1318         if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1319                 return -ERANGE;
1320
1321         dp83640->hwts_tx_en = cfg.tx_type;
1322
1323         switch (cfg.rx_filter) {
1324         case HWTSTAMP_FILTER_NONE:
1325                 dp83640->hwts_rx_en = 0;
1326                 dp83640->layer = 0;
1327                 dp83640->version = 0;
1328                 break;
1329         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1330         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1331         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1332                 dp83640->hwts_rx_en = 1;
1333                 dp83640->layer = PTP_CLASS_L4;
1334                 dp83640->version = PTP_CLASS_V1;
1335                 break;
1336         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1337         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1338         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1339                 dp83640->hwts_rx_en = 1;
1340                 dp83640->layer = PTP_CLASS_L4;
1341                 dp83640->version = PTP_CLASS_V2;
1342                 break;
1343         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1344         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1345         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1346                 dp83640->hwts_rx_en = 1;
1347                 dp83640->layer = PTP_CLASS_L2;
1348                 dp83640->version = PTP_CLASS_V2;
1349                 break;
1350         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1351         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1352         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1353                 dp83640->hwts_rx_en = 1;
1354                 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1355                 dp83640->version = PTP_CLASS_V2;
1356                 break;
1357         default:
1358                 return -ERANGE;
1359         }
1360
1361         txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1362         rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1363
1364         if (dp83640->layer & PTP_CLASS_L2) {
1365                 txcfg0 |= TX_L2_EN;
1366                 rxcfg0 |= RX_L2_EN;
1367         }
1368         if (dp83640->layer & PTP_CLASS_L4) {
1369                 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1370                 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1371         }
1372
1373         if (dp83640->hwts_tx_en)
1374                 txcfg0 |= TX_TS_EN;
1375
1376         if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1377                 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1378
1379         if (dp83640->hwts_rx_en)
1380                 rxcfg0 |= RX_TS_EN;
1381
1382         mutex_lock(&dp83640->clock->extreg_lock);
1383
1384         ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1385         ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1386
1387         mutex_unlock(&dp83640->clock->extreg_lock);
1388
1389         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1390 }
1391
1392 static void rx_timestamp_work(struct work_struct *work)
1393 {
1394         struct dp83640_private *dp83640 =
1395                 container_of(work, struct dp83640_private, ts_work.work);
1396         struct sk_buff *skb;
1397
1398         /* Deliver expired packets. */
1399         while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1400                 struct dp83640_skb_info *skb_info;
1401
1402                 skb_info = (struct dp83640_skb_info *)skb->cb;
1403                 if (!time_after(jiffies, skb_info->tmo)) {
1404                         skb_queue_head(&dp83640->rx_queue, skb);
1405                         break;
1406                 }
1407
1408                 netif_rx_ni(skb);
1409         }
1410
1411         if (!skb_queue_empty(&dp83640->rx_queue))
1412                 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1413 }
1414
1415 static bool dp83640_rxtstamp(struct phy_device *phydev,
1416                              struct sk_buff *skb, int type)
1417 {
1418         struct dp83640_private *dp83640 = phydev->priv;
1419         struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1420         struct list_head *this, *next;
1421         struct rxts *rxts;
1422         struct skb_shared_hwtstamps *shhwtstamps = NULL;
1423         unsigned long flags;
1424
1425         if (is_status_frame(skb, type)) {
1426                 decode_status_frame(dp83640, skb);
1427                 kfree_skb(skb);
1428                 return true;
1429         }
1430
1431         if (!dp83640->hwts_rx_en)
1432                 return false;
1433
1434         if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1435                 return false;
1436
1437         spin_lock_irqsave(&dp83640->rx_lock, flags);
1438         prune_rx_ts(dp83640);
1439         list_for_each_safe(this, next, &dp83640->rxts) {
1440                 rxts = list_entry(this, struct rxts, list);
1441                 if (match(skb, type, rxts)) {
1442                         shhwtstamps = skb_hwtstamps(skb);
1443                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1444                         shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1445                         list_del_init(&rxts->list);
1446                         list_add(&rxts->list, &dp83640->rxpool);
1447                         break;
1448                 }
1449         }
1450         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1451
1452         if (!shhwtstamps) {
1453                 skb_info->ptp_type = type;
1454                 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1455                 skb_queue_tail(&dp83640->rx_queue, skb);
1456                 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1457         } else {
1458                 netif_rx_ni(skb);
1459         }
1460
1461         return true;
1462 }
1463
1464 static void dp83640_txtstamp(struct phy_device *phydev,
1465                              struct sk_buff *skb, int type)
1466 {
1467         struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1468         struct dp83640_private *dp83640 = phydev->priv;
1469
1470         switch (dp83640->hwts_tx_en) {
1471
1472         case HWTSTAMP_TX_ONESTEP_SYNC:
1473                 if (is_sync(skb, type)) {
1474                         kfree_skb(skb);
1475                         return;
1476                 }
1477                 /* fall through */
1478         case HWTSTAMP_TX_ON:
1479                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1480                 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1481                 skb_queue_tail(&dp83640->tx_queue, skb);
1482                 break;
1483
1484         case HWTSTAMP_TX_OFF:
1485         default:
1486                 kfree_skb(skb);
1487                 break;
1488         }
1489 }
1490
1491 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1492 {
1493         struct dp83640_private *dp83640 = dev->priv;
1494
1495         info->so_timestamping =
1496                 SOF_TIMESTAMPING_TX_HARDWARE |
1497                 SOF_TIMESTAMPING_RX_HARDWARE |
1498                 SOF_TIMESTAMPING_RAW_HARDWARE;
1499         info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1500         info->tx_types =
1501                 (1 << HWTSTAMP_TX_OFF) |
1502                 (1 << HWTSTAMP_TX_ON) |
1503                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1504         info->rx_filters =
1505                 (1 << HWTSTAMP_FILTER_NONE) |
1506                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1507                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1508                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1509                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1510         return 0;
1511 }
1512
1513 static struct phy_driver dp83640_driver = {
1514         .phy_id         = DP83640_PHY_ID,
1515         .phy_id_mask    = 0xfffffff0,
1516         .name           = "NatSemi DP83640",
1517         .features       = PHY_BASIC_FEATURES,
1518         .probe          = dp83640_probe,
1519         .remove         = dp83640_remove,
1520         .soft_reset     = dp83640_soft_reset,
1521         .config_init    = dp83640_config_init,
1522         .ack_interrupt  = dp83640_ack_interrupt,
1523         .config_intr    = dp83640_config_intr,
1524         .ts_info        = dp83640_ts_info,
1525         .hwtstamp       = dp83640_hwtstamp,
1526         .rxtstamp       = dp83640_rxtstamp,
1527         .txtstamp       = dp83640_txtstamp,
1528 };
1529
1530 static int __init dp83640_init(void)
1531 {
1532         return phy_driver_register(&dp83640_driver, THIS_MODULE);
1533 }
1534
1535 static void __exit dp83640_exit(void)
1536 {
1537         dp83640_free_clocks();
1538         phy_driver_unregister(&dp83640_driver);
1539 }
1540
1541 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1542 MODULE_AUTHOR("Richard Cochran <[email protected]>");
1543 MODULE_LICENSE("GPL");
1544
1545 module_init(dp83640_init);
1546 module_exit(dp83640_exit);
1547
1548 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1549         { DP83640_PHY_ID, 0xfffffff0 },
1550         { }
1551 };
1552
1553 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);