drivers/i2c/busses/i2c-exynos5.c

   1 /**
   2  * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13
  14 #include <linux/i2c.h>
  15 #include <linux/time.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/slab.h>
  23 #include <linux/io.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/spinlock.h>
  28
  29 /*
  30  * HSI2C controller from Samsung supports 2 modes of operation
  31  * 1. Auto mode: Where in master automatically controls the whole transaction
  32  * 2. Manual mode: Software controls the transaction by issuing commands
  33  *    START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
  34  *
  35  * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
  36  *
  37  * Special bits are available for both modes of operation to set commands
  38  * and for checking transfer status
  39  */
  40
  41 /* Register Map */
  42 #define HSI2C_CTL               0x00
  43 #define HSI2C_FIFO_CTL          0x04
  44 #define HSI2C_TRAILIG_CTL       0x08
  45 #define HSI2C_CLK_CTL           0x0C
  46 #define HSI2C_CLK_SLOT          0x10
  47 #define HSI2C_INT_ENABLE        0x20
  48 #define HSI2C_INT_STATUS        0x24
  49 #define HSI2C_ERR_STATUS        0x2C
  50 #define HSI2C_FIFO_STATUS       0x30
  51 #define HSI2C_TX_DATA           0x34
  52 #define HSI2C_RX_DATA           0x38
  53 #define HSI2C_CONF              0x40
  54 #define HSI2C_AUTO_CONF         0x44
  55 #define HSI2C_TIMEOUT           0x48
  56 #define HSI2C_MANUAL_CMD        0x4C
  57 #define HSI2C_TRANS_STATUS      0x50
  58 #define HSI2C_TIMING_HS1        0x54
  59 #define HSI2C_TIMING_HS2        0x58
  60 #define HSI2C_TIMING_HS3        0x5C
  61 #define HSI2C_TIMING_FS1        0x60
  62 #define HSI2C_TIMING_FS2        0x64
  63 #define HSI2C_TIMING_FS3        0x68
  64 #define HSI2C_TIMING_SLA        0x6C
  65 #define HSI2C_ADDR              0x70
  66
  67 /* I2C_CTL Register bits */
  68 #define HSI2C_FUNC_MODE_I2C                     (1u << 0)
  69 #define HSI2C_MASTER                            (1u << 3)
  70 #define HSI2C_RXCHON                            (1u << 6)
  71 #define HSI2C_TXCHON                            (1u << 7)
  72 #define HSI2C_SW_RST                            (1u << 31)
  73
  74 /* I2C_FIFO_CTL Register bits */
  75 #define HSI2C_RXFIFO_EN                         (1u << 0)
  76 #define HSI2C_TXFIFO_EN                         (1u << 1)
  77 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x)           ((x) << 4)
  78 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x)           ((x) << 16)
  79
  80 /* I2C_TRAILING_CTL Register bits */
  81 #define HSI2C_TRAILING_COUNT                    (0xf)
  82
  83 /* I2C_INT_EN Register bits */
  84 #define HSI2C_INT_TX_ALMOSTEMPTY_EN             (1u << 0)
  85 #define HSI2C_INT_RX_ALMOSTFULL_EN              (1u << 1)
  86 #define HSI2C_INT_TRAILING_EN                   (1u << 6)
  87
  88 /* I2C_INT_STAT Register bits */
  89 #define HSI2C_INT_TX_ALMOSTEMPTY                (1u << 0)
  90 #define HSI2C_INT_RX_ALMOSTFULL                 (1u << 1)
  91 #define HSI2C_INT_TX_UNDERRUN                   (1u << 2)
  92 #define HSI2C_INT_TX_OVERRUN                    (1u << 3)
  93 #define HSI2C_INT_RX_UNDERRUN                   (1u << 4)
  94 #define HSI2C_INT_RX_OVERRUN                    (1u << 5)
  95 #define HSI2C_INT_TRAILING                      (1u << 6)
  96 #define HSI2C_INT_I2C                           (1u << 9)
  97
  98 #define HSI2C_INT_TRANS_DONE                    (1u << 7)
  99 #define HSI2C_INT_TRANS_ABORT                   (1u << 8)
 100 #define HSI2C_INT_NO_DEV_ACK                    (1u << 9)
 101 #define HSI2C_INT_NO_DEV                        (1u << 10)
 102 #define HSI2C_INT_TIMEOUT                       (1u << 11)
 103 #define HSI2C_INT_I2C_TRANS                     (HSI2C_INT_TRANS_DONE | \
 104                                                 HSI2C_INT_TRANS_ABORT | \
 105                                                 HSI2C_INT_NO_DEV_ACK |  \
 106                                                 HSI2C_INT_NO_DEV |      \
 107                                                 HSI2C_INT_TIMEOUT)
 108
 109 /* I2C_FIFO_STAT Register bits */
 110 #define HSI2C_RX_FIFO_EMPTY                     (1u << 24)
 111 #define HSI2C_RX_FIFO_FULL                      (1u << 23)
 112 #define HSI2C_RX_FIFO_LVL(x)                    ((x >> 16) & 0x7f)
 113 #define HSI2C_TX_FIFO_EMPTY                     (1u << 8)
 114 #define HSI2C_TX_FIFO_FULL                      (1u << 7)
 115 #define HSI2C_TX_FIFO_LVL(x)                    ((x >> 0) & 0x7f)
 116
 117 /* I2C_CONF Register bits */
 118 #define HSI2C_AUTO_MODE                         (1u << 31)
 119 #define HSI2C_10BIT_ADDR_MODE                   (1u << 30)
 120 #define HSI2C_HS_MODE                           (1u << 29)
 121
 122 /* I2C_AUTO_CONF Register bits */
 123 #define HSI2C_READ_WRITE                        (1u << 16)
 124 #define HSI2C_STOP_AFTER_TRANS                  (1u << 17)
 125 #define HSI2C_MASTER_RUN                        (1u << 31)
 126
 127 /* I2C_TIMEOUT Register bits */
 128 #define HSI2C_TIMEOUT_EN                        (1u << 31)
 129 #define HSI2C_TIMEOUT_MASK                      0xff
 130
 131 /* I2C_MANUAL_CMD register bits */
 132 #define HSI2C_CMD_READ_DATA                     (1u << 4)
 133 #define HSI2C_CMD_SEND_STOP                     (1u << 2)
 134
 135 /* I2C_TRANS_STATUS register bits */
 136 #define HSI2C_MASTER_BUSY                       (1u << 17)
 137 #define HSI2C_SLAVE_BUSY                        (1u << 16)
 138
 139 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
 140 #define HSI2C_TIMEOUT_AUTO                      (1u << 4)
 141 #define HSI2C_NO_DEV                            (1u << 3)
 142 #define HSI2C_NO_DEV_ACK                        (1u << 2)
 143 #define HSI2C_TRANS_ABORT                       (1u << 1)
 144 #define HSI2C_TRANS_DONE                        (1u << 0)
 145
 146 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
 147 #define HSI2C_MASTER_ST_MASK                    0xf
 148 #define HSI2C_MASTER_ST_IDLE                    0x0
 149 #define HSI2C_MASTER_ST_START                   0x1
 150 #define HSI2C_MASTER_ST_RESTART                 0x2
 151 #define HSI2C_MASTER_ST_STOP                    0x3
 152 #define HSI2C_MASTER_ST_MASTER_ID               0x4
 153 #define HSI2C_MASTER_ST_ADDR0                   0x5
 154 #define HSI2C_MASTER_ST_ADDR1                   0x6
 155 #define HSI2C_MASTER_ST_ADDR2                   0x7
 156 #define HSI2C_MASTER_ST_ADDR_SR                 0x8
 157 #define HSI2C_MASTER_ST_READ                    0x9
 158 #define HSI2C_MASTER_ST_WRITE                   0xa
 159 #define HSI2C_MASTER_ST_NO_ACK                  0xb
 160 #define HSI2C_MASTER_ST_LOSE                    0xc
 161 #define HSI2C_MASTER_ST_WAIT                    0xd
 162 #define HSI2C_MASTER_ST_WAIT_CMD                0xe
 163
 164 /* I2C_ADDR register bits */
 165 #define HSI2C_SLV_ADDR_SLV(x)                   ((x & 0x3ff) << 0)
 166 #define HSI2C_SLV_ADDR_MAS(x)                   ((x & 0x3ff) << 10)
 167 #define HSI2C_MASTER_ID(x)                      ((x & 0xff) << 24)
 168 #define MASTER_ID(x)                            ((x & 0x7) + 0x08)
 169
 170 /*
 171  * Controller operating frequency, timing values for operation
 172  * are calculated against this frequency
 173  */
 174 #define HSI2C_HS_TX_CLOCK       1000000
 175 #define HSI2C_FS_TX_CLOCK       100000
 176
 177 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
 178
 179 enum i2c_type_exynos {
 180         I2C_TYPE_EXYNOS5,
 181         I2C_TYPE_EXYNOS7,
 182 };
 183
 184 struct exynos5_i2c {
 185         struct i2c_adapter      adap;
 186
 187         struct i2c_msg          *msg;
 188         struct completion       msg_complete;
 189         unsigned int            msg_ptr;
 190
 191         unsigned int            irq;
 192
 193         void __iomem            *regs;
 194         struct clk              *clk;
 195         struct device           *dev;
 196         int                     state;
 197
 198         spinlock_t              lock;           /* IRQ synchronization */
 199
 200         /*
 201          * Since the TRANS_DONE bit is cleared on read, and we may read it
 202          * either during an IRQ or after a transaction, keep track of its
 203          * state here.
 204          */
 205         int                     trans_done;
 206
 207         /* Controller operating frequency */
 208         unsigned int            op_clock;
 209
 210         /* Version of HS-I2C Hardware */
 211         const struct exynos_hsi2c_variant *variant;
 212 };
 213
 214 /**
 215  * struct exynos_hsi2c_variant - platform specific HSI2C driver data
 216  * @fifo_depth: the fifo depth supported by the HSI2C module
 217  * @hw: the hardware variant of Exynos I2C controller
 218  *
 219  * Specifies platform specific configuration of HSI2C module.
 220  * Note: A structure for driver specific platform data is used for future
 221  * expansion of its usage.
 222  */
 223 struct exynos_hsi2c_variant {
 224         unsigned int            fifo_depth;
 225         enum i2c_type_exynos    hw;
 226 };
 227
 228 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
 229         .fifo_depth     = 64,
 230         .hw             = I2C_TYPE_EXYNOS5,
 231 };
 232
 233 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
 234         .fifo_depth     = 16,
 235         .hw             = I2C_TYPE_EXYNOS5,
 236 };
 237
 238 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
 239         .fifo_depth     = 16,
 240         .hw             = I2C_TYPE_EXYNOS7,
 241 };
 242
 243 static const struct of_device_id exynos5_i2c_match[] = {
 244         {
 245                 .compatible = "samsung,exynos5-hsi2c",
 246                 .data = &exynos5250_hsi2c_data
 247         }, {
 248                 .compatible = "samsung,exynos5250-hsi2c",
 249                 .data = &exynos5250_hsi2c_data
 250         }, {
 251                 .compatible = "samsung,exynos5260-hsi2c",
 252                 .data = &exynos5260_hsi2c_data
 253         }, {
 254                 .compatible = "samsung,exynos7-hsi2c",
 255                 .data = &exynos7_hsi2c_data
 256         }, {},
 257 };
 258 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
 259
 260 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
 261 {
 262         writel(readl(i2c->regs + HSI2C_INT_STATUS),
 263                                 i2c->regs + HSI2C_INT_STATUS);
 264 }
 265
 266 /*
 267  * exynos5_i2c_set_timing: updates the registers with appropriate
 268  * timing values calculated
 269  *
 270  * Returns 0 on success, -EINVAL if the cycle length cannot
 271  * be calculated.
 272  */
 273 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
 274 {
 275         u32 i2c_timing_s1;
 276         u32 i2c_timing_s2;
 277         u32 i2c_timing_s3;
 278         u32 i2c_timing_sla;
 279         unsigned int t_start_su, t_start_hd;
 280         unsigned int t_stop_su;
 281         unsigned int t_data_su, t_data_hd;
 282         unsigned int t_scl_l, t_scl_h;
 283         unsigned int t_sr_release;
 284         unsigned int t_ftl_cycle;
 285         unsigned int clkin = clk_get_rate(i2c->clk);
 286         unsigned int op_clk = hs_timings ? i2c->op_clock :
 287                 (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK :
 288                 i2c->op_clock;
 289         int div, clk_cycle, temp;
 290
 291         /*
 292          * In case of HSI2C controller in Exynos5 series
 293          * FPCLK / FI2C =
 294          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 295          *
 296          * In case of HSI2C controllers in Exynos7 series
 297          * FPCLK / FI2C =
 298          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
 299          *
 300          * clk_cycle := TSCLK_L + TSCLK_H
 301          * temp := (CLK_DIV + 1) * (clk_cycle + 2)
 302          *
 303          * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
 304          *
 305          */
 306         t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
 307         temp = clkin / op_clk - 8 - t_ftl_cycle;
 308         if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
 309                 temp -= t_ftl_cycle;
 310         div = temp / 512;
 311         clk_cycle = temp / (div + 1) - 2;
 312         if (temp < 4 || div >= 256 || clk_cycle < 2) {
 313                 dev_err(i2c->dev, "%s clock set-up failed\n",
 314                         hs_timings ? "HS" : "FS");
 315                 return -EINVAL;
 316         }
 317
 318         t_scl_l = clk_cycle / 2;
 319         t_scl_h = clk_cycle / 2;
 320         t_start_su = t_scl_l;
 321         t_start_hd = t_scl_l;
 322         t_stop_su = t_scl_l;
 323         t_data_su = t_scl_l / 2;
 324         t_data_hd = t_scl_l / 2;
 325         t_sr_release = clk_cycle;
 326
 327         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 328         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 329         i2c_timing_s3 = div << 16 | t_sr_release << 0;
 330         i2c_timing_sla = t_data_hd << 0;
 331
 332         dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
 333                 t_start_su, t_start_hd, t_stop_su);
 334         dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
 335                 t_data_su, t_scl_l, t_scl_h);
 336         dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
 337                 div, t_sr_release);
 338         dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
 339
 340         if (hs_timings) {
 341                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
 342                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
 343                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
 344         } else {
 345                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
 346                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
 347                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
 348         }
 349         writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
 350
 351         return 0;
 352 }
 353
 354 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
 355 {
 356         /* always set Fast Speed timings */
 357         int ret = exynos5_i2c_set_timing(i2c, false);
 358
 359         if (ret < 0 || i2c->op_clock < HSI2C_HS_TX_CLOCK)
 360                 return ret;
 361
 362         return exynos5_i2c_set_timing(i2c, true);
 363 }
 364
 365 /*
 366  * exynos5_i2c_init: configures the controller for I2C functionality
 367  * Programs I2C controller for Master mode operation
 368  */
 369 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
 370 {
 371         u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
 372         u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
 373
 374         /* Clear to disable Timeout */
 375         i2c_timeout &= ~HSI2C_TIMEOUT_EN;
 376         writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
 377
 378         writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 379                                         i2c->regs + HSI2C_CTL);
 380         writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
 381
 382         if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
 383                 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
 384                                         i2c->regs + HSI2C_ADDR);
 385                 i2c_conf |= HSI2C_HS_MODE;
 386         }
 387
 388         writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
 389 }
 390
 391 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
 392 {
 393         u32 i2c_ctl;
 394
 395         /* Set and clear the bit for reset */
 396         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 397         i2c_ctl |= HSI2C_SW_RST;
 398         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 399
 400         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 401         i2c_ctl &= ~HSI2C_SW_RST;
 402         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 403
 404         /* We don't expect calculations to fail during the run */
 405         exynos5_hsi2c_clock_setup(i2c);
 406         /* Initialize the configure registers */
 407         exynos5_i2c_init(i2c);
 408 }
 409
 410 /*
 411  * exynos5_i2c_irq: top level IRQ servicing routine
 412  *
 413  * INT_STATUS registers gives the interrupt details. Further,
 414  * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
 415  * state of the bus.
 416  */
 417 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
 418 {
 419         struct exynos5_i2c *i2c = dev_id;
 420         u32 fifo_level, int_status, fifo_status, trans_status;
 421         unsigned char byte;
 422         int len = 0;
 423
 424         i2c->state = -EINVAL;
 425
 426         spin_lock(&i2c->lock);
 427
 428         int_status = readl(i2c->regs + HSI2C_INT_STATUS);
 429         writel(int_status, i2c->regs + HSI2C_INT_STATUS);
 430
 431         /* handle interrupt related to the transfer status */
 432         if (i2c->variant->hw == I2C_TYPE_EXYNOS7) {
 433                 if (int_status & HSI2C_INT_TRANS_DONE) {
 434                         i2c->trans_done = 1;
 435                         i2c->state = 0;
 436                 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
 437                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 438                         i2c->state = -EAGAIN;
 439                         goto stop;
 440                 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
 441                         dev_dbg(i2c->dev, "No ACK from device\n");
 442                         i2c->state = -ENXIO;
 443                         goto stop;
 444                 } else if (int_status & HSI2C_INT_NO_DEV) {
 445                         dev_dbg(i2c->dev, "No device\n");
 446                         i2c->state = -ENXIO;
 447                         goto stop;
 448                 } else if (int_status & HSI2C_INT_TIMEOUT) {
 449                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 450                         i2c->state = -ETIMEDOUT;
 451                         goto stop;
 452                 }
 453         } else if (int_status & HSI2C_INT_I2C) {
 454                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 455                 if (trans_status & HSI2C_NO_DEV_ACK) {
 456                         dev_dbg(i2c->dev, "No ACK from device\n");
 457                         i2c->state = -ENXIO;
 458                         goto stop;
 459                 } else if (trans_status & HSI2C_NO_DEV) {
 460                         dev_dbg(i2c->dev, "No device\n");
 461                         i2c->state = -ENXIO;
 462                         goto stop;
 463                 } else if (trans_status & HSI2C_TRANS_ABORT) {
 464                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 465                         i2c->state = -EAGAIN;
 466                         goto stop;
 467                 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
 468                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 469                         i2c->state = -ETIMEDOUT;
 470                         goto stop;
 471                 } else if (trans_status & HSI2C_TRANS_DONE) {
 472                         i2c->trans_done = 1;
 473                         i2c->state = 0;
 474                 }
 475         }
 476
 477         if ((i2c->msg->flags & I2C_M_RD) && (int_status &
 478                         (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
 479                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 480                 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
 481                 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
 482
 483                 while (len > 0) {
 484                         byte = (unsigned char)
 485                                 readl(i2c->regs + HSI2C_RX_DATA);
 486                         i2c->msg->buf[i2c->msg_ptr++] = byte;
 487                         len--;
 488                 }
 489                 i2c->state = 0;
 490         } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
 491                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 492                 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
 493
 494                 len = i2c->variant->fifo_depth - fifo_level;
 495                 if (len > (i2c->msg->len - i2c->msg_ptr)) {
 496                         u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
 497
 498                         int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
 499                         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 500                         len = i2c->msg->len - i2c->msg_ptr;
 501                 }
 502
 503                 while (len > 0) {
 504                         byte = i2c->msg->buf[i2c->msg_ptr++];
 505                         writel(byte, i2c->regs + HSI2C_TX_DATA);
 506                         len--;
 507                 }
 508                 i2c->state = 0;
 509         }
 510
 511  stop:
 512         if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
 513             (i2c->state < 0)) {
 514                 writel(0, i2c->regs + HSI2C_INT_ENABLE);
 515                 exynos5_i2c_clr_pend_irq(i2c);
 516                 complete(&i2c->msg_complete);
 517         }
 518
 519         spin_unlock(&i2c->lock);
 520
 521         return IRQ_HANDLED;
 522 }
 523
 524 /*
 525  * exynos5_i2c_wait_bus_idle
 526  *
 527  * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
 528  * cleared.
 529  *
 530  * Returns -EBUSY if the bus cannot be bought to idle
 531  */
 532 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
 533 {
 534         unsigned long stop_time;
 535         u32 trans_status;
 536
 537         /* wait for 100 milli seconds for the bus to be idle */
 538         stop_time = jiffies + msecs_to_jiffies(100) + 1;
 539         do {
 540                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 541                 if (!(trans_status & HSI2C_MASTER_BUSY))
 542                         return 0;
 543
 544                 usleep_range(50, 200);
 545         } while (time_before(jiffies, stop_time));
 546
 547         return -EBUSY;
 548 }
 549
 550 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
 551 {
 552         u32 val;
 553
 554         val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
 555         writel(val, i2c->regs + HSI2C_CTL);
 556         val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
 557         writel(val, i2c->regs + HSI2C_CONF);
 558
 559         /*
 560          * Specification says master should send nine clock pulses. It can be
 561          * emulated by sending manual read command (nine pulses for read eight
 562          * bits + one pulse for NACK).
 563          */
 564         writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
 565         exynos5_i2c_wait_bus_idle(i2c);
 566         writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
 567         exynos5_i2c_wait_bus_idle(i2c);
 568
 569         val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
 570         writel(val, i2c->regs + HSI2C_CTL);
 571         val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
 572         writel(val, i2c->regs + HSI2C_CONF);
 573 }
 574
 575 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
 576 {
 577         unsigned long timeout;
 578
 579         if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
 580                 return;
 581
 582         /*
 583          * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction
 584          * indicates that bus is stuck (SDA is low). In such case bus recovery
 585          * can be performed.
 586          */
 587         timeout = jiffies + msecs_to_jiffies(100);
 588         for (;;) {
 589                 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
 590
 591                 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)
 592                         return;
 593
 594                 if (time_is_before_jiffies(timeout))
 595                         return;
 596
 597                 exynos5_i2c_bus_recover(i2c);
 598         }
 599 }
 600
 601 /*
 602  * exynos5_i2c_message_start: Configures the bus and starts the xfer
 603  * i2c: struct exynos5_i2c pointer for the current bus
 604  * stop: Enables stop after transfer if set. Set for last transfer of
 605  *       in the list of messages.
 606  *
 607  * Configures the bus for read/write function
 608  * Sets chip address to talk to, message length to be sent.
 609  * Enables appropriate interrupts and sends start xfer command.
 610  */
 611 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
 612 {
 613         u32 i2c_ctl;
 614         u32 int_en = 0;
 615         u32 i2c_auto_conf = 0;
 616         u32 fifo_ctl;
 617         unsigned long flags;
 618         unsigned short trig_lvl;
 619
 620         if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
 621                 int_en |= HSI2C_INT_I2C_TRANS;
 622         else
 623                 int_en |= HSI2C_INT_I2C;
 624
 625         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 626         i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
 627         fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
 628
 629         if (i2c->msg->flags & I2C_M_RD) {
 630                 i2c_ctl |= HSI2C_RXCHON;
 631
 632                 i2c_auto_conf |= HSI2C_READ_WRITE;
 633
 634                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 635                         (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
 636                 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
 637
 638                 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
 639                         HSI2C_INT_TRAILING_EN);
 640         } else {
 641                 i2c_ctl |= HSI2C_TXCHON;
 642
 643                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 644                         (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
 645                 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
 646
 647                 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
 648         }
 649
 650         writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
 651
 652         writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
 653         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 654
 655         exynos5_i2c_bus_check(i2c);
 656
 657         /*
 658          * Enable interrupts before starting the transfer so that we don't
 659          * miss any INT_I2C interrupts.
 660          */
 661         spin_lock_irqsave(&i2c->lock, flags);
 662         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 663
 664         if (stop == 1)
 665                 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
 666         i2c_auto_conf |= i2c->msg->len;
 667         i2c_auto_conf |= HSI2C_MASTER_RUN;
 668         writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
 669         spin_unlock_irqrestore(&i2c->lock, flags);
 670 }
 671
 672 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
 673                               struct i2c_msg *msgs, int stop)
 674 {
 675         unsigned long timeout;
 676         int ret;
 677
 678         i2c->msg = msgs;
 679         i2c->msg_ptr = 0;
 680         i2c->trans_done = 0;
 681
 682         reinit_completion(&i2c->msg_complete);
 683
 684         exynos5_i2c_message_start(i2c, stop);
 685
 686         timeout = wait_for_completion_timeout(&i2c->msg_complete,
 687                                               EXYNOS5_I2C_TIMEOUT);
 688         if (timeout == 0)
 689                 ret = -ETIMEDOUT;
 690         else
 691                 ret = i2c->state;
 692
 693         /*
 694          * If this is the last message to be transfered (stop == 1)
 695          * Then check if the bus can be brought back to idle.
 696          */
 697         if (ret == 0 && stop)
 698                 ret = exynos5_i2c_wait_bus_idle(i2c);
 699
 700         if (ret < 0) {
 701                 exynos5_i2c_reset(i2c);
 702                 if (ret == -ETIMEDOUT)
 703                         dev_warn(i2c->dev, "%s timeout\n",
 704                                  (msgs->flags & I2C_M_RD) ? "rx" : "tx");
 705         }
 706
 707         /* Return the state as in interrupt routine */
 708         return ret;
 709 }
 710
 711 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
 712                         struct i2c_msg *msgs, int num)
 713 {
 714         struct exynos5_i2c *i2c = adap->algo_data;
 715         int i, ret;
 716
 717         ret = clk_enable(i2c->clk);
 718         if (ret)
 719                 return ret;
 720
 721         for (i = 0; i < num; ++i) {
 722                 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
 723                 if (ret)
 724                         break;
 725         }
 726
 727         clk_disable(i2c->clk);
 728
 729         return ret ?: num;
 730 }
 731
 732 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
 733 {
 734         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 735 }
 736
 737 static const struct i2c_algorithm exynos5_i2c_algorithm = {
 738         .master_xfer            = exynos5_i2c_xfer,
 739         .functionality          = exynos5_i2c_func,
 740 };
 741
 742 static int exynos5_i2c_probe(struct platform_device *pdev)
 743 {
 744         struct device_node *np = pdev->dev.of_node;
 745         struct exynos5_i2c *i2c;
 746         struct resource *mem;
 747         int ret;
 748
 749         i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
 750         if (!i2c)
 751                 return -ENOMEM;
 752
 753         if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
 754                 i2c->op_clock = HSI2C_FS_TX_CLOCK;
 755
 756         strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
 757         i2c->adap.owner   = THIS_MODULE;
 758         i2c->adap.algo    = &exynos5_i2c_algorithm;
 759         i2c->adap.retries = 3;
 760
 761         i2c->dev = &pdev->dev;
 762         i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
 763         if (IS_ERR(i2c->clk)) {
 764                 dev_err(&pdev->dev, "cannot get clock\n");
 765                 return -ENOENT;
 766         }
 767
 768         ret = clk_prepare_enable(i2c->clk);
 769         if (ret)
 770                 return ret;
 771
 772         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 773         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
 774         if (IS_ERR(i2c->regs)) {
 775                 ret = PTR_ERR(i2c->regs);
 776                 goto err_clk;
 777         }
 778
 779         i2c->adap.dev.of_node = np;
 780         i2c->adap.algo_data = i2c;
 781         i2c->adap.dev.parent = &pdev->dev;
 782
 783         /* Clear pending interrupts from u-boot or misc causes */
 784         exynos5_i2c_clr_pend_irq(i2c);
 785
 786         spin_lock_init(&i2c->lock);
 787         init_completion(&i2c->msg_complete);
 788
 789         i2c->irq = ret = platform_get_irq(pdev, 0);
 790         if (ret <= 0) {
 791                 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
 792                 ret = -EINVAL;
 793                 goto err_clk;
 794         }
 795
 796         ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
 797                                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 798                                 dev_name(&pdev->dev), i2c);
 799
 800         if (ret != 0) {
 801                 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
 802                 goto err_clk;
 803         }
 804
 805         i2c->variant = of_device_get_match_data(&pdev->dev);
 806
 807         ret = exynos5_hsi2c_clock_setup(i2c);
 808         if (ret)
 809                 goto err_clk;
 810
 811         exynos5_i2c_reset(i2c);
 812
 813         ret = i2c_add_adapter(&i2c->adap);
 814         if (ret < 0)
 815                 goto err_clk;
 816
 817         platform_set_drvdata(pdev, i2c);
 818
 819         clk_disable(i2c->clk);
 820
 821         return 0;
 822
 823  err_clk:
 824         clk_disable_unprepare(i2c->clk);
 825         return ret;
 826 }
 827
 828 static int exynos5_i2c_remove(struct platform_device *pdev)
 829 {
 830         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 831
 832         i2c_del_adapter(&i2c->adap);
 833
 834         clk_unprepare(i2c->clk);
 835
 836         return 0;
 837 }
 838
 839 #ifdef CONFIG_PM_SLEEP
 840 static int exynos5_i2c_suspend_noirq(struct device *dev)
 841 {
 842         struct exynos5_i2c *i2c = dev_get_drvdata(dev);
 843
 844         i2c_mark_adapter_suspended(&i2c->adap);
 845         clk_unprepare(i2c->clk);
 846
 847         return 0;
 848 }
 849
 850 static int exynos5_i2c_resume_noirq(struct device *dev)
 851 {
 852         struct exynos5_i2c *i2c = dev_get_drvdata(dev);
 853         int ret = 0;
 854
 855         ret = clk_prepare_enable(i2c->clk);
 856         if (ret)
 857                 return ret;
 858
 859         ret = exynos5_hsi2c_clock_setup(i2c);
 860         if (ret) {
 861                 clk_disable_unprepare(i2c->clk);
 862                 return ret;
 863         }
 864
 865         exynos5_i2c_init(i2c);
 866         clk_disable(i2c->clk);
 867         i2c_mark_adapter_resumed(&i2c->adap);
 868
 869         return 0;
 870 }
 871 #endif
 872
 873 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
 874         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
 875                                       exynos5_i2c_resume_noirq)
 876 };
 877
 878 static struct platform_driver exynos5_i2c_driver = {
 879         .probe          = exynos5_i2c_probe,
 880         .remove         = exynos5_i2c_remove,
 881         .driver         = {
 882                 .name   = "exynos5-hsi2c",
 883                 .pm     = &exynos5_i2c_dev_pm_ops,
 884                 .of_match_table = exynos5_i2c_match,
 885         },
 886 };
 887
 888 module_platform_driver(exynos5_i2c_driver);
 889
 890 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
 891 MODULE_AUTHOR("Naveen Krishna Chatradhi, <[email protected]>");
 892 MODULE_AUTHOR("Taekgyun Ko, <[email protected]>");
 893 MODULE_LICENSE("GPL v2");