drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

   1 /*
   2  * Copyright 2023 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_12_0_0_offset.h"
  30 #include "gc/gc_12_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v12_structs.h"
  33 #include "mes_v12_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_12_0_0_mes1.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_12_0_0_uni_mes.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin");
  41
  42 static int mes_v12_0_hw_init(void *handle);
  43 static int mes_v12_0_hw_fini(void *handle);
  44 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev);
  45 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev);
  46
  47 #define MES_EOP_SIZE   2048
  48
  49 static void mes_v12_0_ring_set_wptr(struct amdgpu_ring *ring)
  50 {
  51         struct amdgpu_device *adev = ring->adev;
  52
  53         if (ring->use_doorbell) {
  54                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  55                              ring->wptr);
  56                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  57         } else {
  58                 BUG();
  59         }
  60 }
  61
  62 static u64 mes_v12_0_ring_get_rptr(struct amdgpu_ring *ring)
  63 {
  64         return *ring->rptr_cpu_addr;
  65 }
  66
  67 static u64 mes_v12_0_ring_get_wptr(struct amdgpu_ring *ring)
  68 {
  69         u64 wptr;
  70
  71         if (ring->use_doorbell)
  72                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  73         else
  74                 BUG();
  75         return wptr;
  76 }
  77
  78 static const struct amdgpu_ring_funcs mes_v12_0_ring_funcs = {
  79         .type = AMDGPU_RING_TYPE_MES,
  80         .align_mask = 1,
  81         .nop = 0,
  82         .support_64bit_ptrs = true,
  83         .get_rptr = mes_v12_0_ring_get_rptr,
  84         .get_wptr = mes_v12_0_ring_get_wptr,
  85         .set_wptr = mes_v12_0_ring_set_wptr,
  86         .insert_nop = amdgpu_ring_insert_nop,
  87 };
  88
  89 static const char *mes_v12_0_opcodes[] = {
  90         "SET_HW_RSRC",
  91         "SET_SCHEDULING_CONFIG",
  92         "ADD_QUEUE",
  93         "REMOVE_QUEUE",
  94         "PERFORM_YIELD",
  95         "SET_GANG_PRIORITY_LEVEL",
  96         "SUSPEND",
  97         "RESUME",
  98         "RESET",
  99         "SET_LOG_BUFFER",
 100         "CHANGE_GANG_PRORITY",
 101         "QUERY_SCHEDULER_STATUS",
 102         "SET_DEBUG_VMID",
 103         "MISC",
 104         "UPDATE_ROOT_PAGE_TABLE",
 105         "AMD_LOG",
 106         "SET_SE_MODE",
 107         "SET_GANG_SUBMIT",
 108         "SET_HW_RSRC_1",
 109 };
 110
 111 static const char *mes_v12_0_misc_opcodes[] = {
 112         "WRITE_REG",
 113         "INV_GART",
 114         "QUERY_STATUS",
 115         "READ_REG",
 116         "WAIT_REG_MEM",
 117         "SET_SHADER_DEBUGGER",
 118         "NOTIFY_WORK_ON_UNMAPPED_QUEUE",
 119         "NOTIFY_TO_UNMAP_PROCESSES",
 120 };
 121
 122 static const char *mes_v12_0_get_op_string(union MESAPI__MISC *x_pkt)
 123 {
 124         const char *op_str = NULL;
 125
 126         if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_0_opcodes))
 127                 op_str = mes_v12_0_opcodes[x_pkt->header.opcode];
 128
 129         return op_str;
 130 }
 131
 132 static const char *mes_v12_0_get_misc_op_string(union MESAPI__MISC *x_pkt)
 133 {
 134         const char *op_str = NULL;
 135
 136         if ((x_pkt->header.opcode == MES_SCH_API_MISC) &&
 137             (x_pkt->opcode < ARRAY_SIZE(mes_v12_0_misc_opcodes)))
 138                 op_str = mes_v12_0_misc_opcodes[x_pkt->opcode];
 139
 140         return op_str;
 141 }
 142
 143 static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
 144                                                     void *pkt, int size,
 145                                                     int api_status_off)
 146 {
 147         int ndw = size / 4;
 148         signed long r;
 149         union MESAPI__MISC *x_pkt = pkt;
 150         struct MES_API_STATUS *api_status;
 151         struct amdgpu_device *adev = mes->adev;
 152         struct amdgpu_ring *ring = &mes->ring;
 153         unsigned long flags;
 154         const char *op_str, *misc_op_str;
 155         signed long timeout = 3000000; /* 3000 ms */
 156         u32 fence_offset;
 157         u64 fence_gpu_addr;
 158         u64 *fence_ptr;
 159         int ret;
 160
 161         if (x_pkt->header.opcode >= MES_SCH_API_MAX)
 162                 return -EINVAL;
 163
 164         if (amdgpu_emu_mode) {
 165                 timeout *= 100;
 166         } else if (amdgpu_sriov_vf(adev)) {
 167                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 168                 timeout = 15 * 600 * 1000;
 169         }
 170         BUG_ON(size % 4 != 0);
 171
 172         ret = amdgpu_device_wb_get(adev, &fence_offset);
 173         if (ret)
 174                 return ret;
 175         fence_gpu_addr =
 176                 adev->wb.gpu_addr + (fence_offset * 4);
 177         fence_ptr = (u64 *)&adev->wb.wb[fence_offset];
 178         *fence_ptr = 0;
 179
 180         spin_lock_irqsave(&mes->ring_lock, flags);
 181         if (amdgpu_ring_alloc(ring, ndw)) {
 182                 spin_unlock_irqrestore(&mes->ring_lock, flags);
 183                 amdgpu_device_wb_free(adev, fence_offset);
 184                 return -ENOMEM;
 185         }
 186
 187         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 188         api_status->api_completion_fence_addr = fence_gpu_addr;
 189         api_status->api_completion_fence_value = 1;
 190
 191         amdgpu_ring_write_multiple(ring, pkt, ndw);
 192         amdgpu_ring_commit(ring);
 193         spin_unlock_irqrestore(&mes->ring_lock, flags);
 194
 195         op_str = mes_v12_0_get_op_string(x_pkt);
 196         misc_op_str = mes_v12_0_get_misc_op_string(x_pkt);
 197
 198         if (misc_op_str)
 199                 dev_dbg(adev->dev, "MES msg=%s (%s) was emitted\n", op_str, misc_op_str);
 200         else if (op_str)
 201                 dev_dbg(adev->dev, "MES msg=%s was emitted\n", op_str);
 202         else
 203                 dev_dbg(adev->dev, "MES msg=%d was emitted\n", x_pkt->header.opcode);
 204
 205         r = amdgpu_mes_fence_wait_polling(fence_ptr, (u64)1, timeout);
 206         amdgpu_device_wb_free(adev, fence_offset);
 207
 208         if (r < 1) {
 209                 if (misc_op_str)
 210                         dev_err(adev->dev, "MES failed to respond to msg=%s (%s)\n",
 211                                 op_str, misc_op_str);
 212                 else if (op_str)
 213                         dev_err(adev->dev, "MES failed to respond to msg=%s\n",
 214                                 op_str);
 215                 else
 216                         dev_err(adev->dev, "MES failed to respond to msg=%d\n",
 217                                 x_pkt->header.opcode);
 218
 219                 while (halt_if_hws_hang)
 220                         schedule();
 221
 222                 return -ETIMEDOUT;
 223         }
 224
 225         return 0;
 226 }
 227
 228 static int convert_to_mes_queue_type(int queue_type)
 229 {
 230         if (queue_type == AMDGPU_RING_TYPE_GFX)
 231                 return MES_QUEUE_TYPE_GFX;
 232         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 233                 return MES_QUEUE_TYPE_COMPUTE;
 234         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 235                 return MES_QUEUE_TYPE_SDMA;
 236         else
 237                 BUG();
 238         return -1;
 239 }
 240
 241 static int mes_v12_0_add_hw_queue(struct amdgpu_mes *mes,
 242                                   struct mes_add_queue_input *input)
 243 {
 244         struct amdgpu_device *adev = mes->adev;
 245         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 246         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
 247         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 248
 249         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 250
 251         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 252         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 253         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 254
 255         mes_add_queue_pkt.process_id = input->process_id;
 256         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 257         mes_add_queue_pkt.process_va_start = input->process_va_start;
 258         mes_add_queue_pkt.process_va_end = input->process_va_end;
 259         mes_add_queue_pkt.process_quantum = input->process_quantum;
 260         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 261         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 262         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 263         mes_add_queue_pkt.inprocess_gang_priority =
 264                 input->inprocess_gang_priority;
 265         mes_add_queue_pkt.gang_global_priority_level =
 266                 input->gang_global_priority_level;
 267         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 268         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 269
 270         mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 271
 272         mes_add_queue_pkt.queue_type =
 273                 convert_to_mes_queue_type(input->queue_type);
 274         mes_add_queue_pkt.paging = input->paging;
 275         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 276         mes_add_queue_pkt.gws_base = input->gws_base;
 277         mes_add_queue_pkt.gws_size = input->gws_size;
 278         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 279         mes_add_queue_pkt.tma_addr = input->tma_addr;
 280         mes_add_queue_pkt.trap_en = input->trap_en;
 281         mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear;
 282         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 283
 284         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 285         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 286         mes_add_queue_pkt.gds_size = input->queue_size;
 287
 288         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 289         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 290         mes_add_queue_pkt.gds_size = input->queue_size;
 291
 292         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 293                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 294                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 295 }
 296
 297 static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes,
 298                                      struct mes_remove_queue_input *input)
 299 {
 300         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 301
 302         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 303
 304         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 305         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 306         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 307
 308         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 309         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 310
 311         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 312                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 313                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 314 }
 315
 316 static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes,
 317                                       struct mes_map_legacy_queue_input *input)
 318 {
 319         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 320
 321         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 322
 323         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 324         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 325         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 326
 327         mes_add_queue_pkt.pipe_id = input->pipe_id;
 328         mes_add_queue_pkt.queue_id = input->queue_id;
 329         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 330         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 331         mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 332         mes_add_queue_pkt.queue_type =
 333                 convert_to_mes_queue_type(input->queue_type);
 334         mes_add_queue_pkt.map_legacy_kq = 1;
 335
 336         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 337                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 338                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 339 }
 340
 341 static int mes_v12_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 342                         struct mes_unmap_legacy_queue_input *input)
 343 {
 344         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 345
 346         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 347
 348         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 349         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 350         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 351
 352         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 353         mes_remove_queue_pkt.gang_context_addr = 0;
 354
 355         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 356         mes_remove_queue_pkt.queue_id = input->queue_id;
 357
 358         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 359                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 360                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 361                 mes_remove_queue_pkt.tf_data =
 362                         lower_32_bits(input->trail_fence_data);
 363         } else {
 364                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 365                 mes_remove_queue_pkt.queue_type =
 366                         convert_to_mes_queue_type(input->queue_type);
 367         }
 368
 369         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 370                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 371                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 372 }
 373
 374 static int mes_v12_0_suspend_gang(struct amdgpu_mes *mes,
 375                                   struct mes_suspend_gang_input *input)
 376 {
 377         return 0;
 378 }
 379
 380 static int mes_v12_0_resume_gang(struct amdgpu_mes *mes,
 381                                  struct mes_resume_gang_input *input)
 382 {
 383         return 0;
 384 }
 385
 386 static int mes_v12_0_query_sched_status(struct amdgpu_mes *mes)
 387 {
 388         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 389
 390         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 391
 392         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 393         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 394         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 395
 396         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 397                         &mes_status_pkt, sizeof(mes_status_pkt),
 398                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 399 }
 400
 401 static int mes_v12_0_misc_op(struct amdgpu_mes *mes,
 402                              struct mes_misc_op_input *input)
 403 {
 404         union MESAPI__MISC misc_pkt;
 405
 406         memset(&misc_pkt, 0, sizeof(misc_pkt));
 407
 408         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 409         misc_pkt.header.opcode = MES_SCH_API_MISC;
 410         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 411
 412         switch (input->op) {
 413         case MES_MISC_OP_READ_REG:
 414                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 415                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 416                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 417                 break;
 418         case MES_MISC_OP_WRITE_REG:
 419                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 420                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 421                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 422                 break;
 423         case MES_MISC_OP_WRM_REG_WAIT:
 424                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 425                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 426                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 427                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 428                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 429                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 430                 break;
 431         case MES_MISC_OP_WRM_REG_WR_WAIT:
 432                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 433                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 434                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 435                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 436                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 437                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 438                 break;
 439         case MES_MISC_OP_SET_SHADER_DEBUGGER:
 440                 misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER;
 441                 misc_pkt.set_shader_debugger.process_context_addr =
 442                                 input->set_shader_debugger.process_context_addr;
 443                 misc_pkt.set_shader_debugger.flags.u32all =
 444                                 input->set_shader_debugger.flags.u32all;
 445                 misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl =
 446                                 input->set_shader_debugger.spi_gdbg_per_vmid_cntl;
 447                 memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl,
 448                                 input->set_shader_debugger.tcp_watch_cntl,
 449                                 sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
 450                 misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en;
 451                 break;
 452         default:
 453                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 454                 return -EINVAL;
 455         }
 456
 457         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 458                         &misc_pkt, sizeof(misc_pkt),
 459                         offsetof(union MESAPI__MISC, api_status));
 460 }
 461
 462 static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes)
 463 {
 464         union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt;
 465
 466         memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt));
 467
 468         mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER;
 469         mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1;
 470         mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 471         mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
 472
 473         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 474                         &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt),
 475                         offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 476 }
 477
 478 static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes)
 479 {
 480         int i;
 481         struct amdgpu_device *adev = mes->adev;
 482         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 483
 484         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 485
 486         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 487         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 488         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 489
 490         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 491         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 492         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 493         mes_set_hw_res_pkt.paging_vmid = 0;
 494         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 495         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 496                 mes->query_status_fence_gpu_addr;
 497
 498         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 499                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 500                         mes->compute_hqd_mask[i];
 501
 502         for (i = 0; i < MAX_GFX_PIPES; i++)
 503                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 504
 505         for (i = 0; i < MAX_SDMA_PIPES; i++)
 506                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 507
 508         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 509                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 510                         mes->aggregated_doorbells[i];
 511
 512         for (i = 0; i < 5; i++) {
 513                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 514                 mes_set_hw_res_pkt.mmhub_base[i] =
 515                                 adev->reg_offset[MMHUB_HWIP][0][i];
 516                 mes_set_hw_res_pkt.osssys_base[i] =
 517                 adev->reg_offset[OSSSYS_HWIP][0][i];
 518         }
 519
 520         mes_set_hw_res_pkt.disable_reset = 1;
 521         mes_set_hw_res_pkt.disable_mes_log = 1;
 522         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 523         mes_set_hw_res_pkt.enable_reg_active_poll = 1;
 524
 525         /*
 526          * Keep oversubscribe timer for sdma . When we have unmapped doorbell
 527          * handling support, other queue will not use the oversubscribe timer.
 528          * handling  mode - 0: disabled; 1: basic version; 2: basic+ version
 529          */
 530         mes_set_hw_res_pkt.oversubscription_timer = 50;
 531         mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
 532
 533         mes_set_hw_res_pkt.enable_mes_event_int_logging = 0;
 534         mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
 535
 536         return mes_v12_0_submit_pkt_and_poll_completion(mes,
 537                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 538                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 539 }
 540
 541 static void mes_v12_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
 542 {
 543         struct amdgpu_device *adev = mes->adev;
 544         uint32_t data;
 545
 546         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
 547         data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
 548                   CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
 549                   CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
 550         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
 551                 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
 552         data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
 553         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
 554
 555         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
 556         data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
 557                   CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
 558                   CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
 559         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
 560                 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
 561         data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
 562         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
 563
 564         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
 565         data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
 566                   CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
 567                   CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
 568         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
 569                 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
 570         data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
 571         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
 572
 573         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
 574         data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
 575                   CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
 576                   CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
 577         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
 578                 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
 579         data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
 580         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
 581
 582         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
 583         data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
 584                   CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
 585                   CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
 586         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
 587                 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
 588         data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
 589         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
 590
 591         data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
 592         WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
 593 }
 594
 595
 596 static void mes_v12_0_enable_unmapped_doorbell_handling(
 597                 struct amdgpu_mes *mes, bool enable)
 598 {
 599         struct amdgpu_device *adev = mes->adev;
 600         uint32_t data = RREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL);
 601
 602         /*
 603          * The default PROC_LSB settng is 0xc which means doorbell
 604          * addr[16:12] gives the doorbell page number. For kfd, each
 605          * process will use 2 pages of doorbell, we need to change the
 606          * setting to 0xd
 607          */
 608         data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK;
 609         data |= 0xd <<  CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT;
 610
 611         data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT;
 612
 613         WREG32_SOC15(GC, 0, regCP_UNMAPPED_DOORBELL, data);
 614 }
 615
 616 static const struct amdgpu_mes_funcs mes_v12_0_funcs = {
 617         .add_hw_queue = mes_v12_0_add_hw_queue,
 618         .remove_hw_queue = mes_v12_0_remove_hw_queue,
 619         .map_legacy_queue = mes_v12_0_map_legacy_queue,
 620         .unmap_legacy_queue = mes_v12_0_unmap_legacy_queue,
 621         .suspend_gang = mes_v12_0_suspend_gang,
 622         .resume_gang = mes_v12_0_resume_gang,
 623         .misc_op = mes_v12_0_misc_op,
 624 };
 625
 626 static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 627                                            enum admgpu_mes_pipe pipe)
 628 {
 629         int r;
 630         const struct mes_firmware_header_v1_0 *mes_hdr;
 631         const __le32 *fw_data;
 632         unsigned fw_size;
 633
 634         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 635                 adev->mes.fw[pipe]->data;
 636
 637         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 638                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 639         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 640
 641         r = amdgpu_bo_create_reserved(adev, fw_size,
 642                                       PAGE_SIZE,
 643                                       AMDGPU_GEM_DOMAIN_VRAM,
 644                                       &adev->mes.ucode_fw_obj[pipe],
 645                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 646                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 647         if (r) {
 648                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 649                 return r;
 650         }
 651
 652         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 653
 654         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 655         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 656
 657         return 0;
 658 }
 659
 660 static int mes_v12_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 661                                                 enum admgpu_mes_pipe pipe)
 662 {
 663         int r;
 664         const struct mes_firmware_header_v1_0 *mes_hdr;
 665         const __le32 *fw_data;
 666         unsigned fw_size;
 667
 668         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 669                 adev->mes.fw[pipe]->data;
 670
 671         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 672                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 673         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 674
 675         r = amdgpu_bo_create_reserved(adev, fw_size,
 676                                       64 * 1024,
 677                                       AMDGPU_GEM_DOMAIN_VRAM,
 678                                       &adev->mes.data_fw_obj[pipe],
 679                                       &adev->mes.data_fw_gpu_addr[pipe],
 680                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 681         if (r) {
 682                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 683                 return r;
 684         }
 685
 686         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 687
 688         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 689         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 690
 691         return 0;
 692 }
 693
 694 static void mes_v12_0_free_ucode_buffers(struct amdgpu_device *adev,
 695                                          enum admgpu_mes_pipe pipe)
 696 {
 697         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 698                               &adev->mes.data_fw_gpu_addr[pipe],
 699                               (void **)&adev->mes.data_fw_ptr[pipe]);
 700
 701         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 702                               &adev->mes.ucode_fw_gpu_addr[pipe],
 703                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 704 }
 705
 706 static void mes_v12_0_enable(struct amdgpu_device *adev, bool enable)
 707 {
 708         uint64_t ucode_addr;
 709         uint32_t pipe, data = 0;
 710
 711         if (enable) {
 712                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 713                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 714                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 715                        (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);
 716                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 717
 718                 mutex_lock(&adev->srbm_mutex);
 719                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 720                         if ((!adev->enable_mes_kiq || adev->enable_uni_mes) &&
 721                             pipe == AMDGPU_MES_KIQ_PIPE)
 722                                 continue;
 723
 724                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 725
 726                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 727                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 728                                      lower_32_bits(ucode_addr));
 729                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 730                                      upper_32_bits(ucode_addr));
 731                 }
 732                 soc21_grbm_select(adev, 0, 0, 0, 0);
 733                 mutex_unlock(&adev->srbm_mutex);
 734
 735                 /* unhalt MES and activate pipe0 */
 736                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 737                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 738                        (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);
 739                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 740
 741                 if (amdgpu_emu_mode)
 742                         msleep(100);
 743                 else if (adev->enable_uni_mes)
 744                         udelay(500);
 745                 else
 746                         udelay(50);
 747         } else {
 748                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 749                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 750                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 751                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 752                                      MES_INVALIDATE_ICACHE, 1);
 753                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 754                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 755                        (!adev->enable_uni_mes && adev->enable_mes_kiq) ? 1 : 0);
 756                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 757                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 758         }
 759 }
 760
 761 static void mes_v12_0_set_ucode_start_addr(struct amdgpu_device *adev)
 762 {
 763         uint64_t ucode_addr;
 764         int pipe;
 765
 766         mes_v12_0_enable(adev, false);
 767
 768         mutex_lock(&adev->srbm_mutex);
 769         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 770                 if ((!adev->enable_mes_kiq || adev->enable_uni_mes) &&
 771                     pipe == AMDGPU_MES_KIQ_PIPE)
 772                         continue;
 773
 774                 /* me=3, queue=0 */
 775                 soc21_grbm_select(adev, 3, pipe, 0, 0);
 776
 777                 /* set ucode start address */
 778                 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 779                 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 780                                 lower_32_bits(ucode_addr));
 781                 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 782                                 upper_32_bits(ucode_addr));
 783
 784                 soc21_grbm_select(adev, 0, 0, 0, 0);
 785         }
 786         mutex_unlock(&adev->srbm_mutex);
 787 }
 788
 789 /* This function is for backdoor MES firmware */
 790 static int mes_v12_0_load_microcode(struct amdgpu_device *adev,
 791                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 792 {
 793         int r;
 794         uint32_t data;
 795
 796         mes_v12_0_enable(adev, false);
 797
 798         if (!adev->mes.fw[pipe])
 799                 return -EINVAL;
 800
 801         r = mes_v12_0_allocate_ucode_buffer(adev, pipe);
 802         if (r)
 803                 return r;
 804
 805         r = mes_v12_0_allocate_ucode_data_buffer(adev, pipe);
 806         if (r) {
 807                 mes_v12_0_free_ucode_buffers(adev, pipe);
 808                 return r;
 809         }
 810
 811         mutex_lock(&adev->srbm_mutex);
 812         /* me=3, pipe=0, queue=0 */
 813         soc21_grbm_select(adev, 3, pipe, 0, 0);
 814
 815         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 816
 817         /* set ucode fimrware address */
 818         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 819                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 820         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 821                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 822
 823         /* set ucode instruction cache boundary to 2M-1 */
 824         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 825
 826         /* set ucode data firmware address */
 827         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 828                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 829         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 830                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 831
 832         /* Set data cache boundary CP_MES_MDBOUND_LO */
 833         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF);
 834
 835         if (prime_icache) {
 836                 /* invalidate ICACHE */
 837                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 838                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 839                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 840                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 841
 842                 /* prime the ICACHE. */
 843                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 844                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 845                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 846         }
 847
 848         soc21_grbm_select(adev, 0, 0, 0, 0);
 849         mutex_unlock(&adev->srbm_mutex);
 850
 851         return 0;
 852 }
 853
 854 static int mes_v12_0_allocate_eop_buf(struct amdgpu_device *adev,
 855                                       enum admgpu_mes_pipe pipe)
 856 {
 857         int r;
 858         u32 *eop;
 859
 860         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 861                               AMDGPU_GEM_DOMAIN_GTT,
 862                               &adev->mes.eop_gpu_obj[pipe],
 863                               &adev->mes.eop_gpu_addr[pipe],
 864                               (void **)&eop);
 865         if (r) {
 866                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 867                 return r;
 868         }
 869
 870         memset(eop, 0,
 871                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 872
 873         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 874         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 875
 876         return 0;
 877 }
 878
 879 static int mes_v12_0_mqd_init(struct amdgpu_ring *ring)
 880 {
 881         struct v12_compute_mqd *mqd = ring->mqd_ptr;
 882         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 883         uint32_t tmp;
 884
 885         mqd->header = 0xC0310800;
 886         mqd->compute_pipelinestat_enable = 0x00000001;
 887         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 888         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 889         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 890         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 891         mqd->compute_misc_reserved = 0x00000007;
 892
 893         eop_base_addr = ring->eop_gpu_addr >> 8;
 894
 895         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 896         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 897         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 898                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 899
 900         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 901         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 902         mqd->cp_hqd_eop_control = tmp;
 903
 904         /* disable the queue if it's active */
 905         ring->wptr = 0;
 906         mqd->cp_hqd_pq_rptr = 0;
 907         mqd->cp_hqd_pq_wptr_lo = 0;
 908         mqd->cp_hqd_pq_wptr_hi = 0;
 909
 910         /* set the pointer to the MQD */
 911         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 912         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 913
 914         /* set MQD vmid to 0 */
 915         tmp = regCP_MQD_CONTROL_DEFAULT;
 916         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 917         mqd->cp_mqd_control = tmp;
 918
 919         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 920         hqd_gpu_addr = ring->gpu_addr >> 8;
 921         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 922         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 923
 924         /* set the wb address whether it's enabled or not */
 925         wb_gpu_addr = ring->rptr_gpu_addr;
 926         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 927         mqd->cp_hqd_pq_rptr_report_addr_hi =
 928                 upper_32_bits(wb_gpu_addr) & 0xffff;
 929
 930         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 931         wb_gpu_addr = ring->wptr_gpu_addr;
 932         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 933         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 934
 935         /* set up the HQD, this is similar to CP_RB0_CNTL */
 936         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 937         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 938                             (order_base_2(ring->ring_size / 4) - 1));
 939         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 940                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 941         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 942         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 943         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 944         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 945         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 946         mqd->cp_hqd_pq_control = tmp;
 947
 948         /* enable doorbell */
 949         tmp = 0;
 950         if (ring->use_doorbell) {
 951                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 952                                     DOORBELL_OFFSET, ring->doorbell_index);
 953                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 954                                     DOORBELL_EN, 1);
 955                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 956                                     DOORBELL_SOURCE, 0);
 957                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 958                                     DOORBELL_HIT, 0);
 959         } else {
 960                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 961                                     DOORBELL_EN, 0);
 962         }
 963         mqd->cp_hqd_pq_doorbell_control = tmp;
 964
 965         mqd->cp_hqd_vmid = 0;
 966         /* activate the queue */
 967         mqd->cp_hqd_active = 1;
 968
 969         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 970         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 971                             PRELOAD_SIZE, 0x55);
 972         mqd->cp_hqd_persistent_state = tmp;
 973
 974         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 975         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 976         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 977
 978         /*
 979          * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped
 980          * doorbell handling. This is a reserved CP internal register can
 981          * not be accesss by others
 982          */
 983         mqd->reserved_184 = BIT(15);
 984
 985         return 0;
 986 }
 987
 988 static void mes_v12_0_queue_init_register(struct amdgpu_ring *ring)
 989 {
 990         struct v12_compute_mqd *mqd = ring->mqd_ptr;
 991         struct amdgpu_device *adev = ring->adev;
 992         uint32_t data = 0;
 993
 994         mutex_lock(&adev->srbm_mutex);
 995         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 996
 997         /* set CP_HQD_VMID.VMID = 0. */
 998         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 999         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
1000         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
1001
1002         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
1003         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1004         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1005                              DOORBELL_EN, 0);
1006         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1007
1008         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
1009         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
1010         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
1011
1012         /* set CP_MQD_CONTROL.VMID=0 */
1013         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
1014         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
1015         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
1016
1017         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
1018         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
1019         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
1020
1021         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
1022         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
1023                      mqd->cp_hqd_pq_rptr_report_addr_lo);
1024         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1025                      mqd->cp_hqd_pq_rptr_report_addr_hi);
1026
1027         /* set CP_HQD_PQ_CONTROL */
1028         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
1029
1030         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
1031         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
1032                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
1033         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1034                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
1035
1036         /* set CP_HQD_PQ_DOORBELL_CONTROL */
1037         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
1038                      mqd->cp_hqd_pq_doorbell_control);
1039
1040         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
1041         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
1042
1043         /* set CP_HQD_ACTIVE.ACTIVE=1 */
1044         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
1045
1046         soc21_grbm_select(adev, 0, 0, 0, 0);
1047         mutex_unlock(&adev->srbm_mutex);
1048 }
1049
1050 static int mes_v12_0_kiq_enable_queue(struct amdgpu_device *adev)
1051 {
1052         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1053         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
1054         int r;
1055
1056         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
1057                 return -EINVAL;
1058
1059         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
1060         if (r) {
1061                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
1062                 return r;
1063         }
1064
1065         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
1066
1067         r = amdgpu_ring_test_ring(kiq_ring);
1068         if (r) {
1069                 DRM_ERROR("kfq enable failed\n");
1070                 kiq_ring->sched.ready = false;
1071         }
1072         return r;
1073 }
1074
1075 static int mes_v12_0_queue_init(struct amdgpu_device *adev,
1076                                 enum admgpu_mes_pipe pipe)
1077 {
1078         struct amdgpu_ring *ring;
1079         int r;
1080
1081         if (pipe == AMDGPU_MES_KIQ_PIPE)
1082                 ring = &adev->gfx.kiq[0].ring;
1083         else if (pipe == AMDGPU_MES_SCHED_PIPE)
1084                 ring = &adev->mes.ring;
1085         else
1086                 BUG();
1087
1088         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
1089             (amdgpu_in_reset(adev) || adev->in_suspend)) {
1090                 *(ring->wptr_cpu_addr) = 0;
1091                 *(ring->rptr_cpu_addr) = 0;
1092                 amdgpu_ring_clear_ring(ring);
1093         }
1094
1095         r = mes_v12_0_mqd_init(ring);
1096         if (r)
1097                 return r;
1098
1099         if (pipe == AMDGPU_MES_SCHED_PIPE) {
1100                 if (adev->enable_uni_mes) {
1101                         mes_v12_0_queue_init_register(ring);
1102                 } else {
1103                         r = mes_v12_0_kiq_enable_queue(adev);
1104                         if (r)
1105                                 return r;
1106                 }
1107         } else {
1108                 mes_v12_0_queue_init_register(ring);
1109         }
1110
1111         /* get MES scheduler/KIQ versions */
1112         mutex_lock(&adev->srbm_mutex);
1113         soc21_grbm_select(adev, 3, pipe, 0, 0);
1114
1115         if (pipe == AMDGPU_MES_SCHED_PIPE)
1116                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1117         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
1118                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
1119
1120         soc21_grbm_select(adev, 0, 0, 0, 0);
1121         mutex_unlock(&adev->srbm_mutex);
1122
1123         return 0;
1124 }
1125
1126 static int mes_v12_0_ring_init(struct amdgpu_device *adev)
1127 {
1128         struct amdgpu_ring *ring;
1129
1130         ring = &adev->mes.ring;
1131
1132         ring->funcs = &mes_v12_0_ring_funcs;
1133
1134         ring->me = 3;
1135         ring->pipe = 0;
1136         ring->queue = 0;
1137
1138         ring->ring_obj = NULL;
1139         ring->use_doorbell = true;
1140         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1141         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1142         ring->no_scheduler = true;
1143         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1144
1145         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1146                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1147 }
1148
1149 static int mes_v12_0_kiq_ring_init(struct amdgpu_device *adev)
1150 {
1151         struct amdgpu_ring *ring;
1152
1153         spin_lock_init(&adev->gfx.kiq[0].ring_lock);
1154
1155         ring = &adev->gfx.kiq[0].ring;
1156
1157         ring->me = 3;
1158         ring->pipe = adev->enable_uni_mes ? 0 : 1;
1159         ring->queue = 0;
1160
1161         ring->adev = NULL;
1162         ring->ring_obj = NULL;
1163         ring->use_doorbell = true;
1164         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1165         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1166         ring->no_scheduler = true;
1167         sprintf(ring->name, "mes_kiq_%d.%d.%d",
1168                 ring->me, ring->pipe, ring->queue);
1169
1170         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1171                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1172 }
1173
1174 static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev,
1175                                  enum admgpu_mes_pipe pipe)
1176 {
1177         int r, mqd_size = sizeof(struct v12_compute_mqd);
1178         struct amdgpu_ring *ring;
1179
1180         if (pipe == AMDGPU_MES_KIQ_PIPE)
1181                 ring = &adev->gfx.kiq[0].ring;
1182         else if (pipe == AMDGPU_MES_SCHED_PIPE)
1183                 ring = &adev->mes.ring;
1184         else
1185                 BUG();
1186
1187         if (ring->mqd_obj)
1188                 return 0;
1189
1190         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1191                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1192                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
1193         if (r) {
1194                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1195                 return r;
1196         }
1197
1198         memset(ring->mqd_ptr, 0, mqd_size);
1199
1200         /* prepare MQD backup */
1201         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1202         if (!adev->mes.mqd_backup[pipe])
1203                 dev_warn(adev->dev,
1204                          "no memory to create MQD backup for ring %s\n",
1205                          ring->name);
1206
1207         return 0;
1208 }
1209
1210 static int mes_v12_0_sw_init(void *handle)
1211 {
1212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213         int pipe, r;
1214
1215         adev->mes.funcs = &mes_v12_0_funcs;
1216         adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
1217         adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
1218
1219         r = amdgpu_mes_init(adev);
1220         if (r)
1221                 return r;
1222
1223         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1224                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1225                         continue;
1226
1227                 r = mes_v12_0_allocate_eop_buf(adev, pipe);
1228                 if (r)
1229                         return r;
1230
1231                 r = mes_v12_0_mqd_sw_init(adev, pipe);
1232                 if (r)
1233                         return r;
1234         }
1235
1236         if (adev->enable_mes_kiq) {
1237                 r = mes_v12_0_kiq_ring_init(adev);
1238                 if (r)
1239                         return r;
1240         }
1241
1242         r = mes_v12_0_ring_init(adev);
1243         if (r)
1244                 return r;
1245
1246         return 0;
1247 }
1248
1249 static int mes_v12_0_sw_fini(void *handle)
1250 {
1251         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1252         int pipe;
1253
1254         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1255         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1256
1257         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1258                 kfree(adev->mes.mqd_backup[pipe]);
1259
1260                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1261                                       &adev->mes.eop_gpu_addr[pipe],
1262                                       NULL);
1263                 amdgpu_ucode_release(&adev->mes.fw[pipe]);
1264         }
1265
1266         amdgpu_bo_free_kernel(&adev->gfx.kiq[0].ring.mqd_obj,
1267                               &adev->gfx.kiq[0].ring.mqd_gpu_addr,
1268                               &adev->gfx.kiq[0].ring.mqd_ptr);
1269
1270         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1271                               &adev->mes.ring.mqd_gpu_addr,
1272                               &adev->mes.ring.mqd_ptr);
1273
1274         amdgpu_ring_fini(&adev->gfx.kiq[0].ring);
1275         amdgpu_ring_fini(&adev->mes.ring);
1276
1277         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1278                 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1279                 mes_v12_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1280         }
1281
1282         amdgpu_mes_fini(adev);
1283         return 0;
1284 }
1285
1286 static void mes_v12_0_kiq_dequeue_sched(struct amdgpu_device *adev)
1287 {
1288         uint32_t data;
1289         int i;
1290
1291         mutex_lock(&adev->srbm_mutex);
1292         soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
1293
1294         /* disable the queue if it's active */
1295         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1296                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1297                 for (i = 0; i < adev->usec_timeout; i++) {
1298                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1299                                 break;
1300                         udelay(1);
1301                 }
1302         }
1303         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1304         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1305                                 DOORBELL_EN, 0);
1306         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1307                                 DOORBELL_HIT, 1);
1308         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1309
1310         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1311
1312         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1313         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1314         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1315
1316         soc21_grbm_select(adev, 0, 0, 0, 0);
1317         mutex_unlock(&adev->srbm_mutex);
1318
1319         adev->mes.ring.sched.ready = false;
1320 }
1321
1322 static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring)
1323 {
1324         uint32_t tmp;
1325         struct amdgpu_device *adev = ring->adev;
1326
1327         /* tell RLC which is KIQ queue */
1328         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1329         tmp &= 0xffffff00;
1330         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1331         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1332         tmp |= 0x80;
1333         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1334 }
1335
1336 static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev)
1337 {
1338         int r = 0;
1339
1340         mes_v12_0_kiq_setting(&adev->gfx.kiq[0].ring);
1341
1342         if (adev->enable_uni_mes)
1343                 return mes_v12_0_hw_init(adev);
1344
1345         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1346
1347                 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1348                 if (r) {
1349                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1350                         return r;
1351                 }
1352
1353                 r = mes_v12_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1354                 if (r) {
1355                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1356                         return r;
1357                 }
1358
1359                 mes_v12_0_set_ucode_start_addr(adev);
1360
1361         } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1362                 mes_v12_0_set_ucode_start_addr(adev);
1363
1364         mes_v12_0_enable(adev, true);
1365
1366         r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1367         if (r)
1368                 goto failure;
1369
1370         r = mes_v12_0_hw_init(adev);
1371         if (r)
1372                 goto failure;
1373
1374         return r;
1375
1376 failure:
1377         mes_v12_0_hw_fini(adev);
1378         return r;
1379 }
1380
1381 static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev)
1382 {
1383         if (adev->mes.ring.sched.ready) {
1384                 mes_v12_0_kiq_dequeue_sched(adev);
1385                 adev->mes.ring.sched.ready = false;
1386         }
1387
1388         mes_v12_0_enable(adev, false);
1389
1390         return 0;
1391 }
1392
1393 static int mes_v12_0_hw_init(void *handle)
1394 {
1395         int r;
1396         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1397
1398         if (adev->mes.ring.sched.ready)
1399                 goto out;
1400
1401         if (!adev->enable_mes_kiq || adev->enable_uni_mes) {
1402                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1403                         r = mes_v12_0_load_microcode(adev,
1404                                              AMDGPU_MES_SCHED_PIPE, true);
1405                         if (r) {
1406                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1407                                 return r;
1408                         }
1409
1410                         mes_v12_0_set_ucode_start_addr(adev);
1411
1412                 } else if (adev->firmware.load_type ==
1413                            AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1414
1415                         mes_v12_0_set_ucode_start_addr(adev);
1416                 }
1417
1418                 mes_v12_0_enable(adev, true);
1419         }
1420
1421         r = mes_v12_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1422         if (r)
1423                 goto failure;
1424
1425         r = mes_v12_0_set_hw_resources(&adev->mes);
1426         if (r)
1427                 goto failure;
1428
1429         if (adev->enable_uni_mes)
1430                 mes_v12_0_set_hw_resources_1(&adev->mes);
1431
1432         mes_v12_0_init_aggregated_doorbell(&adev->mes);
1433
1434         /* Enable the MES to handle doorbell ring on unmapped queue */
1435         mes_v12_0_enable_unmapped_doorbell_handling(&adev->mes, true);
1436
1437         r = mes_v12_0_query_sched_status(&adev->mes);
1438         if (r) {
1439                 DRM_ERROR("MES is busy\n");
1440                 goto failure;
1441         }
1442
1443 out:
1444         /*
1445          * Disable KIQ ring usage from the driver once MES is enabled.
1446          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1447          * with MES enabled.
1448          */
1449         adev->gfx.kiq[0].ring.sched.ready = false;
1450         adev->mes.ring.sched.ready = true;
1451
1452         return 0;
1453
1454 failure:
1455         mes_v12_0_hw_fini(adev);
1456         return r;
1457 }
1458
1459 static int mes_v12_0_hw_fini(void *handle)
1460 {
1461         return 0;
1462 }
1463
1464 static int mes_v12_0_suspend(void *handle)
1465 {
1466         int r;
1467         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1468
1469         r = amdgpu_mes_suspend(adev);
1470         if (r)
1471                 return r;
1472
1473         return mes_v12_0_hw_fini(adev);
1474 }
1475
1476 static int mes_v12_0_resume(void *handle)
1477 {
1478         int r;
1479         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1480
1481         r = mes_v12_0_hw_init(adev);
1482         if (r)
1483                 return r;
1484
1485         return amdgpu_mes_resume(adev);
1486 }
1487
1488 static int mes_v12_0_early_init(void *handle)
1489 {
1490         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1491         int pipe, r;
1492
1493         if (adev->enable_uni_mes) {
1494                 r = amdgpu_mes_init_microcode(adev, AMDGPU_MES_SCHED_PIPE);
1495                 if (!r)
1496                         return 0;
1497
1498                 adev->enable_uni_mes = false;
1499         }
1500
1501         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1502                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1503                         continue;
1504                 r = amdgpu_mes_init_microcode(adev, pipe);
1505                 if (r)
1506                         return r;
1507         }
1508
1509         return 0;
1510 }
1511
1512 static int mes_v12_0_late_init(void *handle)
1513 {
1514         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1515
1516         /* it's only intended for use in mes_self_test case, not for s0ix and reset */
1517         if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend)
1518                 amdgpu_mes_self_test(adev);
1519
1520         return 0;
1521 }
1522
1523 static const struct amd_ip_funcs mes_v12_0_ip_funcs = {
1524         .name = "mes_v12_0",
1525         .early_init = mes_v12_0_early_init,
1526         .late_init = mes_v12_0_late_init,
1527         .sw_init = mes_v12_0_sw_init,
1528         .sw_fini = mes_v12_0_sw_fini,
1529         .hw_init = mes_v12_0_hw_init,
1530         .hw_fini = mes_v12_0_hw_fini,
1531         .suspend = mes_v12_0_suspend,
1532         .resume = mes_v12_0_resume,
1533 };
1534
1535 const struct amdgpu_ip_block_version mes_v12_0_ip_block = {
1536         .type = AMD_IP_BLOCK_TYPE_MES,
1537         .major = 12,
1538         .minor = 0,
1539         .rev = 0,
1540         .funcs = &mes_v12_0_ip_funcs,
1541 };