drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "soc15.h"
  28 #include "soc15d.h"
  29 #include "soc15_common.h"
  30 #include "vega10_enum.h"
  31
  32 #include "v9_structs.h"
  33
  34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  35
  36 #include "gc/gc_9_4_3_offset.h"
  37 #include "gc/gc_9_4_3_sh_mask.h"
  38
  39 #include "gfx_v9_4_3.h"
  40 #include "amdgpu_xcp.h"
  41 #include "amdgpu_aca.h"
  42
  43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
  44 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin");
  45 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
  46 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin");
  47
  48 #define GFX9_MEC_HPD_SIZE 4096
  49 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  50
  51 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042
  52 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301
  53
  54 #define mmSMNAID_XCD0_MCA_SMU 0x36430400        /* SMN AID XCD0 */
  55 #define mmSMNAID_XCD1_MCA_SMU 0x38430400        /* SMN AID XCD1 */
  56 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400        /* SMN XCD XCD0 */
  57
  58 struct amdgpu_gfx_ras gfx_v9_4_3_ras;
  59
  60 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
  61 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev);
  62 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev);
  63 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev);
  64 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
  65                                 struct amdgpu_cu_info *cu_info);
  66
  67 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring,
  68                                 uint64_t queue_mask)
  69 {
  70         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
  71         amdgpu_ring_write(kiq_ring,
  72                 PACKET3_SET_RESOURCES_VMID_MASK(0) |
  73                 /* vmid_mask:0* queue_type:0 (KIQ) */
  74                 PACKET3_SET_RESOURCES_QUEUE_TYPE(0));
  75         amdgpu_ring_write(kiq_ring,
  76                         lower_32_bits(queue_mask));     /* queue mask lo */
  77         amdgpu_ring_write(kiq_ring,
  78                         upper_32_bits(queue_mask));     /* queue mask hi */
  79         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
  80         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
  81         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
  82         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
  83 }
  84
  85 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring,
  86                                  struct amdgpu_ring *ring)
  87 {
  88         struct amdgpu_device *adev = kiq_ring->adev;
  89         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
  90         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  91         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
  92
  93         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
  94         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
  95         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
  96                          PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
  97                          PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
  98                          PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
  99                          PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 100                          PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
 101                          /*queue_type: normal compute queue */
 102                          PACKET3_MAP_QUEUES_QUEUE_TYPE(0) |
 103                          /* alloc format: all_on_one_pipe */
 104                          PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) |
 105                          PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 106                          /* num_queues: must be 1 */
 107                          PACKET3_MAP_QUEUES_NUM_QUEUES(1));
 108         amdgpu_ring_write(kiq_ring,
 109                         PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 110         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 111         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 112         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 113         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 114 }
 115
 116 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 117                                    struct amdgpu_ring *ring,
 118                                    enum amdgpu_unmap_queues_action action,
 119                                    u64 gpu_addr, u64 seq)
 120 {
 121         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 122
 123         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 124         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 125                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 126                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 127                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 128                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 129         amdgpu_ring_write(kiq_ring,
 130                         PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 131
 132         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 133                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 134                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 135                 amdgpu_ring_write(kiq_ring, seq);
 136         } else {
 137                 amdgpu_ring_write(kiq_ring, 0);
 138                 amdgpu_ring_write(kiq_ring, 0);
 139                 amdgpu_ring_write(kiq_ring, 0);
 140         }
 141 }
 142
 143 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring,
 144                                    struct amdgpu_ring *ring,
 145                                    u64 addr,
 146                                    u64 seq)
 147 {
 148         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 149
 150         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 151         amdgpu_ring_write(kiq_ring,
 152                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 153                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 154                           PACKET3_QUERY_STATUS_COMMAND(2));
 155         /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 156         amdgpu_ring_write(kiq_ring,
 157                         PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 158                         PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 159         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 160         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 161         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 162         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 163 }
 164
 165 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 166                                 uint16_t pasid, uint32_t flush_type,
 167                                 bool all_hub)
 168 {
 169         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
 170         amdgpu_ring_write(kiq_ring,
 171                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
 172                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
 173                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
 174                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
 175 }
 176
 177 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = {
 178         .kiq_set_resources = gfx_v9_4_3_kiq_set_resources,
 179         .kiq_map_queues = gfx_v9_4_3_kiq_map_queues,
 180         .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues,
 181         .kiq_query_status = gfx_v9_4_3_kiq_query_status,
 182         .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs,
 183         .set_resources_size = 8,
 184         .map_queues_size = 7,
 185         .unmap_queues_size = 6,
 186         .query_status_size = 7,
 187         .invalidate_tlbs_size = 2,
 188 };
 189
 190 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 191 {
 192         int i, num_xcc;
 193
 194         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 195         for (i = 0; i < num_xcc; i++)
 196                 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
 197 }
 198
 199 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
 200 {
 201         int i, num_xcc, dev_inst;
 202
 203         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 204         for (i = 0; i < num_xcc; i++) {
 205                 dev_inst = GET_INST(GC, i);
 206
 207                 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG,
 208                              GOLDEN_GB_ADDR_CONFIG);
 209                 /* Golden settings applied by driver for ASIC with rev_id 0 */
 210                 if (adev->rev_id == 0) {
 211                         WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,
 212                                               REDUCE_FIFO_DEPTH_BY_2, 2);
 213                 } else {
 214                         WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2,
 215                                                 SPARE, 0x1);
 216                 }
 217         }
 218 }
 219
 220 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 221                                        bool wc, uint32_t reg, uint32_t val)
 222 {
 223         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 224         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 225                                 WRITE_DATA_DST_SEL(0) |
 226                                 (wc ? WR_CONFIRM : 0));
 227         amdgpu_ring_write(ring, reg);
 228         amdgpu_ring_write(ring, 0);
 229         amdgpu_ring_write(ring, val);
 230 }
 231
 232 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 233                                   int mem_space, int opt, uint32_t addr0,
 234                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 235                                   uint32_t inv)
 236 {
 237         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 238         amdgpu_ring_write(ring,
 239                                  /* memory (1) or register (0) */
 240                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 241                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 242                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 243                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 244
 245         if (mem_space)
 246                 BUG_ON(addr0 & 0x3); /* Dword align */
 247         amdgpu_ring_write(ring, addr0);
 248         amdgpu_ring_write(ring, addr1);
 249         amdgpu_ring_write(ring, ref);
 250         amdgpu_ring_write(ring, mask);
 251         amdgpu_ring_write(ring, inv); /* poll interval */
 252 }
 253
 254 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring)
 255 {
 256         uint32_t scratch_reg0_offset, xcc_offset;
 257         struct amdgpu_device *adev = ring->adev;
 258         uint32_t tmp = 0;
 259         unsigned i;
 260         int r;
 261
 262         /* Use register offset which is local to XCC in the packet */
 263         xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 264         scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0);
 265         WREG32(scratch_reg0_offset, 0xCAFEDEAD);
 266         tmp = RREG32(scratch_reg0_offset);
 267
 268         r = amdgpu_ring_alloc(ring, 3);
 269         if (r)
 270                 return r;
 271
 272         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 273         amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START);
 274         amdgpu_ring_write(ring, 0xDEADBEEF);
 275         amdgpu_ring_commit(ring);
 276
 277         for (i = 0; i < adev->usec_timeout; i++) {
 278                 tmp = RREG32(scratch_reg0_offset);
 279                 if (tmp == 0xDEADBEEF)
 280                         break;
 281                 udelay(1);
 282         }
 283
 284         if (i >= adev->usec_timeout)
 285                 r = -ETIMEDOUT;
 286         return r;
 287 }
 288
 289 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 290 {
 291         struct amdgpu_device *adev = ring->adev;
 292         struct amdgpu_ib ib;
 293         struct dma_fence *f = NULL;
 294
 295         unsigned index;
 296         uint64_t gpu_addr;
 297         uint32_t tmp;
 298         long r;
 299
 300         r = amdgpu_device_wb_get(adev, &index);
 301         if (r)
 302                 return r;
 303
 304         gpu_addr = adev->wb.gpu_addr + (index * 4);
 305         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 306         memset(&ib, 0, sizeof(ib));
 307
 308         r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
 309         if (r)
 310                 goto err1;
 311
 312         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 313         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 314         ib.ptr[2] = lower_32_bits(gpu_addr);
 315         ib.ptr[3] = upper_32_bits(gpu_addr);
 316         ib.ptr[4] = 0xDEADBEEF;
 317         ib.length_dw = 5;
 318
 319         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 320         if (r)
 321                 goto err2;
 322
 323         r = dma_fence_wait_timeout(f, false, timeout);
 324         if (r == 0) {
 325                 r = -ETIMEDOUT;
 326                 goto err2;
 327         } else if (r < 0) {
 328                 goto err2;
 329         }
 330
 331         tmp = adev->wb.wb[index];
 332         if (tmp == 0xDEADBEEF)
 333                 r = 0;
 334         else
 335                 r = -EINVAL;
 336
 337 err2:
 338         amdgpu_ib_free(adev, &ib, NULL);
 339         dma_fence_put(f);
 340 err1:
 341         amdgpu_device_wb_free(adev, index);
 342         return r;
 343 }
 344
 345
 346 /* This value might differs per partition */
 347 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev)
 348 {
 349         uint64_t clock;
 350
 351         mutex_lock(&adev->gfx.gpu_clock_mutex);
 352         WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
 353         clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) |
 354                 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
 355         mutex_unlock(&adev->gfx.gpu_clock_mutex);
 356
 357         return clock;
 358 }
 359
 360 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev)
 361 {
 362         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 363         amdgpu_ucode_release(&adev->gfx.me_fw);
 364         amdgpu_ucode_release(&adev->gfx.ce_fw);
 365         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 366         amdgpu_ucode_release(&adev->gfx.mec_fw);
 367         amdgpu_ucode_release(&adev->gfx.mec2_fw);
 368
 369         kfree(adev->gfx.rlc.register_list_format);
 370 }
 371
 372 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev,
 373                                           const char *chip_name)
 374 {
 375         char fw_name[30];
 376         int err;
 377         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 378         uint16_t version_major;
 379         uint16_t version_minor;
 380
 381         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 382
 383         err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
 384         if (err)
 385                 goto out;
 386         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 387
 388         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 389         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 390         err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 391 out:
 392         if (err)
 393                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 394
 395         return err;
 396 }
 397
 398 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev)
 399 {
 400         return true;
 401 }
 402
 403 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev)
 404 {
 405         if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev))
 406                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 407 }
 408
 409 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev,
 410                                           const char *chip_name)
 411 {
 412         char fw_name[30];
 413         int err;
 414
 415         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 416
 417         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
 418         if (err)
 419                 goto out;
 420         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 421         amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 422
 423         adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
 424         adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
 425
 426         gfx_v9_4_3_check_if_need_gfxoff(adev);
 427
 428 out:
 429         if (err)
 430                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 431         return err;
 432 }
 433
 434 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev)
 435 {
 436         char ucode_prefix[15];
 437         int r;
 438
 439         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 440
 441         r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix);
 442         if (r)
 443                 return r;
 444
 445         r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix);
 446         if (r)
 447                 return r;
 448
 449         return r;
 450 }
 451
 452 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev)
 453 {
 454         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 455         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 456 }
 457
 458 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev)
 459 {
 460         int r, i, num_xcc;
 461         u32 *hpd;
 462         const __le32 *fw_data;
 463         unsigned fw_size;
 464         u32 *fw;
 465         size_t mec_hpd_size;
 466
 467         const struct gfx_firmware_header_v1_0 *mec_hdr;
 468
 469         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 470         for (i = 0; i < num_xcc; i++)
 471                 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap,
 472                         AMDGPU_MAX_COMPUTE_QUEUES);
 473
 474         /* take ownership of the relevant compute queues */
 475         amdgpu_gfx_compute_queue_acquire(adev);
 476         mec_hpd_size =
 477                 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE;
 478         if (mec_hpd_size) {
 479                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 480                                               AMDGPU_GEM_DOMAIN_VRAM |
 481                                               AMDGPU_GEM_DOMAIN_GTT,
 482                                               &adev->gfx.mec.hpd_eop_obj,
 483                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 484                                               (void **)&hpd);
 485                 if (r) {
 486                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 487                         gfx_v9_4_3_mec_fini(adev);
 488                         return r;
 489                 }
 490
 491                 if (amdgpu_emu_mode == 1) {
 492                         for (i = 0; i < mec_hpd_size / 4; i++) {
 493                                 memset((void *)(hpd + i), 0, 4);
 494                                 if (i % 50 == 0)
 495                                         msleep(1);
 496                         }
 497                 } else {
 498                         memset(hpd, 0, mec_hpd_size);
 499                 }
 500
 501                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 502                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 503         }
 504
 505         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 506
 507         fw_data = (const __le32 *)
 508                 (adev->gfx.mec_fw->data +
 509                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
 510         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
 511
 512         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
 513                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
 514                                       &adev->gfx.mec.mec_fw_obj,
 515                                       &adev->gfx.mec.mec_fw_gpu_addr,
 516                                       (void **)&fw);
 517         if (r) {
 518                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
 519                 gfx_v9_4_3_mec_fini(adev);
 520                 return r;
 521         }
 522
 523         memcpy(fw, fw_data, fw_size);
 524
 525         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
 526         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
 527
 528         return 0;
 529 }
 530
 531 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 532                                         u32 sh_num, u32 instance, int xcc_id)
 533 {
 534         u32 data;
 535
 536         if (instance == 0xffffffff)
 537                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 538                                      INSTANCE_BROADCAST_WRITES, 1);
 539         else
 540                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
 541                                      INSTANCE_INDEX, instance);
 542
 543         if (se_num == 0xffffffff)
 544                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 545                                      SE_BROADCAST_WRITES, 1);
 546         else
 547                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
 548
 549         if (sh_num == 0xffffffff)
 550                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 551                                      SH_BROADCAST_WRITES, 1);
 552         else
 553                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
 554
 555         WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data);
 556 }
 557
 558 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address)
 559 {
 560         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
 561                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 562                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 563                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
 564                 (SQ_IND_INDEX__FORCE_READ_MASK));
 565         return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
 566 }
 567
 568 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 569                            uint32_t wave, uint32_t thread,
 570                            uint32_t regno, uint32_t num, uint32_t *out)
 571 {
 572         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX,
 573                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 574                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
 575                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 576                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
 577                 (SQ_IND_INDEX__FORCE_READ_MASK) |
 578                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 579         while (num--)
 580                 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA);
 581 }
 582
 583 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev,
 584                                       uint32_t xcc_id, uint32_t simd, uint32_t wave,
 585                                       uint32_t *dst, int *no_fields)
 586 {
 587         /* type 1 wave data */
 588         dst[(*no_fields)++] = 1;
 589         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS);
 590         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO);
 591         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI);
 592         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO);
 593         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI);
 594         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID);
 595         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0);
 596         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1);
 597         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC);
 598         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC);
 599         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS);
 600         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS);
 601         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0);
 602         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0);
 603         dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE);
 604 }
 605
 606 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 607                                        uint32_t wave, uint32_t start,
 608                                        uint32_t size, uint32_t *dst)
 609 {
 610         wave_read_regs(adev, xcc_id, simd, wave, 0,
 611                        start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
 612 }
 613
 614 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 615                                        uint32_t wave, uint32_t thread,
 616                                        uint32_t start, uint32_t size,
 617                                        uint32_t *dst)
 618 {
 619         wave_read_regs(adev, xcc_id, simd, wave, thread,
 620                        start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 621 }
 622
 623 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev,
 624                                         u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
 625 {
 626         soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
 627 }
 628
 629
 630 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
 631                                                 int num_xccs_per_xcp)
 632 {
 633         int ret, i, num_xcc;
 634         u32 tmp = 0;
 635
 636         if (adev->psp.funcs) {
 637                 ret = psp_spatial_partition(&adev->psp,
 638                                             NUM_XCC(adev->gfx.xcc_mask) /
 639                                                     num_xccs_per_xcp);
 640                 if (ret)
 641                         return ret;
 642         } else {
 643                 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 644
 645                 for (i = 0; i < num_xcc; i++) {
 646                         tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
 647                                             num_xccs_per_xcp);
 648                         tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
 649                                             i % num_xccs_per_xcp);
 650                         WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,
 651                                      tmp);
 652                 }
 653                 ret = 0;
 654         }
 655
 656         adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
 657
 658         return ret;
 659 }
 660
 661 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
 662 {
 663         int xcc;
 664
 665         xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
 666         if (!xcc) {
 667                 dev_err(adev->dev, "Couldn't find xcc mapping from IH node");
 668                 return -EINVAL;
 669         }
 670
 671         return xcc - 1;
 672 }
 673
 674 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
 675         .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter,
 676         .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh,
 677         .read_wave_data = &gfx_v9_4_3_read_wave_data,
 678         .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs,
 679         .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs,
 680         .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q,
 681         .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition,
 682         .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
 683 };
 684
 685 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle,
 686                                       struct aca_bank *bank, enum aca_smu_type type,
 687                                       void *data)
 688 {
 689         struct aca_bank_info info;
 690         u64 misc0;
 691         u32 instlo;
 692         int ret;
 693
 694         ret = aca_bank_info_decode(bank, &info);
 695         if (ret)
 696                 return ret;
 697
 698         /* NOTE: overwrite info.die_id with xcd id for gfx */
 699         instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
 700         instlo &= GENMASK(31, 1);
 701         info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1;
 702
 703         misc0 = bank->regs[ACA_REG_IDX_MISC0];
 704
 705         switch (type) {
 706         case ACA_SMU_TYPE_UE:
 707                 ret = aca_error_cache_log_bank_error(handle, &info,
 708                                                      ACA_ERROR_TYPE_UE, 1ULL);
 709                 break;
 710         case ACA_SMU_TYPE_CE:
 711                 ret = aca_error_cache_log_bank_error(handle, &info,
 712                                                      ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0));
 713                 break;
 714         default:
 715                 return -EINVAL;
 716         }
 717
 718         return ret;
 719 }
 720
 721 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
 722                                          enum aca_smu_type type, void *data)
 723 {
 724         u32 instlo;
 725
 726         instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
 727         instlo &= GENMASK(31, 1);
 728         switch (instlo) {
 729         case mmSMNAID_XCD0_MCA_SMU:
 730         case mmSMNAID_XCD1_MCA_SMU:
 731         case mmSMNXCD_XCD0_MCA_SMU:
 732                 return true;
 733         default:
 734                 break;
 735         }
 736
 737         return false;
 738 }
 739
 740 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = {
 741         .aca_bank_parser = gfx_v9_4_3_aca_bank_parser,
 742         .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid,
 743 };
 744
 745 static const struct aca_info gfx_v9_4_3_aca_info = {
 746         .hwip = ACA_HWIP_TYPE_SMU,
 747         .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,
 748         .bank_ops = &gfx_v9_4_3_aca_bank_ops,
 749 };
 750
 751 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
 752 {
 753         u32 gb_addr_config;
 754
 755         adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
 756         adev->gfx.ras = &gfx_v9_4_3_ras;
 757
 758         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 759         case IP_VERSION(9, 4, 3):
 760         case IP_VERSION(9, 4, 4):
 761                 adev->gfx.config.max_hw_contexts = 8;
 762                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 763                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 764                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 765                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 766                 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG);
 767                 break;
 768         default:
 769                 BUG();
 770                 break;
 771         }
 772
 773         adev->gfx.config.gb_addr_config = gb_addr_config;
 774
 775         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
 776                         REG_GET_FIELD(
 777                                         adev->gfx.config.gb_addr_config,
 778                                         GB_ADDR_CONFIG,
 779                                         NUM_PIPES);
 780
 781         adev->gfx.config.max_tile_pipes =
 782                 adev->gfx.config.gb_addr_config_fields.num_pipes;
 783
 784         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
 785                         REG_GET_FIELD(
 786                                         adev->gfx.config.gb_addr_config,
 787                                         GB_ADDR_CONFIG,
 788                                         NUM_BANKS);
 789         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
 790                         REG_GET_FIELD(
 791                                         adev->gfx.config.gb_addr_config,
 792                                         GB_ADDR_CONFIG,
 793                                         MAX_COMPRESSED_FRAGS);
 794         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
 795                         REG_GET_FIELD(
 796                                         adev->gfx.config.gb_addr_config,
 797                                         GB_ADDR_CONFIG,
 798                                         NUM_RB_PER_SE);
 799         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
 800                         REG_GET_FIELD(
 801                                         adev->gfx.config.gb_addr_config,
 802                                         GB_ADDR_CONFIG,
 803                                         NUM_SHADER_ENGINES);
 804         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
 805                         REG_GET_FIELD(
 806                                         adev->gfx.config.gb_addr_config,
 807                                         GB_ADDR_CONFIG,
 808                                         PIPE_INTERLEAVE_SIZE));
 809
 810         return 0;
 811 }
 812
 813 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 814                                         int xcc_id, int mec, int pipe, int queue)
 815 {
 816         unsigned irq_type;
 817         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
 818         unsigned int hw_prio;
 819         uint32_t xcc_doorbell_start;
 820
 821         ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings +
 822                                        ring_id];
 823
 824         /* mec0 is me1 */
 825         ring->xcc_id = xcc_id;
 826         ring->me = mec + 1;
 827         ring->pipe = pipe;
 828         ring->queue = queue;
 829
 830         ring->ring_obj = NULL;
 831         ring->use_doorbell = true;
 832         xcc_doorbell_start = adev->doorbell_index.mec_ring0 +
 833                              xcc_id * adev->doorbell_index.xcc_doorbell_range;
 834         ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1;
 835         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
 836                              (ring_id + xcc_id * adev->gfx.num_compute_rings) *
 837                                      GFX9_MEC_HPD_SIZE;
 838         ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
 839         sprintf(ring->name, "comp_%d.%d.%d.%d",
 840                         ring->xcc_id, ring->me, ring->pipe, ring->queue);
 841
 842         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 843                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 844                 + ring->pipe;
 845         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 846                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 847         /* type-2 packets are deprecated on MEC, use type-3 instead */
 848         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 849                                 hw_prio, NULL);
 850 }
 851
 852 static int gfx_v9_4_3_sw_init(void *handle)
 853 {
 854         int i, j, k, r, ring_id, xcc_id, num_xcc;
 855         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 856
 857         adev->gfx.mec.num_mec = 2;
 858         adev->gfx.mec.num_pipe_per_mec = 4;
 859         adev->gfx.mec.num_queue_per_pipe = 8;
 860
 861         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 862
 863         /* EOP Event */
 864         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
 865         if (r)
 866                 return r;
 867
 868         /* Privileged reg */
 869         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
 870                               &adev->gfx.priv_reg_irq);
 871         if (r)
 872                 return r;
 873
 874         /* Privileged inst */
 875         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
 876                               &adev->gfx.priv_inst_irq);
 877         if (r)
 878                 return r;
 879
 880         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 881
 882         r = adev->gfx.rlc.funcs->init(adev);
 883         if (r) {
 884                 DRM_ERROR("Failed to init rlc BOs!\n");
 885                 return r;
 886         }
 887
 888         r = gfx_v9_4_3_mec_init(adev);
 889         if (r) {
 890                 DRM_ERROR("Failed to init MEC BOs!\n");
 891                 return r;
 892         }
 893
 894         /* set up the compute queues - allocate horizontally across pipes */
 895         for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
 896                 ring_id = 0;
 897                 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
 898                         for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
 899                                 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
 900                                      k++) {
 901                                         if (!amdgpu_gfx_is_mec_queue_enabled(
 902                                                         adev, xcc_id, i, k, j))
 903                                                 continue;
 904
 905                                         r = gfx_v9_4_3_compute_ring_init(adev,
 906                                                                        ring_id,
 907                                                                        xcc_id,
 908                                                                        i, k, j);
 909                                         if (r)
 910                                                 return r;
 911
 912                                         ring_id++;
 913                                 }
 914                         }
 915                 }
 916
 917                 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id);
 918                 if (r) {
 919                         DRM_ERROR("Failed to init KIQ BOs!\n");
 920                         return r;
 921                 }
 922
 923                 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id);
 924                 if (r)
 925                         return r;
 926
 927                 /* create MQD for all compute queues as wel as KIQ for SRIOV case */
 928                 r = amdgpu_gfx_mqd_sw_init(adev,
 929                                 sizeof(struct v9_mqd_allocation), xcc_id);
 930                 if (r)
 931                         return r;
 932         }
 933
 934         r = gfx_v9_4_3_gpu_early_init(adev);
 935         if (r)
 936                 return r;
 937
 938         r = amdgpu_gfx_ras_sw_init(adev);
 939         if (r)
 940                 return r;
 941
 942
 943         if (!amdgpu_sriov_vf(adev))
 944                 r = amdgpu_gfx_sysfs_init(adev);
 945
 946         return r;
 947 }
 948
 949 static int gfx_v9_4_3_sw_fini(void *handle)
 950 {
 951         int i, num_xcc;
 952         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 953
 954         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 955         for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++)
 956                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 957
 958         for (i = 0; i < num_xcc; i++) {
 959                 amdgpu_gfx_mqd_sw_fini(adev, i);
 960                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring);
 961                 amdgpu_gfx_kiq_fini(adev, i);
 962         }
 963
 964         gfx_v9_4_3_mec_fini(adev);
 965         amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
 966         gfx_v9_4_3_free_microcode(adev);
 967         if (!amdgpu_sriov_vf(adev))
 968                 amdgpu_gfx_sysfs_fini(adev);
 969
 970         return 0;
 971 }
 972
 973 #define DEFAULT_SH_MEM_BASES    (0x6000)
 974 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev,
 975                                              int xcc_id)
 976 {
 977         int i;
 978         uint32_t sh_mem_config;
 979         uint32_t sh_mem_bases;
 980         uint32_t data;
 981
 982         /*
 983          * Configure apertures:
 984          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
 985          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
 986          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
 987          */
 988         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
 989
 990         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
 991                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
 992                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
 993
 994         mutex_lock(&adev->srbm_mutex);
 995         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
 996                 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
 997                 /* CP and shaders */
 998                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config);
 999                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases);
1000
1001                 /* Enable trap for each kfd vmid. */
1002                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL);
1003                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1004                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data);
1005         }
1006         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1007         mutex_unlock(&adev->srbm_mutex);
1008
1009         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1010            acccess. These should be enabled by FW for target VMIDs. */
1011         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1012                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0);
1013                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0);
1014                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0);
1015                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0);
1016         }
1017 }
1018
1019 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id)
1020 {
1021         int vmid;
1022
1023         /*
1024          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1025          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1026          * the driver can enable them for graphics. VMID0 should maintain
1027          * access so that HWS firmware can save/restore entries.
1028          */
1029         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
1030                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0);
1031                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0);
1032                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0);
1033                 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0);
1034         }
1035 }
1036
1037 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev,
1038                                           int xcc_id)
1039 {
1040         u32 tmp;
1041         int i;
1042
1043         /* XXX SH_MEM regs */
1044         /* where to put LDS, scratch, GPUVM in FSA64 space */
1045         mutex_lock(&adev->srbm_mutex);
1046         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1047                 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id));
1048                 /* CP and shaders */
1049                 if (i == 0) {
1050                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1051                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1052                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
1053                                             !!adev->gmc.noretry);
1054                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1055                                          regSH_MEM_CONFIG, tmp);
1056                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1057                                          regSH_MEM_BASES, 0);
1058                 } else {
1059                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1060                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1061                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE,
1062                                             !!adev->gmc.noretry);
1063                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1064                                          regSH_MEM_CONFIG, tmp);
1065                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1066                                             (adev->gmc.private_aperture_start >>
1067                                              48));
1068                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1069                                             (adev->gmc.shared_aperture_start >>
1070                                              48));
1071                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id),
1072                                          regSH_MEM_BASES, tmp);
1073                 }
1074         }
1075         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0));
1076
1077         mutex_unlock(&adev->srbm_mutex);
1078
1079         gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id);
1080         gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id);
1081 }
1082
1083 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev)
1084 {
1085         int i, num_xcc;
1086
1087         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1088
1089         gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
1090         adev->gfx.config.db_debug2 =
1091                 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2);
1092
1093         for (i = 0; i < num_xcc; i++)
1094                 gfx_v9_4_3_xcc_constants_init(adev, i);
1095 }
1096
1097 static void
1098 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev,
1099                                            int xcc_id)
1100 {
1101         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1);
1102 }
1103
1104 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id)
1105 {
1106         /*
1107          * Rlc save restore list is workable since v2_1.
1108          * And it's needed by gfxoff feature.
1109          */
1110         if (adev->gfx.rlc.is_rlc_v2_1)
1111                 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id);
1112 }
1113
1114 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id)
1115 {
1116         uint32_t data;
1117
1118         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG);
1119         data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK;
1120         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data);
1121 }
1122
1123 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev)
1124 {
1125         uint32_t rlc_setting;
1126
1127         /* if RLC is not enabled, do nothing */
1128         rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL);
1129         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
1130                 return false;
1131
1132         return true;
1133 }
1134
1135 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
1136 {
1137         uint32_t data;
1138         unsigned i;
1139
1140         data = RLC_SAFE_MODE__CMD_MASK;
1141         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
1142         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1143
1144         /* wait for RLC_SAFE_MODE */
1145         for (i = 0; i < adev->usec_timeout; i++) {
1146                 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
1147                         break;
1148                 udelay(1);
1149         }
1150 }
1151
1152 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev,
1153                                            int xcc_id)
1154 {
1155         uint32_t data;
1156
1157         data = RLC_SAFE_MODE__CMD_MASK;
1158         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data);
1159 }
1160
1161 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
1162 {
1163         int xcc_id, num_xcc;
1164         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
1165
1166         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1167         for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
1168                 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];
1169                 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0);
1170                 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1);
1171                 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2);
1172                 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3);
1173                 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);
1174                 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX);
1175                 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT);
1176         }
1177         adev->gfx.rlc.rlcg_reg_access_supported = true;
1178 }
1179
1180 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev)
1181 {
1182         /* init spm vmid with 0xf */
1183         if (adev->gfx.rlc.funcs->update_spm_vmid)
1184                 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf);
1185
1186         return 0;
1187 }
1188
1189 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev,
1190                                                int xcc_id)
1191 {
1192         u32 i, j, k;
1193         u32 mask;
1194
1195         mutex_lock(&adev->grbm_idx_mutex);
1196         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1197                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1198                         gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff,
1199                                                     xcc_id);
1200                         for (k = 0; k < adev->usec_timeout; k++) {
1201                                 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0)
1202                                         break;
1203                                 udelay(1);
1204                         }
1205                         if (k == adev->usec_timeout) {
1206                                 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff,
1207                                                             0xffffffff,
1208                                                             0xffffffff, xcc_id);
1209                                 mutex_unlock(&adev->grbm_idx_mutex);
1210                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1211                                          i, j);
1212                                 return;
1213                         }
1214                 }
1215         }
1216         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
1217                                     xcc_id);
1218         mutex_unlock(&adev->grbm_idx_mutex);
1219
1220         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1221                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1222                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1223                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1224         for (k = 0; k < adev->usec_timeout; k++) {
1225                 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1226                         break;
1227                 udelay(1);
1228         }
1229 }
1230
1231 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1232                                                      bool enable, int xcc_id)
1233 {
1234         u32 tmp;
1235
1236         /* These interrupts should be enabled to drive DS clock */
1237
1238         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0);
1239
1240         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1241         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1242         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1243
1244         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp);
1245 }
1246
1247 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id)
1248 {
1249         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1250                               RLC_ENABLE_F32, 0);
1251         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1252         gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id);
1253 }
1254
1255 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev)
1256 {
1257         int i, num_xcc;
1258
1259         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1260         for (i = 0; i < num_xcc; i++)
1261                 gfx_v9_4_3_xcc_rlc_stop(adev, i);
1262 }
1263
1264 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id)
1265 {
1266         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1267                               SOFT_RESET_RLC, 1);
1268         udelay(50);
1269         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET,
1270                               SOFT_RESET_RLC, 0);
1271         udelay(50);
1272 }
1273
1274 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev)
1275 {
1276         int i, num_xcc;
1277
1278         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1279         for (i = 0; i < num_xcc; i++)
1280                 gfx_v9_4_3_xcc_rlc_reset(adev, i);
1281 }
1282
1283 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id)
1284 {
1285         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL,
1286                               RLC_ENABLE_F32, 1);
1287         udelay(50);
1288
1289         /* carrizo do enable cp interrupt after cp inited */
1290         if (!(adev->flags & AMD_IS_APU)) {
1291                 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
1292                 udelay(50);
1293         }
1294 }
1295
1296 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev)
1297 {
1298 #ifdef AMDGPU_RLC_DEBUG_RETRY
1299         u32 rlc_ucode_ver;
1300 #endif
1301         int i, num_xcc;
1302
1303         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1304         for (i = 0; i < num_xcc; i++) {
1305                 gfx_v9_4_3_xcc_rlc_start(adev, i);
1306 #ifdef AMDGPU_RLC_DEBUG_RETRY
1307                 /* RLC_GPM_GENERAL_6 : RLC Ucode version */
1308                 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6);
1309                 if (rlc_ucode_ver == 0x108) {
1310                         dev_info(adev->dev,
1311                                  "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
1312                                  rlc_ucode_ver, adev->gfx.rlc_fw_version);
1313                         /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
1314                          * default is 0x9C4 to create a 100us interval */
1315                         WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4);
1316                         /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
1317                          * to disable the page fault retry interrupts, default is
1318                          * 0x100 (256) */
1319                         WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100);
1320                 }
1321 #endif
1322         }
1323 }
1324
1325 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev,
1326                                              int xcc_id)
1327 {
1328         const struct rlc_firmware_header_v2_0 *hdr;
1329         const __le32 *fw_data;
1330         unsigned i, fw_size;
1331
1332         if (!adev->gfx.rlc_fw)
1333                 return -EINVAL;
1334
1335         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1336         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1337
1338         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1339                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1340         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1341
1342         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR,
1343                         RLCG_UCODE_LOADING_START_ADDRESS);
1344         for (i = 0; i < fw_size; i++) {
1345                 if (amdgpu_emu_mode == 1 && i % 100 == 0) {
1346                         dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i);
1347                         msleep(1);
1348                 }
1349                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
1350         }
1351         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1352
1353         return 0;
1354 }
1355
1356 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id)
1357 {
1358         int r;
1359
1360         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1361                 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id);
1362                 /* legacy rlc firmware loading */
1363                 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id);
1364                 if (r)
1365                         return r;
1366                 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id);
1367         }
1368
1369         amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
1370         /* disable CG */
1371         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0);
1372         gfx_v9_4_3_xcc_init_pg(adev, xcc_id);
1373         amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
1374
1375         return 0;
1376 }
1377
1378 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev)
1379 {
1380         int r, i, num_xcc;
1381
1382         if (amdgpu_sriov_vf(adev))
1383                 return 0;
1384
1385         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1386         for (i = 0; i < num_xcc; i++) {
1387                 r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
1388                 if (r)
1389                         return r;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1396                                        unsigned vmid)
1397 {
1398         u32 reg, pre_data, data;
1399
1400         reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL);
1401         if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev))
1402                 pre_data = RREG32_NO_KIQ(reg);
1403         else
1404                 pre_data = RREG32(reg);
1405
1406         data =  pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK);
1407         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
1408
1409         if (pre_data != data) {
1410                 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) {
1411                         WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1412                 } else
1413                         WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data);
1414         }
1415 }
1416
1417 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = {
1418         {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)},
1419         {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)},
1420 };
1421
1422 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev,
1423                                         uint32_t offset,
1424                                         struct soc15_reg_rlcg *entries, int arr_size)
1425 {
1426         int i, inst;
1427         uint32_t reg;
1428
1429         if (!entries)
1430                 return false;
1431
1432         for (i = 0; i < arr_size; i++) {
1433                 const struct soc15_reg_rlcg *entry;
1434
1435                 entry = &entries[i];
1436                 inst = adev->ip_map.logical_to_dev_inst ?
1437                                adev->ip_map.logical_to_dev_inst(
1438                                        adev, entry->hwip, entry->instance) :
1439                                entry->instance;
1440                 reg = adev->reg_offset[entry->hwip][inst][entry->segment] +
1441                       entry->reg;
1442                 if (offset == reg)
1443                         return true;
1444         }
1445
1446         return false;
1447 }
1448
1449 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
1450 {
1451         return gfx_v9_4_3_check_rlcg_range(adev, offset,
1452                                         (void *)rlcg_access_gc_9_4_3,
1453                                         ARRAY_SIZE(rlcg_access_gc_9_4_3));
1454 }
1455
1456 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev,
1457                                              bool enable, int xcc_id)
1458 {
1459         if (enable) {
1460                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0);
1461         } else {
1462                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL,
1463                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
1464                 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
1465         }
1466         udelay(50);
1467 }
1468
1469 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev,
1470                                                     int xcc_id)
1471 {
1472         const struct gfx_firmware_header_v1_0 *mec_hdr;
1473         const __le32 *fw_data;
1474         unsigned i;
1475         u32 tmp;
1476         u32 mec_ucode_addr_offset;
1477         u32 mec_ucode_data_offset;
1478
1479         if (!adev->gfx.mec_fw)
1480                 return -EINVAL;
1481
1482         gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id);
1483
1484         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1485         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
1486
1487         fw_data = (const __le32 *)
1488                 (adev->gfx.mec_fw->data +
1489                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1490         tmp = 0;
1491         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
1492         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
1493         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp);
1494
1495         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO,
1496                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1497         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI,
1498                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1499
1500         mec_ucode_addr_offset =
1501                 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR);
1502         mec_ucode_data_offset =
1503                 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA);
1504
1505         /* MEC1 */
1506         WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset);
1507         for (i = 0; i < mec_hdr->jt_size; i++)
1508                 WREG32(mec_ucode_data_offset,
1509                        le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
1510
1511         WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
1512         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
1513
1514         return 0;
1515 }
1516
1517 /* KIQ functions */
1518 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id)
1519 {
1520         uint32_t tmp;
1521         struct amdgpu_device *adev = ring->adev;
1522
1523         /* tell RLC which is KIQ queue */
1524         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
1525         tmp &= 0xffffff00;
1526         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1527         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1528         tmp |= 0x80;
1529         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
1530 }
1531
1532 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
1533 {
1534         struct amdgpu_device *adev = ring->adev;
1535
1536         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
1537                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
1538                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
1539                         mqd->cp_hqd_queue_priority =
1540                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
1541                 }
1542         }
1543 }
1544
1545 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)
1546 {
1547         struct amdgpu_device *adev = ring->adev;
1548         struct v9_mqd *mqd = ring->mqd_ptr;
1549         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
1550         uint32_t tmp;
1551
1552         mqd->header = 0xC0310800;
1553         mqd->compute_pipelinestat_enable = 0x00000001;
1554         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
1555         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
1556         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
1557         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
1558         mqd->compute_misc_reserved = 0x00000003;
1559
1560         mqd->dynamic_cu_mask_addr_lo =
1561                 lower_32_bits(ring->mqd_gpu_addr
1562                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1563         mqd->dynamic_cu_mask_addr_hi =
1564                 upper_32_bits(ring->mqd_gpu_addr
1565                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
1566
1567         eop_base_addr = ring->eop_gpu_addr >> 8;
1568         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
1569         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
1570
1571         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1572         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL);
1573         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
1574                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
1575
1576         mqd->cp_hqd_eop_control = tmp;
1577
1578         /* enable doorbell? */
1579         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL);
1580
1581         if (ring->use_doorbell) {
1582                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1583                                     DOORBELL_OFFSET, ring->doorbell_index);
1584                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1585                                     DOORBELL_EN, 1);
1586                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1587                                     DOORBELL_SOURCE, 0);
1588                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1589                                     DOORBELL_HIT, 0);
1590         } else {
1591                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
1592                                          DOORBELL_EN, 0);
1593         }
1594
1595         mqd->cp_hqd_pq_doorbell_control = tmp;
1596
1597         /* disable the queue if it's active */
1598         ring->wptr = 0;
1599         mqd->cp_hqd_dequeue_request = 0;
1600         mqd->cp_hqd_pq_rptr = 0;
1601         mqd->cp_hqd_pq_wptr_lo = 0;
1602         mqd->cp_hqd_pq_wptr_hi = 0;
1603
1604         /* set the pointer to the MQD */
1605         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
1606         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
1607
1608         /* set MQD vmid to 0 */
1609         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL);
1610         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
1611         mqd->cp_mqd_control = tmp;
1612
1613         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1614         hqd_gpu_addr = ring->gpu_addr >> 8;
1615         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
1616         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
1617
1618         /* set up the HQD, this is similar to CP_RB0_CNTL */
1619         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL);
1620         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
1621                             (order_base_2(ring->ring_size / 4) - 1));
1622         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
1623                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
1624 #ifdef __BIG_ENDIAN
1625         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
1626 #endif
1627         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
1628         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
1629         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
1630         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
1631         mqd->cp_hqd_pq_control = tmp;
1632
1633         /* set the wb address whether it's enabled or not */
1634         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
1635         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
1636         mqd->cp_hqd_pq_rptr_report_addr_hi =
1637                 upper_32_bits(wb_gpu_addr) & 0xffff;
1638
1639         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1640         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1641         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
1642         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
1643
1644         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1645         ring->wptr = 0;
1646         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR);
1647
1648         /* set the vmid for the queue */
1649         mqd->cp_hqd_vmid = 0;
1650
1651         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE);
1652         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
1653         mqd->cp_hqd_persistent_state = tmp;
1654
1655         /* set MIN_IB_AVAIL_SIZE */
1656         tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL);
1657         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
1658         mqd->cp_hqd_ib_control = tmp;
1659
1660         /* set static priority for a queue/ring */
1661         gfx_v9_4_3_mqd_set_priority(ring, mqd);
1662         mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
1663
1664         /* map_queues packet doesn't need activate the queue,
1665          * so only kiq need set this field.
1666          */
1667         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
1668                 mqd->cp_hqd_active = 1;
1669
1670         return 0;
1671 }
1672
1673 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring,
1674                                             int xcc_id)
1675 {
1676         struct amdgpu_device *adev = ring->adev;
1677         struct v9_mqd *mqd = ring->mqd_ptr;
1678         int j;
1679
1680         /* disable wptr polling */
1681         WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
1682
1683         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR,
1684                mqd->cp_hqd_eop_base_addr_lo);
1685         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI,
1686                mqd->cp_hqd_eop_base_addr_hi);
1687
1688         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
1689         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL,
1690                mqd->cp_hqd_eop_control);
1691
1692         /* enable doorbell? */
1693         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1694                mqd->cp_hqd_pq_doorbell_control);
1695
1696         /* disable the queue if it's active */
1697         if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1698                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1699                 for (j = 0; j < adev->usec_timeout; j++) {
1700                         if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1701                                 break;
1702                         udelay(1);
1703                 }
1704                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1705                        mqd->cp_hqd_dequeue_request);
1706                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR,
1707                        mqd->cp_hqd_pq_rptr);
1708                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1709                        mqd->cp_hqd_pq_wptr_lo);
1710                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1711                        mqd->cp_hqd_pq_wptr_hi);
1712         }
1713
1714         /* set the pointer to the MQD */
1715         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR,
1716                mqd->cp_mqd_base_addr_lo);
1717         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI,
1718                mqd->cp_mqd_base_addr_hi);
1719
1720         /* set MQD vmid to 0 */
1721         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL,
1722                mqd->cp_mqd_control);
1723
1724         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
1725         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE,
1726                mqd->cp_hqd_pq_base_lo);
1727         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI,
1728                mqd->cp_hqd_pq_base_hi);
1729
1730         /* set up the HQD, this is similar to CP_RB0_CNTL */
1731         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL,
1732                mqd->cp_hqd_pq_control);
1733
1734         /* set the wb address whether it's enabled or not */
1735         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR,
1736                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
1737         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
1738                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
1739
1740         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
1741         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR,
1742                mqd->cp_hqd_pq_wptr_poll_addr_lo);
1743         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
1744                mqd->cp_hqd_pq_wptr_poll_addr_hi);
1745
1746         /* enable the doorbell if requested */
1747         if (ring->use_doorbell) {
1748                 WREG32_SOC15(
1749                         GC, GET_INST(GC, xcc_id),
1750                         regCP_MEC_DOORBELL_RANGE_LOWER,
1751                         ((adev->doorbell_index.kiq +
1752                           xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1753                          2) << 2);
1754                 WREG32_SOC15(
1755                         GC, GET_INST(GC, xcc_id),
1756                         regCP_MEC_DOORBELL_RANGE_UPPER,
1757                         ((adev->doorbell_index.userqueue_end +
1758                           xcc_id * adev->doorbell_index.xcc_doorbell_range) *
1759                          2) << 2);
1760         }
1761
1762         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL,
1763                mqd->cp_hqd_pq_doorbell_control);
1764
1765         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
1766         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO,
1767                mqd->cp_hqd_pq_wptr_lo);
1768         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI,
1769                mqd->cp_hqd_pq_wptr_hi);
1770
1771         /* set the vmid for the queue */
1772         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid);
1773
1774         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE,
1775                mqd->cp_hqd_persistent_state);
1776
1777         /* activate the queue */
1778         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE,
1779                mqd->cp_hqd_active);
1780
1781         if (ring->use_doorbell)
1782                 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1);
1783
1784         return 0;
1785 }
1786
1787 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring,
1788                                             int xcc_id)
1789 {
1790         struct amdgpu_device *adev = ring->adev;
1791         int j;
1792
1793         /* disable the queue if it's active */
1794         if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) {
1795
1796                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1);
1797
1798                 for (j = 0; j < adev->usec_timeout; j++) {
1799                         if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1))
1800                                 break;
1801                         udelay(1);
1802                 }
1803
1804                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
1805                         DRM_DEBUG("%s dequeue request failed.\n", ring->name);
1806
1807                         /* Manual disable if dequeue request times out */
1808                         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0);
1809                 }
1810
1811                 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST,
1812                       0);
1813         }
1814
1815         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0);
1816         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0);
1817         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT);
1818         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
1819         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1820         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0);
1821         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0);
1822         WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0);
1823
1824         return 0;
1825 }
1826
1827 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1828 {
1829         struct amdgpu_device *adev = ring->adev;
1830         struct v9_mqd *mqd = ring->mqd_ptr;
1831         struct v9_mqd *tmp_mqd;
1832
1833         gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id);
1834
1835         /* GPU could be in bad state during probe, driver trigger the reset
1836          * after load the SMU, in this case , the mqd is not be initialized.
1837          * driver need to re-init the mqd.
1838          * check mqd->cp_hqd_pq_control since this value should not be 0
1839          */
1840         tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup;
1841         if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) {
1842                 /* for GPU_RESET case , reset MQD to a clean status */
1843                 if (adev->gfx.kiq[xcc_id].mqd_backup)
1844                         memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation));
1845
1846                 /* reset ring buffer */
1847                 ring->wptr = 0;
1848                 amdgpu_ring_clear_ring(ring);
1849                 mutex_lock(&adev->srbm_mutex);
1850                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1851                 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1852                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1853                 mutex_unlock(&adev->srbm_mutex);
1854         } else {
1855                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1856                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1857                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1858                 mutex_lock(&adev->srbm_mutex);
1859                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
1860                         amdgpu_ring_clear_ring(ring);
1861                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1862                 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1863                 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id);
1864                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1865                 mutex_unlock(&adev->srbm_mutex);
1866
1867                 if (adev->gfx.kiq[xcc_id].mqd_backup)
1868                         memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
1869         }
1870
1871         return 0;
1872 }
1873
1874 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id)
1875 {
1876         struct amdgpu_device *adev = ring->adev;
1877         struct v9_mqd *mqd = ring->mqd_ptr;
1878         int mqd_idx = ring - &adev->gfx.compute_ring[0];
1879         struct v9_mqd *tmp_mqd;
1880
1881         /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control
1882          * is not be initialized before
1883          */
1884         tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
1885
1886         if (!tmp_mqd->cp_hqd_pq_control ||
1887             (!amdgpu_in_reset(adev) && !adev->in_suspend)) {
1888                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
1889                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
1890                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
1891                 mutex_lock(&adev->srbm_mutex);
1892                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id));
1893                 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id);
1894                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1895                 mutex_unlock(&adev->srbm_mutex);
1896
1897                 if (adev->gfx.mec.mqd_backup[mqd_idx])
1898                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
1899         } else {
1900                 /* restore MQD to a clean status */
1901                 if (adev->gfx.mec.mqd_backup[mqd_idx])
1902                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
1903                 /* reset ring buffer */
1904                 ring->wptr = 0;
1905                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
1906                 amdgpu_ring_clear_ring(ring);
1907         }
1908
1909         return 0;
1910 }
1911
1912 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id)
1913 {
1914         struct amdgpu_ring *ring;
1915         int j;
1916
1917         for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1918                 ring = &adev->gfx.compute_ring[j +  xcc_id * adev->gfx.num_compute_rings];
1919                 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
1920                         mutex_lock(&adev->srbm_mutex);
1921                         soc15_grbm_select(adev, ring->me,
1922                                         ring->pipe,
1923                                         ring->queue, 0, GET_INST(GC, xcc_id));
1924                         gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id);
1925                         soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
1926                         mutex_unlock(&adev->srbm_mutex);
1927                 }
1928         }
1929
1930         return 0;
1931 }
1932
1933 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)
1934 {
1935         struct amdgpu_ring *ring;
1936         int r;
1937
1938         ring = &adev->gfx.kiq[xcc_id].ring;
1939
1940         r = amdgpu_bo_reserve(ring->mqd_obj, false);
1941         if (unlikely(r != 0))
1942                 return r;
1943
1944         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1945         if (unlikely(r != 0)) {
1946                 amdgpu_bo_unreserve(ring->mqd_obj);
1947                 return r;
1948         }
1949
1950         gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id);
1951         amdgpu_bo_kunmap(ring->mqd_obj);
1952         ring->mqd_ptr = NULL;
1953         amdgpu_bo_unreserve(ring->mqd_obj);
1954         return 0;
1955 }
1956
1957 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)
1958 {
1959         struct amdgpu_ring *ring = NULL;
1960         int r = 0, i;
1961
1962         gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);
1963
1964         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1965                 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
1966
1967                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
1968                 if (unlikely(r != 0))
1969                         goto done;
1970                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
1971                 if (!r) {
1972                         r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id);
1973                         amdgpu_bo_kunmap(ring->mqd_obj);
1974                         ring->mqd_ptr = NULL;
1975                 }
1976                 amdgpu_bo_unreserve(ring->mqd_obj);
1977                 if (r)
1978                         goto done;
1979         }
1980
1981         r = amdgpu_gfx_enable_kcq(adev, xcc_id);
1982 done:
1983         return r;
1984 }
1985
1986 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)
1987 {
1988         struct amdgpu_ring *ring;
1989         int r, j;
1990
1991         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id);
1992
1993         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1994                 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id);
1995
1996                 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id);
1997                 if (r)
1998                         return r;
1999         }
2000
2001         r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id);
2002         if (r)
2003                 return r;
2004
2005         r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id);
2006         if (r)
2007                 return r;
2008
2009         for (j = 0; j < adev->gfx.num_compute_rings; j++) {
2010                 ring = &adev->gfx.compute_ring
2011                                 [j + xcc_id * adev->gfx.num_compute_rings];
2012                 r = amdgpu_ring_test_helper(ring);
2013                 if (r)
2014                         return r;
2015         }
2016
2017         gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id);
2018
2019         return 0;
2020 }
2021
2022 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev)
2023 {
2024         int r = 0, i, num_xcc;
2025
2026         if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr,
2027                                             AMDGPU_XCP_FL_NONE) ==
2028             AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE)
2029                 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr,
2030                                                      amdgpu_user_partt_mode);
2031
2032         if (r)
2033                 return r;
2034
2035         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2036         for (i = 0; i < num_xcc; i++) {
2037                 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
2038                 if (r)
2039                         return r;
2040         }
2041
2042         return 0;
2043 }
2044
2045 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable,
2046                                      int xcc_id)
2047 {
2048         gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id);
2049 }
2050
2051 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id)
2052 {
2053         if (amdgpu_gfx_disable_kcq(adev, xcc_id))
2054                 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id);
2055
2056         if (amdgpu_sriov_vf(adev)) {
2057                 /* must disable polling for SRIOV when hw finished, otherwise
2058                  * CPC engine may still keep fetching WB address which is already
2059                  * invalid after sw finished and trigger DMAR reading error in
2060                  * hypervisor side.
2061                  */
2062                 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0);
2063                 return;
2064         }
2065
2066         /* Use deinitialize sequence from CAIL when unbinding device
2067          * from driver, otherwise KIQ is hanging when binding back
2068          */
2069         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
2070                 mutex_lock(&adev->srbm_mutex);
2071                 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
2072                                   adev->gfx.kiq[xcc_id].ring.pipe,
2073                                   adev->gfx.kiq[xcc_id].ring.queue, 0,
2074                                   GET_INST(GC, xcc_id));
2075                 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring,
2076                                                  xcc_id);
2077                 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
2078                 mutex_unlock(&adev->srbm_mutex);
2079         }
2080
2081         gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id);
2082         gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id);
2083 }
2084
2085 static int gfx_v9_4_3_hw_init(void *handle)
2086 {
2087         int r;
2088         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2089
2090         if (!amdgpu_sriov_vf(adev))
2091                 gfx_v9_4_3_init_golden_registers(adev);
2092
2093         gfx_v9_4_3_constants_init(adev);
2094
2095         r = adev->gfx.rlc.funcs->resume(adev);
2096         if (r)
2097                 return r;
2098
2099         r = gfx_v9_4_3_cp_resume(adev);
2100         if (r)
2101                 return r;
2102
2103         return r;
2104 }
2105
2106 static int gfx_v9_4_3_hw_fini(void *handle)
2107 {
2108         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2109         int i, num_xcc;
2110
2111         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2112         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2113
2114         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2115         for (i = 0; i < num_xcc; i++) {
2116                 gfx_v9_4_3_xcc_fini(adev, i);
2117         }
2118
2119         return 0;
2120 }
2121
2122 static int gfx_v9_4_3_suspend(void *handle)
2123 {
2124         return gfx_v9_4_3_hw_fini(handle);
2125 }
2126
2127 static int gfx_v9_4_3_resume(void *handle)
2128 {
2129         return gfx_v9_4_3_hw_init(handle);
2130 }
2131
2132 static bool gfx_v9_4_3_is_idle(void *handle)
2133 {
2134         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2135         int i, num_xcc;
2136
2137         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2138         for (i = 0; i < num_xcc; i++) {
2139                 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS),
2140                                         GRBM_STATUS, GUI_ACTIVE))
2141                         return false;
2142         }
2143         return true;
2144 }
2145
2146 static int gfx_v9_4_3_wait_for_idle(void *handle)
2147 {
2148         unsigned i;
2149         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2150
2151         for (i = 0; i < adev->usec_timeout; i++) {
2152                 if (gfx_v9_4_3_is_idle(handle))
2153                         return 0;
2154                 udelay(1);
2155         }
2156         return -ETIMEDOUT;
2157 }
2158
2159 static int gfx_v9_4_3_soft_reset(void *handle)
2160 {
2161         u32 grbm_soft_reset = 0;
2162         u32 tmp;
2163         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2164
2165         /* GRBM_STATUS */
2166         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS);
2167         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
2168                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
2169                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
2170                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
2171                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
2172                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
2173                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2174                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2175                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2176                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
2177         }
2178
2179         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
2180                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2181                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
2182         }
2183
2184         /* GRBM_STATUS2 */
2185         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2);
2186         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
2187                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
2188                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2189
2190
2191         if (grbm_soft_reset) {
2192                 /* stop the rlc */
2193                 adev->gfx.rlc.funcs->stop(adev);
2194
2195                 /* Disable MEC parsing/prefetching */
2196                 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0);
2197
2198                 if (grbm_soft_reset) {
2199                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2200                         tmp |= grbm_soft_reset;
2201                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2202                         WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2203                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2204
2205                         udelay(50);
2206
2207                         tmp &= ~grbm_soft_reset;
2208                         WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp);
2209                         tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET);
2210                 }
2211
2212                 /* Wait a little for things to settle down */
2213                 udelay(50);
2214         }
2215         return 0;
2216 }
2217
2218 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring,
2219                                           uint32_t vmid,
2220                                           uint32_t gds_base, uint32_t gds_size,
2221                                           uint32_t gws_base, uint32_t gws_size,
2222                                           uint32_t oa_base, uint32_t oa_size)
2223 {
2224         struct amdgpu_device *adev = ring->adev;
2225
2226         /* GDS Base */
2227         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2228                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid,
2229                                    gds_base);
2230
2231         /* GDS Size */
2232         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2233                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid,
2234                                    gds_size);
2235
2236         /* GWS */
2237         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2238                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid,
2239                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
2240
2241         /* OA */
2242         gfx_v9_4_3_write_data_to_reg(ring, 0, false,
2243                                    SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid,
2244                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
2245 }
2246
2247 static int gfx_v9_4_3_early_init(void *handle)
2248 {
2249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2250
2251         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
2252                                           AMDGPU_MAX_COMPUTE_RINGS);
2253         gfx_v9_4_3_set_kiq_pm4_funcs(adev);
2254         gfx_v9_4_3_set_ring_funcs(adev);
2255         gfx_v9_4_3_set_irq_funcs(adev);
2256         gfx_v9_4_3_set_gds_init(adev);
2257         gfx_v9_4_3_set_rlc_funcs(adev);
2258
2259         /* init rlcg reg access ctrl */
2260         gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev);
2261
2262         return gfx_v9_4_3_init_microcode(adev);
2263 }
2264
2265 static int gfx_v9_4_3_late_init(void *handle)
2266 {
2267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2268         int r;
2269
2270         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2271         if (r)
2272                 return r;
2273
2274         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2275         if (r)
2276                 return r;
2277
2278         if (adev->gfx.ras &&
2279             adev->gfx.ras->enable_watchdog_timer)
2280                 adev->gfx.ras->enable_watchdog_timer(adev);
2281
2282         return 0;
2283 }
2284
2285 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev,
2286                                             bool enable, int xcc_id)
2287 {
2288         uint32_t def, data;
2289
2290         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
2291                 return;
2292
2293         def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2294                                   regRLC_CGTT_MGCG_OVERRIDE);
2295
2296         if (enable)
2297                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2298         else
2299                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
2300
2301         if (def != data)
2302                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2303                              regRLC_CGTT_MGCG_OVERRIDE, data);
2304
2305 }
2306
2307 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev,
2308                                                 bool enable, int xcc_id)
2309 {
2310         uint32_t def, data;
2311
2312         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
2313                 return;
2314
2315         def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id),
2316                                   regRLC_CGTT_MGCG_OVERRIDE);
2317
2318         if (enable)
2319                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2320         else
2321                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK;
2322
2323         if (def != data)
2324                 WREG32_SOC15(GC, GET_INST(GC, xcc_id),
2325                              regRLC_CGTT_MGCG_OVERRIDE, data);
2326 }
2327
2328 static void
2329 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev,
2330                                                 bool enable, int xcc_id)
2331 {
2332         uint32_t data, def;
2333
2334         /* It is disabled by HW by default */
2335         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2336                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
2337                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2338
2339                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2340                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2341                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2342                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2343
2344                 if (def != data)
2345                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2346
2347                 /* MGLS is a global flag to control all MGLS in GFX */
2348                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
2349                         /* 2 - RLC memory Light sleep */
2350                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
2351                                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2352                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2353                                 if (def != data)
2354                                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2355                         }
2356                         /* 3 - CP memory Light sleep */
2357                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2358                                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2359                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2360                                 if (def != data)
2361                                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2362                         }
2363                 }
2364         } else {
2365                 /* 1 - MGCG_OVERRIDE */
2366                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2367
2368                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
2369                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
2370                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
2371                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
2372
2373                 if (def != data)
2374                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2375
2376                 /* 2 - disable MGLS in RLC */
2377                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL);
2378                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
2379                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
2380                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data);
2381                 }
2382
2383                 /* 3 - disable MGLS in CP */
2384                 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL);
2385                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2386                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2387                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data);
2388                 }
2389         }
2390
2391 }
2392
2393 static void
2394 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
2395                                                 bool enable, int xcc_id)
2396 {
2397         uint32_t def, data;
2398
2399         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2400
2401                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE);
2402                 /* unset CGCG override */
2403                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
2404                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2405                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2406                 else
2407                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
2408                 /* update CGCG and CGLS override bits */
2409                 if (def != data)
2410                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data);
2411
2412                 /* CGCG Hysteresis: 400us */
2413                 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2414
2415                 data = (0x2710
2416                         << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
2417                        RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
2418                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
2419                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
2420                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2421                 if (def != data)
2422                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2423
2424                 /* set IDLE_POLL_COUNT(0x33450100)*/
2425                 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL);
2426                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
2427                         (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2428                 if (def != data)
2429                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data);
2430         } else {
2431                 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL);
2432                 /* reset CGCG/CGLS bits */
2433                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2434                 /* disable cgcg and cgls in FSM */
2435                 if (def != data)
2436                         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data);
2437         }
2438
2439 }
2440
2441 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev,
2442                                                   bool enable, int xcc_id)
2443 {
2444         amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id);
2445
2446         if (enable) {
2447                 /* FGCG */
2448                 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2449                 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2450
2451                 /* CGCG/CGLS should be enabled after MGCG/MGLS
2452                  * ===  MGCG + MGLS ===
2453                  */
2454                 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2455                                                                 xcc_id);
2456                 /* ===  CGCG + CGLS === */
2457                 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2458                                                                 xcc_id);
2459         } else {
2460                 /* CGCG/CGLS should be disabled before MGCG/MGLS
2461                  * ===  CGCG + CGLS ===
2462                  */
2463                 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable,
2464                                                                 xcc_id);
2465                 /* ===  MGCG + MGLS === */
2466                 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable,
2467                                                                 xcc_id);
2468
2469                 /* FGCG */
2470                 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id);
2471                 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id);
2472         }
2473
2474         amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id);
2475
2476         return 0;
2477 }
2478
2479 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
2480         .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled,
2481         .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode,
2482         .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode,
2483         .init = gfx_v9_4_3_rlc_init,
2484         .resume = gfx_v9_4_3_rlc_resume,
2485         .stop = gfx_v9_4_3_rlc_stop,
2486         .reset = gfx_v9_4_3_rlc_reset,
2487         .start = gfx_v9_4_3_rlc_start,
2488         .update_spm_vmid = gfx_v9_4_3_update_spm_vmid,
2489         .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
2490 };
2491
2492 static int gfx_v9_4_3_set_powergating_state(void *handle,
2493                                           enum amd_powergating_state state)
2494 {
2495         return 0;
2496 }
2497
2498 static int gfx_v9_4_3_set_clockgating_state(void *handle,
2499                                           enum amd_clockgating_state state)
2500 {
2501         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2502         int i, num_xcc;
2503
2504         if (amdgpu_sriov_vf(adev))
2505                 return 0;
2506
2507         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2508         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2509         case IP_VERSION(9, 4, 3):
2510         case IP_VERSION(9, 4, 4):
2511                 for (i = 0; i < num_xcc; i++)
2512                         gfx_v9_4_3_xcc_update_gfx_clock_gating(
2513                                 adev, state == AMD_CG_STATE_GATE, i);
2514                 break;
2515         default:
2516                 break;
2517         }
2518         return 0;
2519 }
2520
2521 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags)
2522 {
2523         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2524         int data;
2525
2526         if (amdgpu_sriov_vf(adev))
2527                 *flags = 0;
2528
2529         /* AMD_CG_SUPPORT_GFX_MGCG */
2530         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE));
2531         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
2532                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
2533
2534         /* AMD_CG_SUPPORT_GFX_CGCG */
2535         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL));
2536         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
2537                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
2538
2539         /* AMD_CG_SUPPORT_GFX_CGLS */
2540         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
2541                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
2542
2543         /* AMD_CG_SUPPORT_GFX_RLC_LS */
2544         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL));
2545         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
2546                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
2547
2548         /* AMD_CG_SUPPORT_GFX_CP_LS */
2549         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL));
2550         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
2551                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
2552 }
2553
2554 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2555 {
2556         struct amdgpu_device *adev = ring->adev;
2557         u32 ref_and_mask, reg_mem_engine;
2558         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
2559
2560         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
2561                 switch (ring->me) {
2562                 case 1:
2563                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
2564                         break;
2565                 case 2:
2566                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
2567                         break;
2568                 default:
2569                         return;
2570                 }
2571                 reg_mem_engine = 0;
2572         } else {
2573                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
2574                 reg_mem_engine = 1; /* pfp */
2575         }
2576
2577         gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1,
2578                               adev->nbio.funcs->get_hdp_flush_req_offset(adev),
2579                               adev->nbio.funcs->get_hdp_flush_done_offset(adev),
2580                               ref_and_mask, ref_and_mask, 0x20);
2581 }
2582
2583 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring,
2584                                           struct amdgpu_job *job,
2585                                           struct amdgpu_ib *ib,
2586                                           uint32_t flags)
2587 {
2588         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
2589         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
2590
2591         /* Currently, there is a high possibility to get wave ID mismatch
2592          * between ME and GDS, leading to a hw deadlock, because ME generates
2593          * different wave IDs than the GDS expects. This situation happens
2594          * randomly when at least 5 compute pipes use GDS ordered append.
2595          * The wave IDs generated by ME are also wrong after suspend/resume.
2596          * Those are probably bugs somewhere else in the kernel driver.
2597          *
2598          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
2599          * GDS to 0 for this ring (me/pipe).
2600          */
2601         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
2602                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2603                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
2604                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
2605         }
2606
2607         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2608         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
2609         amdgpu_ring_write(ring,
2610 #ifdef __BIG_ENDIAN
2611                                 (2 << 0) |
2612 #endif
2613                                 lower_32_bits(ib->gpu_addr));
2614         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
2615         amdgpu_ring_write(ring, control);
2616 }
2617
2618 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
2619                                      u64 seq, unsigned flags)
2620 {
2621         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2622         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2623         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
2624
2625         /* RELEASE_MEM - flush caches, send int */
2626         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
2627         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
2628                                                EOP_TC_NC_ACTION_EN) :
2629                                               (EOP_TCL1_ACTION_EN |
2630                                                EOP_TC_ACTION_EN |
2631                                                EOP_TC_WB_ACTION_EN |
2632                                                EOP_TC_MD_ACTION_EN)) |
2633                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2634                                  EVENT_INDEX(5)));
2635         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2636
2637         /*
2638          * the address should be Qword aligned if 64bit write, Dword
2639          * aligned if only send 32bit data low (discard data high)
2640          */
2641         if (write64bit)
2642                 BUG_ON(addr & 0x7);
2643         else
2644                 BUG_ON(addr & 0x3);
2645         amdgpu_ring_write(ring, lower_32_bits(addr));
2646         amdgpu_ring_write(ring, upper_32_bits(addr));
2647         amdgpu_ring_write(ring, lower_32_bits(seq));
2648         amdgpu_ring_write(ring, upper_32_bits(seq));
2649         amdgpu_ring_write(ring, 0);
2650 }
2651
2652 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2653 {
2654         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2655         uint32_t seq = ring->fence_drv.sync_seq;
2656         uint64_t addr = ring->fence_drv.gpu_addr;
2657
2658         gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0,
2659                               lower_32_bits(addr), upper_32_bits(addr),
2660                               seq, 0xffffffff, 4);
2661 }
2662
2663 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring,
2664                                         unsigned vmid, uint64_t pd_addr)
2665 {
2666         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2667 }
2668
2669 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring)
2670 {
2671         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
2672 }
2673
2674 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring)
2675 {
2676         u64 wptr;
2677
2678         /* XXX check if swapping is necessary on BE */
2679         if (ring->use_doorbell)
2680                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
2681         else
2682                 BUG();
2683         return wptr;
2684 }
2685
2686 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring)
2687 {
2688         struct amdgpu_device *adev = ring->adev;
2689
2690         /* XXX check if swapping is necessary on BE */
2691         if (ring->use_doorbell) {
2692                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
2693                 WDOORBELL64(ring->doorbell_index, ring->wptr);
2694         } else {
2695                 BUG(); /* only DOORBELL method supported on gfx9 now */
2696         }
2697 }
2698
2699 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
2700                                          u64 seq, unsigned int flags)
2701 {
2702         struct amdgpu_device *adev = ring->adev;
2703
2704         /* we only allocate 32bit for each seq wb address */
2705         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
2706
2707         /* write fence seq to the "addr" */
2708         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2709         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2710                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
2711         amdgpu_ring_write(ring, lower_32_bits(addr));
2712         amdgpu_ring_write(ring, upper_32_bits(addr));
2713         amdgpu_ring_write(ring, lower_32_bits(seq));
2714
2715         if (flags & AMDGPU_FENCE_FLAG_INT) {
2716                 /* set register to trigger INT */
2717                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2718                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
2719                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
2720                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
2721                 amdgpu_ring_write(ring, 0);
2722                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
2723         }
2724 }
2725
2726 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
2727                                     uint32_t reg_val_offs)
2728 {
2729         struct amdgpu_device *adev = ring->adev;
2730
2731         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
2732         amdgpu_ring_write(ring, 0 |     /* src: register*/
2733                                 (5 << 8) |      /* dst: memory */
2734                                 (1 << 20));     /* write confirm */
2735         amdgpu_ring_write(ring, reg);
2736         amdgpu_ring_write(ring, 0);
2737         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
2738                                 reg_val_offs * 4));
2739         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
2740                                 reg_val_offs * 4));
2741 }
2742
2743 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
2744                                     uint32_t val)
2745 {
2746         uint32_t cmd = 0;
2747
2748         switch (ring->funcs->type) {
2749         case AMDGPU_RING_TYPE_GFX:
2750                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
2751                 break;
2752         case AMDGPU_RING_TYPE_KIQ:
2753                 cmd = (1 << 16); /* no inc addr */
2754                 break;
2755         default:
2756                 cmd = WR_CONFIRM;
2757                 break;
2758         }
2759         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2760         amdgpu_ring_write(ring, cmd);
2761         amdgpu_ring_write(ring, reg);
2762         amdgpu_ring_write(ring, 0);
2763         amdgpu_ring_write(ring, val);
2764 }
2765
2766 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
2767                                         uint32_t val, uint32_t mask)
2768 {
2769         gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
2770 }
2771
2772 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
2773                                                   uint32_t reg0, uint32_t reg1,
2774                                                   uint32_t ref, uint32_t mask)
2775 {
2776         amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
2777                                                    ref, mask);
2778 }
2779
2780 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2781         struct amdgpu_device *adev, int me, int pipe,
2782         enum amdgpu_interrupt_state state, int xcc_id)
2783 {
2784         u32 mec_int_cntl, mec_int_cntl_reg;
2785
2786         /*
2787          * amdgpu controls only the first MEC. That's why this function only
2788          * handles the setting of interrupts for this specific MEC. All other
2789          * pipes' interrupts are set by amdkfd.
2790          */
2791
2792         if (me == 1) {
2793                 switch (pipe) {
2794                 case 0:
2795                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL);
2796                         break;
2797                 case 1:
2798                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL);
2799                         break;
2800                 case 2:
2801                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL);
2802                         break;
2803                 case 3:
2804                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL);
2805                         break;
2806                 default:
2807                         DRM_DEBUG("invalid pipe %d\n", pipe);
2808                         return;
2809                 }
2810         } else {
2811                 DRM_DEBUG("invalid me %d\n", me);
2812                 return;
2813         }
2814
2815         switch (state) {
2816         case AMDGPU_IRQ_STATE_DISABLE:
2817                 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id);
2818                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2819                                              TIME_STAMP_INT_ENABLE, 0);
2820                 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
2821                 break;
2822         case AMDGPU_IRQ_STATE_ENABLE:
2823                 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id);
2824                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
2825                                              TIME_STAMP_INT_ENABLE, 1);
2826                 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id);
2827                 break;
2828         default:
2829                 break;
2830         }
2831 }
2832
2833 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev,
2834                                              struct amdgpu_irq_src *source,
2835                                              unsigned type,
2836                                              enum amdgpu_interrupt_state state)
2837 {
2838         int i, num_xcc;
2839
2840         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2841         switch (state) {
2842         case AMDGPU_IRQ_STATE_DISABLE:
2843         case AMDGPU_IRQ_STATE_ENABLE:
2844                 for (i = 0; i < num_xcc; i++)
2845                         WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2846                                 PRIV_REG_INT_ENABLE,
2847                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2848                 break;
2849         default:
2850                 break;
2851         }
2852
2853         return 0;
2854 }
2855
2856 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev,
2857                                               struct amdgpu_irq_src *source,
2858                                               unsigned type,
2859                                               enum amdgpu_interrupt_state state)
2860 {
2861         int i, num_xcc;
2862
2863         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2864         switch (state) {
2865         case AMDGPU_IRQ_STATE_DISABLE:
2866         case AMDGPU_IRQ_STATE_ENABLE:
2867                 for (i = 0; i < num_xcc; i++)
2868                         WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0,
2869                                 PRIV_INSTR_INT_ENABLE,
2870                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2871                 break;
2872         default:
2873                 break;
2874         }
2875
2876         return 0;
2877 }
2878
2879 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev,
2880                                             struct amdgpu_irq_src *src,
2881                                             unsigned type,
2882                                             enum amdgpu_interrupt_state state)
2883 {
2884         int i, num_xcc;
2885
2886         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2887         for (i = 0; i < num_xcc; i++) {
2888                 switch (type) {
2889                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
2890                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2891                                 adev, 1, 0, state, i);
2892                         break;
2893                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
2894                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2895                                 adev, 1, 1, state, i);
2896                         break;
2897                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
2898                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2899                                 adev, 1, 2, state, i);
2900                         break;
2901                 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
2902                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2903                                 adev, 1, 3, state, i);
2904                         break;
2905                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
2906                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2907                                 adev, 2, 0, state, i);
2908                         break;
2909                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
2910                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2911                                 adev, 2, 1, state, i);
2912                         break;
2913                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
2914                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2915                                 adev, 2, 2, state, i);
2916                         break;
2917                 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
2918                         gfx_v9_4_3_xcc_set_compute_eop_interrupt_state(
2919                                 adev, 2, 3, state, i);
2920                         break;
2921                 default:
2922                         break;
2923                 }
2924         }
2925
2926         return 0;
2927 }
2928
2929 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev,
2930                             struct amdgpu_irq_src *source,
2931                             struct amdgpu_iv_entry *entry)
2932 {
2933         int i, xcc_id;
2934         u8 me_id, pipe_id, queue_id;
2935         struct amdgpu_ring *ring;
2936
2937         DRM_DEBUG("IH: CP EOP\n");
2938         me_id = (entry->ring_id & 0x0c) >> 2;
2939         pipe_id = (entry->ring_id & 0x03) >> 0;
2940         queue_id = (entry->ring_id & 0x70) >> 4;
2941
2942         xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2943
2944         if (xcc_id == -EINVAL)
2945                 return -EINVAL;
2946
2947         switch (me_id) {
2948         case 0:
2949         case 1:
2950         case 2:
2951                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2952                         ring = &adev->gfx.compute_ring
2953                                         [i +
2954                                          xcc_id * adev->gfx.num_compute_rings];
2955                         /* Per-queue interrupt is supported for MEC starting from VI.
2956                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
2957                           */
2958
2959                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
2960                                 amdgpu_fence_process(ring);
2961                 }
2962                 break;
2963         }
2964         return 0;
2965 }
2966
2967 static void gfx_v9_4_3_fault(struct amdgpu_device *adev,
2968                            struct amdgpu_iv_entry *entry)
2969 {
2970         u8 me_id, pipe_id, queue_id;
2971         struct amdgpu_ring *ring;
2972         int i, xcc_id;
2973
2974         me_id = (entry->ring_id & 0x0c) >> 2;
2975         pipe_id = (entry->ring_id & 0x03) >> 0;
2976         queue_id = (entry->ring_id & 0x70) >> 4;
2977
2978         xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id);
2979
2980         if (xcc_id == -EINVAL)
2981                 return;
2982
2983         switch (me_id) {
2984         case 0:
2985         case 1:
2986         case 2:
2987                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2988                         ring = &adev->gfx.compute_ring
2989                                         [i +
2990                                          xcc_id * adev->gfx.num_compute_rings];
2991                         if (ring->me == me_id && ring->pipe == pipe_id &&
2992                             ring->queue == queue_id)
2993                                 drm_sched_fault(&ring->sched);
2994                 }
2995                 break;
2996         }
2997 }
2998
2999 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev,
3000                                  struct amdgpu_irq_src *source,
3001                                  struct amdgpu_iv_entry *entry)
3002 {
3003         DRM_ERROR("Illegal register access in command stream\n");
3004         gfx_v9_4_3_fault(adev, entry);
3005         return 0;
3006 }
3007
3008 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev,
3009                                   struct amdgpu_irq_src *source,
3010                                   struct amdgpu_iv_entry *entry)
3011 {
3012         DRM_ERROR("Illegal instruction in command stream\n");
3013         gfx_v9_4_3_fault(adev, entry);
3014         return 0;
3015 }
3016
3017 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring)
3018 {
3019         const unsigned int cp_coher_cntl =
3020                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) |
3021                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) |
3022                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) |
3023                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) |
3024                         PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1);
3025
3026         /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */
3027         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5));
3028         amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */
3029         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
3030         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
3031         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
3032         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
3033         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
3034 }
3035
3036 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring,
3037                                         uint32_t pipe, bool enable)
3038 {
3039         struct amdgpu_device *adev = ring->adev;
3040         uint32_t val;
3041         uint32_t wcl_cs_reg;
3042
3043         /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */
3044         val = enable ? 0x1 : 0x7f;
3045
3046         switch (pipe) {
3047         case 0:
3048                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0);
3049                 break;
3050         case 1:
3051                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1);
3052                 break;
3053         case 2:
3054                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2);
3055                 break;
3056         case 3:
3057                 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3);
3058                 break;
3059         default:
3060                 DRM_DEBUG("invalid pipe %d\n", pipe);
3061                 return;
3062         }
3063
3064         amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
3065
3066 }
3067 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
3068 {
3069         struct amdgpu_device *adev = ring->adev;
3070         uint32_t val;
3071         int i;
3072
3073         /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit
3074          * number of gfx waves. Setting 5 bit will make sure gfx only gets
3075          * around 25% of gpu resources.
3076          */
3077         val = enable ? 0x1f : 0x07ffffff;
3078         amdgpu_ring_emit_wreg(ring,
3079                               SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX),
3080                               val);
3081
3082         /* Restrict waves for normal/low priority compute queues as well
3083          * to get best QoS for high priority compute jobs.
3084          *
3085          * amdgpu controls only 1st ME(0-3 CS pipes).
3086          */
3087         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3088                 if (i != ring->pipe)
3089                         gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable);
3090
3091         }
3092 }
3093
3094 enum amdgpu_gfx_cp_ras_mem_id {
3095         AMDGPU_GFX_CP_MEM1 = 1,
3096         AMDGPU_GFX_CP_MEM2,
3097         AMDGPU_GFX_CP_MEM3,
3098         AMDGPU_GFX_CP_MEM4,
3099         AMDGPU_GFX_CP_MEM5,
3100 };
3101
3102 enum amdgpu_gfx_gcea_ras_mem_id {
3103         AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4,
3104         AMDGPU_GFX_GCEA_IORD_CMDMEM,
3105         AMDGPU_GFX_GCEA_GMIWR_CMDMEM,
3106         AMDGPU_GFX_GCEA_GMIRD_CMDMEM,
3107         AMDGPU_GFX_GCEA_DRAMWR_CMDMEM,
3108         AMDGPU_GFX_GCEA_DRAMRD_CMDMEM,
3109         AMDGPU_GFX_GCEA_MAM_DMEM0,
3110         AMDGPU_GFX_GCEA_MAM_DMEM1,
3111         AMDGPU_GFX_GCEA_MAM_DMEM2,
3112         AMDGPU_GFX_GCEA_MAM_DMEM3,
3113         AMDGPU_GFX_GCEA_MAM_AMEM0,
3114         AMDGPU_GFX_GCEA_MAM_AMEM1,
3115         AMDGPU_GFX_GCEA_MAM_AMEM2,
3116         AMDGPU_GFX_GCEA_MAM_AMEM3,
3117         AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER,
3118         AMDGPU_GFX_GCEA_WRET_TAGMEM,
3119         AMDGPU_GFX_GCEA_RRET_TAGMEM,
3120         AMDGPU_GFX_GCEA_IOWR_DATAMEM,
3121         AMDGPU_GFX_GCEA_GMIWR_DATAMEM,
3122         AMDGPU_GFX_GCEA_DRAM_DATAMEM,
3123 };
3124
3125 enum amdgpu_gfx_gc_cane_ras_mem_id {
3126         AMDGPU_GFX_GC_CANE_MEM0 = 0,
3127 };
3128
3129 enum amdgpu_gfx_gcutcl2_ras_mem_id {
3130         AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160,
3131 };
3132
3133 enum amdgpu_gfx_gds_ras_mem_id {
3134         AMDGPU_GFX_GDS_MEM0 = 0,
3135 };
3136
3137 enum amdgpu_gfx_lds_ras_mem_id {
3138         AMDGPU_GFX_LDS_BANK0 = 0,
3139         AMDGPU_GFX_LDS_BANK1,
3140         AMDGPU_GFX_LDS_BANK2,
3141         AMDGPU_GFX_LDS_BANK3,
3142         AMDGPU_GFX_LDS_BANK4,
3143         AMDGPU_GFX_LDS_BANK5,
3144         AMDGPU_GFX_LDS_BANK6,
3145         AMDGPU_GFX_LDS_BANK7,
3146         AMDGPU_GFX_LDS_BANK8,
3147         AMDGPU_GFX_LDS_BANK9,
3148         AMDGPU_GFX_LDS_BANK10,
3149         AMDGPU_GFX_LDS_BANK11,
3150         AMDGPU_GFX_LDS_BANK12,
3151         AMDGPU_GFX_LDS_BANK13,
3152         AMDGPU_GFX_LDS_BANK14,
3153         AMDGPU_GFX_LDS_BANK15,
3154         AMDGPU_GFX_LDS_BANK16,
3155         AMDGPU_GFX_LDS_BANK17,
3156         AMDGPU_GFX_LDS_BANK18,
3157         AMDGPU_GFX_LDS_BANK19,
3158         AMDGPU_GFX_LDS_BANK20,
3159         AMDGPU_GFX_LDS_BANK21,
3160         AMDGPU_GFX_LDS_BANK22,
3161         AMDGPU_GFX_LDS_BANK23,
3162         AMDGPU_GFX_LDS_BANK24,
3163         AMDGPU_GFX_LDS_BANK25,
3164         AMDGPU_GFX_LDS_BANK26,
3165         AMDGPU_GFX_LDS_BANK27,
3166         AMDGPU_GFX_LDS_BANK28,
3167         AMDGPU_GFX_LDS_BANK29,
3168         AMDGPU_GFX_LDS_BANK30,
3169         AMDGPU_GFX_LDS_BANK31,
3170         AMDGPU_GFX_LDS_SP_BUFFER_A,
3171         AMDGPU_GFX_LDS_SP_BUFFER_B,
3172 };
3173
3174 enum amdgpu_gfx_rlc_ras_mem_id {
3175         AMDGPU_GFX_RLC_GPMF32 = 1,
3176         AMDGPU_GFX_RLC_RLCVF32,
3177         AMDGPU_GFX_RLC_SCRATCH,
3178         AMDGPU_GFX_RLC_SRM_ARAM,
3179         AMDGPU_GFX_RLC_SRM_DRAM,
3180         AMDGPU_GFX_RLC_TCTAG,
3181         AMDGPU_GFX_RLC_SPM_SE,
3182         AMDGPU_GFX_RLC_SPM_GRBMT,
3183 };
3184
3185 enum amdgpu_gfx_sp_ras_mem_id {
3186         AMDGPU_GFX_SP_SIMDID0 = 0,
3187 };
3188
3189 enum amdgpu_gfx_spi_ras_mem_id {
3190         AMDGPU_GFX_SPI_MEM0 = 0,
3191         AMDGPU_GFX_SPI_MEM1,
3192         AMDGPU_GFX_SPI_MEM2,
3193         AMDGPU_GFX_SPI_MEM3,
3194 };
3195
3196 enum amdgpu_gfx_sqc_ras_mem_id {
3197         AMDGPU_GFX_SQC_INST_CACHE_A = 100,
3198         AMDGPU_GFX_SQC_INST_CACHE_B = 101,
3199         AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102,
3200         AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103,
3201         AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104,
3202         AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105,
3203         AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106,
3204         AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107,
3205         AMDGPU_GFX_SQC_DATA_CACHE_A = 200,
3206         AMDGPU_GFX_SQC_DATA_CACHE_B = 201,
3207         AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202,
3208         AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203,
3209         AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204,
3210         AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205,
3211         AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206,
3212         AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207,
3213         AMDGPU_GFX_SQC_DIRTY_BIT_A = 208,
3214         AMDGPU_GFX_SQC_DIRTY_BIT_B = 209,
3215         AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210,
3216         AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211,
3217         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212,
3218         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213,
3219         AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108,
3220 };
3221
3222 enum amdgpu_gfx_sq_ras_mem_id {
3223         AMDGPU_GFX_SQ_SGPR_MEM0 = 0,
3224         AMDGPU_GFX_SQ_SGPR_MEM1,
3225         AMDGPU_GFX_SQ_SGPR_MEM2,
3226         AMDGPU_GFX_SQ_SGPR_MEM3,
3227 };
3228
3229 enum amdgpu_gfx_ta_ras_mem_id {
3230         AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1,
3231         AMDGPU_GFX_TA_FS_AFIFO_RAM_HI,
3232         AMDGPU_GFX_TA_FS_CFIFO_RAM,
3233         AMDGPU_GFX_TA_FSX_LFIFO,
3234         AMDGPU_GFX_TA_FS_DFIFO_RAM,
3235 };
3236
3237 enum amdgpu_gfx_tcc_ras_mem_id {
3238         AMDGPU_GFX_TCC_MEM1 = 1,
3239 };
3240
3241 enum amdgpu_gfx_tca_ras_mem_id {
3242         AMDGPU_GFX_TCA_MEM1 = 1,
3243 };
3244
3245 enum amdgpu_gfx_tci_ras_mem_id {
3246         AMDGPU_GFX_TCIW_MEM = 1,
3247 };
3248
3249 enum amdgpu_gfx_tcp_ras_mem_id {
3250         AMDGPU_GFX_TCP_LFIFO0 = 1,
3251         AMDGPU_GFX_TCP_SET0BANK0_RAM,
3252         AMDGPU_GFX_TCP_SET0BANK1_RAM,
3253         AMDGPU_GFX_TCP_SET0BANK2_RAM,
3254         AMDGPU_GFX_TCP_SET0BANK3_RAM,
3255         AMDGPU_GFX_TCP_SET1BANK0_RAM,
3256         AMDGPU_GFX_TCP_SET1BANK1_RAM,
3257         AMDGPU_GFX_TCP_SET1BANK2_RAM,
3258         AMDGPU_GFX_TCP_SET1BANK3_RAM,
3259         AMDGPU_GFX_TCP_SET2BANK0_RAM,
3260         AMDGPU_GFX_TCP_SET2BANK1_RAM,
3261         AMDGPU_GFX_TCP_SET2BANK2_RAM,
3262         AMDGPU_GFX_TCP_SET2BANK3_RAM,
3263         AMDGPU_GFX_TCP_SET3BANK0_RAM,
3264         AMDGPU_GFX_TCP_SET3BANK1_RAM,
3265         AMDGPU_GFX_TCP_SET3BANK2_RAM,
3266         AMDGPU_GFX_TCP_SET3BANK3_RAM,
3267         AMDGPU_GFX_TCP_VM_FIFO,
3268         AMDGPU_GFX_TCP_DB_TAGRAM0,
3269         AMDGPU_GFX_TCP_DB_TAGRAM1,
3270         AMDGPU_GFX_TCP_DB_TAGRAM2,
3271         AMDGPU_GFX_TCP_DB_TAGRAM3,
3272         AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0,
3273         AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1,
3274         AMDGPU_GFX_TCP_CMD_FIFO,
3275 };
3276
3277 enum amdgpu_gfx_td_ras_mem_id {
3278         AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1,
3279         AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM,
3280         AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM,
3281 };
3282
3283 enum amdgpu_gfx_tcx_ras_mem_id {
3284         AMDGPU_GFX_TCX_FIFOD0 = 0,
3285         AMDGPU_GFX_TCX_FIFOD1,
3286         AMDGPU_GFX_TCX_FIFOD2,
3287         AMDGPU_GFX_TCX_FIFOD3,
3288         AMDGPU_GFX_TCX_FIFOD4,
3289         AMDGPU_GFX_TCX_FIFOD5,
3290         AMDGPU_GFX_TCX_FIFOD6,
3291         AMDGPU_GFX_TCX_FIFOD7,
3292         AMDGPU_GFX_TCX_FIFOB0,
3293         AMDGPU_GFX_TCX_FIFOB1,
3294         AMDGPU_GFX_TCX_FIFOB2,
3295         AMDGPU_GFX_TCX_FIFOB3,
3296         AMDGPU_GFX_TCX_FIFOB4,
3297         AMDGPU_GFX_TCX_FIFOB5,
3298         AMDGPU_GFX_TCX_FIFOB6,
3299         AMDGPU_GFX_TCX_FIFOB7,
3300         AMDGPU_GFX_TCX_FIFOA0,
3301         AMDGPU_GFX_TCX_FIFOA1,
3302         AMDGPU_GFX_TCX_FIFOA2,
3303         AMDGPU_GFX_TCX_FIFOA3,
3304         AMDGPU_GFX_TCX_FIFOA4,
3305         AMDGPU_GFX_TCX_FIFOA5,
3306         AMDGPU_GFX_TCX_FIFOA6,
3307         AMDGPU_GFX_TCX_FIFOA7,
3308         AMDGPU_GFX_TCX_CFIFO0,
3309         AMDGPU_GFX_TCX_CFIFO1,
3310         AMDGPU_GFX_TCX_CFIFO2,
3311         AMDGPU_GFX_TCX_CFIFO3,
3312         AMDGPU_GFX_TCX_CFIFO4,
3313         AMDGPU_GFX_TCX_CFIFO5,
3314         AMDGPU_GFX_TCX_CFIFO6,
3315         AMDGPU_GFX_TCX_CFIFO7,
3316         AMDGPU_GFX_TCX_FIFO_ACKB0,
3317         AMDGPU_GFX_TCX_FIFO_ACKB1,
3318         AMDGPU_GFX_TCX_FIFO_ACKB2,
3319         AMDGPU_GFX_TCX_FIFO_ACKB3,
3320         AMDGPU_GFX_TCX_FIFO_ACKB4,
3321         AMDGPU_GFX_TCX_FIFO_ACKB5,
3322         AMDGPU_GFX_TCX_FIFO_ACKB6,
3323         AMDGPU_GFX_TCX_FIFO_ACKB7,
3324         AMDGPU_GFX_TCX_FIFO_ACKD0,
3325         AMDGPU_GFX_TCX_FIFO_ACKD1,
3326         AMDGPU_GFX_TCX_FIFO_ACKD2,
3327         AMDGPU_GFX_TCX_FIFO_ACKD3,
3328         AMDGPU_GFX_TCX_FIFO_ACKD4,
3329         AMDGPU_GFX_TCX_FIFO_ACKD5,
3330         AMDGPU_GFX_TCX_FIFO_ACKD6,
3331         AMDGPU_GFX_TCX_FIFO_ACKD7,
3332         AMDGPU_GFX_TCX_DST_FIFOA0,
3333         AMDGPU_GFX_TCX_DST_FIFOA1,
3334         AMDGPU_GFX_TCX_DST_FIFOA2,
3335         AMDGPU_GFX_TCX_DST_FIFOA3,
3336         AMDGPU_GFX_TCX_DST_FIFOA4,
3337         AMDGPU_GFX_TCX_DST_FIFOA5,
3338         AMDGPU_GFX_TCX_DST_FIFOA6,
3339         AMDGPU_GFX_TCX_DST_FIFOA7,
3340         AMDGPU_GFX_TCX_DST_FIFOB0,
3341         AMDGPU_GFX_TCX_DST_FIFOB1,
3342         AMDGPU_GFX_TCX_DST_FIFOB2,
3343         AMDGPU_GFX_TCX_DST_FIFOB3,
3344         AMDGPU_GFX_TCX_DST_FIFOB4,
3345         AMDGPU_GFX_TCX_DST_FIFOB5,
3346         AMDGPU_GFX_TCX_DST_FIFOB6,
3347         AMDGPU_GFX_TCX_DST_FIFOB7,
3348         AMDGPU_GFX_TCX_DST_FIFOD0,
3349         AMDGPU_GFX_TCX_DST_FIFOD1,
3350         AMDGPU_GFX_TCX_DST_FIFOD2,
3351         AMDGPU_GFX_TCX_DST_FIFOD3,
3352         AMDGPU_GFX_TCX_DST_FIFOD4,
3353         AMDGPU_GFX_TCX_DST_FIFOD5,
3354         AMDGPU_GFX_TCX_DST_FIFOD6,
3355         AMDGPU_GFX_TCX_DST_FIFOD7,
3356         AMDGPU_GFX_TCX_DST_FIFO_ACKB0,
3357         AMDGPU_GFX_TCX_DST_FIFO_ACKB1,
3358         AMDGPU_GFX_TCX_DST_FIFO_ACKB2,
3359         AMDGPU_GFX_TCX_DST_FIFO_ACKB3,
3360         AMDGPU_GFX_TCX_DST_FIFO_ACKB4,
3361         AMDGPU_GFX_TCX_DST_FIFO_ACKB5,
3362         AMDGPU_GFX_TCX_DST_FIFO_ACKB6,
3363         AMDGPU_GFX_TCX_DST_FIFO_ACKB7,
3364         AMDGPU_GFX_TCX_DST_FIFO_ACKD0,
3365         AMDGPU_GFX_TCX_DST_FIFO_ACKD1,
3366         AMDGPU_GFX_TCX_DST_FIFO_ACKD2,
3367         AMDGPU_GFX_TCX_DST_FIFO_ACKD3,
3368         AMDGPU_GFX_TCX_DST_FIFO_ACKD4,
3369         AMDGPU_GFX_TCX_DST_FIFO_ACKD5,
3370         AMDGPU_GFX_TCX_DST_FIFO_ACKD6,
3371         AMDGPU_GFX_TCX_DST_FIFO_ACKD7,
3372 };
3373
3374 enum amdgpu_gfx_atc_l2_ras_mem_id {
3375         AMDGPU_GFX_ATC_L2_MEM0 = 0,
3376 };
3377
3378 enum amdgpu_gfx_utcl2_ras_mem_id {
3379         AMDGPU_GFX_UTCL2_MEM0 = 0,
3380 };
3381
3382 enum amdgpu_gfx_vml2_ras_mem_id {
3383         AMDGPU_GFX_VML2_MEM0 = 0,
3384 };
3385
3386 enum amdgpu_gfx_vml2_walker_ras_mem_id {
3387         AMDGPU_GFX_VML2_WALKER_MEM0 = 0,
3388 };
3389
3390 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = {
3391         {AMDGPU_GFX_CP_MEM1, "CP_MEM1"},
3392         {AMDGPU_GFX_CP_MEM2, "CP_MEM2"},
3393         {AMDGPU_GFX_CP_MEM3, "CP_MEM3"},
3394         {AMDGPU_GFX_CP_MEM4, "CP_MEM4"},
3395         {AMDGPU_GFX_CP_MEM5, "CP_MEM5"},
3396 };
3397
3398 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = {
3399         {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"},
3400         {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"},
3401         {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"},
3402         {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"},
3403         {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"},
3404         {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"},
3405         {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"},
3406         {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"},
3407         {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"},
3408         {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"},
3409         {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"},
3410         {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"},
3411         {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"},
3412         {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"},
3413         {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"},
3414         {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"},
3415         {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"},
3416         {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"},
3417         {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"},
3418         {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"},
3419 };
3420
3421 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = {
3422         {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"},
3423 };
3424
3425 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = {
3426         {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"},
3427 };
3428
3429 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = {
3430         {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"},
3431 };
3432
3433 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = {
3434         {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"},
3435         {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"},
3436         {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"},
3437         {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"},
3438         {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"},
3439         {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"},
3440         {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"},
3441         {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"},
3442         {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"},
3443         {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"},
3444         {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"},
3445         {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"},
3446         {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"},
3447         {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"},
3448         {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"},
3449         {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"},
3450         {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"},
3451         {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"},
3452         {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"},
3453         {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"},
3454         {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"},
3455         {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"},
3456         {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"},
3457         {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"},
3458         {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"},
3459         {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"},
3460         {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"},
3461         {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"},
3462         {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"},
3463         {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"},
3464         {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"},
3465         {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"},
3466         {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"},
3467         {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"},
3468 };
3469
3470 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = {
3471         {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"},
3472         {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"},
3473         {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"},
3474         {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"},
3475         {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"},
3476         {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"},
3477         {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"},
3478         {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"},
3479 };
3480
3481 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = {
3482         {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"},
3483 };
3484
3485 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = {
3486         {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"},
3487         {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"},
3488         {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"},
3489         {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"},
3490 };
3491
3492 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = {
3493         {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"},
3494         {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"},
3495         {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"},
3496         {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"},
3497         {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"},
3498         {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"},
3499         {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"},
3500         {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"},
3501         {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"},
3502         {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"},
3503         {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"},
3504         {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"},
3505         {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"},
3506         {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"},
3507         {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"},
3508         {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"},
3509         {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"},
3510         {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"},
3511         {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"},
3512         {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"},
3513         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"},
3514         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"},
3515         {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"},
3516 };
3517
3518 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = {
3519         {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"},
3520         {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"},
3521         {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"},
3522         {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"},
3523 };
3524
3525 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = {
3526         {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"},
3527         {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"},
3528         {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"},
3529         {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"},
3530         {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"},
3531 };
3532
3533 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = {
3534         {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"},
3535 };
3536
3537 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = {
3538         {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"},
3539 };
3540
3541 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = {
3542         {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"},
3543 };
3544
3545 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = {
3546         {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"},
3547         {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"},
3548         {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"},
3549         {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"},
3550         {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"},
3551         {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"},
3552         {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"},
3553         {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"},
3554         {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"},
3555         {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"},
3556         {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"},
3557         {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"},
3558         {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"},
3559         {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"},
3560         {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"},
3561         {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"},
3562         {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"},
3563         {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"},
3564         {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"},
3565         {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"},
3566         {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"},
3567         {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"},
3568         {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"},
3569         {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"},
3570         {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"},
3571 };
3572
3573 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = {
3574         {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"},
3575         {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"},
3576         {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"},
3577 };
3578
3579 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = {
3580         {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"},
3581         {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"},
3582         {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"},
3583         {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"},
3584         {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"},
3585         {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"},
3586         {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"},
3587         {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"},
3588         {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"},
3589         {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"},
3590         {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"},
3591         {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"},
3592         {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"},
3593         {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"},
3594         {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"},
3595         {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"},
3596         {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"},
3597         {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"},
3598         {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"},
3599         {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"},
3600         {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"},
3601         {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"},
3602         {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"},
3603         {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"},
3604         {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"},
3605         {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"},
3606         {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"},
3607         {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"},
3608         {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"},
3609         {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"},
3610         {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"},
3611         {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"},
3612         {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"},
3613         {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"},
3614         {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"},
3615         {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"},
3616         {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"},
3617         {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"},
3618         {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"},
3619         {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"},
3620         {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"},
3621         {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"},
3622         {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"},
3623         {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"},
3624         {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"},
3625         {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"},
3626         {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"},
3627         {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"},
3628         {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"},
3629         {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"},
3630         {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"},
3631         {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"},
3632         {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"},
3633         {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"},
3634         {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"},
3635         {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"},
3636         {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"},
3637         {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"},
3638         {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"},
3639         {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"},
3640         {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"},
3641         {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"},
3642         {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"},
3643         {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"},
3644         {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"},
3645         {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"},
3646         {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"},
3647         {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"},
3648         {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"},
3649         {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"},
3650         {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"},
3651         {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"},
3652         {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"},
3653         {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"},
3654         {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"},
3655         {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"},
3656         {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"},
3657         {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"},
3658         {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"},
3659         {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"},
3660         {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"},
3661         {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"},
3662         {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"},
3663         {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"},
3664         {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"},
3665         {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"},
3666         {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"},
3667         {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"},
3668 };
3669
3670 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = {
3671         {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"},
3672 };
3673
3674 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = {
3675         {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"},
3676 };
3677
3678 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = {
3679         {AMDGPU_GFX_VML2_MEM, "VML2_MEM"},
3680 };
3681
3682 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = {
3683         {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"},
3684 };
3685
3686 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = {
3687         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list)
3688         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list)
3689         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list)
3690         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list)
3691         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list)
3692         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list)
3693         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list)
3694         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list)
3695         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list)
3696         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list)
3697         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list)
3698         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list)
3699         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list)
3700         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list)
3701         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list)
3702         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list)
3703         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list)
3704         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list)
3705         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list)
3706         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list)
3707         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list)
3708         AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list)
3709 };
3710
3711 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = {
3712         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH),
3713             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3714             AMDGPU_GFX_RLC_MEM, 1},
3715         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI),
3716             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3717             AMDGPU_GFX_CP_MEM, 1},
3718         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI),
3719             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3720             AMDGPU_GFX_CP_MEM, 1},
3721         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI),
3722             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3723             AMDGPU_GFX_CP_MEM, 1},
3724         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI),
3725             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3726             AMDGPU_GFX_GDS_MEM, 1},
3727         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI),
3728             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3729             AMDGPU_GFX_GC_CANE_MEM, 1},
3730         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI),
3731             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3732             AMDGPU_GFX_SPI_MEM, 1},
3733         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI),
3734             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3735             AMDGPU_GFX_SP_MEM, 4},
3736         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI),
3737             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3738             AMDGPU_GFX_SP_MEM, 4},
3739         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI),
3740             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3741             AMDGPU_GFX_SQ_MEM, 4},
3742         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI),
3743             5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3744             AMDGPU_GFX_SQC_MEM, 4},
3745         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI),
3746             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3747             AMDGPU_GFX_TCX_MEM, 1},
3748         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI),
3749             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3750             AMDGPU_GFX_TCC_MEM, 1},
3751         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI),
3752             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3753             AMDGPU_GFX_TA_MEM, 4},
3754         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG),
3755             27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3756             AMDGPU_GFX_TCI_MEM, 1},
3757         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG),
3758             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3759             AMDGPU_GFX_TCP_MEM, 4},
3760         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI),
3761             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3762             AMDGPU_GFX_TD_MEM, 4},
3763         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI),
3764             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3765             AMDGPU_GFX_GCEA_MEM, 1},
3766         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI),
3767             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3768             AMDGPU_GFX_LDS_MEM, 4},
3769 };
3770
3771 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = {
3772         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH),
3773             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"},
3774             AMDGPU_GFX_RLC_MEM, 1},
3775         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI),
3776             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"},
3777             AMDGPU_GFX_CP_MEM, 1},
3778         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI),
3779             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"},
3780             AMDGPU_GFX_CP_MEM, 1},
3781         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI),
3782             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"},
3783             AMDGPU_GFX_CP_MEM, 1},
3784         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI),
3785             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"},
3786             AMDGPU_GFX_GDS_MEM, 1},
3787         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI),
3788             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"},
3789             AMDGPU_GFX_GC_CANE_MEM, 1},
3790         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI),
3791             1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"},
3792             AMDGPU_GFX_SPI_MEM, 1},
3793         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI),
3794             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"},
3795             AMDGPU_GFX_SP_MEM, 4},
3796         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI),
3797             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"},
3798             AMDGPU_GFX_SP_MEM, 4},
3799         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI),
3800             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"},
3801             AMDGPU_GFX_SQ_MEM, 4},
3802         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI),
3803             5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"},
3804             AMDGPU_GFX_SQC_MEM, 4},
3805         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI),
3806             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"},
3807             AMDGPU_GFX_TCX_MEM, 1},
3808         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI),
3809             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"},
3810             AMDGPU_GFX_TCC_MEM, 1},
3811         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI),
3812             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"},
3813             AMDGPU_GFX_TA_MEM, 4},
3814         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG),
3815             27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"},
3816             AMDGPU_GFX_TCI_MEM, 1},
3817         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG),
3818             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"},
3819             AMDGPU_GFX_TCP_MEM, 4},
3820         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI),
3821             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"},
3822             AMDGPU_GFX_TD_MEM, 4},
3823         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI),
3824             2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"},
3825             AMDGPU_GFX_TCA_MEM, 1},
3826         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI),
3827             16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"},
3828             AMDGPU_GFX_GCEA_MEM, 1},
3829         {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI),
3830             10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"},
3831             AMDGPU_GFX_LDS_MEM, 4},
3832 };
3833
3834 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev,
3835                                         void *ras_error_status, int xcc_id)
3836 {
3837         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
3838         unsigned long ce_count = 0, ue_count = 0;
3839         uint32_t i, j, k;
3840
3841         /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */
3842         struct amdgpu_smuio_mcm_config_info mcm_info = {
3843                 .socket_id = adev->smuio.funcs->get_socket_id(adev),
3844                 .die_id = xcc_id & 0x01 ? 1 : 0,
3845         };
3846
3847         mutex_lock(&adev->grbm_idx_mutex);
3848
3849         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3850                 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3851                         for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3852                                 /* no need to select if instance number is 1 */
3853                                 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3854                                     gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3855                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3856
3857                                 amdgpu_ras_inst_query_ras_error_count(adev,
3858                                         &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3859                                         1,
3860                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent,
3861                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size,
3862                                         GET_INST(GC, xcc_id),
3863                                         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE,
3864                                         &ce_count);
3865
3866                                 amdgpu_ras_inst_query_ras_error_count(adev,
3867                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3868                                         1,
3869                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
3870                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
3871                                         GET_INST(GC, xcc_id),
3872                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
3873                                         &ue_count);
3874                         }
3875                 }
3876         }
3877
3878         /* handle extra register entries of UE */
3879         for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) {
3880                 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) {
3881                         for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
3882                                 /* no need to select if instance number is 1 */
3883                                 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 ||
3884                                         gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1)
3885                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3886
3887                                 amdgpu_ras_inst_query_ras_error_count(adev,
3888                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3889                                         1,
3890                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent,
3891                                         gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size,
3892                                         GET_INST(GC, xcc_id),
3893                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
3894                                         &ue_count);
3895                         }
3896                 }
3897         }
3898
3899         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3900                         xcc_id);
3901         mutex_unlock(&adev->grbm_idx_mutex);
3902
3903         /* the caller should make sure initialize value of
3904          * err_data->ue_count and err_data->ce_count
3905          */
3906         amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count);
3907         amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count);
3908 }
3909
3910 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev,
3911                                         void *ras_error_status, int xcc_id)
3912 {
3913         uint32_t i, j, k;
3914
3915         mutex_lock(&adev->grbm_idx_mutex);
3916
3917         for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) {
3918                 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) {
3919                         for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) {
3920                                 /* no need to select if instance number is 1 */
3921                                 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 ||
3922                                     gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1)
3923                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3924
3925                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3926                                         &(gfx_v9_4_3_ce_reg_list[i].reg_entry),
3927                                         1,
3928                                         GET_INST(GC, xcc_id));
3929
3930                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3931                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3932                                         1,
3933                                         GET_INST(GC, xcc_id));
3934                         }
3935                 }
3936         }
3937
3938         /* handle extra register entries of UE */
3939         for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) {
3940                 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) {
3941                         for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) {
3942                                 /* no need to select if instance number is 1 */
3943                                 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 ||
3944                                         gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1)
3945                                         gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id);
3946
3947                                 amdgpu_ras_inst_reset_ras_error_count(adev,
3948                                         &(gfx_v9_4_3_ue_reg_list[i].reg_entry),
3949                                         1,
3950                                         GET_INST(GC, xcc_id));
3951                         }
3952                 }
3953         }
3954
3955         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3956                         xcc_id);
3957         mutex_unlock(&adev->grbm_idx_mutex);
3958 }
3959
3960 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev,
3961                                         void *ras_error_status, int xcc_id)
3962 {
3963         uint32_t i;
3964         uint32_t data;
3965
3966         if (amdgpu_sriov_vf(adev))
3967                 return;
3968
3969         data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG);
3970         data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
3971                              amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0);
3972
3973         if (amdgpu_watchdog_timer.timeout_fatal_disable &&
3974             (amdgpu_watchdog_timer.period < 1 ||
3975              amdgpu_watchdog_timer.period > 0x23)) {
3976                 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
3977                 amdgpu_watchdog_timer.period = 0x23;
3978         }
3979         data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
3980                              amdgpu_watchdog_timer.period);
3981
3982         mutex_lock(&adev->grbm_idx_mutex);
3983         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3984                 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id);
3985                 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data);
3986         }
3987         gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
3988                         xcc_id);
3989         mutex_unlock(&adev->grbm_idx_mutex);
3990 }
3991
3992 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev,
3993                                         void *ras_error_status)
3994 {
3995         amdgpu_gfx_ras_error_func(adev, ras_error_status,
3996                         gfx_v9_4_3_inst_query_ras_err_count);
3997 }
3998
3999 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev)
4000 {
4001         amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count);
4002 }
4003
4004 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev)
4005 {
4006         amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer);
4007 }
4008
4009 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = {
4010         .name = "gfx_v9_4_3",
4011         .early_init = gfx_v9_4_3_early_init,
4012         .late_init = gfx_v9_4_3_late_init,
4013         .sw_init = gfx_v9_4_3_sw_init,
4014         .sw_fini = gfx_v9_4_3_sw_fini,
4015         .hw_init = gfx_v9_4_3_hw_init,
4016         .hw_fini = gfx_v9_4_3_hw_fini,
4017         .suspend = gfx_v9_4_3_suspend,
4018         .resume = gfx_v9_4_3_resume,
4019         .is_idle = gfx_v9_4_3_is_idle,
4020         .wait_for_idle = gfx_v9_4_3_wait_for_idle,
4021         .soft_reset = gfx_v9_4_3_soft_reset,
4022         .set_clockgating_state = gfx_v9_4_3_set_clockgating_state,
4023         .set_powergating_state = gfx_v9_4_3_set_powergating_state,
4024         .get_clockgating_state = gfx_v9_4_3_get_clockgating_state,
4025         .dump_ip_state = NULL,
4026         .print_ip_state = NULL,
4027 };
4028
4029 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
4030         .type = AMDGPU_RING_TYPE_COMPUTE,
4031         .align_mask = 0xff,
4032         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4033         .support_64bit_ptrs = true,
4034         .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4035         .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4036         .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4037         .emit_frame_size =
4038                 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4039                 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4040                 5 + /* hdp invalidate */
4041                 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4042                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4043                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4044                 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4045                 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */
4046                 7 + /* gfx_v9_4_3_emit_mem_sync */
4047                 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */
4048                 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */
4049         .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4050         .emit_ib = gfx_v9_4_3_ring_emit_ib_compute,
4051         .emit_fence = gfx_v9_4_3_ring_emit_fence,
4052         .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync,
4053         .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush,
4054         .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch,
4055         .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush,
4056         .test_ring = gfx_v9_4_3_ring_test_ring,
4057         .test_ib = gfx_v9_4_3_ring_test_ib,
4058         .insert_nop = amdgpu_ring_insert_nop,
4059         .pad_ib = amdgpu_ring_generic_pad_ib,
4060         .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4061         .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4062         .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4063         .emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
4064         .emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
4065 };
4066
4067 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {
4068         .type = AMDGPU_RING_TYPE_KIQ,
4069         .align_mask = 0xff,
4070         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4071         .support_64bit_ptrs = true,
4072         .get_rptr = gfx_v9_4_3_ring_get_rptr_compute,
4073         .get_wptr = gfx_v9_4_3_ring_get_wptr_compute,
4074         .set_wptr = gfx_v9_4_3_ring_set_wptr_compute,
4075         .emit_frame_size =
4076                 20 + /* gfx_v9_4_3_ring_emit_gds_switch */
4077                 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */
4078                 5 + /* hdp invalidate */
4079                 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */
4080                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4081                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4082                 2 + /* gfx_v9_4_3_ring_emit_vm_flush */
4083                 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */
4084         .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */
4085         .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq,
4086         .test_ring = gfx_v9_4_3_ring_test_ring,
4087         .insert_nop = amdgpu_ring_insert_nop,
4088         .pad_ib = amdgpu_ring_generic_pad_ib,
4089         .emit_rreg = gfx_v9_4_3_ring_emit_rreg,
4090         .emit_wreg = gfx_v9_4_3_ring_emit_wreg,
4091         .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait,
4092         .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait,
4093 };
4094
4095 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev)
4096 {
4097         int i, j, num_xcc;
4098
4099         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
4100         for (i = 0; i < num_xcc; i++) {
4101                 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
4102
4103                 for (j = 0; j < adev->gfx.num_compute_rings; j++)
4104                         adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs
4105                                         = &gfx_v9_4_3_ring_funcs_compute;
4106         }
4107 }
4108
4109 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = {
4110         .set = gfx_v9_4_3_set_eop_interrupt_state,
4111         .process = gfx_v9_4_3_eop_irq,
4112 };
4113
4114 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = {
4115         .set = gfx_v9_4_3_set_priv_reg_fault_state,
4116         .process = gfx_v9_4_3_priv_reg_irq,
4117 };
4118
4119 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = {
4120         .set = gfx_v9_4_3_set_priv_inst_fault_state,
4121         .process = gfx_v9_4_3_priv_inst_irq,
4122 };
4123
4124 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev)
4125 {
4126         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4127         adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
4128
4129         adev->gfx.priv_reg_irq.num_types = 1;
4130         adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
4131
4132         adev->gfx.priv_inst_irq.num_types = 1;
4133         adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
4134 }
4135
4136 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev)
4137 {
4138         adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
4139 }
4140
4141
4142 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev)
4143 {
4144         /* init asci gds info */
4145         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4146         case IP_VERSION(9, 4, 3):
4147         case IP_VERSION(9, 4, 4):
4148                 /* 9.4.3 removed all the GDS internal memory,
4149                  * only support GWS opcode in kernel, like barrier
4150                  * semaphore.etc */
4151                 adev->gds.gds_size = 0;
4152                 break;
4153         default:
4154                 adev->gds.gds_size = 0x10000;
4155                 break;
4156         }
4157
4158         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
4159         case IP_VERSION(9, 4, 3):
4160         case IP_VERSION(9, 4, 4):
4161                 /* deprecated for 9.4.3, no usage at all */
4162                 adev->gds.gds_compute_max_wave_id = 0;
4163                 break;
4164         default:
4165                 /* this really depends on the chip */
4166                 adev->gds.gds_compute_max_wave_id = 0x7ff;
4167                 break;
4168         }
4169
4170         adev->gds.gws_size = 64;
4171         adev->gds.oa_size = 16;
4172 }
4173
4174 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4175                                                  u32 bitmap, int xcc_id)
4176 {
4177         u32 data;
4178
4179         if (!bitmap)
4180                 return;
4181
4182         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4183         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4184
4185         WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data);
4186 }
4187
4188 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id)
4189 {
4190         u32 data, mask;
4191
4192         data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);
4193         data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG);
4194
4195         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4196         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4197
4198         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4199
4200         return (~data) & mask;
4201 }
4202
4203 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,
4204                                  struct amdgpu_cu_info *cu_info)
4205 {
4206         int i, j, k, counter, xcc_id, active_cu_number = 0;
4207         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4208         unsigned disable_masks[4 * 4];
4209
4210         if (!adev || !cu_info)
4211                 return -EINVAL;
4212
4213         /*
4214          * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs
4215          */
4216         if (adev->gfx.config.max_shader_engines *
4217                 adev->gfx.config.max_sh_per_se > 16)
4218                 return -EINVAL;
4219
4220         amdgpu_gfx_parse_disable_cu(disable_masks,
4221                                     adev->gfx.config.max_shader_engines,
4222                                     adev->gfx.config.max_sh_per_se);
4223
4224         mutex_lock(&adev->grbm_idx_mutex);
4225         for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
4226                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4227                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4228                                 mask = 1;
4229                                 ao_bitmap = 0;
4230                                 counter = 0;
4231                                 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id);
4232                                 gfx_v9_4_3_set_user_cu_inactive_bitmap(
4233                                         adev,
4234                                         disable_masks[i * adev->gfx.config.max_sh_per_se + j],
4235                                         xcc_id);
4236                                 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id);
4237
4238                                 cu_info->bitmap[xcc_id][i][j] = bitmap;
4239
4240                                 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4241                                         if (bitmap & mask) {
4242                                                 if (counter < adev->gfx.config.max_cu_per_sh)
4243                                                         ao_bitmap |= mask;
4244                                                 counter++;
4245                                         }
4246                                         mask <<= 1;
4247                                 }
4248                                 active_cu_number += counter;
4249                                 if (i < 2 && j < 2)
4250                                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4251                                 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4252                         }
4253                 }
4254                 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,
4255                                             xcc_id);
4256         }
4257         mutex_unlock(&adev->grbm_idx_mutex);
4258
4259         cu_info->number = active_cu_number;
4260         cu_info->ao_cu_mask = ao_cu_mask;
4261         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4262
4263         return 0;
4264 }
4265
4266 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = {
4267         .type = AMD_IP_BLOCK_TYPE_GFX,
4268         .major = 9,
4269         .minor = 4,
4270         .rev = 3,
4271         .funcs = &gfx_v9_4_3_ip_funcs,
4272 };
4273
4274 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask)
4275 {
4276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4277         uint32_t tmp_mask;
4278         int i, r;
4279
4280         /* TODO : Initialize golden regs */
4281         /* gfx_v9_4_3_init_golden_registers(adev); */
4282
4283         tmp_mask = inst_mask;
4284         for_each_inst(i, tmp_mask)
4285                 gfx_v9_4_3_xcc_constants_init(adev, i);
4286
4287         if (!amdgpu_sriov_vf(adev)) {
4288                 tmp_mask = inst_mask;
4289                 for_each_inst(i, tmp_mask) {
4290                         r = gfx_v9_4_3_xcc_rlc_resume(adev, i);
4291                         if (r)
4292                                 return r;
4293                 }
4294         }
4295
4296         tmp_mask = inst_mask;
4297         for_each_inst(i, tmp_mask) {
4298                 r = gfx_v9_4_3_xcc_cp_resume(adev, i);
4299                 if (r)
4300                         return r;
4301         }
4302
4303         return 0;
4304 }
4305
4306 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask)
4307 {
4308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4309         int i;
4310
4311         for_each_inst(i, inst_mask)
4312                 gfx_v9_4_3_xcc_fini(adev, i);
4313
4314         return 0;
4315 }
4316
4317 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = {
4318         .suspend = &gfx_v9_4_3_xcp_suspend,
4319         .resume = &gfx_v9_4_3_xcp_resume
4320 };
4321
4322 struct amdgpu_ras_block_hw_ops  gfx_v9_4_3_ras_ops = {
4323         .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count,
4324         .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
4325 };
4326
4327 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
4328 {
4329         int r;
4330
4331         r = amdgpu_ras_block_late_init(adev, ras_block);
4332         if (r)
4333                 return r;
4334
4335         r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX,
4336                                 &gfx_v9_4_3_aca_info,
4337                                 NULL);
4338         if (r)
4339                 goto late_fini;
4340
4341         return 0;
4342
4343 late_fini:
4344         amdgpu_ras_block_late_fini(adev, ras_block);
4345
4346         return r;
4347 }
4348
4349 struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
4350         .ras_block = {
4351                 .hw_ops = &gfx_v9_4_3_ras_ops,
4352                 .ras_late_init = &gfx_v9_4_3_ras_late_init,
4353         },
4354         .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer,
4355 };