2 * Copyright 2015 Advanced Micro Devices, Inc.
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11 * the following conditions:
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21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
33 #include "amdgpu_trace.h"
35 static int amdgpu_bo_list_create(struct amdgpu_fpriv *fpriv,
36 struct amdgpu_bo_list **result,
41 *result = kzalloc(sizeof(struct amdgpu_bo_list), GFP_KERNEL);
45 mutex_lock(&fpriv->bo_list_lock);
46 r = idr_alloc(&fpriv->bo_list_handles, *result,
49 mutex_unlock(&fpriv->bo_list_lock);
55 mutex_init(&(*result)->lock);
56 (*result)->num_entries = 0;
57 (*result)->array = NULL;
59 mutex_lock(&(*result)->lock);
60 mutex_unlock(&fpriv->bo_list_lock);
65 static void amdgpu_bo_list_destroy(struct amdgpu_fpriv *fpriv, int id)
67 struct amdgpu_bo_list *list;
69 mutex_lock(&fpriv->bo_list_lock);
70 list = idr_find(&fpriv->bo_list_handles, id);
72 mutex_lock(&list->lock);
73 idr_remove(&fpriv->bo_list_handles, id);
74 mutex_unlock(&list->lock);
75 amdgpu_bo_list_free(list);
77 mutex_unlock(&fpriv->bo_list_lock);
80 static int amdgpu_bo_list_set(struct amdgpu_device *adev,
81 struct drm_file *filp,
82 struct amdgpu_bo_list *list,
83 struct drm_amdgpu_bo_list_entry *info,
86 struct amdgpu_bo_list_entry *array;
87 struct amdgpu_bo *gds_obj = adev->gds.gds_gfx_bo;
88 struct amdgpu_bo *gws_obj = adev->gds.gws_gfx_bo;
89 struct amdgpu_bo *oa_obj = adev->gds.oa_gfx_bo;
91 bool has_userptr = false;
94 array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry));
97 memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry));
99 for (i = 0; i < num_entries; ++i) {
100 struct amdgpu_bo_list_entry *entry = &array[i];
101 struct drm_gem_object *gobj;
103 gobj = drm_gem_object_lookup(adev->ddev, filp, info[i].bo_handle);
107 entry->robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
108 drm_gem_object_unreference_unlocked(gobj);
109 entry->priority = info[i].bo_priority;
110 entry->prefered_domains = entry->robj->initial_domain;
111 entry->allowed_domains = entry->prefered_domains;
112 if (entry->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
113 entry->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
114 if (amdgpu_ttm_tt_has_userptr(entry->robj->tbo.ttm)) {
116 entry->prefered_domains = AMDGPU_GEM_DOMAIN_GTT;
117 entry->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
119 entry->tv.bo = &entry->robj->tbo;
120 entry->tv.shared = true;
122 if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GDS)
123 gds_obj = entry->robj;
124 if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_GWS)
125 gws_obj = entry->robj;
126 if (entry->prefered_domains == AMDGPU_GEM_DOMAIN_OA)
127 oa_obj = entry->robj;
129 trace_amdgpu_bo_list_set(list, entry->robj);
132 for (i = 0; i < list->num_entries; ++i)
133 amdgpu_bo_unref(&list->array[i].robj);
135 drm_free_large(list->array);
137 list->gds_obj = gds_obj;
138 list->gws_obj = gws_obj;
139 list->oa_obj = oa_obj;
140 list->has_userptr = has_userptr;
142 list->num_entries = num_entries;
147 drm_free_large(array);
151 struct amdgpu_bo_list *
152 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id)
154 struct amdgpu_bo_list *result;
156 mutex_lock(&fpriv->bo_list_lock);
157 result = idr_find(&fpriv->bo_list_handles, id);
159 mutex_lock(&result->lock);
160 mutex_unlock(&fpriv->bo_list_lock);
164 void amdgpu_bo_list_put(struct amdgpu_bo_list *list)
166 mutex_unlock(&list->lock);
169 void amdgpu_bo_list_free(struct amdgpu_bo_list *list)
173 for (i = 0; i < list->num_entries; ++i)
174 amdgpu_bo_unref(&list->array[i].robj);
176 mutex_destroy(&list->lock);
177 drm_free_large(list->array);
181 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
182 struct drm_file *filp)
184 const uint32_t info_size = sizeof(struct drm_amdgpu_bo_list_entry);
186 struct amdgpu_device *adev = dev->dev_private;
187 struct amdgpu_fpriv *fpriv = filp->driver_priv;
188 union drm_amdgpu_bo_list *args = data;
189 uint32_t handle = args->in.list_handle;
190 const void __user *uptr = (const void*)(long)args->in.bo_info_ptr;
192 struct drm_amdgpu_bo_list_entry *info;
193 struct amdgpu_bo_list *list;
197 info = drm_malloc_ab(args->in.bo_number,
198 sizeof(struct drm_amdgpu_bo_list_entry));
202 /* copy the handle array from userspace to a kernel buffer */
204 if (likely(info_size == args->in.bo_info_size)) {
205 unsigned long bytes = args->in.bo_number *
206 args->in.bo_info_size;
208 if (copy_from_user(info, uptr, bytes))
212 unsigned long bytes = min(args->in.bo_info_size, info_size);
215 memset(info, 0, args->in.bo_number * info_size);
216 for (i = 0; i < args->in.bo_number; ++i) {
217 if (copy_from_user(&info[i], uptr, bytes))
220 uptr += args->in.bo_info_size;
224 switch (args->in.operation) {
225 case AMDGPU_BO_LIST_OP_CREATE:
226 r = amdgpu_bo_list_create(fpriv, &list, &handle);
230 r = amdgpu_bo_list_set(adev, filp, list, info,
232 amdgpu_bo_list_put(list);
238 case AMDGPU_BO_LIST_OP_DESTROY:
239 amdgpu_bo_list_destroy(fpriv, handle);
243 case AMDGPU_BO_LIST_OP_UPDATE:
245 list = amdgpu_bo_list_get(fpriv, handle);
249 r = amdgpu_bo_list_set(adev, filp, list, info,
251 amdgpu_bo_list_put(list);
262 memset(args, 0, sizeof(*args));
263 args->out.list_handle = handle;
264 drm_free_large(info);
269 drm_free_large(info);