Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: MediaTek mmsys controller
   8
   9 maintainers:
  10   - Matthias Brugger <[email protected]>
  11
  12 description:
  13   The MediaTek mmsys system controller provides clock control, routing control,
  14   and miscellaneous control in mmsys partition.
  15
  16 properties:
  17   $nodename:
  18     pattern: "^syscon@[0-9a-f]+$"
  19
  20   compatible:
  21     oneOf:
  22       - items:
  23           - enum:
  24               - mediatek,mt2701-mmsys
  25               - mediatek,mt2712-mmsys
  26               - mediatek,mt6765-mmsys
  27               - mediatek,mt6779-mmsys
  28               - mediatek,mt6797-mmsys
  29               - mediatek,mt8167-mmsys
  30               - mediatek,mt8173-mmsys
  31               - mediatek,mt8183-mmsys
  32               - mediatek,mt8186-mmsys
  33               - mediatek,mt8192-mmsys
  34               - mediatek,mt8365-mmsys
  35           - const: syscon
  36       - items:
  37           - const: mediatek,mt7623-mmsys
  38           - const: mediatek,mt2701-mmsys
  39           - const: syscon
  40
  41   reg:
  42     maxItems: 1
  43
  44   power-domains:
  45     description:
  46       A phandle and PM domain specifier as defined by bindings
  47       of the power controller specified by phandle. See
  48       Documentation/devicetree/bindings/power/power-domain.yaml for details.
  49
  50   mboxes:
  51     description:
  52       Using mailbox to communicate with GCE, it should have this
  53       property and list of phandle, mailbox specifiers. See
  54       Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
  55     $ref: /schemas/types.yaml#/definitions/phandle-array
  56
  57   mediatek,gce-client-reg:
  58     description:
  59       The register of client driver can be configured by gce with 4 arguments
  60       defined in this property, such as phandle of gce, subsys id,
  61       register offset and size.
  62       Each subsys id is mapping to a base address of display function blocks
  63       register which is defined in the gce header
  64       include/dt-bindings/gce/<chip>-gce.h.
  65     $ref: /schemas/types.yaml#/definitions/phandle-array
  66     maxItems: 1
  67
  68   "#clock-cells":
  69     const: 1
  70
  71   '#reset-cells':
  72     const: 1
  73
  74 required:
  75   - compatible
  76   - reg
  77   - "#clock-cells"
  78
  79 additionalProperties: false
  80
  81 examples:
  82   - |
  83     #include <dt-bindings/power/mt8173-power.h>
  84     #include <dt-bindings/gce/mt8173-gce.h>
  85
  86     mmsys: syscon@14000000 {
  87         compatible = "mediatek,mt8173-mmsys", "syscon";
  88         reg = <0x14000000 0x1000>;
  89         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
  90         #clock-cells = <1>;
  91         #reset-cells = <1>;
  92         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
  93                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
  94         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
  95     };