drivers/spi/spi-bcm63xx.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009-2012 Florian Fainelli <[email protected]>
   5  * Copyright (C) 2010 Tanguy Bouzeloc <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the
  19  * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/delay.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/completion.h>
  32 #include <linux/err.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <bcm63xx_dev_spi.h>
  37
  38 #define PFX             KBUILD_MODNAME
  39 #define DRV_VER         "0.1.2"
  40
  41 struct bcm63xx_spi {
  42         struct completion       done;
  43
  44         void __iomem            *regs;
  45         int                     irq;
  46
  47         /* Platform data */
  48         u32                     speed_hz;
  49         unsigned                fifo_size;
  50
  51         /* Data buffers */
  52         const unsigned char     *tx_ptr;
  53         unsigned char           *rx_ptr;
  54
  55         /* data iomem */
  56         u8 __iomem              *tx_io;
  57         const u8 __iomem        *rx_io;
  58
  59         int                     remaining_bytes;
  60
  61         struct clk              *clk;
  62         struct platform_device  *pdev;
  63 };
  64
  65 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
  66                                 unsigned int offset)
  67 {
  68         return bcm_readb(bs->regs + bcm63xx_spireg(offset));
  69 }
  70
  71 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
  72                                 unsigned int offset)
  73 {
  74         return bcm_readw(bs->regs + bcm63xx_spireg(offset));
  75 }
  76
  77 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
  78                                   u8 value, unsigned int offset)
  79 {
  80         bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
  81 }
  82
  83 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
  84                                   u16 value, unsigned int offset)
  85 {
  86         bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
  87 }
  88
  89 static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
  90         { 20000000, SPI_CLK_20MHZ },
  91         { 12500000, SPI_CLK_12_50MHZ },
  92         {  6250000, SPI_CLK_6_250MHZ },
  93         {  3125000, SPI_CLK_3_125MHZ },
  94         {  1563000, SPI_CLK_1_563MHZ },
  95         {   781000, SPI_CLK_0_781MHZ },
  96         {   391000, SPI_CLK_0_391MHZ }
  97 };
  98
  99 static int bcm63xx_spi_check_transfer(struct spi_device *spi,
 100                                         struct spi_transfer *t)
 101 {
 102         u8 bits_per_word;
 103
 104         bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 105         if (bits_per_word != 8) {
 106                 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
 107                         __func__, bits_per_word);
 108                 return -EINVAL;
 109         }
 110
 111         if (spi->chip_select > spi->master->num_chipselect) {
 112                 dev_err(&spi->dev, "%s, unsupported slave %d\n",
 113                         __func__, spi->chip_select);
 114                 return -EINVAL;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
 121                                       struct spi_transfer *t)
 122 {
 123         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 124         u32 hz;
 125         u8 clk_cfg, reg;
 126         int i;
 127
 128         hz = (t) ? t->speed_hz : spi->max_speed_hz;
 129
 130         /* Find the closest clock configuration */
 131         for (i = 0; i < SPI_CLK_MASK; i++) {
 132                 if (hz <= bcm63xx_spi_freq_table[i][0]) {
 133                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 134                         break;
 135                 }
 136         }
 137
 138         /* No matching configuration found, default to lowest */
 139         if (i == SPI_CLK_MASK)
 140                 clk_cfg = SPI_CLK_0_391MHZ;
 141
 142         /* clear existing clock configuration bits of the register */
 143         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 144         reg &= ~SPI_CLK_MASK;
 145         reg |= clk_cfg;
 146
 147         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 148         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 149                 clk_cfg, hz);
 150 }
 151
 152 /* the spi->mode bits understood by this driver: */
 153 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 154
 155 static int bcm63xx_spi_setup(struct spi_device *spi)
 156 {
 157         struct bcm63xx_spi *bs;
 158         int ret;
 159
 160         bs = spi_master_get_devdata(spi->master);
 161
 162         if (!spi->bits_per_word)
 163                 spi->bits_per_word = 8;
 164
 165         if (spi->mode & ~MODEBITS) {
 166                 dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
 167                         __func__, spi->mode & ~MODEBITS);
 168                 return -EINVAL;
 169         }
 170
 171         ret = bcm63xx_spi_check_transfer(spi, NULL);
 172         if (ret < 0) {
 173                 dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
 174                         spi->mode & ~MODEBITS);
 175                 return ret;
 176         }
 177
 178         dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
 179                 __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
 180
 181         return 0;
 182 }
 183
 184 /* Fill the TX FIFO with as many bytes as possible */
 185 static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
 186 {
 187         u8 size;
 188
 189         /* Fill the Tx FIFO with as many bytes as possible */
 190         size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
 191                 bs->fifo_size;
 192         memcpy_toio(bs->tx_io, bs->tx_ptr, size);
 193         bs->remaining_bytes -= size;
 194 }
 195
 196 static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,
 197                                         struct spi_transfer *t)
 198 {
 199         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 200         u16 msg_ctl;
 201         u16 cmd;
 202
 203         /* Disable the CMD_DONE interrupt */
 204         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 205
 206         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 207                 t->tx_buf, t->rx_buf, t->len);
 208
 209         /* Transmitter is inhibited */
 210         bs->tx_ptr = t->tx_buf;
 211         bs->rx_ptr = t->rx_buf;
 212
 213         if (t->tx_buf) {
 214                 bs->remaining_bytes = t->len;
 215                 bcm63xx_spi_fill_tx_fifo(bs);
 216         }
 217
 218         init_completion(&bs->done);
 219
 220         /* Fill in the Message control register */
 221         msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
 222
 223         if (t->rx_buf && t->tx_buf)
 224                 msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
 225         else if (t->rx_buf)
 226                 msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
 227         else if (t->tx_buf)
 228                 msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
 229
 230         bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 231
 232         /* Issue the transfer */
 233         cmd = SPI_CMD_START_IMMEDIATE;
 234         cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 235         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 236         bcm_spi_writew(bs, cmd, SPI_CMD);
 237
 238         /* Enable the CMD_DONE interrupt */
 239         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 240
 241         return t->len - bs->remaining_bytes;
 242 }
 243
 244 static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
 245 {
 246         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 247
 248         pm_runtime_get_sync(&bs->pdev->dev);
 249
 250         return 0;
 251 }
 252
 253 static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
 254 {
 255         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 256
 257         pm_runtime_put(&bs->pdev->dev);
 258
 259         return 0;
 260 }
 261
 262 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 263                                         struct spi_message *m)
 264 {
 265         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 266         struct spi_transfer *t;
 267         struct spi_device *spi = m->spi;
 268         int status = 0;
 269         unsigned int timeout = 0;
 270
 271         list_for_each_entry(t, &m->transfers, transfer_list) {
 272                 unsigned int len = t->len;
 273                 u8 rx_tail;
 274
 275                 status = bcm63xx_spi_check_transfer(spi, t);
 276                 if (status < 0)
 277                         goto exit;
 278
 279                 /* configure adapter for a new transfer */
 280                 bcm63xx_spi_setup_transfer(spi, t);
 281
 282                 while (len) {
 283                         /* send the data */
 284                         len -= bcm63xx_txrx_bufs(spi, t);
 285
 286                         timeout = wait_for_completion_timeout(&bs->done, HZ);
 287                         if (!timeout) {
 288                                 status = -ETIMEDOUT;
 289                                 goto exit;
 290                         }
 291
 292                         /* read out all data */
 293                         rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
 294
 295                         /* Read out all the data */
 296                         if (rx_tail)
 297                                 memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
 298                 }
 299
 300                 m->actual_length += t->len;
 301         }
 302 exit:
 303         m->status = status;
 304         spi_finalize_current_message(master);
 305
 306         return 0;
 307 }
 308
 309 /* This driver supports single master mode only. Hence
 310  * CMD_DONE is the only interrupt we care about
 311  */
 312 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 313 {
 314         struct spi_master *master = (struct spi_master *)dev_id;
 315         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 316         u8 intr;
 317
 318         /* Read interupts and clear them immediately */
 319         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 320         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 321         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 322
 323         /* A transfer completed */
 324         if (intr & SPI_INTR_CMD_DONE)
 325                 complete(&bs->done);
 326
 327         return IRQ_HANDLED;
 328 }
 329
 330
 331 static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
 332 {
 333         struct resource *r;
 334         struct device *dev = &pdev->dev;
 335         struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
 336         int irq;
 337         struct spi_master *master;
 338         struct clk *clk;
 339         struct bcm63xx_spi *bs;
 340         int ret;
 341
 342         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 343         if (!r) {
 344                 dev_err(dev, "no iomem\n");
 345                 ret = -ENXIO;
 346                 goto out;
 347         }
 348
 349         irq = platform_get_irq(pdev, 0);
 350         if (irq < 0) {
 351                 dev_err(dev, "no irq\n");
 352                 ret = -ENXIO;
 353                 goto out;
 354         }
 355
 356         clk = clk_get(dev, "spi");
 357         if (IS_ERR(clk)) {
 358                 dev_err(dev, "no clock for device\n");
 359                 ret = PTR_ERR(clk);
 360                 goto out;
 361         }
 362
 363         master = spi_alloc_master(dev, sizeof(*bs));
 364         if (!master) {
 365                 dev_err(dev, "out of memory\n");
 366                 ret = -ENOMEM;
 367                 goto out_clk;
 368         }
 369
 370         bs = spi_master_get_devdata(master);
 371
 372         platform_set_drvdata(pdev, master);
 373         bs->pdev = pdev;
 374
 375         if (!devm_request_mem_region(&pdev->dev, r->start,
 376                                         resource_size(r), PFX)) {
 377                 dev_err(dev, "iomem request failed\n");
 378                 ret = -ENXIO;
 379                 goto out_err;
 380         }
 381
 382         bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
 383                                                         resource_size(r));
 384         if (!bs->regs) {
 385                 dev_err(dev, "unable to ioremap regs\n");
 386                 ret = -ENOMEM;
 387                 goto out_err;
 388         }
 389
 390         bs->irq = irq;
 391         bs->clk = clk;
 392         bs->fifo_size = pdata->fifo_size;
 393
 394         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 395                                                         pdev->name, master);
 396         if (ret) {
 397                 dev_err(dev, "unable to request irq\n");
 398                 goto out_err;
 399         }
 400
 401         master->bus_num = pdata->bus_num;
 402         master->num_chipselect = pdata->num_chipselect;
 403         master->setup = bcm63xx_spi_setup;
 404         master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
 405         master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
 406         master->transfer_one_message = bcm63xx_spi_transfer_one;
 407         master->mode_bits = MODEBITS;
 408         bs->speed_hz = pdata->speed_hz;
 409         bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
 410         bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
 411
 412         /* Initialize hardware */
 413         clk_enable(bs->clk);
 414         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 415
 416         /* register and we are done */
 417         ret = spi_register_master(master);
 418         if (ret) {
 419                 dev_err(dev, "spi register failed\n");
 420                 goto out_clk_disable;
 421         }
 422
 423         dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
 424                  r->start, irq, bs->fifo_size, DRV_VER);
 425
 426         return 0;
 427
 428 out_clk_disable:
 429         clk_disable(clk);
 430 out_err:
 431         platform_set_drvdata(pdev, NULL);
 432         spi_master_put(master);
 433 out_clk:
 434         clk_put(clk);
 435 out:
 436         return ret;
 437 }
 438
 439 static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
 440 {
 441         struct spi_master *master = platform_get_drvdata(pdev);
 442         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 443
 444         spi_unregister_master(master);
 445
 446         /* reset spi block */
 447         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 448
 449         /* HW shutdown */
 450         clk_disable(bs->clk);
 451         clk_put(bs->clk);
 452
 453         platform_set_drvdata(pdev, 0);
 454
 455         return 0;
 456 }
 457
 458 #ifdef CONFIG_PM
 459 static int bcm63xx_spi_suspend(struct device *dev)
 460 {
 461         struct spi_master *master =
 462                         platform_get_drvdata(to_platform_device(dev));
 463         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 464
 465         clk_disable(bs->clk);
 466
 467         return 0;
 468 }
 469
 470 static int bcm63xx_spi_resume(struct device *dev)
 471 {
 472         struct spi_master *master =
 473                         platform_get_drvdata(to_platform_device(dev));
 474         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 475
 476         clk_enable(bs->clk);
 477
 478         return 0;
 479 }
 480
 481 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 482         .suspend        = bcm63xx_spi_suspend,
 483         .resume         = bcm63xx_spi_resume,
 484 };
 485
 486 #define BCM63XX_SPI_PM_OPS      (&bcm63xx_spi_pm_ops)
 487 #else
 488 #define BCM63XX_SPI_PM_OPS      NULL
 489 #endif
 490
 491 static struct platform_driver bcm63xx_spi_driver = {
 492         .driver = {
 493                 .name   = "bcm63xx-spi",
 494                 .owner  = THIS_MODULE,
 495                 .pm     = BCM63XX_SPI_PM_OPS,
 496         },
 497         .probe          = bcm63xx_spi_probe,
 498         .remove         = __devexit_p(bcm63xx_spi_remove),
 499 };
 500
 501 module_platform_driver(bcm63xx_spi_driver);
 502
 503 MODULE_ALIAS("platform:bcm63xx_spi");
 504 MODULE_AUTHOR("Florian Fainelli <[email protected]>");
 505 MODULE_AUTHOR("Tanguy Bouzeloc <[email protected]>");
 506 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 507 MODULE_LICENSE("GPL");