2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/dma-fence-array.h>
29 #include <linux/interval_tree_generic.h>
30 #include <linux/idr.h>
32 #include <drm/amdgpu_drm.h>
34 #include "amdgpu_trace.h"
35 #include "amdgpu_amdkfd.h"
36 #include "amdgpu_gmc.h"
41 * GPUVM is similar to the legacy gart on older asics, however
42 * rather than there being a single global gart table
43 * for the entire GPU, there are multiple VM page tables active
44 * at any given time. The VM page tables can contain a mix
45 * vram pages and system memory pages and system memory pages
46 * can be mapped as snooped (cached system pages) or unsnooped
47 * (uncached system pages).
48 * Each VM has an ID associated with it and there is a page table
49 * associated with each VMID. When execting a command buffer,
50 * the kernel tells the the ring what VMID to use for that command
51 * buffer. VMIDs are allocated dynamically as commands are submitted.
52 * The userspace drivers maintain their own address space and the kernel
53 * sets up their pages tables accordingly when they submit their
54 * command buffers and a VMID is assigned.
55 * Cayman/Trinity support up to 8 active VMs at any given time;
59 #define START(node) ((node)->start)
60 #define LAST(node) ((node)->last)
62 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
63 START, LAST, static, amdgpu_vm_it)
69 * struct amdgpu_pte_update_params - Local structure
71 * Encapsulate some VM table update parameters to reduce
72 * the number of function parameters
75 struct amdgpu_pte_update_params {
78 * @adev: amdgpu device we do this update for
80 struct amdgpu_device *adev;
83 * @vm: optional amdgpu_vm we do this update for
88 * @src: address where to copy page table entries from
93 * @ib: indirect buffer to fill with commands
98 * @func: Function which actually does the update
100 void (*func)(struct amdgpu_pte_update_params *params,
101 struct amdgpu_bo *bo, uint64_t pe,
102 uint64_t addr, unsigned count, uint32_t incr,
107 * DMA addresses to use for mapping, used during VM update by CPU
109 dma_addr_t *pages_addr;
114 * Kernel pointer of PD/PT BO that needs to be updated,
115 * used during VM update by CPU
121 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
123 struct amdgpu_prt_cb {
126 * @adev: amdgpu device
128 struct amdgpu_device *adev;
133 struct dma_fence_cb cb;
137 * amdgpu_vm_level_shift - return the addr shift for each level
139 * @adev: amdgpu_device pointer
143 * The number of bits the pfn needs to be right shifted for a level.
145 static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
148 unsigned shift = 0xff;
154 shift = 9 * (AMDGPU_VM_PDB0 - level) +
155 adev->vm_manager.block_size;
161 dev_err(adev->dev, "the level%d isn't supported.\n", level);
168 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
170 * @adev: amdgpu_device pointer
174 * The number of entries in a page directory or page table.
176 static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
179 unsigned shift = amdgpu_vm_level_shift(adev,
180 adev->vm_manager.root_level);
182 if (level == adev->vm_manager.root_level)
183 /* For the root directory */
184 return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
185 else if (level != AMDGPU_VM_PTB)
186 /* Everything in between */
189 /* For the page tables on the leaves */
190 return AMDGPU_VM_PTE_COUNT(adev);
194 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
196 * @adev: amdgpu_device pointer
200 * The size of the BO for a page directory or page table in bytes.
202 static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
204 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
208 * amdgpu_vm_bo_evicted - vm_bo is evicted
210 * @vm_bo: vm_bo which is evicted
212 * State for PDs/PTs and per VM BOs which are not at the location they should
215 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
217 struct amdgpu_vm *vm = vm_bo->vm;
218 struct amdgpu_bo *bo = vm_bo->bo;
221 if (bo->tbo.type == ttm_bo_type_kernel)
222 list_move(&vm_bo->vm_status, &vm->evicted);
224 list_move_tail(&vm_bo->vm_status, &vm->evicted);
228 * amdgpu_vm_bo_relocated - vm_bo is reloacted
230 * @vm_bo: vm_bo which is relocated
232 * State for PDs/PTs which needs to update their parent PD.
234 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
236 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
240 * amdgpu_vm_bo_moved - vm_bo is moved
242 * @vm_bo: vm_bo which is moved
244 * State for per VM BOs which are moved, but that change is not yet reflected
245 * in the page tables.
247 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
249 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
253 * amdgpu_vm_bo_idle - vm_bo is idle
255 * @vm_bo: vm_bo which is now idle
257 * State for PDs/PTs and per VM BOs which have gone through the state machine
260 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
262 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
263 vm_bo->moved = false;
267 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
269 * @vm_bo: vm_bo which is now invalidated
271 * State for normal BOs which are invalidated and that change not yet reflected
274 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
276 spin_lock(&vm_bo->vm->invalidated_lock);
277 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
278 spin_unlock(&vm_bo->vm->invalidated_lock);
282 * amdgpu_vm_bo_done - vm_bo is done
284 * @vm_bo: vm_bo which is now done
286 * State for normal BOs which are invalidated and that change has been updated
289 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
291 spin_lock(&vm_bo->vm->invalidated_lock);
292 list_del_init(&vm_bo->vm_status);
293 spin_unlock(&vm_bo->vm->invalidated_lock);
297 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
299 * @base: base structure for tracking BO usage in a VM
300 * @vm: vm to which bo is to be added
301 * @bo: amdgpu buffer object
303 * Initialize a bo_va_base structure and add it to the appropriate lists
306 static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
307 struct amdgpu_vm *vm,
308 struct amdgpu_bo *bo)
312 INIT_LIST_HEAD(&base->bo_list);
313 INIT_LIST_HEAD(&base->vm_status);
317 list_add_tail(&base->bo_list, &bo->va);
319 if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
322 vm->bulk_moveable = false;
323 if (bo->tbo.type == ttm_bo_type_kernel)
324 amdgpu_vm_bo_relocated(base);
326 amdgpu_vm_bo_idle(base);
328 if (bo->preferred_domains &
329 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
333 * we checked all the prerequisites, but it looks like this per vm bo
334 * is currently evicted. add the bo to the evicted list to make sure it
335 * is validated on next vm use to avoid fault.
337 amdgpu_vm_bo_evicted(base);
341 * amdgpu_vm_pt_parent - get the parent page directory
343 * @pt: child page table
345 * Helper to get the parent entry for the child page table. NULL if we are at
346 * the root page directory.
348 static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
350 struct amdgpu_bo *parent = pt->base.bo->parent;
355 return list_first_entry(&parent->va, struct amdgpu_vm_pt, base.bo_list);
359 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
361 * @vm: vm providing the BOs
362 * @validated: head of validation list
363 * @entry: entry to add
365 * Add the page directory to the list of BOs to
366 * validate for command submission.
368 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
369 struct list_head *validated,
370 struct amdgpu_bo_list_entry *entry)
372 entry->robj = vm->root.base.bo;
374 entry->tv.bo = &entry->robj->tbo;
375 entry->tv.shared = true;
376 entry->user_pages = NULL;
377 list_add(&entry->tv.head, validated);
381 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
383 * @adev: amdgpu device pointer
384 * @vm: vm providing the BOs
386 * Move all BOs to the end of LRU and remember their positions to put them
389 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
390 struct amdgpu_vm *vm)
392 struct ttm_bo_global *glob = adev->mman.bdev.glob;
393 struct amdgpu_vm_bo_base *bo_base;
395 if (vm->bulk_moveable) {
396 spin_lock(&glob->lru_lock);
397 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
398 spin_unlock(&glob->lru_lock);
402 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
404 spin_lock(&glob->lru_lock);
405 list_for_each_entry(bo_base, &vm->idle, vm_status) {
406 struct amdgpu_bo *bo = bo_base->bo;
411 ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
413 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
416 spin_unlock(&glob->lru_lock);
418 vm->bulk_moveable = true;
422 * amdgpu_vm_validate_pt_bos - validate the page table BOs
424 * @adev: amdgpu device pointer
425 * @vm: vm providing the BOs
426 * @validate: callback to do the validation
427 * @param: parameter for the validation callback
429 * Validate the page table BOs on command submission if neccessary.
434 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
435 int (*validate)(void *p, struct amdgpu_bo *bo),
438 struct amdgpu_vm_bo_base *bo_base, *tmp;
441 vm->bulk_moveable &= list_empty(&vm->evicted);
443 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
444 struct amdgpu_bo *bo = bo_base->bo;
446 r = validate(param, bo);
450 if (bo->tbo.type != ttm_bo_type_kernel) {
451 amdgpu_vm_bo_moved(bo_base);
453 if (vm->use_cpu_for_update)
454 r = amdgpu_bo_kmap(bo, NULL);
456 r = amdgpu_ttm_alloc_gart(&bo->tbo);
460 r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
464 amdgpu_vm_bo_relocated(bo_base);
472 * amdgpu_vm_ready - check VM is ready for updates
476 * Check if all VM PDs/PTs are ready for updates
479 * True if eviction list is empty.
481 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
483 return list_empty(&vm->evicted);
487 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
489 * @adev: amdgpu_device pointer
490 * @vm: VM to clear BO from
492 * @level: level this BO is at
493 * @pte_support_ats: indicate ATS support from PTE
495 * Root PD needs to be reserved when calling this.
498 * 0 on success, errno otherwise.
500 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
501 struct amdgpu_vm *vm, struct amdgpu_bo *bo,
502 unsigned level, bool pte_support_ats)
504 struct ttm_operation_ctx ctx = { true, false };
505 struct dma_fence *fence = NULL;
506 unsigned entries, ats_entries;
507 struct amdgpu_ring *ring;
508 struct amdgpu_job *job;
512 entries = amdgpu_bo_size(bo) / 8;
514 if (pte_support_ats) {
515 if (level == adev->vm_manager.root_level) {
516 ats_entries = amdgpu_vm_level_shift(adev, level);
517 ats_entries += AMDGPU_GPU_PAGE_SHIFT;
518 ats_entries = AMDGPU_GMC_HOLE_START >> ats_entries;
519 ats_entries = min(ats_entries, entries);
520 entries -= ats_entries;
522 ats_entries = entries;
529 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
531 r = reservation_object_reserve_shared(bo->tbo.resv);
535 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
539 r = amdgpu_ttm_alloc_gart(&bo->tbo);
543 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
547 addr = amdgpu_bo_gpu_offset(bo);
551 ats_value = AMDGPU_PTE_DEFAULT_ATC;
552 if (level != AMDGPU_VM_PTB)
553 ats_value |= AMDGPU_PDE_PTE;
555 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
556 ats_entries, 0, ats_value);
557 addr += ats_entries * 8;
561 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
564 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
566 WARN_ON(job->ibs[0].length_dw > 64);
567 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
568 AMDGPU_FENCE_OWNER_UNDEFINED, false);
572 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_UNDEFINED,
577 amdgpu_bo_fence(bo, fence, true);
578 dma_fence_put(fence);
581 return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
582 level, pte_support_ats);
587 amdgpu_job_free(job);
594 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
596 * @adev: amdgpu_device pointer
598 * @bp: resulting BO allocation parameters
600 static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
601 int level, struct amdgpu_bo_param *bp)
603 memset(bp, 0, sizeof(*bp));
605 bp->size = amdgpu_vm_bo_size(adev, level);
606 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
607 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
608 if (bp->size <= PAGE_SIZE && adev->asic_type >= CHIP_VEGA10 &&
609 adev->flags & AMD_IS_APU)
610 bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
611 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
612 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
613 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
614 if (vm->use_cpu_for_update)
615 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
616 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
617 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
618 bp->type = ttm_bo_type_kernel;
619 if (vm->root.base.bo)
620 bp->resv = vm->root.base.bo->tbo.resv;
624 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
626 * @adev: amdgpu_device pointer
629 * @saddr: start of the address range
630 * @eaddr: end of the address range
632 * @ats: indicate ATS support from PTE
634 * Make sure the page directories and page tables are allocated
637 * 0 on success, errno otherwise.
639 static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
640 struct amdgpu_vm *vm,
641 struct amdgpu_vm_pt *parent,
642 uint64_t saddr, uint64_t eaddr,
643 unsigned level, bool ats)
645 unsigned shift = amdgpu_vm_level_shift(adev, level);
646 struct amdgpu_bo_param bp;
647 unsigned pt_idx, from, to;
650 if (!parent->entries) {
651 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
653 parent->entries = kvmalloc_array(num_entries,
654 sizeof(struct amdgpu_vm_pt),
655 GFP_KERNEL | __GFP_ZERO);
656 if (!parent->entries)
660 from = saddr >> shift;
662 if (from >= amdgpu_vm_num_entries(adev, level) ||
663 to >= amdgpu_vm_num_entries(adev, level))
667 saddr = saddr & ((1 << shift) - 1);
668 eaddr = eaddr & ((1 << shift) - 1);
670 amdgpu_vm_bo_param(adev, vm, level, &bp);
672 /* walk over the address space and allocate the page tables */
673 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
674 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
675 struct amdgpu_bo *pt;
677 if (!entry->base.bo) {
678 r = amdgpu_bo_create(adev, &bp, &pt);
682 r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats);
684 amdgpu_bo_unref(&pt->shadow);
685 amdgpu_bo_unref(&pt);
689 if (vm->use_cpu_for_update) {
690 r = amdgpu_bo_kmap(pt, NULL);
692 amdgpu_bo_unref(&pt->shadow);
693 amdgpu_bo_unref(&pt);
698 /* Keep a reference to the root directory to avoid
699 * freeing them up in the wrong order.
701 pt->parent = amdgpu_bo_ref(parent->base.bo);
703 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
706 if (level < AMDGPU_VM_PTB) {
707 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
708 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
710 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
711 sub_eaddr, level, ats);
721 * amdgpu_vm_alloc_pts - Allocate page tables.
723 * @adev: amdgpu_device pointer
724 * @vm: VM to allocate page tables for
725 * @saddr: Start address which needs to be allocated
726 * @size: Size from start address we need.
728 * Make sure the page tables are allocated.
731 * 0 on success, errno otherwise.
733 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
734 struct amdgpu_vm *vm,
735 uint64_t saddr, uint64_t size)
740 /* validate the parameters */
741 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
744 eaddr = saddr + size - 1;
746 if (vm->pte_support_ats)
747 ats = saddr < AMDGPU_GMC_HOLE_START;
749 saddr /= AMDGPU_GPU_PAGE_SIZE;
750 eaddr /= AMDGPU_GPU_PAGE_SIZE;
752 if (eaddr >= adev->vm_manager.max_pfn) {
753 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
754 eaddr, adev->vm_manager.max_pfn);
758 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
759 adev->vm_manager.root_level, ats);
763 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
765 * @adev: amdgpu_device pointer
767 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
769 const struct amdgpu_ip_block *ip_block;
770 bool has_compute_vm_bug;
771 struct amdgpu_ring *ring;
774 has_compute_vm_bug = false;
776 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
778 /* Compute has a VM bug for GFX version < 7.
779 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
780 if (ip_block->version->major <= 7)
781 has_compute_vm_bug = true;
782 else if (ip_block->version->major == 8)
783 if (adev->gfx.mec_fw_version < 673)
784 has_compute_vm_bug = true;
787 for (i = 0; i < adev->num_rings; i++) {
788 ring = adev->rings[i];
789 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
790 /* only compute rings */
791 ring->has_compute_vm_bug = has_compute_vm_bug;
793 ring->has_compute_vm_bug = false;
798 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
800 * @ring: ring on which the job will be submitted
801 * @job: job to submit
804 * True if sync is needed.
806 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
807 struct amdgpu_job *job)
809 struct amdgpu_device *adev = ring->adev;
810 unsigned vmhub = ring->funcs->vmhub;
811 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
812 struct amdgpu_vmid *id;
813 bool gds_switch_needed;
814 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
818 id = &id_mgr->ids[job->vmid];
819 gds_switch_needed = ring->funcs->emit_gds_switch && (
820 id->gds_base != job->gds_base ||
821 id->gds_size != job->gds_size ||
822 id->gws_base != job->gws_base ||
823 id->gws_size != job->gws_size ||
824 id->oa_base != job->oa_base ||
825 id->oa_size != job->oa_size);
827 if (amdgpu_vmid_had_gpu_reset(adev, id))
830 return vm_flush_needed || gds_switch_needed;
834 * amdgpu_vm_flush - hardware flush the vm
836 * @ring: ring to use for flush
838 * @need_pipe_sync: is pipe sync needed
840 * Emit a VM flush when it is necessary.
843 * 0 on success, errno otherwise.
845 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
847 struct amdgpu_device *adev = ring->adev;
848 unsigned vmhub = ring->funcs->vmhub;
849 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
850 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
851 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
852 id->gds_base != job->gds_base ||
853 id->gds_size != job->gds_size ||
854 id->gws_base != job->gws_base ||
855 id->gws_size != job->gws_size ||
856 id->oa_base != job->oa_base ||
857 id->oa_size != job->oa_size);
858 bool vm_flush_needed = job->vm_needs_flush;
859 bool pasid_mapping_needed = id->pasid != job->pasid ||
860 !id->pasid_mapping ||
861 !dma_fence_is_signaled(id->pasid_mapping);
862 struct dma_fence *fence = NULL;
863 unsigned patch_offset = 0;
866 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
867 gds_switch_needed = true;
868 vm_flush_needed = true;
869 pasid_mapping_needed = true;
872 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
873 vm_flush_needed &= !!ring->funcs->emit_vm_flush;
874 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
875 ring->funcs->emit_wreg;
877 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
880 if (ring->funcs->init_cond_exec)
881 patch_offset = amdgpu_ring_init_cond_exec(ring);
884 amdgpu_ring_emit_pipeline_sync(ring);
886 if (vm_flush_needed) {
887 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
888 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
891 if (pasid_mapping_needed)
892 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
894 if (vm_flush_needed || pasid_mapping_needed) {
895 r = amdgpu_fence_emit(ring, &fence, 0);
900 if (vm_flush_needed) {
901 mutex_lock(&id_mgr->lock);
902 dma_fence_put(id->last_flush);
903 id->last_flush = dma_fence_get(fence);
904 id->current_gpu_reset_count =
905 atomic_read(&adev->gpu_reset_counter);
906 mutex_unlock(&id_mgr->lock);
909 if (pasid_mapping_needed) {
910 id->pasid = job->pasid;
911 dma_fence_put(id->pasid_mapping);
912 id->pasid_mapping = dma_fence_get(fence);
914 dma_fence_put(fence);
916 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
917 id->gds_base = job->gds_base;
918 id->gds_size = job->gds_size;
919 id->gws_base = job->gws_base;
920 id->gws_size = job->gws_size;
921 id->oa_base = job->oa_base;
922 id->oa_size = job->oa_size;
923 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
924 job->gds_size, job->gws_base,
925 job->gws_size, job->oa_base,
929 if (ring->funcs->patch_cond_exec)
930 amdgpu_ring_patch_cond_exec(ring, patch_offset);
932 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
933 if (ring->funcs->emit_switch_buffer) {
934 amdgpu_ring_emit_switch_buffer(ring);
935 amdgpu_ring_emit_switch_buffer(ring);
941 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
944 * @bo: requested buffer object
946 * Find @bo inside the requested vm.
947 * Search inside the @bos vm list for the requested vm
948 * Returns the found bo_va or NULL if none is found
950 * Object has to be reserved!
953 * Found bo_va or NULL.
955 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
956 struct amdgpu_bo *bo)
958 struct amdgpu_bo_va *bo_va;
960 list_for_each_entry(bo_va, &bo->va, base.bo_list) {
961 if (bo_va->base.vm == vm) {
969 * amdgpu_vm_do_set_ptes - helper to call the right asic function
971 * @params: see amdgpu_pte_update_params definition
972 * @bo: PD/PT to update
973 * @pe: addr of the page entry
974 * @addr: dst addr to write into pe
975 * @count: number of page entries to update
976 * @incr: increase next addr by incr bytes
977 * @flags: hw access flags
979 * Traces the parameters and calls the right asic functions
980 * to setup the page table using the DMA.
982 static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
983 struct amdgpu_bo *bo,
984 uint64_t pe, uint64_t addr,
985 unsigned count, uint32_t incr,
988 pe += amdgpu_bo_gpu_offset(bo);
989 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
992 amdgpu_vm_write_pte(params->adev, params->ib, pe,
993 addr | flags, count, incr);
996 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
1002 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
1004 * @params: see amdgpu_pte_update_params definition
1005 * @bo: PD/PT to update
1006 * @pe: addr of the page entry
1007 * @addr: dst addr to write into pe
1008 * @count: number of page entries to update
1009 * @incr: increase next addr by incr bytes
1010 * @flags: hw access flags
1012 * Traces the parameters and calls the DMA function to copy the PTEs.
1014 static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
1015 struct amdgpu_bo *bo,
1016 uint64_t pe, uint64_t addr,
1017 unsigned count, uint32_t incr,
1020 uint64_t src = (params->src + (addr >> 12) * 8);
1022 pe += amdgpu_bo_gpu_offset(bo);
1023 trace_amdgpu_vm_copy_ptes(pe, src, count);
1025 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
1029 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1031 * @pages_addr: optional DMA address to use for lookup
1032 * @addr: the unmapped addr
1034 * Look up the physical address of the page that the pte resolves
1038 * The pointer for the page table entry.
1040 static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1044 /* page table offset */
1045 result = pages_addr[addr >> PAGE_SHIFT];
1047 /* in case cpu page size != gpu page size*/
1048 result |= addr & (~PAGE_MASK);
1050 result &= 0xFFFFFFFFFFFFF000ULL;
1056 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
1058 * @params: see amdgpu_pte_update_params definition
1059 * @bo: PD/PT to update
1060 * @pe: kmap addr of the page entry
1061 * @addr: dst addr to write into pe
1062 * @count: number of page entries to update
1063 * @incr: increase next addr by incr bytes
1064 * @flags: hw access flags
1066 * Write count number of PT/PD entries directly.
1068 static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
1069 struct amdgpu_bo *bo,
1070 uint64_t pe, uint64_t addr,
1071 unsigned count, uint32_t incr,
1077 pe += (unsigned long)amdgpu_bo_kptr(bo);
1079 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
1081 for (i = 0; i < count; i++) {
1082 value = params->pages_addr ?
1083 amdgpu_vm_map_gart(params->pages_addr, addr) :
1085 amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
1093 * amdgpu_vm_wait_pd - Wait for PT BOs to be free.
1095 * @adev: amdgpu_device pointer
1097 * @owner: fence owner
1100 * 0 on success, errno otherwise.
1102 static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1105 struct amdgpu_sync sync;
1108 amdgpu_sync_create(&sync);
1109 amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
1110 r = amdgpu_sync_wait(&sync, true);
1111 amdgpu_sync_free(&sync);
1117 * amdgpu_vm_update_func - helper to call update function
1119 * Calls the update function for both the given BO as well as its shadow.
1121 static void amdgpu_vm_update_func(struct amdgpu_pte_update_params *params,
1122 struct amdgpu_bo *bo,
1123 uint64_t pe, uint64_t addr,
1124 unsigned count, uint32_t incr,
1128 params->func(params, bo->shadow, pe, addr, count, incr, flags);
1129 params->func(params, bo, pe, addr, count, incr, flags);
1133 * amdgpu_vm_update_pde - update a single level in the hierarchy
1135 * @param: parameters for the update
1137 * @parent: parent directory
1138 * @entry: entry to update
1140 * Makes sure the requested entry in parent is up to date.
1142 static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
1143 struct amdgpu_vm *vm,
1144 struct amdgpu_vm_pt *parent,
1145 struct amdgpu_vm_pt *entry)
1147 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1148 uint64_t pde, pt, flags;
1151 /* Don't update huge pages here */
1155 for (level = 0, pbo = bo->parent; pbo; ++level)
1158 level += params->adev->vm_manager.root_level;
1159 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1160 pde = (entry - parent->entries) * 8;
1161 amdgpu_vm_update_func(params, bo, pde, pt, 1, 0, flags);
1165 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
1167 * @adev: amdgpu_device pointer
1169 * @parent: parent PD
1170 * @level: VMPT level
1172 * Mark all PD level as invalid after an error.
1174 static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
1175 struct amdgpu_vm *vm,
1176 struct amdgpu_vm_pt *parent,
1179 unsigned pt_idx, num_entries;
1182 * Recurse into the subdirectories. This recursion is harmless because
1183 * we only have a maximum of 5 layers.
1185 num_entries = amdgpu_vm_num_entries(adev, level);
1186 for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) {
1187 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
1189 if (!entry->base.bo)
1192 if (!entry->base.moved)
1193 amdgpu_vm_bo_relocated(&entry->base);
1194 amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
1199 * amdgpu_vm_update_directories - make sure that all directories are valid
1201 * @adev: amdgpu_device pointer
1204 * Makes sure all directories are up to date.
1207 * 0 for success, error for failure.
1209 int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1210 struct amdgpu_vm *vm)
1212 struct amdgpu_pte_update_params params;
1213 struct amdgpu_job *job;
1217 if (list_empty(&vm->relocated))
1221 memset(¶ms, 0, sizeof(params));
1224 if (vm->use_cpu_for_update) {
1225 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
1229 params.func = amdgpu_vm_cpu_set_ptes;
1232 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1236 params.ib = &job->ibs[0];
1237 params.func = amdgpu_vm_do_set_ptes;
1240 while (!list_empty(&vm->relocated)) {
1241 struct amdgpu_vm_pt *pt, *entry;
1243 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1245 amdgpu_vm_bo_idle(&entry->base);
1247 pt = amdgpu_vm_pt_parent(entry);
1251 amdgpu_vm_update_pde(¶ms, vm, pt, entry);
1253 if (!vm->use_cpu_for_update &&
1254 (ndw - params.ib->length_dw) < 32)
1258 if (vm->use_cpu_for_update) {
1261 amdgpu_asic_flush_hdp(adev, NULL);
1262 } else if (params.ib->length_dw == 0) {
1263 amdgpu_job_free(job);
1265 struct amdgpu_bo *root = vm->root.base.bo;
1266 struct amdgpu_ring *ring;
1267 struct dma_fence *fence;
1269 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring,
1272 amdgpu_ring_pad_ib(ring, params.ib);
1273 amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
1274 AMDGPU_FENCE_OWNER_VM, false);
1275 WARN_ON(params.ib->length_dw > ndw);
1276 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM,
1281 amdgpu_bo_fence(root, fence, true);
1282 dma_fence_put(vm->last_update);
1283 vm->last_update = fence;
1286 if (!list_empty(&vm->relocated))
1292 amdgpu_vm_invalidate_level(adev, vm, &vm->root,
1293 adev->vm_manager.root_level);
1294 amdgpu_job_free(job);
1299 * amdgpu_vm_find_entry - find the entry for an address
1301 * @p: see amdgpu_pte_update_params definition
1302 * @addr: virtual address in question
1303 * @entry: resulting entry or NULL
1304 * @parent: parent entry
1306 * Find the vm_pt entry and it's parent for the given address.
1308 void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
1309 struct amdgpu_vm_pt **entry,
1310 struct amdgpu_vm_pt **parent)
1312 unsigned level = p->adev->vm_manager.root_level;
1315 *entry = &p->vm->root;
1316 while ((*entry)->entries) {
1317 unsigned shift = amdgpu_vm_level_shift(p->adev, level++);
1320 *entry = &(*entry)->entries[addr >> shift];
1321 addr &= (1ULL << shift) - 1;
1324 if (level != AMDGPU_VM_PTB)
1329 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
1331 * @p: see amdgpu_pte_update_params definition
1332 * @entry: vm_pt entry to check
1333 * @parent: parent entry
1334 * @nptes: number of PTEs updated with this operation
1335 * @dst: destination address where the PTEs should point to
1336 * @flags: access flags fro the PTEs
1338 * Check if we can update the PD with a huge page.
1340 static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
1341 struct amdgpu_vm_pt *entry,
1342 struct amdgpu_vm_pt *parent,
1343 unsigned nptes, uint64_t dst,
1348 /* In the case of a mixed PT the PDE must point to it*/
1349 if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
1350 nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
1351 /* Set the huge page flag to stop scanning at this PDE */
1352 flags |= AMDGPU_PDE_PTE;
1355 if (!(flags & AMDGPU_PDE_PTE)) {
1357 /* Add the entry to the relocated list to update it. */
1358 entry->huge = false;
1359 amdgpu_vm_bo_relocated(&entry->base);
1365 amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
1367 pde = (entry - parent->entries) * 8;
1368 amdgpu_vm_update_func(p, parent->base.bo, pde, dst, 1, 0, flags);
1372 * amdgpu_vm_update_ptes - make sure that page tables are valid
1374 * @params: see amdgpu_pte_update_params definition
1375 * @start: start of GPU address range
1376 * @end: end of GPU address range
1377 * @dst: destination address to map to, the next dst inside the function
1378 * @flags: mapping flags
1380 * Update the page tables in the range @start - @end.
1383 * 0 for success, -EINVAL for failure.
1385 static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1386 uint64_t start, uint64_t end,
1387 uint64_t dst, uint64_t flags)
1389 struct amdgpu_device *adev = params->adev;
1390 const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1392 uint64_t addr, pe_start;
1393 struct amdgpu_bo *pt;
1396 /* walk over the address space and update the page tables */
1397 for (addr = start; addr < end; addr += nptes,
1398 dst += nptes * AMDGPU_GPU_PAGE_SIZE) {
1399 struct amdgpu_vm_pt *entry, *parent;
1401 amdgpu_vm_get_entry(params, addr, &entry, &parent);
1405 if ((addr & ~mask) == (end & ~mask))
1408 nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1410 amdgpu_vm_handle_huge_pages(params, entry, parent,
1412 /* We don't need to update PTEs for huge pages */
1416 pt = entry->base.bo;
1417 pe_start = (addr & mask) * 8;
1418 amdgpu_vm_update_func(params, pt, pe_start, dst, nptes,
1419 AMDGPU_GPU_PAGE_SIZE, flags);
1427 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1429 * @params: see amdgpu_pte_update_params definition
1431 * @start: first PTE to handle
1432 * @end: last PTE to handle
1433 * @dst: addr those PTEs should point to
1434 * @flags: hw mapping flags
1437 * 0 for success, -EINVAL for failure.
1439 static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
1440 uint64_t start, uint64_t end,
1441 uint64_t dst, uint64_t flags)
1444 * The MC L1 TLB supports variable sized pages, based on a fragment
1445 * field in the PTE. When this field is set to a non-zero value, page
1446 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1447 * flags are considered valid for all PTEs within the fragment range
1448 * and corresponding mappings are assumed to be physically contiguous.
1450 * The L1 TLB can store a single PTE for the whole fragment,
1451 * significantly increasing the space available for translation
1452 * caching. This leads to large improvements in throughput when the
1453 * TLB is under pressure.
1455 * The L2 TLB distributes small and large fragments into two
1456 * asymmetric partitions. The large fragment cache is significantly
1457 * larger. Thus, we try to use large fragments wherever possible.
1458 * Userspace can support this by aligning virtual base address and
1459 * allocation size to the fragment size.
1461 unsigned max_frag = params->adev->vm_manager.fragment_size;
1464 /* system pages are non continuously */
1465 if (params->src || !(flags & AMDGPU_PTE_VALID))
1466 return amdgpu_vm_update_ptes(params, start, end, dst, flags);
1468 while (start != end) {
1469 uint64_t frag_flags, frag_end;
1472 /* This intentionally wraps around if no bit is set */
1473 frag = min((unsigned)ffs(start) - 1,
1474 (unsigned)fls64(end - start) - 1);
1475 if (frag >= max_frag) {
1476 frag_flags = AMDGPU_PTE_FRAG(max_frag);
1477 frag_end = end & ~((1ULL << max_frag) - 1);
1479 frag_flags = AMDGPU_PTE_FRAG(frag);
1480 frag_end = start + (1 << frag);
1483 r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
1484 flags | frag_flags);
1488 dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
1496 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1498 * @adev: amdgpu_device pointer
1499 * @exclusive: fence we need to sync to
1500 * @pages_addr: DMA addresses to use for mapping
1502 * @start: start of mapped range
1503 * @last: last mapped entry
1504 * @flags: flags for the entries
1505 * @addr: addr to set the area to
1506 * @fence: optional resulting fence
1508 * Fill in the page table entries between @start and @last.
1511 * 0 for success, -EINVAL for failure.
1513 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1514 struct dma_fence *exclusive,
1515 dma_addr_t *pages_addr,
1516 struct amdgpu_vm *vm,
1517 uint64_t start, uint64_t last,
1518 uint64_t flags, uint64_t addr,
1519 struct dma_fence **fence)
1521 struct amdgpu_ring *ring;
1522 void *owner = AMDGPU_FENCE_OWNER_VM;
1523 unsigned nptes, ncmds, ndw;
1524 struct amdgpu_job *job;
1525 struct amdgpu_pte_update_params params;
1526 struct dma_fence *f = NULL;
1529 memset(¶ms, 0, sizeof(params));
1533 /* sync to everything on unmapping */
1534 if (!(flags & AMDGPU_PTE_VALID))
1535 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1537 if (vm->use_cpu_for_update) {
1538 /* params.src is used as flag to indicate system Memory */
1542 /* Wait for PT BOs to be free. PTs share the same resv. object
1545 r = amdgpu_vm_wait_pd(adev, vm, owner);
1549 params.func = amdgpu_vm_cpu_set_ptes;
1550 params.pages_addr = pages_addr;
1551 return amdgpu_vm_frag_ptes(¶ms, start, last + 1,
1555 ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
1557 nptes = last - start + 1;
1560 * reserve space for two commands every (1 << BLOCK_SIZE)
1561 * entries or 2k dwords (whatever is smaller)
1563 * The second command is for the shadow pagetables.
1565 if (vm->root.base.bo->shadow)
1566 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
1568 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1574 /* copy commands needed */
1575 ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
1580 params.func = amdgpu_vm_do_copy_ptes;
1583 /* set page commands needed */
1586 /* extra commands for begin/end fragments */
1587 if (vm->root.base.bo->shadow)
1588 ndw += 2 * 10 * adev->vm_manager.fragment_size * 2;
1590 ndw += 2 * 10 * adev->vm_manager.fragment_size;
1592 params.func = amdgpu_vm_do_set_ptes;
1595 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1599 params.ib = &job->ibs[0];
1605 /* Put the PTEs at the end of the IB. */
1606 i = ndw - nptes * 2;
1607 pte= (uint64_t *)&(job->ibs->ptr[i]);
1608 params.src = job->ibs->gpu_addr + i * 4;
1610 for (i = 0; i < nptes; ++i) {
1611 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1612 AMDGPU_GPU_PAGE_SIZE);
1618 r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
1622 r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1627 r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
1631 r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1635 amdgpu_ring_pad_ib(ring, params.ib);
1636 WARN_ON(params.ib->length_dw > ndw);
1637 r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f);
1641 amdgpu_bo_fence(vm->root.base.bo, f, true);
1642 dma_fence_put(*fence);
1647 amdgpu_job_free(job);
1652 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1654 * @adev: amdgpu_device pointer
1655 * @exclusive: fence we need to sync to
1656 * @pages_addr: DMA addresses to use for mapping
1658 * @mapping: mapped range and flags to use for the update
1659 * @flags: HW flags for the mapping
1660 * @nodes: array of drm_mm_nodes with the MC addresses
1661 * @fence: optional resulting fence
1663 * Split the mapping into smaller chunks so that each update fits
1667 * 0 for success, -EINVAL for failure.
1669 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1670 struct dma_fence *exclusive,
1671 dma_addr_t *pages_addr,
1672 struct amdgpu_vm *vm,
1673 struct amdgpu_bo_va_mapping *mapping,
1675 struct drm_mm_node *nodes,
1676 struct dma_fence **fence)
1678 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1679 uint64_t pfn, start = mapping->start;
1682 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1683 * but in case of something, we filter the flags in first place
1685 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1686 flags &= ~AMDGPU_PTE_READABLE;
1687 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1688 flags &= ~AMDGPU_PTE_WRITEABLE;
1690 flags &= ~AMDGPU_PTE_EXECUTABLE;
1691 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1693 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1694 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1696 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1697 (adev->asic_type >= CHIP_VEGA10)) {
1698 flags |= AMDGPU_PTE_PRT;
1699 flags &= ~AMDGPU_PTE_VALID;
1702 trace_amdgpu_vm_bo_update(mapping);
1704 pfn = mapping->offset >> PAGE_SHIFT;
1706 while (pfn >= nodes->size) {
1713 dma_addr_t *dma_addr = NULL;
1714 uint64_t max_entries;
1715 uint64_t addr, last;
1718 addr = nodes->start << PAGE_SHIFT;
1719 max_entries = (nodes->size - pfn) *
1720 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1723 max_entries = S64_MAX;
1729 max_entries = min(max_entries, 16ull * 1024ull);
1731 count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1733 uint64_t idx = pfn + count;
1735 if (pages_addr[idx] !=
1736 (pages_addr[idx - 1] + PAGE_SIZE))
1740 if (count < min_linear_pages) {
1741 addr = pfn << PAGE_SHIFT;
1742 dma_addr = pages_addr;
1744 addr = pages_addr[pfn];
1745 max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1748 } else if (flags & AMDGPU_PTE_VALID) {
1749 addr += adev->vm_manager.vram_base_offset;
1750 addr += pfn << PAGE_SHIFT;
1753 last = min((uint64_t)mapping->last, start + max_entries - 1);
1754 r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1755 start, last, flags, addr,
1760 pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1761 if (nodes && nodes->size == pfn) {
1767 } while (unlikely(start != mapping->last + 1));
1773 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1775 * @adev: amdgpu_device pointer
1776 * @bo_va: requested BO and VM object
1777 * @clear: if true clear the entries
1779 * Fill in the page table entries for @bo_va.
1782 * 0 for success, -EINVAL for failure.
1784 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1785 struct amdgpu_bo_va *bo_va,
1788 struct amdgpu_bo *bo = bo_va->base.bo;
1789 struct amdgpu_vm *vm = bo_va->base.vm;
1790 struct amdgpu_bo_va_mapping *mapping;
1791 dma_addr_t *pages_addr = NULL;
1792 struct ttm_mem_reg *mem;
1793 struct drm_mm_node *nodes;
1794 struct dma_fence *exclusive, **last_update;
1803 struct ttm_dma_tt *ttm;
1806 nodes = mem->mm_node;
1807 if (mem->mem_type == TTM_PL_TT) {
1808 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
1809 pages_addr = ttm->dma_address;
1811 exclusive = reservation_object_get_excl(bo->tbo.resv);
1815 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1819 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
1820 last_update = &vm->last_update;
1822 last_update = &bo_va->last_pt_update;
1824 if (!clear && bo_va->base.moved) {
1825 bo_va->base.moved = false;
1826 list_splice_init(&bo_va->valids, &bo_va->invalids);
1828 } else if (bo_va->cleared != clear) {
1829 list_splice_init(&bo_va->valids, &bo_va->invalids);
1832 list_for_each_entry(mapping, &bo_va->invalids, list) {
1833 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1834 mapping, flags, nodes,
1840 if (vm->use_cpu_for_update) {
1843 amdgpu_asic_flush_hdp(adev, NULL);
1846 /* If the BO is not in its preferred location add it back to
1847 * the evicted list so that it gets validated again on the
1848 * next command submission.
1850 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
1851 uint32_t mem_type = bo->tbo.mem.mem_type;
1853 if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
1854 amdgpu_vm_bo_evicted(&bo_va->base);
1856 amdgpu_vm_bo_idle(&bo_va->base);
1858 amdgpu_vm_bo_done(&bo_va->base);
1861 list_splice_init(&bo_va->invalids, &bo_va->valids);
1862 bo_va->cleared = clear;
1864 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1865 list_for_each_entry(mapping, &bo_va->valids, list)
1866 trace_amdgpu_vm_bo_mapping(mapping);
1873 * amdgpu_vm_update_prt_state - update the global PRT state
1875 * @adev: amdgpu_device pointer
1877 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1879 unsigned long flags;
1882 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1883 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1884 adev->gmc.gmc_funcs->set_prt(adev, enable);
1885 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1889 * amdgpu_vm_prt_get - add a PRT user
1891 * @adev: amdgpu_device pointer
1893 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1895 if (!adev->gmc.gmc_funcs->set_prt)
1898 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1899 amdgpu_vm_update_prt_state(adev);
1903 * amdgpu_vm_prt_put - drop a PRT user
1905 * @adev: amdgpu_device pointer
1907 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1909 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1910 amdgpu_vm_update_prt_state(adev);
1914 * amdgpu_vm_prt_cb - callback for updating the PRT status
1916 * @fence: fence for the callback
1917 * @_cb: the callback function
1919 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1921 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1923 amdgpu_vm_prt_put(cb->adev);
1928 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1930 * @adev: amdgpu_device pointer
1931 * @fence: fence for the callback
1933 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1934 struct dma_fence *fence)
1936 struct amdgpu_prt_cb *cb;
1938 if (!adev->gmc.gmc_funcs->set_prt)
1941 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1943 /* Last resort when we are OOM */
1945 dma_fence_wait(fence, false);
1947 amdgpu_vm_prt_put(adev);
1950 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1952 amdgpu_vm_prt_cb(fence, &cb->cb);
1957 * amdgpu_vm_free_mapping - free a mapping
1959 * @adev: amdgpu_device pointer
1961 * @mapping: mapping to be freed
1962 * @fence: fence of the unmap operation
1964 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1966 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1967 struct amdgpu_vm *vm,
1968 struct amdgpu_bo_va_mapping *mapping,
1969 struct dma_fence *fence)
1971 if (mapping->flags & AMDGPU_PTE_PRT)
1972 amdgpu_vm_add_prt_cb(adev, fence);
1977 * amdgpu_vm_prt_fini - finish all prt mappings
1979 * @adev: amdgpu_device pointer
1982 * Register a cleanup callback to disable PRT support after VM dies.
1984 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1986 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1987 struct dma_fence *excl, **shared;
1988 unsigned i, shared_count;
1991 r = reservation_object_get_fences_rcu(resv, &excl,
1992 &shared_count, &shared);
1994 /* Not enough memory to grab the fence list, as last resort
1995 * block for all the fences to complete.
1997 reservation_object_wait_timeout_rcu(resv, true, false,
1998 MAX_SCHEDULE_TIMEOUT);
2002 /* Add a callback for each fence in the reservation object */
2003 amdgpu_vm_prt_get(adev);
2004 amdgpu_vm_add_prt_cb(adev, excl);
2006 for (i = 0; i < shared_count; ++i) {
2007 amdgpu_vm_prt_get(adev);
2008 amdgpu_vm_add_prt_cb(adev, shared[i]);
2015 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2017 * @adev: amdgpu_device pointer
2019 * @fence: optional resulting fence (unchanged if no work needed to be done
2020 * or if an error occurred)
2022 * Make sure all freed BOs are cleared in the PT.
2023 * PTs have to be reserved and mutex must be locked!
2029 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2030 struct amdgpu_vm *vm,
2031 struct dma_fence **fence)
2033 struct amdgpu_bo_va_mapping *mapping;
2034 uint64_t init_pte_value = 0;
2035 struct dma_fence *f = NULL;
2038 while (!list_empty(&vm->freed)) {
2039 mapping = list_first_entry(&vm->freed,
2040 struct amdgpu_bo_va_mapping, list);
2041 list_del(&mapping->list);
2043 if (vm->pte_support_ats &&
2044 mapping->start < AMDGPU_GMC_HOLE_START)
2045 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2047 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
2048 mapping->start, mapping->last,
2049 init_pte_value, 0, &f);
2050 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2058 dma_fence_put(*fence);
2069 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2071 * @adev: amdgpu_device pointer
2074 * Make sure all BOs which are moved are updated in the PTs.
2079 * PTs have to be reserved!
2081 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2082 struct amdgpu_vm *vm)
2084 struct amdgpu_bo_va *bo_va, *tmp;
2085 struct reservation_object *resv;
2089 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2090 /* Per VM BOs never need to bo cleared in the page tables */
2091 r = amdgpu_vm_bo_update(adev, bo_va, false);
2096 spin_lock(&vm->invalidated_lock);
2097 while (!list_empty(&vm->invalidated)) {
2098 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2100 resv = bo_va->base.bo->tbo.resv;
2101 spin_unlock(&vm->invalidated_lock);
2103 /* Try to reserve the BO to avoid clearing its ptes */
2104 if (!amdgpu_vm_debug && reservation_object_trylock(resv))
2106 /* Somebody else is using the BO right now */
2110 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2115 reservation_object_unlock(resv);
2116 spin_lock(&vm->invalidated_lock);
2118 spin_unlock(&vm->invalidated_lock);
2124 * amdgpu_vm_bo_add - add a bo to a specific vm
2126 * @adev: amdgpu_device pointer
2128 * @bo: amdgpu buffer object
2130 * Add @bo into the requested vm.
2131 * Add @bo to the list of bos associated with the vm
2134 * Newly added bo_va or NULL for failure
2136 * Object has to be reserved!
2138 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2139 struct amdgpu_vm *vm,
2140 struct amdgpu_bo *bo)
2142 struct amdgpu_bo_va *bo_va;
2144 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2145 if (bo_va == NULL) {
2148 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2150 bo_va->ref_count = 1;
2151 INIT_LIST_HEAD(&bo_va->valids);
2152 INIT_LIST_HEAD(&bo_va->invalids);
2159 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2161 * @adev: amdgpu_device pointer
2162 * @bo_va: bo_va to store the address
2163 * @mapping: the mapping to insert
2165 * Insert a new mapping into all structures.
2167 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2168 struct amdgpu_bo_va *bo_va,
2169 struct amdgpu_bo_va_mapping *mapping)
2171 struct amdgpu_vm *vm = bo_va->base.vm;
2172 struct amdgpu_bo *bo = bo_va->base.bo;
2174 mapping->bo_va = bo_va;
2175 list_add(&mapping->list, &bo_va->invalids);
2176 amdgpu_vm_it_insert(mapping, &vm->va);
2178 if (mapping->flags & AMDGPU_PTE_PRT)
2179 amdgpu_vm_prt_get(adev);
2181 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv &&
2182 !bo_va->base.moved) {
2183 list_move(&bo_va->base.vm_status, &vm->moved);
2185 trace_amdgpu_vm_bo_map(bo_va, mapping);
2189 * amdgpu_vm_bo_map - map bo inside a vm
2191 * @adev: amdgpu_device pointer
2192 * @bo_va: bo_va to store the address
2193 * @saddr: where to map the BO
2194 * @offset: requested offset in the BO
2195 * @size: BO size in bytes
2196 * @flags: attributes of pages (read/write/valid/etc.)
2198 * Add a mapping of the BO at the specefied addr into the VM.
2201 * 0 for success, error for failure.
2203 * Object has to be reserved and unreserved outside!
2205 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2206 struct amdgpu_bo_va *bo_va,
2207 uint64_t saddr, uint64_t offset,
2208 uint64_t size, uint64_t flags)
2210 struct amdgpu_bo_va_mapping *mapping, *tmp;
2211 struct amdgpu_bo *bo = bo_va->base.bo;
2212 struct amdgpu_vm *vm = bo_va->base.vm;
2215 /* validate the parameters */
2216 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2217 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2220 /* make sure object fit at this offset */
2221 eaddr = saddr + size - 1;
2222 if (saddr >= eaddr ||
2223 (bo && offset + size > amdgpu_bo_size(bo)))
2226 saddr /= AMDGPU_GPU_PAGE_SIZE;
2227 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2229 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2231 /* bo and tmp overlap, invalid addr */
2232 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2233 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2234 tmp->start, tmp->last + 1);
2238 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2242 mapping->start = saddr;
2243 mapping->last = eaddr;
2244 mapping->offset = offset;
2245 mapping->flags = flags;
2247 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2253 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2255 * @adev: amdgpu_device pointer
2256 * @bo_va: bo_va to store the address
2257 * @saddr: where to map the BO
2258 * @offset: requested offset in the BO
2259 * @size: BO size in bytes
2260 * @flags: attributes of pages (read/write/valid/etc.)
2262 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2263 * mappings as we do so.
2266 * 0 for success, error for failure.
2268 * Object has to be reserved and unreserved outside!
2270 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2271 struct amdgpu_bo_va *bo_va,
2272 uint64_t saddr, uint64_t offset,
2273 uint64_t size, uint64_t flags)
2275 struct amdgpu_bo_va_mapping *mapping;
2276 struct amdgpu_bo *bo = bo_va->base.bo;
2280 /* validate the parameters */
2281 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2282 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2285 /* make sure object fit at this offset */
2286 eaddr = saddr + size - 1;
2287 if (saddr >= eaddr ||
2288 (bo && offset + size > amdgpu_bo_size(bo)))
2291 /* Allocate all the needed memory */
2292 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2296 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2302 saddr /= AMDGPU_GPU_PAGE_SIZE;
2303 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2305 mapping->start = saddr;
2306 mapping->last = eaddr;
2307 mapping->offset = offset;
2308 mapping->flags = flags;
2310 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2316 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2318 * @adev: amdgpu_device pointer
2319 * @bo_va: bo_va to remove the address from
2320 * @saddr: where to the BO is mapped
2322 * Remove a mapping of the BO at the specefied addr from the VM.
2325 * 0 for success, error for failure.
2327 * Object has to be reserved and unreserved outside!
2329 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2330 struct amdgpu_bo_va *bo_va,
2333 struct amdgpu_bo_va_mapping *mapping;
2334 struct amdgpu_vm *vm = bo_va->base.vm;
2337 saddr /= AMDGPU_GPU_PAGE_SIZE;
2339 list_for_each_entry(mapping, &bo_va->valids, list) {
2340 if (mapping->start == saddr)
2344 if (&mapping->list == &bo_va->valids) {
2347 list_for_each_entry(mapping, &bo_va->invalids, list) {
2348 if (mapping->start == saddr)
2352 if (&mapping->list == &bo_va->invalids)
2356 list_del(&mapping->list);
2357 amdgpu_vm_it_remove(mapping, &vm->va);
2358 mapping->bo_va = NULL;
2359 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2362 list_add(&mapping->list, &vm->freed);
2364 amdgpu_vm_free_mapping(adev, vm, mapping,
2365 bo_va->last_pt_update);
2371 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2373 * @adev: amdgpu_device pointer
2374 * @vm: VM structure to use
2375 * @saddr: start of the range
2376 * @size: size of the range
2378 * Remove all mappings in a range, split them as appropriate.
2381 * 0 for success, error for failure.
2383 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2384 struct amdgpu_vm *vm,
2385 uint64_t saddr, uint64_t size)
2387 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2391 eaddr = saddr + size - 1;
2392 saddr /= AMDGPU_GPU_PAGE_SIZE;
2393 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2395 /* Allocate all the needed memory */
2396 before = kzalloc(sizeof(*before), GFP_KERNEL);
2399 INIT_LIST_HEAD(&before->list);
2401 after = kzalloc(sizeof(*after), GFP_KERNEL);
2406 INIT_LIST_HEAD(&after->list);
2408 /* Now gather all removed mappings */
2409 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2411 /* Remember mapping split at the start */
2412 if (tmp->start < saddr) {
2413 before->start = tmp->start;
2414 before->last = saddr - 1;
2415 before->offset = tmp->offset;
2416 before->flags = tmp->flags;
2417 before->bo_va = tmp->bo_va;
2418 list_add(&before->list, &tmp->bo_va->invalids);
2421 /* Remember mapping split at the end */
2422 if (tmp->last > eaddr) {
2423 after->start = eaddr + 1;
2424 after->last = tmp->last;
2425 after->offset = tmp->offset;
2426 after->offset += after->start - tmp->start;
2427 after->flags = tmp->flags;
2428 after->bo_va = tmp->bo_va;
2429 list_add(&after->list, &tmp->bo_va->invalids);
2432 list_del(&tmp->list);
2433 list_add(&tmp->list, &removed);
2435 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2438 /* And free them up */
2439 list_for_each_entry_safe(tmp, next, &removed, list) {
2440 amdgpu_vm_it_remove(tmp, &vm->va);
2441 list_del(&tmp->list);
2443 if (tmp->start < saddr)
2445 if (tmp->last > eaddr)
2449 list_add(&tmp->list, &vm->freed);
2450 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2453 /* Insert partial mapping before the range */
2454 if (!list_empty(&before->list)) {
2455 amdgpu_vm_it_insert(before, &vm->va);
2456 if (before->flags & AMDGPU_PTE_PRT)
2457 amdgpu_vm_prt_get(adev);
2462 /* Insert partial mapping after the range */
2463 if (!list_empty(&after->list)) {
2464 amdgpu_vm_it_insert(after, &vm->va);
2465 if (after->flags & AMDGPU_PTE_PRT)
2466 amdgpu_vm_prt_get(adev);
2475 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2477 * @vm: the requested VM
2478 * @addr: the address
2480 * Find a mapping by it's address.
2483 * The amdgpu_bo_va_mapping matching for addr or NULL
2486 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2489 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2493 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2495 * @vm: the requested vm
2496 * @ticket: CS ticket
2498 * Trace all mappings of BOs reserved during a command submission.
2500 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2502 struct amdgpu_bo_va_mapping *mapping;
2504 if (!trace_amdgpu_vm_bo_cs_enabled())
2507 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2508 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2509 if (mapping->bo_va && mapping->bo_va->base.bo) {
2510 struct amdgpu_bo *bo;
2512 bo = mapping->bo_va->base.bo;
2513 if (READ_ONCE(bo->tbo.resv->lock.ctx) != ticket)
2517 trace_amdgpu_vm_bo_cs(mapping);
2522 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2524 * @adev: amdgpu_device pointer
2525 * @bo_va: requested bo_va
2527 * Remove @bo_va->bo from the requested vm.
2529 * Object have to be reserved!
2531 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2532 struct amdgpu_bo_va *bo_va)
2534 struct amdgpu_bo_va_mapping *mapping, *next;
2535 struct amdgpu_bo *bo = bo_va->base.bo;
2536 struct amdgpu_vm *vm = bo_va->base.vm;
2538 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv)
2539 vm->bulk_moveable = false;
2541 list_del(&bo_va->base.bo_list);
2543 spin_lock(&vm->invalidated_lock);
2544 list_del(&bo_va->base.vm_status);
2545 spin_unlock(&vm->invalidated_lock);
2547 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2548 list_del(&mapping->list);
2549 amdgpu_vm_it_remove(mapping, &vm->va);
2550 mapping->bo_va = NULL;
2551 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2552 list_add(&mapping->list, &vm->freed);
2554 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2555 list_del(&mapping->list);
2556 amdgpu_vm_it_remove(mapping, &vm->va);
2557 amdgpu_vm_free_mapping(adev, vm, mapping,
2558 bo_va->last_pt_update);
2561 dma_fence_put(bo_va->last_pt_update);
2566 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2568 * @adev: amdgpu_device pointer
2569 * @bo: amdgpu buffer object
2570 * @evicted: is the BO evicted
2572 * Mark @bo as invalid.
2574 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2575 struct amdgpu_bo *bo, bool evicted)
2577 struct amdgpu_vm_bo_base *bo_base;
2579 /* shadow bo doesn't have bo base, its validation needs its parent */
2580 if (bo->parent && bo->parent->shadow == bo)
2583 list_for_each_entry(bo_base, &bo->va, bo_list) {
2584 struct amdgpu_vm *vm = bo_base->vm;
2586 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2587 amdgpu_vm_bo_evicted(bo_base);
2593 bo_base->moved = true;
2595 if (bo->tbo.type == ttm_bo_type_kernel)
2596 amdgpu_vm_bo_relocated(bo_base);
2597 else if (bo->tbo.resv == vm->root.base.bo->tbo.resv)
2598 amdgpu_vm_bo_moved(bo_base);
2600 amdgpu_vm_bo_invalidated(bo_base);
2605 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2610 * VM page table as power of two
2612 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2614 /* Total bits covered by PD + PTs */
2615 unsigned bits = ilog2(vm_size) + 18;
2617 /* Make sure the PD is 4K in size up to 8GB address space.
2618 Above that split equal between PD and PTs */
2622 return ((bits + 3) / 2);
2626 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2628 * @adev: amdgpu_device pointer
2629 * @min_vm_size: the minimum vm size in GB if it's set auto
2630 * @fragment_size_default: Default PTE fragment size
2631 * @max_level: max VMPT level
2632 * @max_bits: max address space size in bits
2635 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2636 uint32_t fragment_size_default, unsigned max_level,
2639 unsigned int max_size = 1 << (max_bits - 30);
2640 unsigned int vm_size;
2643 /* adjust vm size first */
2644 if (amdgpu_vm_size != -1) {
2645 vm_size = amdgpu_vm_size;
2646 if (vm_size > max_size) {
2647 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2648 amdgpu_vm_size, max_size);
2653 unsigned int phys_ram_gb;
2655 /* Optimal VM size depends on the amount of physical
2656 * RAM available. Underlying requirements and
2659 * - Need to map system memory and VRAM from all GPUs
2660 * - VRAM from other GPUs not known here
2661 * - Assume VRAM <= system memory
2662 * - On GFX8 and older, VM space can be segmented for
2664 * - Need to allow room for fragmentation, guard pages etc.
2666 * This adds up to a rough guess of system memory x3.
2667 * Round up to power of two to maximize the available
2668 * VM size with the given page table size.
2671 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2672 (1 << 30) - 1) >> 30;
2673 vm_size = roundup_pow_of_two(
2674 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2677 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2679 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2680 if (amdgpu_vm_block_size != -1)
2681 tmp >>= amdgpu_vm_block_size - 9;
2682 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2683 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2684 switch (adev->vm_manager.num_level) {
2686 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2689 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2692 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2695 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2697 /* block size depends on vm size and hw setup*/
2698 if (amdgpu_vm_block_size != -1)
2699 adev->vm_manager.block_size =
2700 min((unsigned)amdgpu_vm_block_size, max_bits
2701 - AMDGPU_GPU_PAGE_SHIFT
2702 - 9 * adev->vm_manager.num_level);
2703 else if (adev->vm_manager.num_level > 1)
2704 adev->vm_manager.block_size = 9;
2706 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2708 if (amdgpu_vm_fragment_size == -1)
2709 adev->vm_manager.fragment_size = fragment_size_default;
2711 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2713 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2714 vm_size, adev->vm_manager.num_level + 1,
2715 adev->vm_manager.block_size,
2716 adev->vm_manager.fragment_size);
2720 * amdgpu_vm_init - initialize a vm instance
2722 * @adev: amdgpu_device pointer
2724 * @vm_context: Indicates if it GFX or Compute context
2725 * @pasid: Process address space identifier
2730 * 0 for success, error for failure.
2732 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2733 int vm_context, unsigned int pasid)
2735 struct amdgpu_bo_param bp;
2736 struct amdgpu_bo *root;
2739 vm->va = RB_ROOT_CACHED;
2740 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2741 vm->reserved_vmid[i] = NULL;
2742 INIT_LIST_HEAD(&vm->evicted);
2743 INIT_LIST_HEAD(&vm->relocated);
2744 INIT_LIST_HEAD(&vm->moved);
2745 INIT_LIST_HEAD(&vm->idle);
2746 INIT_LIST_HEAD(&vm->invalidated);
2747 spin_lock_init(&vm->invalidated_lock);
2748 INIT_LIST_HEAD(&vm->freed);
2750 /* create scheduler entity for page table updates */
2751 r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
2752 adev->vm_manager.vm_pte_num_rqs, NULL);
2756 vm->pte_support_ats = false;
2758 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2759 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2760 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2762 if (adev->asic_type == CHIP_RAVEN)
2763 vm->pte_support_ats = true;
2765 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2766 AMDGPU_VM_USE_CPU_FOR_GFX);
2768 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2769 vm->use_cpu_for_update ? "CPU" : "SDMA");
2770 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2771 "CPU update of VM recommended only for large BAR system\n");
2772 vm->last_update = NULL;
2774 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
2775 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2776 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
2777 r = amdgpu_bo_create(adev, &bp, &root);
2779 goto error_free_sched_entity;
2781 r = amdgpu_bo_reserve(root, true);
2783 goto error_free_root;
2785 r = amdgpu_vm_clear_bo(adev, vm, root,
2786 adev->vm_manager.root_level,
2787 vm->pte_support_ats);
2789 goto error_unreserve;
2791 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2792 amdgpu_bo_unreserve(vm->root.base.bo);
2795 unsigned long flags;
2797 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2798 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2800 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2802 goto error_free_root;
2807 INIT_KFIFO(vm->faults);
2808 vm->fault_credit = 16;
2813 amdgpu_bo_unreserve(vm->root.base.bo);
2816 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2817 amdgpu_bo_unref(&vm->root.base.bo);
2818 vm->root.base.bo = NULL;
2820 error_free_sched_entity:
2821 drm_sched_entity_destroy(&vm->entity);
2827 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2829 * @adev: amdgpu_device pointer
2832 * This only works on GFX VMs that don't have any BOs added and no
2833 * page tables allocated yet.
2835 * Changes the following VM parameters:
2836 * - use_cpu_for_update
2837 * - pte_supports_ats
2838 * - pasid (old PASID is released, because compute manages its own PASIDs)
2840 * Reinitializes the page directory to reflect the changed ATS
2844 * 0 for success, -errno for errors.
2846 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
2848 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2851 r = amdgpu_bo_reserve(vm->root.base.bo, true);
2856 if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
2862 unsigned long flags;
2864 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2865 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2867 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2874 /* Check if PD needs to be reinitialized and do it before
2875 * changing any other state, in case it fails.
2877 if (pte_support_ats != vm->pte_support_ats) {
2878 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
2879 adev->vm_manager.root_level,
2885 /* Update VM state */
2886 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2887 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2888 vm->pte_support_ats = pte_support_ats;
2889 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2890 vm->use_cpu_for_update ? "CPU" : "SDMA");
2891 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2892 "CPU update of VM recommended only for large BAR system\n");
2895 unsigned long flags;
2897 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2898 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2899 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2901 /* Free the original amdgpu allocated pasid
2902 * Will be replaced with kfd allocated pasid
2904 amdgpu_pasid_free(vm->pasid);
2908 /* Free the shadow bo for compute VM */
2909 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2918 unsigned long flags;
2920 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2921 idr_remove(&adev->vm_manager.pasid_idr, pasid);
2922 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2925 amdgpu_bo_unreserve(vm->root.base.bo);
2930 * amdgpu_vm_release_compute - release a compute vm
2931 * @adev: amdgpu_device pointer
2932 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2934 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2935 * pasid from vm. Compute should stop use of vm after this call.
2937 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2940 unsigned long flags;
2942 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2943 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2944 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2950 * amdgpu_vm_free_levels - free PD/PT levels
2952 * @adev: amdgpu device structure
2953 * @parent: PD/PT starting level to free
2954 * @level: level of parent structure
2956 * Free the page directory or page table level and all sub levels.
2958 static void amdgpu_vm_free_levels(struct amdgpu_device *adev,
2959 struct amdgpu_vm_pt *parent,
2962 unsigned i, num_entries = amdgpu_vm_num_entries(adev, level);
2964 if (parent->base.bo) {
2965 list_del(&parent->base.bo_list);
2966 list_del(&parent->base.vm_status);
2967 amdgpu_bo_unref(&parent->base.bo->shadow);
2968 amdgpu_bo_unref(&parent->base.bo);
2971 if (parent->entries)
2972 for (i = 0; i < num_entries; i++)
2973 amdgpu_vm_free_levels(adev, &parent->entries[i],
2976 kvfree(parent->entries);
2980 * amdgpu_vm_fini - tear down a vm instance
2982 * @adev: amdgpu_device pointer
2986 * Unbind the VM and remove all bos from the vm bo list
2988 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2990 struct amdgpu_bo_va_mapping *mapping, *tmp;
2991 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2992 struct amdgpu_bo *root;
2996 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2998 /* Clear pending page faults from IH when the VM is destroyed */
2999 while (kfifo_get(&vm->faults, &fault))
3000 amdgpu_ih_clear_fault(adev, fault);
3003 unsigned long flags;
3005 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3006 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3007 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3010 drm_sched_entity_destroy(&vm->entity);
3012 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3013 dev_err(adev->dev, "still active bo inside vm\n");
3015 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3016 &vm->va.rb_root, rb) {
3017 list_del(&mapping->list);
3018 amdgpu_vm_it_remove(mapping, &vm->va);
3021 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3022 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3023 amdgpu_vm_prt_fini(adev, vm);
3024 prt_fini_needed = false;
3027 list_del(&mapping->list);
3028 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3031 root = amdgpu_bo_ref(vm->root.base.bo);
3032 r = amdgpu_bo_reserve(root, true);
3034 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
3036 amdgpu_vm_free_levels(adev, &vm->root,
3037 adev->vm_manager.root_level);
3038 amdgpu_bo_unreserve(root);
3040 amdgpu_bo_unref(&root);
3041 dma_fence_put(vm->last_update);
3042 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3043 amdgpu_vmid_free_reserved(adev, vm, i);
3047 * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
3049 * @adev: amdgpu_device pointer
3050 * @pasid: PASID do identify the VM
3052 * This function is expected to be called in interrupt context.
3055 * True if there was fault credit, false otherwise
3057 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
3060 struct amdgpu_vm *vm;
3062 spin_lock(&adev->vm_manager.pasid_lock);
3063 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3065 /* VM not found, can't track fault credit */
3066 spin_unlock(&adev->vm_manager.pasid_lock);
3070 /* No lock needed. only accessed by IRQ handler */
3071 if (!vm->fault_credit) {
3072 /* Too many faults in this VM */
3073 spin_unlock(&adev->vm_manager.pasid_lock);
3078 spin_unlock(&adev->vm_manager.pasid_lock);
3083 * amdgpu_vm_manager_init - init the VM manager
3085 * @adev: amdgpu_device pointer
3087 * Initialize the VM manager structures
3089 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3093 amdgpu_vmid_mgr_init(adev);
3095 adev->vm_manager.fence_context =
3096 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3097 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3098 adev->vm_manager.seqno[i] = 0;
3100 spin_lock_init(&adev->vm_manager.prt_lock);
3101 atomic_set(&adev->vm_manager.num_prt_users, 0);
3103 /* If not overridden by the user, by default, only in large BAR systems
3104 * Compute VM tables will be updated by CPU
3106 #ifdef CONFIG_X86_64
3107 if (amdgpu_vm_update_mode == -1) {
3108 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3109 adev->vm_manager.vm_update_mode =
3110 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3112 adev->vm_manager.vm_update_mode = 0;
3114 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3116 adev->vm_manager.vm_update_mode = 0;
3119 idr_init(&adev->vm_manager.pasid_idr);
3120 spin_lock_init(&adev->vm_manager.pasid_lock);
3124 * amdgpu_vm_manager_fini - cleanup VM manager
3126 * @adev: amdgpu_device pointer
3128 * Cleanup the VM manager and free resources.
3130 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3132 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3133 idr_destroy(&adev->vm_manager.pasid_idr);
3135 amdgpu_vmid_mgr_fini(adev);
3139 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3141 * @dev: drm device pointer
3142 * @data: drm_amdgpu_vm
3143 * @filp: drm file pointer
3146 * 0 for success, -errno for errors.
3148 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3150 union drm_amdgpu_vm *args = data;
3151 struct amdgpu_device *adev = dev->dev_private;
3152 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3155 switch (args->in.op) {
3156 case AMDGPU_VM_OP_RESERVE_VMID:
3157 /* current, we only have requirement to reserve vmid from gfxhub */
3158 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3162 case AMDGPU_VM_OP_UNRESERVE_VMID:
3163 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
3173 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3175 * @adev: drm device pointer
3176 * @pasid: PASID identifier for VM
3177 * @task_info: task_info to fill.
3179 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3180 struct amdgpu_task_info *task_info)
3182 struct amdgpu_vm *vm;
3184 spin_lock(&adev->vm_manager.pasid_lock);
3186 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3188 *task_info = vm->task_info;
3190 spin_unlock(&adev->vm_manager.pasid_lock);
3194 * amdgpu_vm_set_task_info - Sets VMs task info.
3196 * @vm: vm for which to set the info
3198 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3200 if (!vm->task_info.pid) {
3201 vm->task_info.pid = current->pid;
3202 get_task_comm(vm->task_info.task_name, current);
3204 if (current->group_leader->mm == current->mm) {
3205 vm->task_info.tgid = current->group_leader->pid;
3206 get_task_comm(vm->task_info.process_name, current->group_leader);