drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *          Christian König
  28  */
  29 #include <linux/seq_file.h>
  30 #include <linux/slab.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/debugfs.h>
  33
  34 #include <drm/amdgpu_drm.h>
  35 #include "amdgpu.h"
  36 #include "atom.h"
  37
  38 /*
  39  * Rings
  40  * Most engines on the GPU are fed via ring buffers.  Ring
  41  * buffers are areas of GPU accessible memory that the host
  42  * writes commands into and the GPU reads commands out of.
  43  * There is a rptr (read pointer) that determines where the
  44  * GPU is currently reading, and a wptr (write pointer)
  45  * which determines where the host has written.  When the
  46  * pointers are equal, the ring is idle.  When the host
  47  * writes commands to the ring buffer, it increments the
  48  * wptr.  The GPU then starts fetching commands and executes
  49  * them until the pointers are equal again.
  50  */
  51
  52 /**
  53  * amdgpu_ring_alloc - allocate space on the ring buffer
  54  *
  55  * @adev: amdgpu_device pointer
  56  * @ring: amdgpu_ring structure holding ring information
  57  * @ndw: number of dwords to allocate in the ring buffer
  58  *
  59  * Allocate @ndw dwords in the ring buffer (all asics).
  60  * Returns 0 on success, error on failure.
  61  */
  62 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
  63 {
  64         /* Align requested size with padding so unlock_commit can
  65          * pad safely */
  66         ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
  67
  68         /* Make sure we aren't trying to allocate more space
  69          * than the maximum for one submission
  70          */
  71         if (WARN_ON_ONCE(ndw > ring->max_dw))
  72                 return -ENOMEM;
  73
  74         ring->count_dw = ndw;
  75         ring->wptr_old = ring->wptr;
  76
  77         if (ring->funcs->begin_use)
  78                 ring->funcs->begin_use(ring);
  79
  80         return 0;
  81 }
  82
  83 /** amdgpu_ring_insert_nop - insert NOP packets
  84  *
  85  * @ring: amdgpu_ring structure holding ring information
  86  * @count: the number of NOP packets to insert
  87  *
  88  * This is the generic insert_nop function for rings except SDMA
  89  */
  90 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  91 {
  92         int i;
  93
  94         for (i = 0; i < count; i++)
  95                 amdgpu_ring_write(ring, ring->funcs->nop);
  96 }
  97
  98 /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
  99  *
 100  * @ring: amdgpu_ring structure holding ring information
 101  * @ib: IB to add NOP packets to
 102  *
 103  * This is the generic pad_ib function for rings except SDMA
 104  */
 105 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 106 {
 107         while (ib->length_dw & ring->funcs->align_mask)
 108                 ib->ptr[ib->length_dw++] = ring->funcs->nop;
 109 }
 110
 111 /**
 112  * amdgpu_ring_commit - tell the GPU to execute the new
 113  * commands on the ring buffer
 114  *
 115  * @adev: amdgpu_device pointer
 116  * @ring: amdgpu_ring structure holding ring information
 117  *
 118  * Update the wptr (write pointer) to tell the GPU to
 119  * execute new commands on the ring buffer (all asics).
 120  */
 121 void amdgpu_ring_commit(struct amdgpu_ring *ring)
 122 {
 123         uint32_t count;
 124
 125         /* We pad to match fetch size */
 126         count = ring->funcs->align_mask + 1 -
 127                 (ring->wptr & ring->funcs->align_mask);
 128         count %= ring->funcs->align_mask + 1;
 129         ring->funcs->insert_nop(ring, count);
 130
 131         mb();
 132         amdgpu_ring_set_wptr(ring);
 133
 134         if (ring->funcs->end_use)
 135                 ring->funcs->end_use(ring);
 136 }
 137
 138 /**
 139  * amdgpu_ring_undo - reset the wptr
 140  *
 141  * @ring: amdgpu_ring structure holding ring information
 142  *
 143  * Reset the driver's copy of the wptr (all asics).
 144  */
 145 void amdgpu_ring_undo(struct amdgpu_ring *ring)
 146 {
 147         ring->wptr = ring->wptr_old;
 148
 149         if (ring->funcs->end_use)
 150                 ring->funcs->end_use(ring);
 151 }
 152
 153 /**
 154  * amdgpu_ring_init - init driver ring struct.
 155  *
 156  * @adev: amdgpu_device pointer
 157  * @ring: amdgpu_ring structure holding ring information
 158  * @max_ndw: maximum number of dw for ring alloc
 159  * @nop: nop packet for this ring
 160  *
 161  * Initialize the driver information for the selected ring (all asics).
 162  * Returns 0 on success, error on failure.
 163  */
 164 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
 165                      unsigned int max_dw, struct amdgpu_irq_src *irq_src,
 166                      unsigned int irq_type, unsigned int hw_prio)
 167 {
 168         int r, i;
 169         int sched_hw_submission = amdgpu_sched_hw_submission;
 170         u32 *num_sched;
 171         u32 hw_ip;
 172
 173         /* Set the hw submission limit higher for KIQ because
 174          * it's used for a number of gfx/compute tasks by both
 175          * KFD and KGD which may have outstanding fences and
 176          * it doesn't really use the gpu scheduler anyway;
 177          * KIQ tasks get submitted directly to the ring.
 178          */
 179         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 180                 sched_hw_submission = max(sched_hw_submission, 256);
 181         else if (ring == &adev->sdma.instance[0].page)
 182                 sched_hw_submission = 256;
 183
 184         if (ring->adev == NULL) {
 185                 if (adev->num_rings >= AMDGPU_MAX_RINGS)
 186                         return -EINVAL;
 187
 188                 ring->adev = adev;
 189                 ring->idx = adev->num_rings++;
 190                 adev->rings[ring->idx] = ring;
 191                 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
 192                 if (r)
 193                         return r;
 194         }
 195
 196         r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
 197         if (r) {
 198                 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
 199                 return r;
 200         }
 201
 202         r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
 203         if (r) {
 204                 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
 205                 return r;
 206         }
 207
 208         r = amdgpu_device_wb_get(adev, &ring->fence_offs);
 209         if (r) {
 210                 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
 211                 return r;
 212         }
 213
 214         r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
 215         if (r) {
 216                 dev_err(adev->dev,
 217                         "(%d) ring trail_fence_offs wb alloc failed\n", r);
 218                 return r;
 219         }
 220         ring->trail_fence_gpu_addr =
 221                 adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
 222         ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
 223
 224         r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
 225         if (r) {
 226                 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
 227                 return r;
 228         }
 229         ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
 230         ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
 231         /* always set cond_exec_polling to CONTINUE */
 232         *ring->cond_exe_cpu_addr = 1;
 233
 234         r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
 235         if (r) {
 236                 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
 237                 return r;
 238         }
 239
 240         ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
 241
 242         ring->buf_mask = (ring->ring_size / 4) - 1;
 243         ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
 244                 0xffffffffffffffff : ring->buf_mask;
 245         /* Allocate ring buffer */
 246         if (ring->ring_obj == NULL) {
 247                 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
 248                                             AMDGPU_GEM_DOMAIN_GTT,
 249                                             &ring->ring_obj,
 250                                             &ring->gpu_addr,
 251                                             (void **)&ring->ring);
 252                 if (r) {
 253                         dev_err(adev->dev, "(%d) ring create failed\n", r);
 254                         return r;
 255                 }
 256                 amdgpu_ring_clear_ring(ring);
 257         }
 258
 259         ring->max_dw = max_dw;
 260         ring->priority = DRM_SCHED_PRIORITY_NORMAL;
 261         mutex_init(&ring->priority_mutex);
 262
 263         if (ring->funcs->type >= AMDGPU_RING_TYPE_GFX &&
 264             ring->funcs->type <= AMDGPU_RING_TYPE_VCN_JPEG) {
 265                 hw_ip = ring->funcs->type;
 266                 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
 267                 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
 268                         &ring->sched;
 269         }
 270
 271         for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
 272                 atomic_set(&ring->num_jobs[i], 0);
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * amdgpu_ring_fini - tear down the driver ring struct.
 279  *
 280  * @adev: amdgpu_device pointer
 281  * @ring: amdgpu_ring structure holding ring information
 282  *
 283  * Tear down the driver information for the selected ring (all asics).
 284  */
 285 void amdgpu_ring_fini(struct amdgpu_ring *ring)
 286 {
 287
 288         /* Not to finish a ring which is not initialized */
 289         if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
 290                 return;
 291
 292         ring->sched.ready = false;
 293
 294         amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
 295         amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
 296
 297         amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
 298         amdgpu_device_wb_free(ring->adev, ring->fence_offs);
 299
 300         amdgpu_bo_free_kernel(&ring->ring_obj,
 301                               &ring->gpu_addr,
 302                               (void **)&ring->ring);
 303
 304         dma_fence_put(ring->vmid_wait);
 305         ring->vmid_wait = NULL;
 306         ring->me = 0;
 307
 308         ring->adev->rings[ring->idx] = NULL;
 309 }
 310
 311 /**
 312  * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
 313  *
 314  * @adev: amdgpu_device pointer
 315  * @reg0: register to write
 316  * @reg1: register to wait on
 317  * @ref: reference value to write/wait on
 318  * @mask: mask to wait on
 319  *
 320  * Helper for rings that don't support write and wait in a
 321  * single oneshot packet.
 322  */
 323 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
 324                                                 uint32_t reg0, uint32_t reg1,
 325                                                 uint32_t ref, uint32_t mask)
 326 {
 327         amdgpu_ring_emit_wreg(ring, reg0, ref);
 328         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
 329 }
 330
 331 /**
 332  * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
 333  *
 334  * @ring: ring to try the recovery on
 335  * @vmid: VMID we try to get going again
 336  * @fence: timedout fence
 337  *
 338  * Tries to get a ring proceeding again when it is stuck.
 339  */
 340 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
 341                                struct dma_fence *fence)
 342 {
 343         ktime_t deadline = ktime_add_us(ktime_get(), 10000);
 344
 345         if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
 346                 return false;
 347
 348         atomic_inc(&ring->adev->gpu_reset_counter);
 349         while (!dma_fence_is_signaled(fence) &&
 350                ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
 351                 ring->funcs->soft_recovery(ring, vmid);
 352
 353         return dma_fence_is_signaled(fence);
 354 }
 355
 356 /*
 357  * Debugfs info
 358  */
 359 #if defined(CONFIG_DEBUG_FS)
 360
 361 /* Layout of file is 12 bytes consisting of
 362  * - rptr
 363  * - wptr
 364  * - driver's copy of wptr
 365  *
 366  * followed by n-words of ring data
 367  */
 368 static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
 369                                         size_t size, loff_t *pos)
 370 {
 371         struct amdgpu_ring *ring = file_inode(f)->i_private;
 372         int r, i;
 373         uint32_t value, result, early[3];
 374
 375         if (*pos & 3 || size & 3)
 376                 return -EINVAL;
 377
 378         result = 0;
 379
 380         if (*pos < 12) {
 381                 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
 382                 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
 383                 early[2] = ring->wptr & ring->buf_mask;
 384                 for (i = *pos / 4; i < 3 && size; i++) {
 385                         r = put_user(early[i], (uint32_t *)buf);
 386                         if (r)
 387                                 return r;
 388                         buf += 4;
 389                         result += 4;
 390                         size -= 4;
 391                         *pos += 4;
 392                 }
 393         }
 394
 395         while (size) {
 396                 if (*pos >= (ring->ring_size + 12))
 397                         return result;
 398
 399                 value = ring->ring[(*pos - 12)/4];
 400                 r = put_user(value, (uint32_t*)buf);
 401                 if (r)
 402                         return r;
 403                 buf += 4;
 404                 result += 4;
 405                 size -= 4;
 406                 *pos += 4;
 407         }
 408
 409         return result;
 410 }
 411
 412 static const struct file_operations amdgpu_debugfs_ring_fops = {
 413         .owner = THIS_MODULE,
 414         .read = amdgpu_debugfs_ring_read,
 415         .llseek = default_llseek
 416 };
 417
 418 #endif
 419
 420 int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
 421                              struct amdgpu_ring *ring)
 422 {
 423 #if defined(CONFIG_DEBUG_FS)
 424         struct drm_minor *minor = adev->ddev->primary;
 425         struct dentry *ent, *root = minor->debugfs_root;
 426         char name[32];
 427
 428         sprintf(name, "amdgpu_ring_%s", ring->name);
 429
 430         ent = debugfs_create_file(name,
 431                                   S_IFREG | S_IRUGO, root,
 432                                   ring, &amdgpu_debugfs_ring_fops);
 433         if (!ent)
 434                 return -ENOMEM;
 435
 436         i_size_write(ent->d_inode, ring->ring_size + 12);
 437         ring->ent = ent;
 438 #endif
 439         return 0;
 440 }
 441
 442 /**
 443  * amdgpu_ring_test_helper - tests ring and set sched readiness status
 444  *
 445  * @ring: ring to try the recovery on
 446  *
 447  * Tests ring and set sched readiness status
 448  *
 449  * Returns 0 on success, error on failure.
 450  */
 451 int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
 452 {
 453         struct amdgpu_device *adev = ring->adev;
 454         int r;
 455
 456         r = amdgpu_ring_test_ring(ring);
 457         if (r)
 458                 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
 459                               ring->name, r);
 460         else
 461                 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
 462                               ring->name);
 463
 464         ring->sched.ready = !r;
 465         return r;
 466 }