drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37
  38 #define MAX_NUM_OF_FEATURES_PER_SUBSET          8
  39 #define MAX_NUM_OF_SUBSETS                      8
  40
  41 struct od_attribute {
  42         struct kobj_attribute   attribute;
  43         struct list_head        entry;
  44 };
  45
  46 struct od_kobj {
  47         struct kobject          kobj;
  48         struct list_head        entry;
  49         struct list_head        attribute;
  50         void                    *priv;
  51 };
  52
  53 struct od_feature_ops {
  54         umode_t (*is_visible)(struct amdgpu_device *adev);
  55         ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
  56                         char *buf);
  57         ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
  58                          const char *buf, size_t count);
  59 };
  60
  61 struct od_feature_item {
  62         const char              *name;
  63         struct od_feature_ops   ops;
  64 };
  65
  66 struct od_feature_container {
  67         char                            *name;
  68         struct od_feature_ops           ops;
  69         struct od_feature_item          sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET];
  70 };
  71
  72 struct od_feature_set {
  73         struct od_feature_container     containers[MAX_NUM_OF_SUBSETS];
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 const char * const amdgpu_pp_profile_name[] = {
  86         "BOOTUP_DEFAULT",
  87         "3D_FULL_SCREEN",
  88         "POWER_SAVING",
  89         "VIDEO",
  90         "VR",
  91         "COMPUTE",
  92         "CUSTOM",
  93         "WINDOW_3D",
  94         "CAPPED",
  95         "UNCAPPED",
  96 };
  97
  98 /**
  99  * DOC: power_dpm_state
 100  *
 101  * The power_dpm_state file is a legacy interface and is only provided for
 102  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 103  * certain power related parameters.  The file power_dpm_state is used for this.
 104  * It accepts the following arguments:
 105  *
 106  * - battery
 107  *
 108  * - balanced
 109  *
 110  * - performance
 111  *
 112  * battery
 113  *
 114  * On older GPUs, the vbios provided a special power state for battery
 115  * operation.  Selecting battery switched to this state.  This is no
 116  * longer provided on newer GPUs so the option does nothing in that case.
 117  *
 118  * balanced
 119  *
 120  * On older GPUs, the vbios provided a special power state for balanced
 121  * operation.  Selecting balanced switched to this state.  This is no
 122  * longer provided on newer GPUs so the option does nothing in that case.
 123  *
 124  * performance
 125  *
 126  * On older GPUs, the vbios provided a special power state for performance
 127  * operation.  Selecting performance switched to this state.  This is no
 128  * longer provided on newer GPUs so the option does nothing in that case.
 129  *
 130  */
 131
 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 133                                           struct device_attribute *attr,
 134                                           char *buf)
 135 {
 136         struct drm_device *ddev = dev_get_drvdata(dev);
 137         struct amdgpu_device *adev = drm_to_adev(ddev);
 138         enum amd_pm_state_type pm;
 139         int ret;
 140
 141         if (amdgpu_in_reset(adev))
 142                 return -EPERM;
 143         if (adev->in_suspend && !adev->in_runpm)
 144                 return -EPERM;
 145
 146         ret = pm_runtime_get_sync(ddev->dev);
 147         if (ret < 0) {
 148                 pm_runtime_put_autosuspend(ddev->dev);
 149                 return ret;
 150         }
 151
 152         amdgpu_dpm_get_current_power_state(adev, &pm);
 153
 154         pm_runtime_mark_last_busy(ddev->dev);
 155         pm_runtime_put_autosuspend(ddev->dev);
 156
 157         return sysfs_emit(buf, "%s\n",
 158                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 159                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 160 }
 161
 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 163                                           struct device_attribute *attr,
 164                                           const char *buf,
 165                                           size_t count)
 166 {
 167         struct drm_device *ddev = dev_get_drvdata(dev);
 168         struct amdgpu_device *adev = drm_to_adev(ddev);
 169         enum amd_pm_state_type  state;
 170         int ret;
 171
 172         if (amdgpu_in_reset(adev))
 173                 return -EPERM;
 174         if (adev->in_suspend && !adev->in_runpm)
 175                 return -EPERM;
 176
 177         if (strncmp("battery", buf, strlen("battery")) == 0)
 178                 state = POWER_STATE_TYPE_BATTERY;
 179         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180                 state = POWER_STATE_TYPE_BALANCED;
 181         else if (strncmp("performance", buf, strlen("performance")) == 0)
 182                 state = POWER_STATE_TYPE_PERFORMANCE;
 183         else
 184                 return -EINVAL;
 185
 186         ret = pm_runtime_get_sync(ddev->dev);
 187         if (ret < 0) {
 188                 pm_runtime_put_autosuspend(ddev->dev);
 189                 return ret;
 190         }
 191
 192         amdgpu_dpm_set_power_state(adev, state);
 193
 194         pm_runtime_mark_last_busy(ddev->dev);
 195         pm_runtime_put_autosuspend(ddev->dev);
 196
 197         return count;
 198 }
 199
 200
 201 /**
 202  * DOC: power_dpm_force_performance_level
 203  *
 204  * The amdgpu driver provides a sysfs API for adjusting certain power
 205  * related parameters.  The file power_dpm_force_performance_level is
 206  * used for this.  It accepts the following arguments:
 207  *
 208  * - auto
 209  *
 210  * - low
 211  *
 212  * - high
 213  *
 214  * - manual
 215  *
 216  * - profile_standard
 217  *
 218  * - profile_min_sclk
 219  *
 220  * - profile_min_mclk
 221  *
 222  * - profile_peak
 223  *
 224  * auto
 225  *
 226  * When auto is selected, the driver will attempt to dynamically select
 227  * the optimal power profile for current conditions in the driver.
 228  *
 229  * low
 230  *
 231  * When low is selected, the clocks are forced to the lowest power state.
 232  *
 233  * high
 234  *
 235  * When high is selected, the clocks are forced to the highest power state.
 236  *
 237  * manual
 238  *
 239  * When manual is selected, the user can manually adjust which power states
 240  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 241  * and pp_dpm_pcie files and adjust the power state transition heuristics
 242  * via the pp_power_profile_mode sysfs file.
 243  *
 244  * profile_standard
 245  * profile_min_sclk
 246  * profile_min_mclk
 247  * profile_peak
 248  *
 249  * When the profiling modes are selected, clock and power gating are
 250  * disabled and the clocks are set for different profiling cases. This
 251  * mode is recommended for profiling specific work loads where you do
 252  * not want clock or power gating for clock fluctuation to interfere
 253  * with your results. profile_standard sets the clocks to a fixed clock
 254  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 255  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 256  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 257  *
 258  */
 259
 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 261                                                             struct device_attribute *attr,
 262                                                             char *buf)
 263 {
 264         struct drm_device *ddev = dev_get_drvdata(dev);
 265         struct amdgpu_device *adev = drm_to_adev(ddev);
 266         enum amd_dpm_forced_level level = 0xff;
 267         int ret;
 268
 269         if (amdgpu_in_reset(adev))
 270                 return -EPERM;
 271         if (adev->in_suspend && !adev->in_runpm)
 272                 return -EPERM;
 273
 274         ret = pm_runtime_get_sync(ddev->dev);
 275         if (ret < 0) {
 276                 pm_runtime_put_autosuspend(ddev->dev);
 277                 return ret;
 278         }
 279
 280         level = amdgpu_dpm_get_performance_level(adev);
 281
 282         pm_runtime_mark_last_busy(ddev->dev);
 283         pm_runtime_put_autosuspend(ddev->dev);
 284
 285         return sysfs_emit(buf, "%s\n",
 286                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 287                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 288                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 289                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 290                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 291                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 292                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 293                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 294                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 295                           "unknown");
 296 }
 297
 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 299                                                             struct device_attribute *attr,
 300                                                             const char *buf,
 301                                                             size_t count)
 302 {
 303         struct drm_device *ddev = dev_get_drvdata(dev);
 304         struct amdgpu_device *adev = drm_to_adev(ddev);
 305         enum amd_dpm_forced_level level;
 306         int ret = 0;
 307
 308         if (amdgpu_in_reset(adev))
 309                 return -EPERM;
 310         if (adev->in_suspend && !adev->in_runpm)
 311                 return -EPERM;
 312
 313         if (strncmp("low", buf, strlen("low")) == 0) {
 314                 level = AMD_DPM_FORCED_LEVEL_LOW;
 315         } else if (strncmp("high", buf, strlen("high")) == 0) {
 316                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 317         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 318                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 319         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 321         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 323         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 325         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 327         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 329         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 331         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 333         }  else {
 334                 return -EINVAL;
 335         }
 336
 337         ret = pm_runtime_get_sync(ddev->dev);
 338         if (ret < 0) {
 339                 pm_runtime_put_autosuspend(ddev->dev);
 340                 return ret;
 341         }
 342
 343         mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 344         if (amdgpu_dpm_force_performance_level(adev, level)) {
 345                 pm_runtime_mark_last_busy(ddev->dev);
 346                 pm_runtime_put_autosuspend(ddev->dev);
 347                 mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 348                 return -EINVAL;
 349         }
 350         /* override whatever a user ctx may have set */
 351         adev->pm.stable_pstate_ctx = NULL;
 352         mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 353
 354         pm_runtime_mark_last_busy(ddev->dev);
 355         pm_runtime_put_autosuspend(ddev->dev);
 356
 357         return count;
 358 }
 359
 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 361                 struct device_attribute *attr,
 362                 char *buf)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct amdgpu_device *adev = drm_to_adev(ddev);
 366         struct pp_states_info data;
 367         uint32_t i;
 368         int buf_len, ret;
 369
 370         if (amdgpu_in_reset(adev))
 371                 return -EPERM;
 372         if (adev->in_suspend && !adev->in_runpm)
 373                 return -EPERM;
 374
 375         ret = pm_runtime_get_sync(ddev->dev);
 376         if (ret < 0) {
 377                 pm_runtime_put_autosuspend(ddev->dev);
 378                 return ret;
 379         }
 380
 381         if (amdgpu_dpm_get_pp_num_states(adev, &data))
 382                 memset(&data, 0, sizeof(data));
 383
 384         pm_runtime_mark_last_busy(ddev->dev);
 385         pm_runtime_put_autosuspend(ddev->dev);
 386
 387         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 388         for (i = 0; i < data.nums; i++)
 389                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 390                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 391                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 392                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 393                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 394
 395         return buf_len;
 396 }
 397
 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 399                 struct device_attribute *attr,
 400                 char *buf)
 401 {
 402         struct drm_device *ddev = dev_get_drvdata(dev);
 403         struct amdgpu_device *adev = drm_to_adev(ddev);
 404         struct pp_states_info data = {0};
 405         enum amd_pm_state_type pm = 0;
 406         int i = 0, ret = 0;
 407
 408         if (amdgpu_in_reset(adev))
 409                 return -EPERM;
 410         if (adev->in_suspend && !adev->in_runpm)
 411                 return -EPERM;
 412
 413         ret = pm_runtime_get_sync(ddev->dev);
 414         if (ret < 0) {
 415                 pm_runtime_put_autosuspend(ddev->dev);
 416                 return ret;
 417         }
 418
 419         amdgpu_dpm_get_current_power_state(adev, &pm);
 420
 421         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 422
 423         pm_runtime_mark_last_busy(ddev->dev);
 424         pm_runtime_put_autosuspend(ddev->dev);
 425
 426         if (ret)
 427                 return ret;
 428
 429         for (i = 0; i < data.nums; i++) {
 430                 if (pm == data.states[i])
 431                         break;
 432         }
 433
 434         if (i == data.nums)
 435                 i = -EINVAL;
 436
 437         return sysfs_emit(buf, "%d\n", i);
 438 }
 439
 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 441                 struct device_attribute *attr,
 442                 char *buf)
 443 {
 444         struct drm_device *ddev = dev_get_drvdata(dev);
 445         struct amdgpu_device *adev = drm_to_adev(ddev);
 446
 447         if (amdgpu_in_reset(adev))
 448                 return -EPERM;
 449         if (adev->in_suspend && !adev->in_runpm)
 450                 return -EPERM;
 451
 452         if (adev->pm.pp_force_state_enabled)
 453                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 454         else
 455                 return sysfs_emit(buf, "\n");
 456 }
 457
 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 459                 struct device_attribute *attr,
 460                 const char *buf,
 461                 size_t count)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = drm_to_adev(ddev);
 465         enum amd_pm_state_type state = 0;
 466         struct pp_states_info data;
 467         unsigned long idx;
 468         int ret;
 469
 470         if (amdgpu_in_reset(adev))
 471                 return -EPERM;
 472         if (adev->in_suspend && !adev->in_runpm)
 473                 return -EPERM;
 474
 475         adev->pm.pp_force_state_enabled = false;
 476
 477         if (strlen(buf) == 1)
 478                 return count;
 479
 480         ret = kstrtoul(buf, 0, &idx);
 481         if (ret || idx >= ARRAY_SIZE(data.states))
 482                 return -EINVAL;
 483
 484         idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 485
 486         ret = pm_runtime_get_sync(ddev->dev);
 487         if (ret < 0) {
 488                 pm_runtime_put_autosuspend(ddev->dev);
 489                 return ret;
 490         }
 491
 492         ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 493         if (ret)
 494                 goto err_out;
 495
 496         state = data.states[idx];
 497
 498         /* only set user selected power states */
 499         if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 500             state != POWER_STATE_TYPE_DEFAULT) {
 501                 ret = amdgpu_dpm_dispatch_task(adev,
 502                                 AMD_PP_TASK_ENABLE_USER_STATE, &state);
 503                 if (ret)
 504                         goto err_out;
 505
 506                 adev->pm.pp_force_state_enabled = true;
 507         }
 508
 509         pm_runtime_mark_last_busy(ddev->dev);
 510         pm_runtime_put_autosuspend(ddev->dev);
 511
 512         return count;
 513
 514 err_out:
 515         pm_runtime_mark_last_busy(ddev->dev);
 516         pm_runtime_put_autosuspend(ddev->dev);
 517         return ret;
 518 }
 519
 520 /**
 521  * DOC: pp_table
 522  *
 523  * The amdgpu driver provides a sysfs API for uploading new powerplay
 524  * tables.  The file pp_table is used for this.  Reading the file
 525  * will dump the current power play table.  Writing to the file
 526  * will attempt to upload a new powerplay table and re-initialize
 527  * powerplay using that new table.
 528  *
 529  */
 530
 531 static ssize_t amdgpu_get_pp_table(struct device *dev,
 532                 struct device_attribute *attr,
 533                 char *buf)
 534 {
 535         struct drm_device *ddev = dev_get_drvdata(dev);
 536         struct amdgpu_device *adev = drm_to_adev(ddev);
 537         char *table = NULL;
 538         int size, ret;
 539
 540         if (amdgpu_in_reset(adev))
 541                 return -EPERM;
 542         if (adev->in_suspend && !adev->in_runpm)
 543                 return -EPERM;
 544
 545         ret = pm_runtime_get_sync(ddev->dev);
 546         if (ret < 0) {
 547                 pm_runtime_put_autosuspend(ddev->dev);
 548                 return ret;
 549         }
 550
 551         size = amdgpu_dpm_get_pp_table(adev, &table);
 552
 553         pm_runtime_mark_last_busy(ddev->dev);
 554         pm_runtime_put_autosuspend(ddev->dev);
 555
 556         if (size <= 0)
 557                 return size;
 558
 559         if (size >= PAGE_SIZE)
 560                 size = PAGE_SIZE - 1;
 561
 562         memcpy(buf, table, size);
 563
 564         return size;
 565 }
 566
 567 static ssize_t amdgpu_set_pp_table(struct device *dev,
 568                 struct device_attribute *attr,
 569                 const char *buf,
 570                 size_t count)
 571 {
 572         struct drm_device *ddev = dev_get_drvdata(dev);
 573         struct amdgpu_device *adev = drm_to_adev(ddev);
 574         int ret = 0;
 575
 576         if (amdgpu_in_reset(adev))
 577                 return -EPERM;
 578         if (adev->in_suspend && !adev->in_runpm)
 579                 return -EPERM;
 580
 581         ret = pm_runtime_get_sync(ddev->dev);
 582         if (ret < 0) {
 583                 pm_runtime_put_autosuspend(ddev->dev);
 584                 return ret;
 585         }
 586
 587         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 588
 589         pm_runtime_mark_last_busy(ddev->dev);
 590         pm_runtime_put_autosuspend(ddev->dev);
 591
 592         if (ret)
 593                 return ret;
 594
 595         return count;
 596 }
 597
 598 /**
 599  * DOC: pp_od_clk_voltage
 600  *
 601  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 602  * in each power level within a power state.  The pp_od_clk_voltage is used for
 603  * this.
 604  *
 605  * Note that the actual memory controller clock rate are exposed, not
 606  * the effective memory clock of the DRAMs. To translate it, use the
 607  * following formula:
 608  *
 609  * Clock conversion (Mhz):
 610  *
 611  * HBM: effective_memory_clock = memory_controller_clock * 1
 612  *
 613  * G5: effective_memory_clock = memory_controller_clock * 1
 614  *
 615  * G6: effective_memory_clock = memory_controller_clock * 2
 616  *
 617  * DRAM data rate (MT/s):
 618  *
 619  * HBM: effective_memory_clock * 2 = data_rate
 620  *
 621  * G5: effective_memory_clock * 4 = data_rate
 622  *
 623  * G6: effective_memory_clock * 8 = data_rate
 624  *
 625  * Bandwidth (MB/s):
 626  *
 627  * data_rate * vram_bit_width / 8 = memory_bandwidth
 628  *
 629  * Some examples:
 630  *
 631  * G5 on RX460:
 632  *
 633  * memory_controller_clock = 1750 Mhz
 634  *
 635  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 636  *
 637  * data rate = 1750 * 4 = 7000 MT/s
 638  *
 639  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 640  *
 641  * G6 on RX5700:
 642  *
 643  * memory_controller_clock = 875 Mhz
 644  *
 645  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 646  *
 647  * data rate = 1750 * 8 = 14000 MT/s
 648  *
 649  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 650  *
 651  * < For Vega10 and previous ASICs >
 652  *
 653  * Reading the file will display:
 654  *
 655  * - a list of engine clock levels and voltages labeled OD_SCLK
 656  *
 657  * - a list of memory clock levels and voltages labeled OD_MCLK
 658  *
 659  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 660  *
 661  * To manually adjust these settings, first select manual using
 662  * power_dpm_force_performance_level. Enter a new value for each
 663  * level by writing a string that contains "s/m level clock voltage" to
 664  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 665  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 666  * 810 mV.  When you have edited all of the states as needed, write
 667  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 668  * default power levels, write "r" (reset) to the file to reset them.
 669  *
 670  *
 671  * < For Vega20 and newer ASICs >
 672  *
 673  * Reading the file will display:
 674  *
 675  * - minimum and maximum engine clock labeled OD_SCLK
 676  *
 677  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 678  *   clock labeled OD_MCLK
 679  *
 680  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 681  *   They can be used to calibrate the sclk voltage curve. This is
 682  *   available for Vega20 and NV1X.
 683  *
 684  * - voltage offset(in mV) applied on target voltage calculation.
 685  *   This is available for Sienna Cichlid, Navy Flounder, Dimgrey
 686  *   Cavefish and some later SMU13 ASICs. For these ASICs, the target
 687  *   voltage calculation can be illustrated by "voltage = voltage
 688  *   calculated from v/f curve + overdrive vddgfx offset"
 689  *
 690  * - a list of valid ranges for sclk, mclk, voltage curve points
 691  *   or voltage offset labeled OD_RANGE
 692  *
 693  * < For APUs >
 694  *
 695  * Reading the file will display:
 696  *
 697  * - minimum and maximum engine clock labeled OD_SCLK
 698  *
 699  * - a list of valid ranges for sclk labeled OD_RANGE
 700  *
 701  * < For VanGogh >
 702  *
 703  * Reading the file will display:
 704  *
 705  * - minimum and maximum engine clock labeled OD_SCLK
 706  * - minimum and maximum core clocks labeled OD_CCLK
 707  *
 708  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 709  *
 710  * To manually adjust these settings:
 711  *
 712  * - First select manual using power_dpm_force_performance_level
 713  *
 714  * - For clock frequency setting, enter a new value by writing a
 715  *   string that contains "s/m index clock" to the file. The index
 716  *   should be 0 if to set minimum clock. And 1 if to set maximum
 717  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 718  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 719  *   clocks on VanGogh, the string contains "p core index clock".
 720  *   E.g., "p 2 0 800" would set the minimum core clock on core
 721  *   2 to 800Mhz.
 722  *
 723  *   For sclk voltage curve supported by Vega20 and NV1X, enter the new
 724  *   values by writing a string that contains "vc point clock voltage"
 725  *   to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
 726  *   600" will update point1 with clock set as 300Mhz and voltage as 600mV.
 727  *   "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
 728  *   voltage 1000mV.
 729  *
 730  *   For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
 731  *   Cavefish and some later SMU13 ASICs, enter the new value by writing a
 732  *   string that contains "vo offset". E.g., "vo -10" will update the extra
 733  *   voltage offset applied to the whole v/f curve line as -10mv.
 734  *
 735  * - When you have edited all of the states as needed, write "c" (commit)
 736  *   to the file to commit your changes
 737  *
 738  * - If you want to reset to the default power levels, write "r" (reset)
 739  *   to the file to reset them
 740  *
 741  */
 742
 743 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 744                 struct device_attribute *attr,
 745                 const char *buf,
 746                 size_t count)
 747 {
 748         struct drm_device *ddev = dev_get_drvdata(dev);
 749         struct amdgpu_device *adev = drm_to_adev(ddev);
 750         int ret;
 751         uint32_t parameter_size = 0;
 752         long parameter[64];
 753         char buf_cpy[128];
 754         char *tmp_str;
 755         char *sub_str;
 756         const char delimiter[3] = {' ', '\n', '\0'};
 757         uint32_t type;
 758
 759         if (amdgpu_in_reset(adev))
 760                 return -EPERM;
 761         if (adev->in_suspend && !adev->in_runpm)
 762                 return -EPERM;
 763
 764         if (count > 127 || count == 0)
 765                 return -EINVAL;
 766
 767         if (*buf == 's')
 768                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 769         else if (*buf == 'p')
 770                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 771         else if (*buf == 'm')
 772                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 773         else if (*buf == 'r')
 774                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 775         else if (*buf == 'c')
 776                 type = PP_OD_COMMIT_DPM_TABLE;
 777         else if (!strncmp(buf, "vc", 2))
 778                 type = PP_OD_EDIT_VDDC_CURVE;
 779         else if (!strncmp(buf, "vo", 2))
 780                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 781         else
 782                 return -EINVAL;
 783
 784         memcpy(buf_cpy, buf, count);
 785         buf_cpy[count] = 0;
 786
 787         tmp_str = buf_cpy;
 788
 789         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 790              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 791                 tmp_str++;
 792         while (isspace(*++tmp_str));
 793
 794         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 795                 if (strlen(sub_str) == 0)
 796                         continue;
 797                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 798                 if (ret)
 799                         return -EINVAL;
 800                 parameter_size++;
 801
 802                 if (!tmp_str)
 803                         break;
 804
 805                 while (isspace(*tmp_str))
 806                         tmp_str++;
 807         }
 808
 809         ret = pm_runtime_get_sync(ddev->dev);
 810         if (ret < 0) {
 811                 pm_runtime_put_autosuspend(ddev->dev);
 812                 return ret;
 813         }
 814
 815         if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 816                                               type,
 817                                               parameter,
 818                                               parameter_size))
 819                 goto err_out;
 820
 821         if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 822                                           parameter, parameter_size))
 823                 goto err_out;
 824
 825         if (type == PP_OD_COMMIT_DPM_TABLE) {
 826                 if (amdgpu_dpm_dispatch_task(adev,
 827                                              AMD_PP_TASK_READJUST_POWER_STATE,
 828                                              NULL))
 829                         goto err_out;
 830         }
 831
 832         pm_runtime_mark_last_busy(ddev->dev);
 833         pm_runtime_put_autosuspend(ddev->dev);
 834
 835         return count;
 836
 837 err_out:
 838         pm_runtime_mark_last_busy(ddev->dev);
 839         pm_runtime_put_autosuspend(ddev->dev);
 840         return -EINVAL;
 841 }
 842
 843 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 844                 struct device_attribute *attr,
 845                 char *buf)
 846 {
 847         struct drm_device *ddev = dev_get_drvdata(dev);
 848         struct amdgpu_device *adev = drm_to_adev(ddev);
 849         int size = 0;
 850         int ret;
 851         enum pp_clock_type od_clocks[6] = {
 852                 OD_SCLK,
 853                 OD_MCLK,
 854                 OD_VDDC_CURVE,
 855                 OD_RANGE,
 856                 OD_VDDGFX_OFFSET,
 857                 OD_CCLK,
 858         };
 859         uint clk_index;
 860
 861         if (amdgpu_in_reset(adev))
 862                 return -EPERM;
 863         if (adev->in_suspend && !adev->in_runpm)
 864                 return -EPERM;
 865
 866         ret = pm_runtime_get_sync(ddev->dev);
 867         if (ret < 0) {
 868                 pm_runtime_put_autosuspend(ddev->dev);
 869                 return ret;
 870         }
 871
 872         for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 873                 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 874                 if (ret)
 875                         break;
 876         }
 877         if (ret == -ENOENT) {
 878                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 879                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 880                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 881                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 882                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 883                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 884         }
 885
 886         if (size == 0)
 887                 size = sysfs_emit(buf, "\n");
 888
 889         pm_runtime_mark_last_busy(ddev->dev);
 890         pm_runtime_put_autosuspend(ddev->dev);
 891
 892         return size;
 893 }
 894
 895 /**
 896  * DOC: pp_features
 897  *
 898  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 899  * features to be enabled. The file pp_features is used for this. And
 900  * this is only available for Vega10 and later dGPUs.
 901  *
 902  * Reading back the file will show you the followings:
 903  * - Current ppfeature masks
 904  * - List of the all supported powerplay features with their naming,
 905  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 906  *
 907  * To manually enable or disable a specific feature, just set or clear
 908  * the corresponding bit from original ppfeature masks and input the
 909  * new ppfeature masks.
 910  */
 911 static ssize_t amdgpu_set_pp_features(struct device *dev,
 912                                       struct device_attribute *attr,
 913                                       const char *buf,
 914                                       size_t count)
 915 {
 916         struct drm_device *ddev = dev_get_drvdata(dev);
 917         struct amdgpu_device *adev = drm_to_adev(ddev);
 918         uint64_t featuremask;
 919         int ret;
 920
 921         if (amdgpu_in_reset(adev))
 922                 return -EPERM;
 923         if (adev->in_suspend && !adev->in_runpm)
 924                 return -EPERM;
 925
 926         ret = kstrtou64(buf, 0, &featuremask);
 927         if (ret)
 928                 return -EINVAL;
 929
 930         ret = pm_runtime_get_sync(ddev->dev);
 931         if (ret < 0) {
 932                 pm_runtime_put_autosuspend(ddev->dev);
 933                 return ret;
 934         }
 935
 936         ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 937
 938         pm_runtime_mark_last_busy(ddev->dev);
 939         pm_runtime_put_autosuspend(ddev->dev);
 940
 941         if (ret)
 942                 return -EINVAL;
 943
 944         return count;
 945 }
 946
 947 static ssize_t amdgpu_get_pp_features(struct device *dev,
 948                                       struct device_attribute *attr,
 949                                       char *buf)
 950 {
 951         struct drm_device *ddev = dev_get_drvdata(dev);
 952         struct amdgpu_device *adev = drm_to_adev(ddev);
 953         ssize_t size;
 954         int ret;
 955
 956         if (amdgpu_in_reset(adev))
 957                 return -EPERM;
 958         if (adev->in_suspend && !adev->in_runpm)
 959                 return -EPERM;
 960
 961         ret = pm_runtime_get_sync(ddev->dev);
 962         if (ret < 0) {
 963                 pm_runtime_put_autosuspend(ddev->dev);
 964                 return ret;
 965         }
 966
 967         size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 968         if (size <= 0)
 969                 size = sysfs_emit(buf, "\n");
 970
 971         pm_runtime_mark_last_busy(ddev->dev);
 972         pm_runtime_put_autosuspend(ddev->dev);
 973
 974         return size;
 975 }
 976
 977 /**
 978  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 979  *
 980  * The amdgpu driver provides a sysfs API for adjusting what power levels
 981  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 982  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 983  * this.
 984  *
 985  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 986  * Vega10 and later ASICs.
 987  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 988  *
 989  * Reading back the files will show you the available power levels within
 990  * the power state and the clock information for those levels. If deep sleep is
 991  * applied to a clock, the level will be denoted by a special level 'S:'
 992  * E.g.,
 993  *      S: 19Mhz *
 994  *      0: 615Mhz
 995  *      1: 800Mhz
 996  *      2: 888Mhz
 997  *      3: 1000Mhz
 998  *
 999  *
1000  * To manually adjust these states, first select manual using
1001  * power_dpm_force_performance_level.
1002  * Secondly, enter a new value for each level by inputing a string that
1003  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1004  * E.g.,
1005  *
1006  * .. code-block:: bash
1007  *
1008  *      echo "4 5 6" > pp_dpm_sclk
1009  *
1010  * will enable sclk levels 4, 5, and 6.
1011  *
1012  * NOTE: change to the dcefclk max dpm level is not supported now
1013  */
1014
1015 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1016                 enum pp_clock_type type,
1017                 char *buf)
1018 {
1019         struct drm_device *ddev = dev_get_drvdata(dev);
1020         struct amdgpu_device *adev = drm_to_adev(ddev);
1021         int size = 0;
1022         int ret = 0;
1023
1024         if (amdgpu_in_reset(adev))
1025                 return -EPERM;
1026         if (adev->in_suspend && !adev->in_runpm)
1027                 return -EPERM;
1028
1029         ret = pm_runtime_get_sync(ddev->dev);
1030         if (ret < 0) {
1031                 pm_runtime_put_autosuspend(ddev->dev);
1032                 return ret;
1033         }
1034
1035         ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1036         if (ret == -ENOENT)
1037                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1038
1039         if (size == 0)
1040                 size = sysfs_emit(buf, "\n");
1041
1042         pm_runtime_mark_last_busy(ddev->dev);
1043         pm_runtime_put_autosuspend(ddev->dev);
1044
1045         return size;
1046 }
1047
1048 /*
1049  * Worst case: 32 bits individually specified, in octal at 12 characters
1050  * per line (+1 for \n).
1051  */
1052 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1053
1054 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1055 {
1056         int ret;
1057         unsigned long level;
1058         char *sub_str = NULL;
1059         char *tmp;
1060         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1061         const char delimiter[3] = {' ', '\n', '\0'};
1062         size_t bytes;
1063
1064         *mask = 0;
1065
1066         bytes = min(count, sizeof(buf_cpy) - 1);
1067         memcpy(buf_cpy, buf, bytes);
1068         buf_cpy[bytes] = '\0';
1069         tmp = buf_cpy;
1070         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1071                 if (strlen(sub_str)) {
1072                         ret = kstrtoul(sub_str, 0, &level);
1073                         if (ret || level > 31)
1074                                 return -EINVAL;
1075                         *mask |= 1 << level;
1076                 } else
1077                         break;
1078         }
1079
1080         return 0;
1081 }
1082
1083 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1084                 enum pp_clock_type type,
1085                 const char *buf,
1086                 size_t count)
1087 {
1088         struct drm_device *ddev = dev_get_drvdata(dev);
1089         struct amdgpu_device *adev = drm_to_adev(ddev);
1090         int ret;
1091         uint32_t mask = 0;
1092
1093         if (amdgpu_in_reset(adev))
1094                 return -EPERM;
1095         if (adev->in_suspend && !adev->in_runpm)
1096                 return -EPERM;
1097
1098         ret = amdgpu_read_mask(buf, count, &mask);
1099         if (ret)
1100                 return ret;
1101
1102         ret = pm_runtime_get_sync(ddev->dev);
1103         if (ret < 0) {
1104                 pm_runtime_put_autosuspend(ddev->dev);
1105                 return ret;
1106         }
1107
1108         ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1109
1110         pm_runtime_mark_last_busy(ddev->dev);
1111         pm_runtime_put_autosuspend(ddev->dev);
1112
1113         if (ret)
1114                 return -EINVAL;
1115
1116         return count;
1117 }
1118
1119 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1120                 struct device_attribute *attr,
1121                 char *buf)
1122 {
1123         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1124 }
1125
1126 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1127                 struct device_attribute *attr,
1128                 const char *buf,
1129                 size_t count)
1130 {
1131         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1132 }
1133
1134 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1135                 struct device_attribute *attr,
1136                 char *buf)
1137 {
1138         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1139 }
1140
1141 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1142                 struct device_attribute *attr,
1143                 const char *buf,
1144                 size_t count)
1145 {
1146         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1147 }
1148
1149 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1150                 struct device_attribute *attr,
1151                 char *buf)
1152 {
1153         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1154 }
1155
1156 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1157                 struct device_attribute *attr,
1158                 const char *buf,
1159                 size_t count)
1160 {
1161         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1162 }
1163
1164 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1165                 struct device_attribute *attr,
1166                 char *buf)
1167 {
1168         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1169 }
1170
1171 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1172                 struct device_attribute *attr,
1173                 const char *buf,
1174                 size_t count)
1175 {
1176         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1177 }
1178
1179 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1180                 struct device_attribute *attr,
1181                 char *buf)
1182 {
1183         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1184 }
1185
1186 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1187                 struct device_attribute *attr,
1188                 const char *buf,
1189                 size_t count)
1190 {
1191         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1192 }
1193
1194 static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1195                 struct device_attribute *attr,
1196                 char *buf)
1197 {
1198         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1199 }
1200
1201 static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1202                 struct device_attribute *attr,
1203                 const char *buf,
1204                 size_t count)
1205 {
1206         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1207 }
1208
1209 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1210                 struct device_attribute *attr,
1211                 char *buf)
1212 {
1213         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1214 }
1215
1216 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1217                 struct device_attribute *attr,
1218                 const char *buf,
1219                 size_t count)
1220 {
1221         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1222 }
1223
1224 static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1225                 struct device_attribute *attr,
1226                 char *buf)
1227 {
1228         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1229 }
1230
1231 static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1232                 struct device_attribute *attr,
1233                 const char *buf,
1234                 size_t count)
1235 {
1236         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1237 }
1238
1239 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1240                 struct device_attribute *attr,
1241                 char *buf)
1242 {
1243         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1244 }
1245
1246 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1247                 struct device_attribute *attr,
1248                 const char *buf,
1249                 size_t count)
1250 {
1251         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1252 }
1253
1254 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1255                 struct device_attribute *attr,
1256                 char *buf)
1257 {
1258         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1259 }
1260
1261 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1262                 struct device_attribute *attr,
1263                 const char *buf,
1264                 size_t count)
1265 {
1266         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1267 }
1268
1269 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1270                 struct device_attribute *attr,
1271                 char *buf)
1272 {
1273         struct drm_device *ddev = dev_get_drvdata(dev);
1274         struct amdgpu_device *adev = drm_to_adev(ddev);
1275         uint32_t value = 0;
1276         int ret;
1277
1278         if (amdgpu_in_reset(adev))
1279                 return -EPERM;
1280         if (adev->in_suspend && !adev->in_runpm)
1281                 return -EPERM;
1282
1283         ret = pm_runtime_get_sync(ddev->dev);
1284         if (ret < 0) {
1285                 pm_runtime_put_autosuspend(ddev->dev);
1286                 return ret;
1287         }
1288
1289         value = amdgpu_dpm_get_sclk_od(adev);
1290
1291         pm_runtime_mark_last_busy(ddev->dev);
1292         pm_runtime_put_autosuspend(ddev->dev);
1293
1294         return sysfs_emit(buf, "%d\n", value);
1295 }
1296
1297 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1298                 struct device_attribute *attr,
1299                 const char *buf,
1300                 size_t count)
1301 {
1302         struct drm_device *ddev = dev_get_drvdata(dev);
1303         struct amdgpu_device *adev = drm_to_adev(ddev);
1304         int ret;
1305         long int value;
1306
1307         if (amdgpu_in_reset(adev))
1308                 return -EPERM;
1309         if (adev->in_suspend && !adev->in_runpm)
1310                 return -EPERM;
1311
1312         ret = kstrtol(buf, 0, &value);
1313
1314         if (ret)
1315                 return -EINVAL;
1316
1317         ret = pm_runtime_get_sync(ddev->dev);
1318         if (ret < 0) {
1319                 pm_runtime_put_autosuspend(ddev->dev);
1320                 return ret;
1321         }
1322
1323         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1324
1325         pm_runtime_mark_last_busy(ddev->dev);
1326         pm_runtime_put_autosuspend(ddev->dev);
1327
1328         return count;
1329 }
1330
1331 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1332                 struct device_attribute *attr,
1333                 char *buf)
1334 {
1335         struct drm_device *ddev = dev_get_drvdata(dev);
1336         struct amdgpu_device *adev = drm_to_adev(ddev);
1337         uint32_t value = 0;
1338         int ret;
1339
1340         if (amdgpu_in_reset(adev))
1341                 return -EPERM;
1342         if (adev->in_suspend && !adev->in_runpm)
1343                 return -EPERM;
1344
1345         ret = pm_runtime_get_sync(ddev->dev);
1346         if (ret < 0) {
1347                 pm_runtime_put_autosuspend(ddev->dev);
1348                 return ret;
1349         }
1350
1351         value = amdgpu_dpm_get_mclk_od(adev);
1352
1353         pm_runtime_mark_last_busy(ddev->dev);
1354         pm_runtime_put_autosuspend(ddev->dev);
1355
1356         return sysfs_emit(buf, "%d\n", value);
1357 }
1358
1359 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1360                 struct device_attribute *attr,
1361                 const char *buf,
1362                 size_t count)
1363 {
1364         struct drm_device *ddev = dev_get_drvdata(dev);
1365         struct amdgpu_device *adev = drm_to_adev(ddev);
1366         int ret;
1367         long int value;
1368
1369         if (amdgpu_in_reset(adev))
1370                 return -EPERM;
1371         if (adev->in_suspend && !adev->in_runpm)
1372                 return -EPERM;
1373
1374         ret = kstrtol(buf, 0, &value);
1375
1376         if (ret)
1377                 return -EINVAL;
1378
1379         ret = pm_runtime_get_sync(ddev->dev);
1380         if (ret < 0) {
1381                 pm_runtime_put_autosuspend(ddev->dev);
1382                 return ret;
1383         }
1384
1385         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1386
1387         pm_runtime_mark_last_busy(ddev->dev);
1388         pm_runtime_put_autosuspend(ddev->dev);
1389
1390         return count;
1391 }
1392
1393 /**
1394  * DOC: pp_power_profile_mode
1395  *
1396  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1397  * related to switching between power levels in a power state.  The file
1398  * pp_power_profile_mode is used for this.
1399  *
1400  * Reading this file outputs a list of all of the predefined power profiles
1401  * and the relevant heuristics settings for that profile.
1402  *
1403  * To select a profile or create a custom profile, first select manual using
1404  * power_dpm_force_performance_level.  Writing the number of a predefined
1405  * profile to pp_power_profile_mode will enable those heuristics.  To
1406  * create a custom set of heuristics, write a string of numbers to the file
1407  * starting with the number of the custom profile along with a setting
1408  * for each heuristic parameter.  Due to differences across asic families
1409  * the heuristic parameters vary from family to family.
1410  *
1411  */
1412
1413 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1414                 struct device_attribute *attr,
1415                 char *buf)
1416 {
1417         struct drm_device *ddev = dev_get_drvdata(dev);
1418         struct amdgpu_device *adev = drm_to_adev(ddev);
1419         ssize_t size;
1420         int ret;
1421
1422         if (amdgpu_in_reset(adev))
1423                 return -EPERM;
1424         if (adev->in_suspend && !adev->in_runpm)
1425                 return -EPERM;
1426
1427         ret = pm_runtime_get_sync(ddev->dev);
1428         if (ret < 0) {
1429                 pm_runtime_put_autosuspend(ddev->dev);
1430                 return ret;
1431         }
1432
1433         size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1434         if (size <= 0)
1435                 size = sysfs_emit(buf, "\n");
1436
1437         pm_runtime_mark_last_busy(ddev->dev);
1438         pm_runtime_put_autosuspend(ddev->dev);
1439
1440         return size;
1441 }
1442
1443
1444 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1445                 struct device_attribute *attr,
1446                 const char *buf,
1447                 size_t count)
1448 {
1449         int ret;
1450         struct drm_device *ddev = dev_get_drvdata(dev);
1451         struct amdgpu_device *adev = drm_to_adev(ddev);
1452         uint32_t parameter_size = 0;
1453         long parameter[64];
1454         char *sub_str, buf_cpy[128];
1455         char *tmp_str;
1456         uint32_t i = 0;
1457         char tmp[2];
1458         long int profile_mode = 0;
1459         const char delimiter[3] = {' ', '\n', '\0'};
1460
1461         if (amdgpu_in_reset(adev))
1462                 return -EPERM;
1463         if (adev->in_suspend && !adev->in_runpm)
1464                 return -EPERM;
1465
1466         tmp[0] = *(buf);
1467         tmp[1] = '\0';
1468         ret = kstrtol(tmp, 0, &profile_mode);
1469         if (ret)
1470                 return -EINVAL;
1471
1472         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1473                 if (count < 2 || count > 127)
1474                         return -EINVAL;
1475                 while (isspace(*++buf))
1476                         i++;
1477                 memcpy(buf_cpy, buf, count-i);
1478                 tmp_str = buf_cpy;
1479                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1480                         if (strlen(sub_str) == 0)
1481                                 continue;
1482                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1483                         if (ret)
1484                                 return -EINVAL;
1485                         parameter_size++;
1486                         while (isspace(*tmp_str))
1487                                 tmp_str++;
1488                 }
1489         }
1490         parameter[parameter_size] = profile_mode;
1491
1492         ret = pm_runtime_get_sync(ddev->dev);
1493         if (ret < 0) {
1494                 pm_runtime_put_autosuspend(ddev->dev);
1495                 return ret;
1496         }
1497
1498         ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1499
1500         pm_runtime_mark_last_busy(ddev->dev);
1501         pm_runtime_put_autosuspend(ddev->dev);
1502
1503         if (!ret)
1504                 return count;
1505
1506         return -EINVAL;
1507 }
1508
1509 static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1510                                            enum amd_pp_sensors sensor,
1511                                            void *query)
1512 {
1513         int r, size = sizeof(uint32_t);
1514
1515         if (amdgpu_in_reset(adev))
1516                 return -EPERM;
1517         if (adev->in_suspend && !adev->in_runpm)
1518                 return -EPERM;
1519
1520         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1521         if (r < 0) {
1522                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1523                 return r;
1524         }
1525
1526         /* get the sensor value */
1527         r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1528
1529         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1530         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1531
1532         return r;
1533 }
1534
1535 /**
1536  * DOC: gpu_busy_percent
1537  *
1538  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1539  * is as a percentage.  The file gpu_busy_percent is used for this.
1540  * The SMU firmware computes a percentage of load based on the
1541  * aggregate activity level in the IP cores.
1542  */
1543 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1544                                            struct device_attribute *attr,
1545                                            char *buf)
1546 {
1547         struct drm_device *ddev = dev_get_drvdata(dev);
1548         struct amdgpu_device *adev = drm_to_adev(ddev);
1549         unsigned int value;
1550         int r;
1551
1552         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1553         if (r)
1554                 return r;
1555
1556         return sysfs_emit(buf, "%d\n", value);
1557 }
1558
1559 /**
1560  * DOC: mem_busy_percent
1561  *
1562  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1563  * is as a percentage.  The file mem_busy_percent is used for this.
1564  * The SMU firmware computes a percentage of load based on the
1565  * aggregate activity level in the IP cores.
1566  */
1567 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1568                                            struct device_attribute *attr,
1569                                            char *buf)
1570 {
1571         struct drm_device *ddev = dev_get_drvdata(dev);
1572         struct amdgpu_device *adev = drm_to_adev(ddev);
1573         unsigned int value;
1574         int r;
1575
1576         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1577         if (r)
1578                 return r;
1579
1580         return sysfs_emit(buf, "%d\n", value);
1581 }
1582
1583 /**
1584  * DOC: pcie_bw
1585  *
1586  * The amdgpu driver provides a sysfs API for estimating how much data
1587  * has been received and sent by the GPU in the last second through PCIe.
1588  * The file pcie_bw is used for this.
1589  * The Perf counters count the number of received and sent messages and return
1590  * those values, as well as the maximum payload size of a PCIe packet (mps).
1591  * Note that it is not possible to easily and quickly obtain the size of each
1592  * packet transmitted, so we output the max payload size (mps) to allow for
1593  * quick estimation of the PCIe bandwidth usage
1594  */
1595 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1596                 struct device_attribute *attr,
1597                 char *buf)
1598 {
1599         struct drm_device *ddev = dev_get_drvdata(dev);
1600         struct amdgpu_device *adev = drm_to_adev(ddev);
1601         uint64_t count0 = 0, count1 = 0;
1602         int ret;
1603
1604         if (amdgpu_in_reset(adev))
1605                 return -EPERM;
1606         if (adev->in_suspend && !adev->in_runpm)
1607                 return -EPERM;
1608
1609         if (adev->flags & AMD_IS_APU)
1610                 return -ENODATA;
1611
1612         if (!adev->asic_funcs->get_pcie_usage)
1613                 return -ENODATA;
1614
1615         ret = pm_runtime_get_sync(ddev->dev);
1616         if (ret < 0) {
1617                 pm_runtime_put_autosuspend(ddev->dev);
1618                 return ret;
1619         }
1620
1621         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1622
1623         pm_runtime_mark_last_busy(ddev->dev);
1624         pm_runtime_put_autosuspend(ddev->dev);
1625
1626         return sysfs_emit(buf, "%llu %llu %i\n",
1627                           count0, count1, pcie_get_mps(adev->pdev));
1628 }
1629
1630 /**
1631  * DOC: unique_id
1632  *
1633  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1634  * The file unique_id is used for this.
1635  * This will provide a Unique ID that will persist from machine to machine
1636  *
1637  * NOTE: This will only work for GFX9 and newer. This file will be absent
1638  * on unsupported ASICs (GFX8 and older)
1639  */
1640 static ssize_t amdgpu_get_unique_id(struct device *dev,
1641                 struct device_attribute *attr,
1642                 char *buf)
1643 {
1644         struct drm_device *ddev = dev_get_drvdata(dev);
1645         struct amdgpu_device *adev = drm_to_adev(ddev);
1646
1647         if (amdgpu_in_reset(adev))
1648                 return -EPERM;
1649         if (adev->in_suspend && !adev->in_runpm)
1650                 return -EPERM;
1651
1652         if (adev->unique_id)
1653                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1654
1655         return 0;
1656 }
1657
1658 /**
1659  * DOC: thermal_throttling_logging
1660  *
1661  * Thermal throttling pulls down the clock frequency and thus the performance.
1662  * It's an useful mechanism to protect the chip from overheating. Since it
1663  * impacts performance, the user controls whether it is enabled and if so,
1664  * the log frequency.
1665  *
1666  * Reading back the file shows you the status(enabled or disabled) and
1667  * the interval(in seconds) between each thermal logging.
1668  *
1669  * Writing an integer to the file, sets a new logging interval, in seconds.
1670  * The value should be between 1 and 3600. If the value is less than 1,
1671  * thermal logging is disabled. Values greater than 3600 are ignored.
1672  */
1673 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1674                                                      struct device_attribute *attr,
1675                                                      char *buf)
1676 {
1677         struct drm_device *ddev = dev_get_drvdata(dev);
1678         struct amdgpu_device *adev = drm_to_adev(ddev);
1679
1680         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1681                           adev_to_drm(adev)->unique,
1682                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1683                           adev->throttling_logging_rs.interval / HZ + 1);
1684 }
1685
1686 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1687                                                      struct device_attribute *attr,
1688                                                      const char *buf,
1689                                                      size_t count)
1690 {
1691         struct drm_device *ddev = dev_get_drvdata(dev);
1692         struct amdgpu_device *adev = drm_to_adev(ddev);
1693         long throttling_logging_interval;
1694         unsigned long flags;
1695         int ret = 0;
1696
1697         ret = kstrtol(buf, 0, &throttling_logging_interval);
1698         if (ret)
1699                 return ret;
1700
1701         if (throttling_logging_interval > 3600)
1702                 return -EINVAL;
1703
1704         if (throttling_logging_interval > 0) {
1705                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1706                 /*
1707                  * Reset the ratelimit timer internals.
1708                  * This can effectively restart the timer.
1709                  */
1710                 adev->throttling_logging_rs.interval =
1711                         (throttling_logging_interval - 1) * HZ;
1712                 adev->throttling_logging_rs.begin = 0;
1713                 adev->throttling_logging_rs.printed = 0;
1714                 adev->throttling_logging_rs.missed = 0;
1715                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1716
1717                 atomic_set(&adev->throttling_logging_enabled, 1);
1718         } else {
1719                 atomic_set(&adev->throttling_logging_enabled, 0);
1720         }
1721
1722         return count;
1723 }
1724
1725 /**
1726  * DOC: apu_thermal_cap
1727  *
1728  * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1729  * limit temperature in millidegrees Celsius
1730  *
1731  * Reading back the file shows you core limit value
1732  *
1733  * Writing an integer to the file, sets a new thermal limit. The value
1734  * should be between 0 and 100. If the value is less than 0 or greater
1735  * than 100, then the write request will be ignored.
1736  */
1737 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1738                                          struct device_attribute *attr,
1739                                          char *buf)
1740 {
1741         int ret, size;
1742         u32 limit;
1743         struct drm_device *ddev = dev_get_drvdata(dev);
1744         struct amdgpu_device *adev = drm_to_adev(ddev);
1745
1746         ret = pm_runtime_get_sync(ddev->dev);
1747         if (ret < 0) {
1748                 pm_runtime_put_autosuspend(ddev->dev);
1749                 return ret;
1750         }
1751
1752         ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1753         if (!ret)
1754                 size = sysfs_emit(buf, "%u\n", limit);
1755         else
1756                 size = sysfs_emit(buf, "failed to get thermal limit\n");
1757
1758         pm_runtime_mark_last_busy(ddev->dev);
1759         pm_runtime_put_autosuspend(ddev->dev);
1760
1761         return size;
1762 }
1763
1764 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1765                                          struct device_attribute *attr,
1766                                          const char *buf,
1767                                          size_t count)
1768 {
1769         int ret;
1770         u32 value;
1771         struct drm_device *ddev = dev_get_drvdata(dev);
1772         struct amdgpu_device *adev = drm_to_adev(ddev);
1773
1774         ret = kstrtou32(buf, 10, &value);
1775         if (ret)
1776                 return ret;
1777
1778         if (value > 100) {
1779                 dev_err(dev, "Invalid argument !\n");
1780                 return -EINVAL;
1781         }
1782
1783         ret = pm_runtime_get_sync(ddev->dev);
1784         if (ret < 0) {
1785                 pm_runtime_put_autosuspend(ddev->dev);
1786                 return ret;
1787         }
1788
1789         ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1790         if (ret) {
1791                 dev_err(dev, "failed to update thermal limit\n");
1792                 return ret;
1793         }
1794
1795         pm_runtime_mark_last_busy(ddev->dev);
1796         pm_runtime_put_autosuspend(ddev->dev);
1797
1798         return count;
1799 }
1800
1801 /**
1802  * DOC: gpu_metrics
1803  *
1804  * The amdgpu driver provides a sysfs API for retrieving current gpu
1805  * metrics data. The file gpu_metrics is used for this. Reading the
1806  * file will dump all the current gpu metrics data.
1807  *
1808  * These data include temperature, frequency, engines utilization,
1809  * power consume, throttler status, fan speed and cpu core statistics(
1810  * available for APU only). That's it will give a snapshot of all sensors
1811  * at the same time.
1812  */
1813 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1814                                       struct device_attribute *attr,
1815                                       char *buf)
1816 {
1817         struct drm_device *ddev = dev_get_drvdata(dev);
1818         struct amdgpu_device *adev = drm_to_adev(ddev);
1819         void *gpu_metrics;
1820         ssize_t size = 0;
1821         int ret;
1822
1823         if (amdgpu_in_reset(adev))
1824                 return -EPERM;
1825         if (adev->in_suspend && !adev->in_runpm)
1826                 return -EPERM;
1827
1828         ret = pm_runtime_get_sync(ddev->dev);
1829         if (ret < 0) {
1830                 pm_runtime_put_autosuspend(ddev->dev);
1831                 return ret;
1832         }
1833
1834         size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1835         if (size <= 0)
1836                 goto out;
1837
1838         if (size >= PAGE_SIZE)
1839                 size = PAGE_SIZE - 1;
1840
1841         memcpy(buf, gpu_metrics, size);
1842
1843 out:
1844         pm_runtime_mark_last_busy(ddev->dev);
1845         pm_runtime_put_autosuspend(ddev->dev);
1846
1847         return size;
1848 }
1849
1850 static int amdgpu_show_powershift_percent(struct device *dev,
1851                                         char *buf, enum amd_pp_sensors sensor)
1852 {
1853         struct drm_device *ddev = dev_get_drvdata(dev);
1854         struct amdgpu_device *adev = drm_to_adev(ddev);
1855         uint32_t ss_power;
1856         int r = 0, i;
1857
1858         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1859         if (r == -EOPNOTSUPP) {
1860                 /* sensor not available on dGPU, try to read from APU */
1861                 adev = NULL;
1862                 mutex_lock(&mgpu_info.mutex);
1863                 for (i = 0; i < mgpu_info.num_gpu; i++) {
1864                         if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1865                                 adev = mgpu_info.gpu_ins[i].adev;
1866                                 break;
1867                         }
1868                 }
1869                 mutex_unlock(&mgpu_info.mutex);
1870                 if (adev)
1871                         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1872         }
1873
1874         if (r)
1875                 return r;
1876
1877         return sysfs_emit(buf, "%u%%\n", ss_power);
1878 }
1879
1880 /**
1881  * DOC: smartshift_apu_power
1882  *
1883  * The amdgpu driver provides a sysfs API for reporting APU power
1884  * shift in percentage if platform supports smartshift. Value 0 means that
1885  * there is no powershift and values between [1-100] means that the power
1886  * is shifted to APU, the percentage of boost is with respect to APU power
1887  * limit on the platform.
1888  */
1889
1890 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1891                                                char *buf)
1892 {
1893         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1894 }
1895
1896 /**
1897  * DOC: smartshift_dgpu_power
1898  *
1899  * The amdgpu driver provides a sysfs API for reporting dGPU power
1900  * shift in percentage if platform supports smartshift. Value 0 means that
1901  * there is no powershift and values between [1-100] means that the power is
1902  * shifted to dGPU, the percentage of boost is with respect to dGPU power
1903  * limit on the platform.
1904  */
1905
1906 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1907                                                 char *buf)
1908 {
1909         return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1910 }
1911
1912 /**
1913  * DOC: smartshift_bias
1914  *
1915  * The amdgpu driver provides a sysfs API for reporting the
1916  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1917  * and the default is 0. -100 sets maximum preference to APU
1918  * and 100 sets max perference to dGPU.
1919  */
1920
1921 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1922                                           struct device_attribute *attr,
1923                                           char *buf)
1924 {
1925         int r = 0;
1926
1927         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1928
1929         return r;
1930 }
1931
1932 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1933                                           struct device_attribute *attr,
1934                                           const char *buf, size_t count)
1935 {
1936         struct drm_device *ddev = dev_get_drvdata(dev);
1937         struct amdgpu_device *adev = drm_to_adev(ddev);
1938         int r = 0;
1939         int bias = 0;
1940
1941         if (amdgpu_in_reset(adev))
1942                 return -EPERM;
1943         if (adev->in_suspend && !adev->in_runpm)
1944                 return -EPERM;
1945
1946         r = pm_runtime_get_sync(ddev->dev);
1947         if (r < 0) {
1948                 pm_runtime_put_autosuspend(ddev->dev);
1949                 return r;
1950         }
1951
1952         r = kstrtoint(buf, 10, &bias);
1953         if (r)
1954                 goto out;
1955
1956         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1957                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1958         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1959                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1960
1961         amdgpu_smartshift_bias = bias;
1962         r = count;
1963
1964         /* TODO: update bias level with SMU message */
1965
1966 out:
1967         pm_runtime_mark_last_busy(ddev->dev);
1968         pm_runtime_put_autosuspend(ddev->dev);
1969         return r;
1970 }
1971
1972 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1973                                 uint32_t mask, enum amdgpu_device_attr_states *states)
1974 {
1975         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1976                 *states = ATTR_STATE_UNSUPPORTED;
1977
1978         return 0;
1979 }
1980
1981 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1982                                uint32_t mask, enum amdgpu_device_attr_states *states)
1983 {
1984         uint32_t ss_power;
1985
1986         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1987                 *states = ATTR_STATE_UNSUPPORTED;
1988         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1989                  (void *)&ss_power))
1990                 *states = ATTR_STATE_UNSUPPORTED;
1991         else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1992                  (void *)&ss_power))
1993                 *states = ATTR_STATE_UNSUPPORTED;
1994
1995         return 0;
1996 }
1997
1998 /* Following items will be read out to indicate current plpd policy:
1999  *  - -1: none
2000  *  - 0: disallow
2001  *  - 1: default
2002  *  - 2: optimized
2003  */
2004 static ssize_t amdgpu_get_xgmi_plpd_policy(struct device *dev,
2005                                            struct device_attribute *attr,
2006                                            char *buf)
2007 {
2008         struct drm_device *ddev = dev_get_drvdata(dev);
2009         struct amdgpu_device *adev = drm_to_adev(ddev);
2010         char *mode_desc = "none";
2011         int mode;
2012
2013         if (amdgpu_in_reset(adev))
2014                 return -EPERM;
2015         if (adev->in_suspend && !adev->in_runpm)
2016                 return -EPERM;
2017
2018         mode = amdgpu_dpm_get_xgmi_plpd_mode(adev, &mode_desc);
2019
2020         return sysfs_emit(buf, "%d: %s\n", mode, mode_desc);
2021 }
2022
2023 /* Following argument value is expected from user to change plpd policy
2024  *  - arg 0: disallow plpd
2025  *  - arg 1: default policy
2026  *  - arg 2: optimized policy
2027  */
2028 static ssize_t amdgpu_set_xgmi_plpd_policy(struct device *dev,
2029                                            struct device_attribute *attr,
2030                                            const char *buf, size_t count)
2031 {
2032         struct drm_device *ddev = dev_get_drvdata(dev);
2033         struct amdgpu_device *adev = drm_to_adev(ddev);
2034         int mode, ret;
2035
2036         if (amdgpu_in_reset(adev))
2037                 return -EPERM;
2038         if (adev->in_suspend && !adev->in_runpm)
2039                 return -EPERM;
2040
2041         ret = kstrtos32(buf, 0, &mode);
2042         if (ret)
2043                 return -EINVAL;
2044
2045         ret = pm_runtime_get_sync(ddev->dev);
2046         if (ret < 0) {
2047                 pm_runtime_put_autosuspend(ddev->dev);
2048                 return ret;
2049         }
2050
2051         ret = amdgpu_dpm_set_xgmi_plpd_mode(adev, mode);
2052
2053         pm_runtime_mark_last_busy(ddev->dev);
2054         pm_runtime_put_autosuspend(ddev->dev);
2055
2056         if (ret)
2057                 return ret;
2058
2059         return count;
2060 }
2061
2062 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2063         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2064         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2065         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2066         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2067         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2068         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2069         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2070         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2071         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2072         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2073         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2074         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2075         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2076         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2077         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2078         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2079         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2080         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2081         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2082         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2083         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2084         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2085         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2086         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2087         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2088         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2089         AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2090         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2091         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
2092                               .attr_update = ss_power_attr_update),
2093         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
2094                               .attr_update = ss_power_attr_update),
2095         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
2096                               .attr_update = ss_bias_attr_update),
2097         AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy,                         ATTR_FLAG_BASIC),
2098 };
2099
2100 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2101                                uint32_t mask, enum amdgpu_device_attr_states *states)
2102 {
2103         struct device_attribute *dev_attr = &attr->dev_attr;
2104         uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
2105         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
2106         const char *attr_name = dev_attr->attr.name;
2107
2108         if (!(attr->flags & mask)) {
2109                 *states = ATTR_STATE_UNSUPPORTED;
2110                 return 0;
2111         }
2112
2113 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2114
2115         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2116                 if (gc_ver < IP_VERSION(9, 0, 0))
2117                         *states = ATTR_STATE_UNSUPPORTED;
2118         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2119                 if (gc_ver < IP_VERSION(9, 0, 0) ||
2120                     !amdgpu_device_has_display_hardware(adev))
2121                         *states = ATTR_STATE_UNSUPPORTED;
2122         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2123                 if (mp1_ver < IP_VERSION(10, 0, 0))
2124                         *states = ATTR_STATE_UNSUPPORTED;
2125         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2126                 *states = ATTR_STATE_UNSUPPORTED;
2127                 if (amdgpu_dpm_is_overdrive_supported(adev))
2128                         *states = ATTR_STATE_SUPPORTED;
2129         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2130                 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1))
2131                         *states = ATTR_STATE_UNSUPPORTED;
2132         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2133                 /* PCIe Perf counters won't work on APU nodes */
2134                 if (adev->flags & AMD_IS_APU)
2135                         *states = ATTR_STATE_UNSUPPORTED;
2136         } else if (DEVICE_ATTR_IS(unique_id)) {
2137                 switch (gc_ver) {
2138                 case IP_VERSION(9, 0, 1):
2139                 case IP_VERSION(9, 4, 0):
2140                 case IP_VERSION(9, 4, 1):
2141                 case IP_VERSION(9, 4, 2):
2142                 case IP_VERSION(9, 4, 3):
2143                 case IP_VERSION(10, 3, 0):
2144                 case IP_VERSION(11, 0, 0):
2145                 case IP_VERSION(11, 0, 1):
2146                 case IP_VERSION(11, 0, 2):
2147                 case IP_VERSION(11, 0, 3):
2148                         *states = ATTR_STATE_SUPPORTED;
2149                         break;
2150                 default:
2151                         *states = ATTR_STATE_UNSUPPORTED;
2152                 }
2153         } else if (DEVICE_ATTR_IS(pp_features)) {
2154                 if ((adev->flags & AMD_IS_APU &&
2155                      gc_ver != IP_VERSION(9, 4, 3)) ||
2156                     gc_ver < IP_VERSION(9, 0, 0))
2157                         *states = ATTR_STATE_UNSUPPORTED;
2158         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2159                 if (gc_ver < IP_VERSION(9, 1, 0))
2160                         *states = ATTR_STATE_UNSUPPORTED;
2161         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2162                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2163                       gc_ver == IP_VERSION(10, 3, 0) ||
2164                       gc_ver == IP_VERSION(10, 1, 2) ||
2165                       gc_ver == IP_VERSION(11, 0, 0) ||
2166                       gc_ver == IP_VERSION(11, 0, 2) ||
2167                       gc_ver == IP_VERSION(11, 0, 3) ||
2168                       gc_ver == IP_VERSION(9, 4, 3)))
2169                         *states = ATTR_STATE_UNSUPPORTED;
2170         } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2171                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2172                            gc_ver == IP_VERSION(10, 3, 0) ||
2173                            gc_ver == IP_VERSION(11, 0, 2) ||
2174                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2175                         *states = ATTR_STATE_UNSUPPORTED;
2176         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2177                 if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2178                       gc_ver == IP_VERSION(10, 3, 0) ||
2179                       gc_ver == IP_VERSION(10, 1, 2) ||
2180                       gc_ver == IP_VERSION(11, 0, 0) ||
2181                       gc_ver == IP_VERSION(11, 0, 2) ||
2182                       gc_ver == IP_VERSION(11, 0, 3) ||
2183                       gc_ver == IP_VERSION(9, 4, 3)))
2184                         *states = ATTR_STATE_UNSUPPORTED;
2185         } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2186                 if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2187                            gc_ver == IP_VERSION(10, 3, 0) ||
2188                            gc_ver == IP_VERSION(11, 0, 2) ||
2189                            gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2190                         *states = ATTR_STATE_UNSUPPORTED;
2191         } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2192                 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2193                         *states = ATTR_STATE_UNSUPPORTED;
2194                 else if ((gc_ver == IP_VERSION(10, 3, 0) ||
2195                           gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev))
2196                         *states = ATTR_STATE_UNSUPPORTED;
2197         } else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) {
2198                 if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE)
2199                         *states = ATTR_STATE_UNSUPPORTED;
2200         }
2201
2202         switch (gc_ver) {
2203         case IP_VERSION(9, 4, 1):
2204         case IP_VERSION(9, 4, 2):
2205                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2206                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2207                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2208                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2209                         dev_attr->attr.mode &= ~S_IWUGO;
2210                         dev_attr->store = NULL;
2211                 }
2212                 break;
2213         case IP_VERSION(10, 3, 0):
2214                 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2215                     amdgpu_sriov_vf(adev)) {
2216                         dev_attr->attr.mode &= ~0222;
2217                         dev_attr->store = NULL;
2218                 }
2219                 break;
2220         default:
2221                 break;
2222         }
2223
2224         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2225                 /* SMU MP1 does not support dcefclk level setting */
2226                 if (gc_ver >= IP_VERSION(10, 0, 0)) {
2227                         dev_attr->attr.mode &= ~S_IWUGO;
2228                         dev_attr->store = NULL;
2229                 }
2230         }
2231
2232         /* setting should not be allowed from VF if not in one VF mode */
2233         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2234                 dev_attr->attr.mode &= ~S_IWUGO;
2235                 dev_attr->store = NULL;
2236         }
2237
2238 #undef DEVICE_ATTR_IS
2239
2240         return 0;
2241 }
2242
2243
2244 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2245                                      struct amdgpu_device_attr *attr,
2246                                      uint32_t mask, struct list_head *attr_list)
2247 {
2248         int ret = 0;
2249         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2250         struct amdgpu_device_attr_entry *attr_entry;
2251         struct device_attribute *dev_attr;
2252         const char *name;
2253
2254         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2255                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2256
2257         if (!attr)
2258                 return -EINVAL;
2259
2260         dev_attr = &attr->dev_attr;
2261         name = dev_attr->attr.name;
2262
2263         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2264
2265         ret = attr_update(adev, attr, mask, &attr_states);
2266         if (ret) {
2267                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2268                         name, ret);
2269                 return ret;
2270         }
2271
2272         if (attr_states == ATTR_STATE_UNSUPPORTED)
2273                 return 0;
2274
2275         ret = device_create_file(adev->dev, dev_attr);
2276         if (ret) {
2277                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2278                         name, ret);
2279         }
2280
2281         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2282         if (!attr_entry)
2283                 return -ENOMEM;
2284
2285         attr_entry->attr = attr;
2286         INIT_LIST_HEAD(&attr_entry->entry);
2287
2288         list_add_tail(&attr_entry->entry, attr_list);
2289
2290         return ret;
2291 }
2292
2293 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2294 {
2295         struct device_attribute *dev_attr = &attr->dev_attr;
2296
2297         device_remove_file(adev->dev, dev_attr);
2298 }
2299
2300 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2301                                              struct list_head *attr_list);
2302
2303 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2304                                             struct amdgpu_device_attr *attrs,
2305                                             uint32_t counts,
2306                                             uint32_t mask,
2307                                             struct list_head *attr_list)
2308 {
2309         int ret = 0;
2310         uint32_t i = 0;
2311
2312         for (i = 0; i < counts; i++) {
2313                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2314                 if (ret)
2315                         goto failed;
2316         }
2317
2318         return 0;
2319
2320 failed:
2321         amdgpu_device_attr_remove_groups(adev, attr_list);
2322
2323         return ret;
2324 }
2325
2326 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2327                                              struct list_head *attr_list)
2328 {
2329         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2330
2331         if (list_empty(attr_list))
2332                 return ;
2333
2334         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2335                 amdgpu_device_attr_remove(adev, entry->attr);
2336                 list_del(&entry->entry);
2337                 kfree(entry);
2338         }
2339 }
2340
2341 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2342                                       struct device_attribute *attr,
2343                                       char *buf)
2344 {
2345         struct amdgpu_device *adev = dev_get_drvdata(dev);
2346         int channel = to_sensor_dev_attr(attr)->index;
2347         int r, temp = 0;
2348
2349         if (channel >= PP_TEMP_MAX)
2350                 return -EINVAL;
2351
2352         switch (channel) {
2353         case PP_TEMP_JUNCTION:
2354                 /* get current junction temperature */
2355                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2356                                            (void *)&temp);
2357                 break;
2358         case PP_TEMP_EDGE:
2359                 /* get current edge temperature */
2360                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2361                                            (void *)&temp);
2362                 break;
2363         case PP_TEMP_MEM:
2364                 /* get current memory temperature */
2365                 r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2366                                            (void *)&temp);
2367                 break;
2368         default:
2369                 r = -EINVAL;
2370                 break;
2371         }
2372
2373         if (r)
2374                 return r;
2375
2376         return sysfs_emit(buf, "%d\n", temp);
2377 }
2378
2379 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2380                                              struct device_attribute *attr,
2381                                              char *buf)
2382 {
2383         struct amdgpu_device *adev = dev_get_drvdata(dev);
2384         int hyst = to_sensor_dev_attr(attr)->index;
2385         int temp;
2386
2387         if (hyst)
2388                 temp = adev->pm.dpm.thermal.min_temp;
2389         else
2390                 temp = adev->pm.dpm.thermal.max_temp;
2391
2392         return sysfs_emit(buf, "%d\n", temp);
2393 }
2394
2395 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2396                                              struct device_attribute *attr,
2397                                              char *buf)
2398 {
2399         struct amdgpu_device *adev = dev_get_drvdata(dev);
2400         int hyst = to_sensor_dev_attr(attr)->index;
2401         int temp;
2402
2403         if (hyst)
2404                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2405         else
2406                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2407
2408         return sysfs_emit(buf, "%d\n", temp);
2409 }
2410
2411 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2412                                              struct device_attribute *attr,
2413                                              char *buf)
2414 {
2415         struct amdgpu_device *adev = dev_get_drvdata(dev);
2416         int hyst = to_sensor_dev_attr(attr)->index;
2417         int temp;
2418
2419         if (hyst)
2420                 temp = adev->pm.dpm.thermal.min_mem_temp;
2421         else
2422                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2423
2424         return sysfs_emit(buf, "%d\n", temp);
2425 }
2426
2427 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2428                                              struct device_attribute *attr,
2429                                              char *buf)
2430 {
2431         int channel = to_sensor_dev_attr(attr)->index;
2432
2433         if (channel >= PP_TEMP_MAX)
2434                 return -EINVAL;
2435
2436         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2437 }
2438
2439 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2440                                              struct device_attribute *attr,
2441                                              char *buf)
2442 {
2443         struct amdgpu_device *adev = dev_get_drvdata(dev);
2444         int channel = to_sensor_dev_attr(attr)->index;
2445         int temp = 0;
2446
2447         if (channel >= PP_TEMP_MAX)
2448                 return -EINVAL;
2449
2450         switch (channel) {
2451         case PP_TEMP_JUNCTION:
2452                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2453                 break;
2454         case PP_TEMP_EDGE:
2455                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2456                 break;
2457         case PP_TEMP_MEM:
2458                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2459                 break;
2460         }
2461
2462         return sysfs_emit(buf, "%d\n", temp);
2463 }
2464
2465 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2466                                             struct device_attribute *attr,
2467                                             char *buf)
2468 {
2469         struct amdgpu_device *adev = dev_get_drvdata(dev);
2470         u32 pwm_mode = 0;
2471         int ret;
2472
2473         if (amdgpu_in_reset(adev))
2474                 return -EPERM;
2475         if (adev->in_suspend && !adev->in_runpm)
2476                 return -EPERM;
2477
2478         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2479         if (ret < 0) {
2480                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2481                 return ret;
2482         }
2483
2484         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2485
2486         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2487         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2488
2489         if (ret)
2490                 return -EINVAL;
2491
2492         return sysfs_emit(buf, "%u\n", pwm_mode);
2493 }
2494
2495 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2496                                             struct device_attribute *attr,
2497                                             const char *buf,
2498                                             size_t count)
2499 {
2500         struct amdgpu_device *adev = dev_get_drvdata(dev);
2501         int err, ret;
2502         int value;
2503
2504         if (amdgpu_in_reset(adev))
2505                 return -EPERM;
2506         if (adev->in_suspend && !adev->in_runpm)
2507                 return -EPERM;
2508
2509         err = kstrtoint(buf, 10, &value);
2510         if (err)
2511                 return err;
2512
2513         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2514         if (ret < 0) {
2515                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2516                 return ret;
2517         }
2518
2519         ret = amdgpu_dpm_set_fan_control_mode(adev, value);
2520
2521         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2522         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2523
2524         if (ret)
2525                 return -EINVAL;
2526
2527         return count;
2528 }
2529
2530 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2531                                          struct device_attribute *attr,
2532                                          char *buf)
2533 {
2534         return sysfs_emit(buf, "%i\n", 0);
2535 }
2536
2537 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2538                                          struct device_attribute *attr,
2539                                          char *buf)
2540 {
2541         return sysfs_emit(buf, "%i\n", 255);
2542 }
2543
2544 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2545                                      struct device_attribute *attr,
2546                                      const char *buf, size_t count)
2547 {
2548         struct amdgpu_device *adev = dev_get_drvdata(dev);
2549         int err;
2550         u32 value;
2551         u32 pwm_mode;
2552
2553         if (amdgpu_in_reset(adev))
2554                 return -EPERM;
2555         if (adev->in_suspend && !adev->in_runpm)
2556                 return -EPERM;
2557
2558         err = kstrtou32(buf, 10, &value);
2559         if (err)
2560                 return err;
2561
2562         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2563         if (err < 0) {
2564                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2565                 return err;
2566         }
2567
2568         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2569         if (err)
2570                 goto out;
2571
2572         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2573                 pr_info("manual fan speed control should be enabled first\n");
2574                 err = -EINVAL;
2575                 goto out;
2576         }
2577
2578         err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2579
2580 out:
2581         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2582         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2583
2584         if (err)
2585                 return err;
2586
2587         return count;
2588 }
2589
2590 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2591                                      struct device_attribute *attr,
2592                                      char *buf)
2593 {
2594         struct amdgpu_device *adev = dev_get_drvdata(dev);
2595         int err;
2596         u32 speed = 0;
2597
2598         if (amdgpu_in_reset(adev))
2599                 return -EPERM;
2600         if (adev->in_suspend && !adev->in_runpm)
2601                 return -EPERM;
2602
2603         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2604         if (err < 0) {
2605                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2606                 return err;
2607         }
2608
2609         err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2610
2611         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2612         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2613
2614         if (err)
2615                 return err;
2616
2617         return sysfs_emit(buf, "%i\n", speed);
2618 }
2619
2620 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2621                                            struct device_attribute *attr,
2622                                            char *buf)
2623 {
2624         struct amdgpu_device *adev = dev_get_drvdata(dev);
2625         int err;
2626         u32 speed = 0;
2627
2628         if (amdgpu_in_reset(adev))
2629                 return -EPERM;
2630         if (adev->in_suspend && !adev->in_runpm)
2631                 return -EPERM;
2632
2633         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2634         if (err < 0) {
2635                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2636                 return err;
2637         }
2638
2639         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2640
2641         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2642         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2643
2644         if (err)
2645                 return err;
2646
2647         return sysfs_emit(buf, "%i\n", speed);
2648 }
2649
2650 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2651                                          struct device_attribute *attr,
2652                                          char *buf)
2653 {
2654         struct amdgpu_device *adev = dev_get_drvdata(dev);
2655         u32 min_rpm = 0;
2656         int r;
2657
2658         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2659                                    (void *)&min_rpm);
2660
2661         if (r)
2662                 return r;
2663
2664         return sysfs_emit(buf, "%d\n", min_rpm);
2665 }
2666
2667 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2668                                          struct device_attribute *attr,
2669                                          char *buf)
2670 {
2671         struct amdgpu_device *adev = dev_get_drvdata(dev);
2672         u32 max_rpm = 0;
2673         int r;
2674
2675         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2676                                    (void *)&max_rpm);
2677
2678         if (r)
2679                 return r;
2680
2681         return sysfs_emit(buf, "%d\n", max_rpm);
2682 }
2683
2684 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2685                                            struct device_attribute *attr,
2686                                            char *buf)
2687 {
2688         struct amdgpu_device *adev = dev_get_drvdata(dev);
2689         int err;
2690         u32 rpm = 0;
2691
2692         if (amdgpu_in_reset(adev))
2693                 return -EPERM;
2694         if (adev->in_suspend && !adev->in_runpm)
2695                 return -EPERM;
2696
2697         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2698         if (err < 0) {
2699                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2700                 return err;
2701         }
2702
2703         err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2704
2705         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2706         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2707
2708         if (err)
2709                 return err;
2710
2711         return sysfs_emit(buf, "%i\n", rpm);
2712 }
2713
2714 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2715                                      struct device_attribute *attr,
2716                                      const char *buf, size_t count)
2717 {
2718         struct amdgpu_device *adev = dev_get_drvdata(dev);
2719         int err;
2720         u32 value;
2721         u32 pwm_mode;
2722
2723         if (amdgpu_in_reset(adev))
2724                 return -EPERM;
2725         if (adev->in_suspend && !adev->in_runpm)
2726                 return -EPERM;
2727
2728         err = kstrtou32(buf, 10, &value);
2729         if (err)
2730                 return err;
2731
2732         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2733         if (err < 0) {
2734                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2735                 return err;
2736         }
2737
2738         err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2739         if (err)
2740                 goto out;
2741
2742         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2743                 err = -ENODATA;
2744                 goto out;
2745         }
2746
2747         err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2748
2749 out:
2750         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2751         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2752
2753         if (err)
2754                 return err;
2755
2756         return count;
2757 }
2758
2759 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2760                                             struct device_attribute *attr,
2761                                             char *buf)
2762 {
2763         struct amdgpu_device *adev = dev_get_drvdata(dev);
2764         u32 pwm_mode = 0;
2765         int ret;
2766
2767         if (amdgpu_in_reset(adev))
2768                 return -EPERM;
2769         if (adev->in_suspend && !adev->in_runpm)
2770                 return -EPERM;
2771
2772         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2773         if (ret < 0) {
2774                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2775                 return ret;
2776         }
2777
2778         ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2779
2780         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2781         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2782
2783         if (ret)
2784                 return -EINVAL;
2785
2786         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2787 }
2788
2789 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2790                                             struct device_attribute *attr,
2791                                             const char *buf,
2792                                             size_t count)
2793 {
2794         struct amdgpu_device *adev = dev_get_drvdata(dev);
2795         int err;
2796         int value;
2797         u32 pwm_mode;
2798
2799         if (amdgpu_in_reset(adev))
2800                 return -EPERM;
2801         if (adev->in_suspend && !adev->in_runpm)
2802                 return -EPERM;
2803
2804         err = kstrtoint(buf, 10, &value);
2805         if (err)
2806                 return err;
2807
2808         if (value == 0)
2809                 pwm_mode = AMD_FAN_CTRL_AUTO;
2810         else if (value == 1)
2811                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2812         else
2813                 return -EINVAL;
2814
2815         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2816         if (err < 0) {
2817                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2818                 return err;
2819         }
2820
2821         err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2822
2823         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2824         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2825
2826         if (err)
2827                 return -EINVAL;
2828
2829         return count;
2830 }
2831
2832 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2833                                         struct device_attribute *attr,
2834                                         char *buf)
2835 {
2836         struct amdgpu_device *adev = dev_get_drvdata(dev);
2837         u32 vddgfx;
2838         int r;
2839
2840         /* get the voltage */
2841         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2842                                    (void *)&vddgfx);
2843         if (r)
2844                 return r;
2845
2846         return sysfs_emit(buf, "%d\n", vddgfx);
2847 }
2848
2849 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2850                                               struct device_attribute *attr,
2851                                               char *buf)
2852 {
2853         return sysfs_emit(buf, "vddgfx\n");
2854 }
2855
2856 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2857                                        struct device_attribute *attr,
2858                                        char *buf)
2859 {
2860         struct amdgpu_device *adev = dev_get_drvdata(dev);
2861         u32 vddnb;
2862         int r;
2863
2864         /* only APUs have vddnb */
2865         if  (!(adev->flags & AMD_IS_APU))
2866                 return -EINVAL;
2867
2868         /* get the voltage */
2869         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2870                                    (void *)&vddnb);
2871         if (r)
2872                 return r;
2873
2874         return sysfs_emit(buf, "%d\n", vddnb);
2875 }
2876
2877 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2878                                               struct device_attribute *attr,
2879                                               char *buf)
2880 {
2881         return sysfs_emit(buf, "vddnb\n");
2882 }
2883
2884 static int amdgpu_hwmon_get_power(struct device *dev,
2885                                   enum amd_pp_sensors sensor)
2886 {
2887         struct amdgpu_device *adev = dev_get_drvdata(dev);
2888         unsigned int uw;
2889         u32 query = 0;
2890         int r;
2891
2892         r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2893         if (r)
2894                 return r;
2895
2896         /* convert to microwatts */
2897         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2898
2899         return uw;
2900 }
2901
2902 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2903                                            struct device_attribute *attr,
2904                                            char *buf)
2905 {
2906         ssize_t val;
2907
2908         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
2909         if (val < 0)
2910                 return val;
2911
2912         return sysfs_emit(buf, "%zd\n", val);
2913 }
2914
2915 static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
2916                                              struct device_attribute *attr,
2917                                              char *buf)
2918 {
2919         ssize_t val;
2920
2921         val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
2922         if (val < 0)
2923                 return val;
2924
2925         return sysfs_emit(buf, "%zd\n", val);
2926 }
2927
2928 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2929                                         struct device_attribute *attr,
2930                                         char *buf,
2931                                         enum pp_power_limit_level pp_limit_level)
2932 {
2933         struct amdgpu_device *adev = dev_get_drvdata(dev);
2934         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2935         uint32_t limit;
2936         ssize_t size;
2937         int r;
2938
2939         if (amdgpu_in_reset(adev))
2940                 return -EPERM;
2941         if (adev->in_suspend && !adev->in_runpm)
2942                 return -EPERM;
2943
2944         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2945         if (r < 0) {
2946                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2947                 return r;
2948         }
2949
2950         r = amdgpu_dpm_get_power_limit(adev, &limit,
2951                                       pp_limit_level, power_type);
2952
2953         if (!r)
2954                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2955         else
2956                 size = sysfs_emit(buf, "\n");
2957
2958         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2959         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2960
2961         return size;
2962 }
2963
2964 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2965                                          struct device_attribute *attr,
2966                                          char *buf)
2967 {
2968         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN);
2969 }
2970
2971 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2972                                          struct device_attribute *attr,
2973                                          char *buf)
2974 {
2975         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2976
2977 }
2978
2979 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2980                                          struct device_attribute *attr,
2981                                          char *buf)
2982 {
2983         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2984
2985 }
2986
2987 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2988                                          struct device_attribute *attr,
2989                                          char *buf)
2990 {
2991         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2992
2993 }
2994
2995 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2996                                          struct device_attribute *attr,
2997                                          char *buf)
2998 {
2999         struct amdgpu_device *adev = dev_get_drvdata(dev);
3000         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3001
3002         if (gc_ver == IP_VERSION(10, 3, 1))
3003                 return sysfs_emit(buf, "%s\n",
3004                                   to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
3005                                   "fastPPT" : "slowPPT");
3006         else
3007                 return sysfs_emit(buf, "PPT\n");
3008 }
3009
3010 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3011                 struct device_attribute *attr,
3012                 const char *buf,
3013                 size_t count)
3014 {
3015         struct amdgpu_device *adev = dev_get_drvdata(dev);
3016         int limit_type = to_sensor_dev_attr(attr)->index;
3017         int err;
3018         u32 value;
3019
3020         if (amdgpu_in_reset(adev))
3021                 return -EPERM;
3022         if (adev->in_suspend && !adev->in_runpm)
3023                 return -EPERM;
3024
3025         if (amdgpu_sriov_vf(adev))
3026                 return -EINVAL;
3027
3028         err = kstrtou32(buf, 10, &value);
3029         if (err)
3030                 return err;
3031
3032         value = value / 1000000; /* convert to Watt */
3033         value |= limit_type << 24;
3034
3035         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3036         if (err < 0) {
3037                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3038                 return err;
3039         }
3040
3041         err = amdgpu_dpm_set_power_limit(adev, value);
3042
3043         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3044         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3045
3046         if (err)
3047                 return err;
3048
3049         return count;
3050 }
3051
3052 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3053                                       struct device_attribute *attr,
3054                                       char *buf)
3055 {
3056         struct amdgpu_device *adev = dev_get_drvdata(dev);
3057         uint32_t sclk;
3058         int r;
3059
3060         /* get the sclk */
3061         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3062                                    (void *)&sclk);
3063         if (r)
3064                 return r;
3065
3066         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3067 }
3068
3069 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3070                                             struct device_attribute *attr,
3071                                             char *buf)
3072 {
3073         return sysfs_emit(buf, "sclk\n");
3074 }
3075
3076 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3077                                       struct device_attribute *attr,
3078                                       char *buf)
3079 {
3080         struct amdgpu_device *adev = dev_get_drvdata(dev);
3081         uint32_t mclk;
3082         int r;
3083
3084         /* get the sclk */
3085         r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3086                                    (void *)&mclk);
3087         if (r)
3088                 return r;
3089
3090         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3091 }
3092
3093 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3094                                             struct device_attribute *attr,
3095                                             char *buf)
3096 {
3097         return sysfs_emit(buf, "mclk\n");
3098 }
3099
3100 /**
3101  * DOC: hwmon
3102  *
3103  * The amdgpu driver exposes the following sensor interfaces:
3104  *
3105  * - GPU temperature (via the on-die sensor)
3106  *
3107  * - GPU voltage
3108  *
3109  * - Northbridge voltage (APUs only)
3110  *
3111  * - GPU power
3112  *
3113  * - GPU fan
3114  *
3115  * - GPU gfx/compute engine clock
3116  *
3117  * - GPU memory clock (dGPU only)
3118  *
3119  * hwmon interfaces for GPU temperature:
3120  *
3121  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3122  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3123  *
3124  * - temp[1-3]_label: temperature channel label
3125  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3126  *
3127  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3128  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3129  *
3130  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3131  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3132  *
3133  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3134  *   - these are supported on SOC15 dGPUs only
3135  *
3136  * hwmon interfaces for GPU voltage:
3137  *
3138  * - in0_input: the voltage on the GPU in millivolts
3139  *
3140  * - in1_input: the voltage on the Northbridge in millivolts
3141  *
3142  * hwmon interfaces for GPU power:
3143  *
3144  * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3145  *
3146  * - power1_input: instantaneous power used by the SoC in microWatts.  On APUs this includes the CPU.
3147  *
3148  * - power1_cap_min: minimum cap supported in microWatts
3149  *
3150  * - power1_cap_max: maximum cap supported in microWatts
3151  *
3152  * - power1_cap: selected power cap in microWatts
3153  *
3154  * hwmon interfaces for GPU fan:
3155  *
3156  * - pwm1: pulse width modulation fan level (0-255)
3157  *
3158  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3159  *
3160  * - pwm1_min: pulse width modulation fan control minimum level (0)
3161  *
3162  * - pwm1_max: pulse width modulation fan control maximum level (255)
3163  *
3164  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3165  *
3166  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3167  *
3168  * - fan1_input: fan speed in RPM
3169  *
3170  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3171  *
3172  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3173  *
3174  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3175  *       That will get the former one overridden.
3176  *
3177  * hwmon interfaces for GPU clocks:
3178  *
3179  * - freq1_input: the gfx/compute clock in hertz
3180  *
3181  * - freq2_input: the memory clock in hertz
3182  *
3183  * You can use hwmon tools like sensors to view this information on your system.
3184  *
3185  */
3186
3187 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3188 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3189 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3190 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3191 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3192 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3193 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3194 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3195 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3196 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3197 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3198 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3199 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3200 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3201 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3202 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3203 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3204 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3205 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3206 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3207 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3208 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3209 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3210 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3211 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3212 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3213 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3214 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3215 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3216 static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3217 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3218 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3219 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3220 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3221 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3222 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3223 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3224 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3225 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3226 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3227 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3228 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3229 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3230 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3231 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3232
3233 static struct attribute *hwmon_attributes[] = {
3234         &sensor_dev_attr_temp1_input.dev_attr.attr,
3235         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3236         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3237         &sensor_dev_attr_temp2_input.dev_attr.attr,
3238         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3239         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3240         &sensor_dev_attr_temp3_input.dev_attr.attr,
3241         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3242         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3243         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3244         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3245         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3246         &sensor_dev_attr_temp1_label.dev_attr.attr,
3247         &sensor_dev_attr_temp2_label.dev_attr.attr,
3248         &sensor_dev_attr_temp3_label.dev_attr.attr,
3249         &sensor_dev_attr_pwm1.dev_attr.attr,
3250         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3251         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3252         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3253         &sensor_dev_attr_fan1_input.dev_attr.attr,
3254         &sensor_dev_attr_fan1_min.dev_attr.attr,
3255         &sensor_dev_attr_fan1_max.dev_attr.attr,
3256         &sensor_dev_attr_fan1_target.dev_attr.attr,
3257         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3258         &sensor_dev_attr_in0_input.dev_attr.attr,
3259         &sensor_dev_attr_in0_label.dev_attr.attr,
3260         &sensor_dev_attr_in1_input.dev_attr.attr,
3261         &sensor_dev_attr_in1_label.dev_attr.attr,
3262         &sensor_dev_attr_power1_average.dev_attr.attr,
3263         &sensor_dev_attr_power1_input.dev_attr.attr,
3264         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3265         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3266         &sensor_dev_attr_power1_cap.dev_attr.attr,
3267         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3268         &sensor_dev_attr_power1_label.dev_attr.attr,
3269         &sensor_dev_attr_power2_average.dev_attr.attr,
3270         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3271         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3272         &sensor_dev_attr_power2_cap.dev_attr.attr,
3273         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3274         &sensor_dev_attr_power2_label.dev_attr.attr,
3275         &sensor_dev_attr_freq1_input.dev_attr.attr,
3276         &sensor_dev_attr_freq1_label.dev_attr.attr,
3277         &sensor_dev_attr_freq2_input.dev_attr.attr,
3278         &sensor_dev_attr_freq2_label.dev_attr.attr,
3279         NULL
3280 };
3281
3282 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3283                                         struct attribute *attr, int index)
3284 {
3285         struct device *dev = kobj_to_dev(kobj);
3286         struct amdgpu_device *adev = dev_get_drvdata(dev);
3287         umode_t effective_mode = attr->mode;
3288         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3289         uint32_t tmp;
3290
3291         /* under multi-vf mode, the hwmon attributes are all not supported */
3292         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3293                 return 0;
3294
3295         /* under pp one vf mode manage of hwmon attributes is not supported */
3296         if (amdgpu_sriov_is_pp_one_vf(adev))
3297                 effective_mode &= ~S_IWUSR;
3298
3299         /* Skip fan attributes if fan is not present */
3300         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3301             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3302             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3303             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3304             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3305             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3306             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3307             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3308             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3309                 return 0;
3310
3311         /* Skip fan attributes on APU */
3312         if ((adev->flags & AMD_IS_APU) &&
3313             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3314              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3315              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3316              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3317              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3318              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3319              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3320              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3321              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3322                 return 0;
3323
3324         /* Skip crit temp on APU */
3325         if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3326             (gc_ver == IP_VERSION(9, 4, 3))) &&
3327             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3328              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3329                 return 0;
3330
3331         /* Skip limit attributes if DPM is not enabled */
3332         if (!adev->pm.dpm_enabled &&
3333             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3334              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3335              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3336              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3337              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3338              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3339              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3340              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3341              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3342              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3343              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3344                 return 0;
3345
3346         /* mask fan attributes if we have no bindings for this asic to expose */
3347         if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3348               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3349             ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3350              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3351                 effective_mode &= ~S_IRUGO;
3352
3353         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3354               attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3355               ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3356               attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3357                 effective_mode &= ~S_IWUSR;
3358
3359         /* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3360         if (((adev->family == AMDGPU_FAMILY_SI) ||
3361              ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3362               (gc_ver != IP_VERSION(9, 4, 3)))) &&
3363             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3364              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3365              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3366              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3367                 return 0;
3368
3369         /* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3370         if (((adev->family == AMDGPU_FAMILY_SI) ||
3371              ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3372             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3373                 return 0;
3374
3375         /* not all products support both average and instantaneous */
3376         if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3377             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3378                 return 0;
3379         if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3380             amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3381                 return 0;
3382
3383         /* hide max/min values if we can't both query and manage the fan */
3384         if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3385               (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3386               (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3387               (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3388             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3389              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3390                 return 0;
3391
3392         if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3393              (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3394              (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3395              attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3396                 return 0;
3397
3398         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3399              adev->family == AMDGPU_FAMILY_KV ||        /* not implemented yet */
3400              (gc_ver == IP_VERSION(9, 4, 3))) &&
3401             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3402              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3403                 return 0;
3404
3405         /* only APUs other than gc 9,4,3 have vddnb */
3406         if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3407             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3408              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3409                 return 0;
3410
3411         /* no mclk on APUs other than gc 9,4,3*/
3412         if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3413             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3414              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3415                 return 0;
3416
3417         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3418             (gc_ver != IP_VERSION(9, 4, 3)) &&
3419             (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3420              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3421              attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3422              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3423              attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
3424              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
3425                 return 0;
3426
3427         /* hotspot temperature for gc 9,4,3*/
3428         if (gc_ver == IP_VERSION(9, 4, 3)) {
3429                 if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3430                     attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3431                     attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
3432                         return 0;
3433
3434                 if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3435                     attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)
3436                         return attr->mode;
3437         }
3438
3439         /* only SOC15 dGPUs support hotspot and mem temperatures */
3440         if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3441             (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3442              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3443              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3444              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3445              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3446                 return 0;
3447
3448         /* only Vangogh has fast PPT limit and power labels */
3449         if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3450             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3451              attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3452              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3453              attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3454              attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3455              attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3456                 return 0;
3457
3458         return effective_mode;
3459 }
3460
3461 static const struct attribute_group hwmon_attrgroup = {
3462         .attrs = hwmon_attributes,
3463         .is_visible = hwmon_attributes_visible,
3464 };
3465
3466 static const struct attribute_group *hwmon_groups[] = {
3467         &hwmon_attrgroup,
3468         NULL
3469 };
3470
3471 static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev,
3472                                        enum pp_clock_type od_type,
3473                                        char *buf)
3474 {
3475         int size = 0;
3476         int ret;
3477
3478         if (amdgpu_in_reset(adev))
3479                 return -EPERM;
3480         if (adev->in_suspend && !adev->in_runpm)
3481                 return -EPERM;
3482
3483         ret = pm_runtime_get_sync(adev->dev);
3484         if (ret < 0) {
3485                 pm_runtime_put_autosuspend(adev->dev);
3486                 return ret;
3487         }
3488
3489         size = amdgpu_dpm_print_clock_levels(adev, od_type, buf);
3490         if (size == 0)
3491                 size = sysfs_emit(buf, "\n");
3492
3493         pm_runtime_mark_last_busy(adev->dev);
3494         pm_runtime_put_autosuspend(adev->dev);
3495
3496         return size;
3497 }
3498
3499 static int parse_input_od_command_lines(const char *buf,
3500                                         size_t count,
3501                                         u32 *type,
3502                                         long *params,
3503                                         uint32_t *num_of_params)
3504 {
3505         const char delimiter[3] = {' ', '\n', '\0'};
3506         uint32_t parameter_size = 0;
3507         char buf_cpy[128] = {0};
3508         char *tmp_str, *sub_str;
3509         int ret;
3510
3511         if (count > sizeof(buf_cpy) - 1)
3512                 return -EINVAL;
3513
3514         memcpy(buf_cpy, buf, count);
3515         tmp_str = buf_cpy;
3516
3517         /* skip heading spaces */
3518         while (isspace(*tmp_str))
3519                 tmp_str++;
3520
3521         switch (*tmp_str) {
3522         case 'c':
3523                 *type = PP_OD_COMMIT_DPM_TABLE;
3524                 return 0;
3525         case 'r':
3526                 params[parameter_size] = *type;
3527                 *num_of_params = 1;
3528                 *type = PP_OD_RESTORE_DEFAULT_TABLE;
3529                 return 0;
3530         default:
3531                 break;
3532         }
3533
3534         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
3535                 if (strlen(sub_str) == 0)
3536                         continue;
3537
3538                 ret = kstrtol(sub_str, 0, &params[parameter_size]);
3539                 if (ret)
3540                         return -EINVAL;
3541                 parameter_size++;
3542
3543                 while (isspace(*tmp_str))
3544                         tmp_str++;
3545         }
3546
3547         *num_of_params = parameter_size;
3548
3549         return 0;
3550 }
3551
3552 static int
3553 amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev,
3554                                      enum PP_OD_DPM_TABLE_COMMAND cmd_type,
3555                                      const char *in_buf,
3556                                      size_t count)
3557 {
3558         uint32_t parameter_size = 0;
3559         long parameter[64];
3560         int ret;
3561
3562         if (amdgpu_in_reset(adev))
3563                 return -EPERM;
3564         if (adev->in_suspend && !adev->in_runpm)
3565                 return -EPERM;
3566
3567         ret = parse_input_od_command_lines(in_buf,
3568                                            count,
3569                                            &cmd_type,
3570                                            parameter,
3571                                            &parameter_size);
3572         if (ret)
3573                 return ret;
3574
3575         ret = pm_runtime_get_sync(adev->dev);
3576         if (ret < 0)
3577                 goto err_out0;
3578
3579         ret = amdgpu_dpm_odn_edit_dpm_table(adev,
3580                                             cmd_type,
3581                                             parameter,
3582                                             parameter_size);
3583         if (ret)
3584                 goto err_out1;
3585
3586         if (cmd_type == PP_OD_COMMIT_DPM_TABLE) {
3587                 ret = amdgpu_dpm_dispatch_task(adev,
3588                                                AMD_PP_TASK_READJUST_POWER_STATE,
3589                                                NULL);
3590                 if (ret)
3591                         goto err_out1;
3592         }
3593
3594         pm_runtime_mark_last_busy(adev->dev);
3595         pm_runtime_put_autosuspend(adev->dev);
3596
3597         return count;
3598
3599 err_out1:
3600         pm_runtime_mark_last_busy(adev->dev);
3601 err_out0:
3602         pm_runtime_put_autosuspend(adev->dev);
3603
3604         return ret;
3605 }
3606
3607 /**
3608  * DOC: fan_curve
3609  *
3610  * The amdgpu driver provides a sysfs API for checking and adjusting the fan
3611  * control curve line.
3612  *
3613  * Reading back the file shows you the current settings(temperature in Celsius
3614  * degree and fan speed in pwm) applied to every anchor point of the curve line
3615  * and their permitted ranges if changable.
3616  *
3617  * Writing a desired string(with the format like "anchor_point_index temperature
3618  * fan_speed_in_pwm") to the file, change the settings for the specific anchor
3619  * point accordingly.
3620  *
3621  * When you have finished the editing, write "c" (commit) to the file to commit
3622  * your changes.
3623  *
3624  * If you want to reset to the default value, write "r" (reset) to the file to
3625  * reset them
3626  *
3627  * There are two fan control modes supported: auto and manual. With auto mode,
3628  * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature).
3629  * While with manual mode, users can set their own fan curve line as what
3630  * described here. Normally the ASIC is booted up with auto mode. Any
3631  * settings via this interface will switch the fan control to manual mode
3632  * implicitly.
3633  */
3634 static ssize_t fan_curve_show(struct kobject *kobj,
3635                               struct kobj_attribute *attr,
3636                               char *buf)
3637 {
3638         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3639         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3640
3641         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf);
3642 }
3643
3644 static ssize_t fan_curve_store(struct kobject *kobj,
3645                                struct kobj_attribute *attr,
3646                                const char *buf,
3647                                size_t count)
3648 {
3649         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3650         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3651
3652         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3653                                                              PP_OD_EDIT_FAN_CURVE,
3654                                                              buf,
3655                                                              count);
3656 }
3657
3658 static umode_t fan_curve_visible(struct amdgpu_device *adev)
3659 {
3660         umode_t umode = 0000;
3661
3662         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE)
3663                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3664
3665         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET)
3666                 umode |= S_IWUSR;
3667
3668         return umode;
3669 }
3670
3671 /**
3672  * DOC: acoustic_limit_rpm_threshold
3673  *
3674  * The amdgpu driver provides a sysfs API for checking and adjusting the
3675  * acoustic limit in RPM for fan control.
3676  *
3677  * Reading back the file shows you the current setting and the permitted
3678  * ranges if changable.
3679  *
3680  * Writing an integer to the file, change the setting accordingly.
3681  *
3682  * When you have finished the editing, write "c" (commit) to the file to commit
3683  * your changes.
3684  *
3685  * If you want to reset to the default value, write "r" (reset) to the file to
3686  * reset them
3687  *
3688  * This setting works under auto fan control mode only. It adjusts the PMFW's
3689  * behavior about the maximum speed in RPM the fan can spin. Setting via this
3690  * interface will switch the fan control to auto mode implicitly.
3691  */
3692 static ssize_t acoustic_limit_threshold_show(struct kobject *kobj,
3693                                              struct kobj_attribute *attr,
3694                                              char *buf)
3695 {
3696         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3697         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3698
3699         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf);
3700 }
3701
3702 static ssize_t acoustic_limit_threshold_store(struct kobject *kobj,
3703                                               struct kobj_attribute *attr,
3704                                               const char *buf,
3705                                               size_t count)
3706 {
3707         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3708         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3709
3710         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3711                                                              PP_OD_EDIT_ACOUSTIC_LIMIT,
3712                                                              buf,
3713                                                              count);
3714 }
3715
3716 static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev)
3717 {
3718         umode_t umode = 0000;
3719
3720         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE)
3721                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3722
3723         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET)
3724                 umode |= S_IWUSR;
3725
3726         return umode;
3727 }
3728
3729 /**
3730  * DOC: acoustic_target_rpm_threshold
3731  *
3732  * The amdgpu driver provides a sysfs API for checking and adjusting the
3733  * acoustic target in RPM for fan control.
3734  *
3735  * Reading back the file shows you the current setting and the permitted
3736  * ranges if changable.
3737  *
3738  * Writing an integer to the file, change the setting accordingly.
3739  *
3740  * When you have finished the editing, write "c" (commit) to the file to commit
3741  * your changes.
3742  *
3743  * If you want to reset to the default value, write "r" (reset) to the file to
3744  * reset them
3745  *
3746  * This setting works under auto fan control mode only. It can co-exist with
3747  * other settings which can work also under auto mode. It adjusts the PMFW's
3748  * behavior about the maximum speed in RPM the fan can spin when ASIC
3749  * temperature is not greater than target temperature. Setting via this
3750  * interface will switch the fan control to auto mode implicitly.
3751  */
3752 static ssize_t acoustic_target_threshold_show(struct kobject *kobj,
3753                                               struct kobj_attribute *attr,
3754                                               char *buf)
3755 {
3756         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3757         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3758
3759         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf);
3760 }
3761
3762 static ssize_t acoustic_target_threshold_store(struct kobject *kobj,
3763                                                struct kobj_attribute *attr,
3764                                                const char *buf,
3765                                                size_t count)
3766 {
3767         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3768         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3769
3770         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3771                                                              PP_OD_EDIT_ACOUSTIC_TARGET,
3772                                                              buf,
3773                                                              count);
3774 }
3775
3776 static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev)
3777 {
3778         umode_t umode = 0000;
3779
3780         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE)
3781                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3782
3783         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET)
3784                 umode |= S_IWUSR;
3785
3786         return umode;
3787 }
3788
3789 /**
3790  * DOC: fan_target_temperature
3791  *
3792  * The amdgpu driver provides a sysfs API for checking and adjusting the
3793  * target tempeature in Celsius degree for fan control.
3794  *
3795  * Reading back the file shows you the current setting and the permitted
3796  * ranges if changable.
3797  *
3798  * Writing an integer to the file, change the setting accordingly.
3799  *
3800  * When you have finished the editing, write "c" (commit) to the file to commit
3801  * your changes.
3802  *
3803  * If you want to reset to the default value, write "r" (reset) to the file to
3804  * reset them
3805  *
3806  * This setting works under auto fan control mode only. It can co-exist with
3807  * other settings which can work also under auto mode. Paring with the
3808  * acoustic_target_rpm_threshold setting, they define the maximum speed in
3809  * RPM the fan can spin when ASIC temperature is not greater than target
3810  * temperature. Setting via this interface will switch the fan control to
3811  * auto mode implicitly.
3812  */
3813 static ssize_t fan_target_temperature_show(struct kobject *kobj,
3814                                            struct kobj_attribute *attr,
3815                                            char *buf)
3816 {
3817         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3818         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3819
3820         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf);
3821 }
3822
3823 static ssize_t fan_target_temperature_store(struct kobject *kobj,
3824                                             struct kobj_attribute *attr,
3825                                             const char *buf,
3826                                             size_t count)
3827 {
3828         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3829         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3830
3831         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3832                                                              PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
3833                                                              buf,
3834                                                              count);
3835 }
3836
3837 static umode_t fan_target_temperature_visible(struct amdgpu_device *adev)
3838 {
3839         umode_t umode = 0000;
3840
3841         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE)
3842                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3843
3844         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET)
3845                 umode |= S_IWUSR;
3846
3847         return umode;
3848 }
3849
3850 /**
3851  * DOC: fan_minimum_pwm
3852  *
3853  * The amdgpu driver provides a sysfs API for checking and adjusting the
3854  * minimum fan speed in PWM.
3855  *
3856  * Reading back the file shows you the current setting and the permitted
3857  * ranges if changable.
3858  *
3859  * Writing an integer to the file, change the setting accordingly.
3860  *
3861  * When you have finished the editing, write "c" (commit) to the file to commit
3862  * your changes.
3863  *
3864  * If you want to reset to the default value, write "r" (reset) to the file to
3865  * reset them
3866  *
3867  * This setting works under auto fan control mode only. It can co-exist with
3868  * other settings which can work also under auto mode. It adjusts the PMFW's
3869  * behavior about the minimum fan speed in PWM the fan should spin. Setting
3870  * via this interface will switch the fan control to auto mode implicitly.
3871  */
3872 static ssize_t fan_minimum_pwm_show(struct kobject *kobj,
3873                                     struct kobj_attribute *attr,
3874                                     char *buf)
3875 {
3876         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3877         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3878
3879         return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf);
3880 }
3881
3882 static ssize_t fan_minimum_pwm_store(struct kobject *kobj,
3883                                      struct kobj_attribute *attr,
3884                                      const char *buf,
3885                                      size_t count)
3886 {
3887         struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3888         struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3889
3890         return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3891                                                              PP_OD_EDIT_FAN_MINIMUM_PWM,
3892                                                              buf,
3893                                                              count);
3894 }
3895
3896 static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev)
3897 {
3898         umode_t umode = 0000;
3899
3900         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE)
3901                 umode |= S_IRUSR | S_IRGRP | S_IROTH;
3902
3903         if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET)
3904                 umode |= S_IWUSR;
3905
3906         return umode;
3907 }
3908
3909 static struct od_feature_set amdgpu_od_set = {
3910         .containers = {
3911                 [0] = {
3912                         .name = "fan_ctrl",
3913                         .sub_feature = {
3914                                 [0] = {
3915                                         .name = "fan_curve",
3916                                         .ops = {
3917                                                 .is_visible = fan_curve_visible,
3918                                                 .show = fan_curve_show,
3919                                                 .store = fan_curve_store,
3920                                         },
3921                                 },
3922                                 [1] = {
3923                                         .name = "acoustic_limit_rpm_threshold",
3924                                         .ops = {
3925                                                 .is_visible = acoustic_limit_threshold_visible,
3926                                                 .show = acoustic_limit_threshold_show,
3927                                                 .store = acoustic_limit_threshold_store,
3928                                         },
3929                                 },
3930                                 [2] = {
3931                                         .name = "acoustic_target_rpm_threshold",
3932                                         .ops = {
3933                                                 .is_visible = acoustic_target_threshold_visible,
3934                                                 .show = acoustic_target_threshold_show,
3935                                                 .store = acoustic_target_threshold_store,
3936                                         },
3937                                 },
3938                                 [3] = {
3939                                         .name = "fan_target_temperature",
3940                                         .ops = {
3941                                                 .is_visible = fan_target_temperature_visible,
3942                                                 .show = fan_target_temperature_show,
3943                                                 .store = fan_target_temperature_store,
3944                                         },
3945                                 },
3946                                 [4] = {
3947                                         .name = "fan_minimum_pwm",
3948                                         .ops = {
3949                                                 .is_visible = fan_minimum_pwm_visible,
3950                                                 .show = fan_minimum_pwm_show,
3951                                                 .store = fan_minimum_pwm_store,
3952                                         },
3953                                 },
3954                         },
3955                 },
3956         },
3957 };
3958
3959 static void od_kobj_release(struct kobject *kobj)
3960 {
3961         struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj);
3962
3963         kfree(od_kobj);
3964 }
3965
3966 static const struct kobj_type od_ktype = {
3967         .release        = od_kobj_release,
3968         .sysfs_ops      = &kobj_sysfs_ops,
3969 };
3970
3971 static void amdgpu_od_set_fini(struct amdgpu_device *adev)
3972 {
3973         struct od_kobj *container, *container_next;
3974         struct od_attribute *attribute, *attribute_next;
3975
3976         if (list_empty(&adev->pm.od_kobj_list))
3977                 return;
3978
3979         list_for_each_entry_safe(container, container_next,
3980                                  &adev->pm.od_kobj_list, entry) {
3981                 list_del(&container->entry);
3982
3983                 list_for_each_entry_safe(attribute, attribute_next,
3984                                          &container->attribute, entry) {
3985                         list_del(&attribute->entry);
3986                         sysfs_remove_file(&container->kobj,
3987                                           &attribute->attribute.attr);
3988                         kfree(attribute);
3989                 }
3990
3991                 kobject_put(&container->kobj);
3992         }
3993 }
3994
3995 static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev,
3996                                            struct od_feature_ops *feature_ops)
3997 {
3998         umode_t mode;
3999
4000         if (!feature_ops->is_visible)
4001                 return false;
4002
4003         /*
4004          * If the feature has no user read and write mode set,
4005          * we can assume the feature is actually not supported.(?)
4006          * And the revelant sysfs interface should not be exposed.
4007          */
4008         mode = feature_ops->is_visible(adev);
4009         if (mode & (S_IRUSR | S_IWUSR))
4010                 return true;
4011
4012         return false;
4013 }
4014
4015 static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev,
4016                                         struct od_feature_container *container)
4017 {
4018         int i;
4019
4020         /*
4021          * If there is no valid entry within the container, the container
4022          * is recognized as a self contained container. And the valid entry
4023          * here means it has a valid naming and it is visible/supported by
4024          * the ASIC.
4025          */
4026         for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) {
4027                 if (container->sub_feature[i].name &&
4028                     amdgpu_is_od_feature_supported(adev,
4029                         &container->sub_feature[i].ops))
4030                         return false;
4031         }
4032
4033         return true;
4034 }
4035
4036 static int amdgpu_od_set_init(struct amdgpu_device *adev)
4037 {
4038         struct od_kobj *top_set, *sub_set;
4039         struct od_attribute *attribute;
4040         struct od_feature_container *container;
4041         struct od_feature_item *feature;
4042         int i, j;
4043         int ret;
4044
4045         /* Setup the top `gpu_od` directory which holds all other OD interfaces */
4046         top_set = kzalloc(sizeof(*top_set), GFP_KERNEL);
4047         if (!top_set)
4048                 return -ENOMEM;
4049         list_add(&top_set->entry, &adev->pm.od_kobj_list);
4050
4051         ret = kobject_init_and_add(&top_set->kobj,
4052                                    &od_ktype,
4053                                    &adev->dev->kobj,
4054                                    "%s",
4055                                    "gpu_od");
4056         if (ret)
4057                 goto err_out;
4058         INIT_LIST_HEAD(&top_set->attribute);
4059         top_set->priv = adev;
4060
4061         for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) {
4062                 container = &amdgpu_od_set.containers[i];
4063
4064                 if (!container->name)
4065                         continue;
4066
4067                 /*
4068                  * If there is valid entries within the container, the container
4069                  * will be presented as a sub directory and all its holding entries
4070                  * will be presented as plain files under it.
4071                  * While if there is no valid entry within the container, the container
4072                  * itself will be presented as a plain file under top `gpu_od` directory.
4073                  */
4074                 if (amdgpu_od_is_self_contained(adev, container)) {
4075                         if (!amdgpu_is_od_feature_supported(adev,
4076                              &container->ops))
4077                                 continue;
4078
4079                         /*
4080                          * The container is presented as a plain file under top `gpu_od`
4081                          * directory.
4082                          */
4083                         attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4084                         if (!attribute) {
4085                                 ret = -ENOMEM;
4086                                 goto err_out;
4087                         }
4088                         list_add(&attribute->entry, &top_set->attribute);
4089
4090                         attribute->attribute.attr.mode =
4091                                         container->ops.is_visible(adev);
4092                         attribute->attribute.attr.name = container->name;
4093                         attribute->attribute.show =
4094                                         container->ops.show;
4095                         attribute->attribute.store =
4096                                         container->ops.store;
4097                         ret = sysfs_create_file(&top_set->kobj,
4098                                                 &attribute->attribute.attr);
4099                         if (ret)
4100                                 goto err_out;
4101                 } else {
4102                         /* The container is presented as a sub directory. */
4103                         sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL);
4104                         if (!sub_set) {
4105                                 ret = -ENOMEM;
4106                                 goto err_out;
4107                         }
4108                         list_add(&sub_set->entry, &adev->pm.od_kobj_list);
4109
4110                         ret = kobject_init_and_add(&sub_set->kobj,
4111                                                    &od_ktype,
4112                                                    &top_set->kobj,
4113                                                    "%s",
4114                                                    container->name);
4115                         if (ret)
4116                                 goto err_out;
4117                         INIT_LIST_HEAD(&sub_set->attribute);
4118                         sub_set->priv = adev;
4119
4120                         for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) {
4121                                 feature = &container->sub_feature[j];
4122                                 if (!feature->name)
4123                                         continue;
4124
4125                                 if (!amdgpu_is_od_feature_supported(adev,
4126                                      &feature->ops))
4127                                         continue;
4128
4129                                 /*
4130                                  * With the container presented as a sub directory, the entry within
4131                                  * it is presented as a plain file under the sub directory.
4132                                  */
4133                                 attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4134                                 if (!attribute) {
4135                                         ret = -ENOMEM;
4136                                         goto err_out;
4137                                 }
4138                                 list_add(&attribute->entry, &sub_set->attribute);
4139
4140                                 attribute->attribute.attr.mode =
4141                                                 feature->ops.is_visible(adev);
4142                                 attribute->attribute.attr.name = feature->name;
4143                                 attribute->attribute.show =
4144                                                 feature->ops.show;
4145                                 attribute->attribute.store =
4146                                                 feature->ops.store;
4147                                 ret = sysfs_create_file(&sub_set->kobj,
4148                                                         &attribute->attribute.attr);
4149                                 if (ret)
4150                                         goto err_out;
4151                         }
4152                 }
4153         }
4154
4155         return 0;
4156
4157 err_out:
4158         amdgpu_od_set_fini(adev);
4159
4160         return ret;
4161 }
4162
4163 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
4164 {
4165         uint32_t mask = 0;
4166         int ret;
4167
4168         if (adev->pm.sysfs_initialized)
4169                 return 0;
4170
4171         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
4172
4173         if (adev->pm.dpm_enabled == 0)
4174                 return 0;
4175
4176         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
4177                                                                    DRIVER_NAME, adev,
4178                                                                    hwmon_groups);
4179         if (IS_ERR(adev->pm.int_hwmon_dev)) {
4180                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
4181                 dev_err(adev->dev,
4182                         "Unable to register hwmon device: %d\n", ret);
4183                 return ret;
4184         }
4185
4186         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
4187         case SRIOV_VF_MODE_ONE_VF:
4188                 mask = ATTR_FLAG_ONEVF;
4189                 break;
4190         case SRIOV_VF_MODE_MULTI_VF:
4191                 mask = 0;
4192                 break;
4193         case SRIOV_VF_MODE_BARE_METAL:
4194         default:
4195                 mask = ATTR_FLAG_MASK_ALL;
4196                 break;
4197         }
4198
4199         ret = amdgpu_device_attr_create_groups(adev,
4200                                                amdgpu_device_attrs,
4201                                                ARRAY_SIZE(amdgpu_device_attrs),
4202                                                mask,
4203                                                &adev->pm.pm_attr_list);
4204         if (ret)
4205                 goto err_out0;
4206
4207         if (amdgpu_dpm_is_overdrive_supported(adev)) {
4208                 ret = amdgpu_od_set_init(adev);
4209                 if (ret)
4210                         goto err_out1;
4211         }
4212
4213         adev->pm.sysfs_initialized = true;
4214
4215         return 0;
4216
4217 err_out1:
4218         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4219 err_out0:
4220         if (adev->pm.int_hwmon_dev)
4221                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4222
4223         return ret;
4224 }
4225
4226 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
4227 {
4228         amdgpu_od_set_fini(adev);
4229
4230         if (adev->pm.int_hwmon_dev)
4231                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
4232
4233         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4234 }
4235
4236 /*
4237  * Debugfs info
4238  */
4239 #if defined(CONFIG_DEBUG_FS)
4240
4241 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
4242                                            struct amdgpu_device *adev)
4243 {
4244         uint16_t *p_val;
4245         uint32_t size;
4246         int i;
4247         uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
4248
4249         if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
4250                 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
4251                                 GFP_KERNEL);
4252
4253                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
4254                                             (void *)p_val, &size)) {
4255                         for (i = 0; i < num_cpu_cores; i++)
4256                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
4257                                            *(p_val + i), i);
4258                 }
4259
4260                 kfree(p_val);
4261         }
4262 }
4263
4264 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
4265 {
4266         uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
4267         uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
4268         uint32_t value;
4269         uint64_t value64 = 0;
4270         uint32_t query = 0;
4271         int size;
4272
4273         /* GPU Clocks */
4274         size = sizeof(value);
4275         seq_printf(m, "GFX Clocks and Power:\n");
4276
4277         amdgpu_debugfs_prints_cpu_info(m, adev);
4278
4279         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
4280                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
4281         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
4282                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
4283         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
4284                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
4285         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
4286                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
4287         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
4288                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
4289         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
4290                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
4291         size = sizeof(uint32_t);
4292         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size))
4293                 seq_printf(m, "\t%u.%02u W (average GPU)\n", query >> 8, query & 0xff);
4294         size = sizeof(uint32_t);
4295         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size))
4296                 seq_printf(m, "\t%u.%02u W (current GPU)\n", query >> 8, query & 0xff);
4297         size = sizeof(value);
4298         seq_printf(m, "\n");
4299
4300         /* GPU Temp */
4301         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
4302                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
4303
4304         /* GPU Load */
4305         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
4306                 seq_printf(m, "GPU Load: %u %%\n", value);
4307         /* MEM Load */
4308         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
4309                 seq_printf(m, "MEM Load: %u %%\n", value);
4310
4311         seq_printf(m, "\n");
4312
4313         /* SMC feature mask */
4314         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
4315                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
4316
4317         /* ASICs greater than CHIP_VEGA20 supports these sensors */
4318         if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
4319                 /* VCN clocks */
4320                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
4321                         if (!value) {
4322                                 seq_printf(m, "VCN: Disabled\n");
4323                         } else {
4324                                 seq_printf(m, "VCN: Enabled\n");
4325                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4326                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4327                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4328                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4329                         }
4330                 }
4331                 seq_printf(m, "\n");
4332         } else {
4333                 /* UVD clocks */
4334                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
4335                         if (!value) {
4336                                 seq_printf(m, "UVD: Disabled\n");
4337                         } else {
4338                                 seq_printf(m, "UVD: Enabled\n");
4339                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4340                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4341                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4342                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4343                         }
4344                 }
4345                 seq_printf(m, "\n");
4346
4347                 /* VCE clocks */
4348                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
4349                         if (!value) {
4350                                 seq_printf(m, "VCE: Disabled\n");
4351                         } else {
4352                                 seq_printf(m, "VCE: Enabled\n");
4353                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
4354                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
4355                         }
4356                 }
4357         }
4358
4359         return 0;
4360 }
4361
4362 static const struct cg_flag_name clocks[] = {
4363         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
4364         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
4365         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
4366         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
4367         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
4368         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
4369         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
4370         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
4371         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
4372         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
4373         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
4374         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
4375         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
4376         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
4377         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
4378         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
4379         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
4380         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
4381         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
4382         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
4383         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
4384         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
4385         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
4386         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
4387         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
4388         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
4389         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
4390         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
4391         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
4392         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
4393         {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
4394         {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
4395         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
4396         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
4397         {0, NULL},
4398 };
4399
4400 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
4401 {
4402         int i;
4403
4404         for (i = 0; clocks[i].flag; i++)
4405                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
4406                            (flags & clocks[i].flag) ? "On" : "Off");
4407 }
4408
4409 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
4410 {
4411         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4412         struct drm_device *dev = adev_to_drm(adev);
4413         u64 flags = 0;
4414         int r;
4415
4416         if (amdgpu_in_reset(adev))
4417                 return -EPERM;
4418         if (adev->in_suspend && !adev->in_runpm)
4419                 return -EPERM;
4420
4421         r = pm_runtime_get_sync(dev->dev);
4422         if (r < 0) {
4423                 pm_runtime_put_autosuspend(dev->dev);
4424                 return r;
4425         }
4426
4427         if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
4428                 r = amdgpu_debugfs_pm_info_pp(m, adev);
4429                 if (r)
4430                         goto out;
4431         }
4432
4433         amdgpu_device_ip_get_clockgating_state(adev, &flags);
4434
4435         seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
4436         amdgpu_parse_cg_state(m, flags);
4437         seq_printf(m, "\n");
4438
4439 out:
4440         pm_runtime_mark_last_busy(dev->dev);
4441         pm_runtime_put_autosuspend(dev->dev);
4442
4443         return r;
4444 }
4445
4446 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
4447
4448 /*
4449  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
4450  *
4451  * Reads debug memory region allocated to PMFW
4452  */
4453 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
4454                                          size_t size, loff_t *pos)
4455 {
4456         struct amdgpu_device *adev = file_inode(f)->i_private;
4457         size_t smu_prv_buf_size;
4458         void *smu_prv_buf;
4459         int ret = 0;
4460
4461         if (amdgpu_in_reset(adev))
4462                 return -EPERM;
4463         if (adev->in_suspend && !adev->in_runpm)
4464                 return -EPERM;
4465
4466         ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
4467         if (ret)
4468                 return ret;
4469
4470         if (!smu_prv_buf || !smu_prv_buf_size)
4471                 return -EINVAL;
4472
4473         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
4474                                        smu_prv_buf_size);
4475 }
4476
4477 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
4478         .owner = THIS_MODULE,
4479         .open = simple_open,
4480         .read = amdgpu_pm_prv_buffer_read,
4481         .llseek = default_llseek,
4482 };
4483
4484 #endif
4485
4486 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
4487 {
4488 #if defined(CONFIG_DEBUG_FS)
4489         struct drm_minor *minor = adev_to_drm(adev)->primary;
4490         struct dentry *root = minor->debugfs_root;
4491
4492         if (!adev->pm.dpm_enabled)
4493                 return;
4494
4495         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
4496                             &amdgpu_debugfs_pm_info_fops);
4497
4498         if (adev->pm.smu_prv_buffer_size > 0)
4499                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
4500                                          adev,
4501                                          &amdgpu_debugfs_pm_prv_buffer_fops,
4502                                          adev->pm.smu_prv_buffer_size);
4503
4504         amdgpu_dpm_stb_debug_fs_init(adev);
4505 #endif
4506 }