drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <[email protected]>
  21  *          Alex Deucher <[email protected]>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #include "amd_powerplay.h"
  34
  35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  36
  37 static const struct cg_flag_name clocks[] = {
  38         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  39         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  40         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  42         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  43         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  44         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  46         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  49         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  50         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  51         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  54         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  56         {0, NULL},
  57 };
  58
  59 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  60 {
  61         if (adev->pp_enabled)
  62                 /* TODO */
  63                 return;
  64
  65         if (adev->pm.dpm_enabled) {
  66                 mutex_lock(&adev->pm.mutex);
  67                 if (power_supply_is_system_supplied() > 0)
  68                         adev->pm.dpm.ac_power = true;
  69                 else
  70                         adev->pm.dpm.ac_power = false;
  71                 if (adev->pm.funcs->enable_bapm)
  72                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  73                 mutex_unlock(&adev->pm.mutex);
  74         }
  75 }
  76
  77 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  78                                     struct device_attribute *attr,
  79                                     char *buf)
  80 {
  81         struct drm_device *ddev = dev_get_drvdata(dev);
  82         struct amdgpu_device *adev = ddev->dev_private;
  83         enum amd_pm_state_type pm;
  84
  85         if (adev->pp_enabled) {
  86                 pm = amdgpu_dpm_get_current_power_state(adev);
  87         } else
  88                 pm = adev->pm.dpm.user_state;
  89
  90         return snprintf(buf, PAGE_SIZE, "%s\n",
  91                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  92                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  93 }
  94
  95 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  96                                     struct device_attribute *attr,
  97                                     const char *buf,
  98                                     size_t count)
  99 {
 100         struct drm_device *ddev = dev_get_drvdata(dev);
 101         struct amdgpu_device *adev = ddev->dev_private;
 102         enum amd_pm_state_type  state;
 103
 104         if (strncmp("battery", buf, strlen("battery")) == 0)
 105                 state = POWER_STATE_TYPE_BATTERY;
 106         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 107                 state = POWER_STATE_TYPE_BALANCED;
 108         else if (strncmp("performance", buf, strlen("performance")) == 0)
 109                 state = POWER_STATE_TYPE_PERFORMANCE;
 110         else {
 111                 count = -EINVAL;
 112                 goto fail;
 113         }
 114
 115         if (adev->pp_enabled) {
 116                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 117         } else {
 118                 mutex_lock(&adev->pm.mutex);
 119                 adev->pm.dpm.user_state = state;
 120                 mutex_unlock(&adev->pm.mutex);
 121
 122                 /* Can't set dpm state when the card is off */
 123                 if (!(adev->flags & AMD_IS_PX) ||
 124                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 125                         amdgpu_pm_compute_clocks(adev);
 126         }
 127 fail:
 128         return count;
 129 }
 130
 131 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 132                                                 struct device_attribute *attr,
 133                                                                 char *buf)
 134 {
 135         struct drm_device *ddev = dev_get_drvdata(dev);
 136         struct amdgpu_device *adev = ddev->dev_private;
 137         enum amd_dpm_forced_level level;
 138
 139         if  ((adev->flags & AMD_IS_PX) &&
 140              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 141                 return snprintf(buf, PAGE_SIZE, "off\n");
 142
 143         level = amdgpu_dpm_get_performance_level(adev);
 144         return snprintf(buf, PAGE_SIZE, "%s\n",
 145                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 146                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 147                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 148                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 149                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 150                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 151                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 152                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 153                         "unknown");
 154 }
 155
 156 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 157                                                        struct device_attribute *attr,
 158                                                        const char *buf,
 159                                                        size_t count)
 160 {
 161         struct drm_device *ddev = dev_get_drvdata(dev);
 162         struct amdgpu_device *adev = ddev->dev_private;
 163         enum amd_dpm_forced_level level;
 164         enum amd_dpm_forced_level current_level;
 165         int ret = 0;
 166
 167         /* Can't force performance level when the card is off */
 168         if  ((adev->flags & AMD_IS_PX) &&
 169              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 170                 return -EINVAL;
 171
 172         current_level = amdgpu_dpm_get_performance_level(adev);
 173
 174         if (strncmp("low", buf, strlen("low")) == 0) {
 175                 level = AMD_DPM_FORCED_LEVEL_LOW;
 176         } else if (strncmp("high", buf, strlen("high")) == 0) {
 177                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 178         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 179                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 180         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 181                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 182         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 183                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 184         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 185                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 186         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 187                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 188         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 189                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 190         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 191                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 192         }  else {
 193                 count = -EINVAL;
 194                 goto fail;
 195         }
 196
 197         if (current_level == level)
 198                 return count;
 199
 200         if (adev->pp_enabled)
 201                 amdgpu_dpm_force_performance_level(adev, level);
 202         else {
 203                 mutex_lock(&adev->pm.mutex);
 204                 if (adev->pm.dpm.thermal_active) {
 205                         count = -EINVAL;
 206                         mutex_unlock(&adev->pm.mutex);
 207                         goto fail;
 208                 }
 209                 ret = amdgpu_dpm_force_performance_level(adev, level);
 210                 if (ret)
 211                         count = -EINVAL;
 212                 else
 213                         adev->pm.dpm.forced_level = level;
 214                 mutex_unlock(&adev->pm.mutex);
 215         }
 216
 217 fail:
 218         return count;
 219 }
 220
 221 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 222                 struct device_attribute *attr,
 223                 char *buf)
 224 {
 225         struct drm_device *ddev = dev_get_drvdata(dev);
 226         struct amdgpu_device *adev = ddev->dev_private;
 227         struct pp_states_info data;
 228         int i, buf_len;
 229
 230         if (adev->pp_enabled)
 231                 amdgpu_dpm_get_pp_num_states(adev, &data);
 232
 233         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 234         for (i = 0; i < data.nums; i++)
 235                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 236                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 237                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 238                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 239                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 240
 241         return buf_len;
 242 }
 243
 244 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 245                 struct device_attribute *attr,
 246                 char *buf)
 247 {
 248         struct drm_device *ddev = dev_get_drvdata(dev);
 249         struct amdgpu_device *adev = ddev->dev_private;
 250         struct pp_states_info data;
 251         enum amd_pm_state_type pm = 0;
 252         int i = 0;
 253
 254         if (adev->pp_enabled) {
 255
 256                 pm = amdgpu_dpm_get_current_power_state(adev);
 257                 amdgpu_dpm_get_pp_num_states(adev, &data);
 258
 259                 for (i = 0; i < data.nums; i++) {
 260                         if (pm == data.states[i])
 261                                 break;
 262                 }
 263
 264                 if (i == data.nums)
 265                         i = -EINVAL;
 266         }
 267
 268         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 269 }
 270
 271 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 272                 struct device_attribute *attr,
 273                 char *buf)
 274 {
 275         struct drm_device *ddev = dev_get_drvdata(dev);
 276         struct amdgpu_device *adev = ddev->dev_private;
 277         struct pp_states_info data;
 278         enum amd_pm_state_type pm = 0;
 279         int i;
 280
 281         if (adev->pp_force_state_enabled && adev->pp_enabled) {
 282                 pm = amdgpu_dpm_get_current_power_state(adev);
 283                 amdgpu_dpm_get_pp_num_states(adev, &data);
 284
 285                 for (i = 0; i < data.nums; i++) {
 286                         if (pm == data.states[i])
 287                                 break;
 288                 }
 289
 290                 if (i == data.nums)
 291                         i = -EINVAL;
 292
 293                 return snprintf(buf, PAGE_SIZE, "%d\n", i);
 294
 295         } else
 296                 return snprintf(buf, PAGE_SIZE, "\n");
 297 }
 298
 299 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 300                 struct device_attribute *attr,
 301                 const char *buf,
 302                 size_t count)
 303 {
 304         struct drm_device *ddev = dev_get_drvdata(dev);
 305         struct amdgpu_device *adev = ddev->dev_private;
 306         enum amd_pm_state_type state = 0;
 307         unsigned long idx;
 308         int ret;
 309
 310         if (strlen(buf) == 1)
 311                 adev->pp_force_state_enabled = false;
 312         else if (adev->pp_enabled) {
 313                 struct pp_states_info data;
 314
 315                 ret = kstrtoul(buf, 0, &idx);
 316                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 317                         count = -EINVAL;
 318                         goto fail;
 319                 }
 320
 321                 amdgpu_dpm_get_pp_num_states(adev, &data);
 322                 state = data.states[idx];
 323                 /* only set user selected power states */
 324                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 325                     state != POWER_STATE_TYPE_DEFAULT) {
 326                         amdgpu_dpm_dispatch_task(adev,
 327                                         AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 328                         adev->pp_force_state_enabled = true;
 329                 }
 330         }
 331 fail:
 332         return count;
 333 }
 334
 335 static ssize_t amdgpu_get_pp_table(struct device *dev,
 336                 struct device_attribute *attr,
 337                 char *buf)
 338 {
 339         struct drm_device *ddev = dev_get_drvdata(dev);
 340         struct amdgpu_device *adev = ddev->dev_private;
 341         char *table = NULL;
 342         int size;
 343
 344         if (adev->pp_enabled)
 345                 size = amdgpu_dpm_get_pp_table(adev, &table);
 346         else
 347                 return 0;
 348
 349         if (size >= PAGE_SIZE)
 350                 size = PAGE_SIZE - 1;
 351
 352         memcpy(buf, table, size);
 353
 354         return size;
 355 }
 356
 357 static ssize_t amdgpu_set_pp_table(struct device *dev,
 358                 struct device_attribute *attr,
 359                 const char *buf,
 360                 size_t count)
 361 {
 362         struct drm_device *ddev = dev_get_drvdata(dev);
 363         struct amdgpu_device *adev = ddev->dev_private;
 364
 365         if (adev->pp_enabled)
 366                 amdgpu_dpm_set_pp_table(adev, buf, count);
 367
 368         return count;
 369 }
 370
 371 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 372                 struct device_attribute *attr,
 373                 char *buf)
 374 {
 375         struct drm_device *ddev = dev_get_drvdata(dev);
 376         struct amdgpu_device *adev = ddev->dev_private;
 377         ssize_t size = 0;
 378
 379         if (adev->pp_enabled)
 380                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 381         else if (adev->pm.funcs->print_clock_levels)
 382                 size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
 383
 384         return size;
 385 }
 386
 387 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 388                 struct device_attribute *attr,
 389                 const char *buf,
 390                 size_t count)
 391 {
 392         struct drm_device *ddev = dev_get_drvdata(dev);
 393         struct amdgpu_device *adev = ddev->dev_private;
 394         int ret;
 395         long level;
 396         uint32_t i, mask = 0;
 397         char sub_str[2];
 398
 399         for (i = 0; i < strlen(buf); i++) {
 400                 if (*(buf + i) == '\n')
 401                         continue;
 402                 sub_str[0] = *(buf + i);
 403                 sub_str[1] = '\0';
 404                 ret = kstrtol(sub_str, 0, &level);
 405
 406                 if (ret) {
 407                         count = -EINVAL;
 408                         goto fail;
 409                 }
 410                 mask |= 1 << level;
 411         }
 412
 413         if (adev->pp_enabled)
 414                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 415         else if (adev->pm.funcs->force_clock_level)
 416                 adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
 417 fail:
 418         return count;
 419 }
 420
 421 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 422                 struct device_attribute *attr,
 423                 char *buf)
 424 {
 425         struct drm_device *ddev = dev_get_drvdata(dev);
 426         struct amdgpu_device *adev = ddev->dev_private;
 427         ssize_t size = 0;
 428
 429         if (adev->pp_enabled)
 430                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 431         else if (adev->pm.funcs->print_clock_levels)
 432                 size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
 433
 434         return size;
 435 }
 436
 437 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 438                 struct device_attribute *attr,
 439                 const char *buf,
 440                 size_t count)
 441 {
 442         struct drm_device *ddev = dev_get_drvdata(dev);
 443         struct amdgpu_device *adev = ddev->dev_private;
 444         int ret;
 445         long level;
 446         uint32_t i, mask = 0;
 447         char sub_str[2];
 448
 449         for (i = 0; i < strlen(buf); i++) {
 450                 if (*(buf + i) == '\n')
 451                         continue;
 452                 sub_str[0] = *(buf + i);
 453                 sub_str[1] = '\0';
 454                 ret = kstrtol(sub_str, 0, &level);
 455
 456                 if (ret) {
 457                         count = -EINVAL;
 458                         goto fail;
 459                 }
 460                 mask |= 1 << level;
 461         }
 462
 463         if (adev->pp_enabled)
 464                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 465         else if (adev->pm.funcs->force_clock_level)
 466                 adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
 467 fail:
 468         return count;
 469 }
 470
 471 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 472                 struct device_attribute *attr,
 473                 char *buf)
 474 {
 475         struct drm_device *ddev = dev_get_drvdata(dev);
 476         struct amdgpu_device *adev = ddev->dev_private;
 477         ssize_t size = 0;
 478
 479         if (adev->pp_enabled)
 480                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 481         else if (adev->pm.funcs->print_clock_levels)
 482                 size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
 483
 484         return size;
 485 }
 486
 487 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 488                 struct device_attribute *attr,
 489                 const char *buf,
 490                 size_t count)
 491 {
 492         struct drm_device *ddev = dev_get_drvdata(dev);
 493         struct amdgpu_device *adev = ddev->dev_private;
 494         int ret;
 495         long level;
 496         uint32_t i, mask = 0;
 497         char sub_str[2];
 498
 499         for (i = 0; i < strlen(buf); i++) {
 500                 if (*(buf + i) == '\n')
 501                         continue;
 502                 sub_str[0] = *(buf + i);
 503                 sub_str[1] = '\0';
 504                 ret = kstrtol(sub_str, 0, &level);
 505
 506                 if (ret) {
 507                         count = -EINVAL;
 508                         goto fail;
 509                 }
 510                 mask |= 1 << level;
 511         }
 512
 513         if (adev->pp_enabled)
 514                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 515         else if (adev->pm.funcs->force_clock_level)
 516                 adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
 517 fail:
 518         return count;
 519 }
 520
 521 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 522                 struct device_attribute *attr,
 523                 char *buf)
 524 {
 525         struct drm_device *ddev = dev_get_drvdata(dev);
 526         struct amdgpu_device *adev = ddev->dev_private;
 527         uint32_t value = 0;
 528
 529         if (adev->pp_enabled)
 530                 value = amdgpu_dpm_get_sclk_od(adev);
 531         else if (adev->pm.funcs->get_sclk_od)
 532                 value = adev->pm.funcs->get_sclk_od(adev);
 533
 534         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 535 }
 536
 537 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 538                 struct device_attribute *attr,
 539                 const char *buf,
 540                 size_t count)
 541 {
 542         struct drm_device *ddev = dev_get_drvdata(dev);
 543         struct amdgpu_device *adev = ddev->dev_private;
 544         int ret;
 545         long int value;
 546
 547         ret = kstrtol(buf, 0, &value);
 548
 549         if (ret) {
 550                 count = -EINVAL;
 551                 goto fail;
 552         }
 553
 554         if (adev->pp_enabled) {
 555                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 556                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 557         } else if (adev->pm.funcs->set_sclk_od) {
 558                 adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
 559                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 560                 amdgpu_pm_compute_clocks(adev);
 561         }
 562
 563 fail:
 564         return count;
 565 }
 566
 567 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 568                 struct device_attribute *attr,
 569                 char *buf)
 570 {
 571         struct drm_device *ddev = dev_get_drvdata(dev);
 572         struct amdgpu_device *adev = ddev->dev_private;
 573         uint32_t value = 0;
 574
 575         if (adev->pp_enabled)
 576                 value = amdgpu_dpm_get_mclk_od(adev);
 577         else if (adev->pm.funcs->get_mclk_od)
 578                 value = adev->pm.funcs->get_mclk_od(adev);
 579
 580         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 581 }
 582
 583 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 584                 struct device_attribute *attr,
 585                 const char *buf,
 586                 size_t count)
 587 {
 588         struct drm_device *ddev = dev_get_drvdata(dev);
 589         struct amdgpu_device *adev = ddev->dev_private;
 590         int ret;
 591         long int value;
 592
 593         ret = kstrtol(buf, 0, &value);
 594
 595         if (ret) {
 596                 count = -EINVAL;
 597                 goto fail;
 598         }
 599
 600         if (adev->pp_enabled) {
 601                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 602                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 603         } else if (adev->pm.funcs->set_mclk_od) {
 604                 adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
 605                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 606                 amdgpu_pm_compute_clocks(adev);
 607         }
 608
 609 fail:
 610         return count;
 611 }
 612
 613 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 614 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 615                    amdgpu_get_dpm_forced_performance_level,
 616                    amdgpu_set_dpm_forced_performance_level);
 617 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 618 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 619 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 620                 amdgpu_get_pp_force_state,
 621                 amdgpu_set_pp_force_state);
 622 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 623                 amdgpu_get_pp_table,
 624                 amdgpu_set_pp_table);
 625 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 626                 amdgpu_get_pp_dpm_sclk,
 627                 amdgpu_set_pp_dpm_sclk);
 628 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 629                 amdgpu_get_pp_dpm_mclk,
 630                 amdgpu_set_pp_dpm_mclk);
 631 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 632                 amdgpu_get_pp_dpm_pcie,
 633                 amdgpu_set_pp_dpm_pcie);
 634 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 635                 amdgpu_get_pp_sclk_od,
 636                 amdgpu_set_pp_sclk_od);
 637 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 638                 amdgpu_get_pp_mclk_od,
 639                 amdgpu_set_pp_mclk_od);
 640
 641 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 642                                       struct device_attribute *attr,
 643                                       char *buf)
 644 {
 645         struct amdgpu_device *adev = dev_get_drvdata(dev);
 646         struct drm_device *ddev = adev->ddev;
 647         int temp;
 648
 649         /* Can't get temperature when the card is off */
 650         if  ((adev->flags & AMD_IS_PX) &&
 651              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 652                 return -EINVAL;
 653
 654         if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
 655                 temp = 0;
 656         else
 657                 temp = amdgpu_dpm_get_temperature(adev);
 658
 659         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 660 }
 661
 662 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 663                                              struct device_attribute *attr,
 664                                              char *buf)
 665 {
 666         struct amdgpu_device *adev = dev_get_drvdata(dev);
 667         int hyst = to_sensor_dev_attr(attr)->index;
 668         int temp;
 669
 670         if (hyst)
 671                 temp = adev->pm.dpm.thermal.min_temp;
 672         else
 673                 temp = adev->pm.dpm.thermal.max_temp;
 674
 675         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 676 }
 677
 678 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 679                                             struct device_attribute *attr,
 680                                             char *buf)
 681 {
 682         struct amdgpu_device *adev = dev_get_drvdata(dev);
 683         u32 pwm_mode = 0;
 684
 685         if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
 686                 return -EINVAL;
 687
 688         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 689
 690         /* never 0 (full-speed), fuse or smc-controlled always */
 691         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 692 }
 693
 694 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 695                                             struct device_attribute *attr,
 696                                             const char *buf,
 697                                             size_t count)
 698 {
 699         struct amdgpu_device *adev = dev_get_drvdata(dev);
 700         int err;
 701         int value;
 702
 703         if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
 704                 return -EINVAL;
 705
 706         err = kstrtoint(buf, 10, &value);
 707         if (err)
 708                 return err;
 709
 710         switch (value) {
 711         case 1: /* manual, percent-based */
 712                 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
 713                 break;
 714         default: /* disable */
 715                 amdgpu_dpm_set_fan_control_mode(adev, 0);
 716                 break;
 717         }
 718
 719         return count;
 720 }
 721
 722 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 723                                          struct device_attribute *attr,
 724                                          char *buf)
 725 {
 726         return sprintf(buf, "%i\n", 0);
 727 }
 728
 729 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 730                                          struct device_attribute *attr,
 731                                          char *buf)
 732 {
 733         return sprintf(buf, "%i\n", 255);
 734 }
 735
 736 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 737                                      struct device_attribute *attr,
 738                                      const char *buf, size_t count)
 739 {
 740         struct amdgpu_device *adev = dev_get_drvdata(dev);
 741         int err;
 742         u32 value;
 743
 744         err = kstrtou32(buf, 10, &value);
 745         if (err)
 746                 return err;
 747
 748         value = (value * 100) / 255;
 749
 750         err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 751         if (err)
 752                 return err;
 753
 754         return count;
 755 }
 756
 757 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 758                                      struct device_attribute *attr,
 759                                      char *buf)
 760 {
 761         struct amdgpu_device *adev = dev_get_drvdata(dev);
 762         int err;
 763         u32 speed;
 764
 765         err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 766         if (err)
 767                 return err;
 768
 769         speed = (speed * 255) / 100;
 770
 771         return sprintf(buf, "%i\n", speed);
 772 }
 773
 774 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 775                                            struct device_attribute *attr,
 776                                            char *buf)
 777 {
 778         struct amdgpu_device *adev = dev_get_drvdata(dev);
 779         int err;
 780         u32 speed;
 781
 782         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 783         if (err)
 784                 return err;
 785
 786         return sprintf(buf, "%i\n", speed);
 787 }
 788
 789 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 790 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 791 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 792 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 793 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 794 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 795 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 796 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
 797
 798 static struct attribute *hwmon_attributes[] = {
 799         &sensor_dev_attr_temp1_input.dev_attr.attr,
 800         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 801         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 802         &sensor_dev_attr_pwm1.dev_attr.attr,
 803         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 804         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 805         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 806         &sensor_dev_attr_fan1_input.dev_attr.attr,
 807         NULL
 808 };
 809
 810 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 811                                         struct attribute *attr, int index)
 812 {
 813         struct device *dev = kobj_to_dev(kobj);
 814         struct amdgpu_device *adev = dev_get_drvdata(dev);
 815         umode_t effective_mode = attr->mode;
 816
 817         /* Skip limit attributes if DPM is not enabled */
 818         if (!adev->pm.dpm_enabled &&
 819             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 820              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 821              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 822              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 823              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 824              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 825                 return 0;
 826
 827         if (adev->pp_enabled)
 828                 return effective_mode;
 829
 830         /* Skip fan attributes if fan is not present */
 831         if (adev->pm.no_fan &&
 832             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 833              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 834              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 835              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 836                 return 0;
 837
 838         /* mask fan attributes if we have no bindings for this asic to expose */
 839         if ((!adev->pm.funcs->get_fan_speed_percent &&
 840              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 841             (!adev->pm.funcs->get_fan_control_mode &&
 842              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 843                 effective_mode &= ~S_IRUGO;
 844
 845         if ((!adev->pm.funcs->set_fan_speed_percent &&
 846              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 847             (!adev->pm.funcs->set_fan_control_mode &&
 848              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 849                 effective_mode &= ~S_IWUSR;
 850
 851         /* hide max/min values if we can't both query and manage the fan */
 852         if ((!adev->pm.funcs->set_fan_speed_percent &&
 853              !adev->pm.funcs->get_fan_speed_percent) &&
 854             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 855              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 856                 return 0;
 857
 858         /* requires powerplay */
 859         if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
 860                 return 0;
 861
 862         return effective_mode;
 863 }
 864
 865 static const struct attribute_group hwmon_attrgroup = {
 866         .attrs = hwmon_attributes,
 867         .is_visible = hwmon_attributes_visible,
 868 };
 869
 870 static const struct attribute_group *hwmon_groups[] = {
 871         &hwmon_attrgroup,
 872         NULL
 873 };
 874
 875 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
 876 {
 877         struct amdgpu_device *adev =
 878                 container_of(work, struct amdgpu_device,
 879                              pm.dpm.thermal.work);
 880         /* switch to the thermal state */
 881         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 882
 883         if (!adev->pm.dpm_enabled)
 884                 return;
 885
 886         if (adev->pm.funcs->get_temperature) {
 887                 int temp = amdgpu_dpm_get_temperature(adev);
 888
 889                 if (temp < adev->pm.dpm.thermal.min_temp)
 890                         /* switch back the user state */
 891                         dpm_state = adev->pm.dpm.user_state;
 892         } else {
 893                 if (adev->pm.dpm.thermal.high_to_low)
 894                         /* switch back the user state */
 895                         dpm_state = adev->pm.dpm.user_state;
 896         }
 897         mutex_lock(&adev->pm.mutex);
 898         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 899                 adev->pm.dpm.thermal_active = true;
 900         else
 901                 adev->pm.dpm.thermal_active = false;
 902         adev->pm.dpm.state = dpm_state;
 903         mutex_unlock(&adev->pm.mutex);
 904
 905         amdgpu_pm_compute_clocks(adev);
 906 }
 907
 908 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
 909                                                      enum amd_pm_state_type dpm_state)
 910 {
 911         int i;
 912         struct amdgpu_ps *ps;
 913         u32 ui_class;
 914         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
 915                 true : false;
 916
 917         /* check if the vblank period is too short to adjust the mclk */
 918         if (single_display && adev->pm.funcs->vblank_too_short) {
 919                 if (amdgpu_dpm_vblank_too_short(adev))
 920                         single_display = false;
 921         }
 922
 923         /* certain older asics have a separare 3D performance state,
 924          * so try that first if the user selected performance
 925          */
 926         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 927                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 928         /* balanced states don't exist at the moment */
 929         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 930                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 931
 932 restart_search:
 933         /* Pick the best power state based on current conditions */
 934         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
 935                 ps = &adev->pm.dpm.ps[i];
 936                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 937                 switch (dpm_state) {
 938                 /* user states */
 939                 case POWER_STATE_TYPE_BATTERY:
 940                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 941                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 942                                         if (single_display)
 943                                                 return ps;
 944                                 } else
 945                                         return ps;
 946                         }
 947                         break;
 948                 case POWER_STATE_TYPE_BALANCED:
 949                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 950                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 951                                         if (single_display)
 952                                                 return ps;
 953                                 } else
 954                                         return ps;
 955                         }
 956                         break;
 957                 case POWER_STATE_TYPE_PERFORMANCE:
 958                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 959                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 960                                         if (single_display)
 961                                                 return ps;
 962                                 } else
 963                                         return ps;
 964                         }
 965                         break;
 966                 /* internal states */
 967                 case POWER_STATE_TYPE_INTERNAL_UVD:
 968                         if (adev->pm.dpm.uvd_ps)
 969                                 return adev->pm.dpm.uvd_ps;
 970                         else
 971                                 break;
 972                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 973                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 974                                 return ps;
 975                         break;
 976                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 977                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 978                                 return ps;
 979                         break;
 980                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 981                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 982                                 return ps;
 983                         break;
 984                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 985                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 986                                 return ps;
 987                         break;
 988                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 989                         return adev->pm.dpm.boot_ps;
 990                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 991                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 992                                 return ps;
 993                         break;
 994                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 995                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 996                                 return ps;
 997                         break;
 998                 case POWER_STATE_TYPE_INTERNAL_ULV:
 999                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1000                                 return ps;
1001                         break;
1002                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1003                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1004                                 return ps;
1005                         break;
1006                 default:
1007                         break;
1008                 }
1009         }
1010         /* use a fallback state if we didn't match */
1011         switch (dpm_state) {
1012         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1013                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1014                 goto restart_search;
1015         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1016         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1017         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1018                 if (adev->pm.dpm.uvd_ps) {
1019                         return adev->pm.dpm.uvd_ps;
1020                 } else {
1021                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1022                         goto restart_search;
1023                 }
1024         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1025                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1026                 goto restart_search;
1027         case POWER_STATE_TYPE_INTERNAL_ACPI:
1028                 dpm_state = POWER_STATE_TYPE_BATTERY;
1029                 goto restart_search;
1030         case POWER_STATE_TYPE_BATTERY:
1031         case POWER_STATE_TYPE_BALANCED:
1032         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1033                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1034                 goto restart_search;
1035         default:
1036                 break;
1037         }
1038
1039         return NULL;
1040 }
1041
1042 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1043 {
1044         struct amdgpu_ps *ps;
1045         enum amd_pm_state_type dpm_state;
1046         int ret;
1047         bool equal;
1048
1049         /* if dpm init failed */
1050         if (!adev->pm.dpm_enabled)
1051                 return;
1052
1053         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1054                 /* add other state override checks here */
1055                 if ((!adev->pm.dpm.thermal_active) &&
1056                     (!adev->pm.dpm.uvd_active))
1057                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1058         }
1059         dpm_state = adev->pm.dpm.state;
1060
1061         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1062         if (ps)
1063                 adev->pm.dpm.requested_ps = ps;
1064         else
1065                 return;
1066
1067         if (amdgpu_dpm == 1) {
1068                 printk("switching from power state:\n");
1069                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1070                 printk("switching to power state:\n");
1071                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1072         }
1073
1074         /* update whether vce is active */
1075         ps->vce_active = adev->pm.dpm.vce_active;
1076
1077         amdgpu_dpm_display_configuration_changed(adev);
1078
1079         ret = amdgpu_dpm_pre_set_power_state(adev);
1080         if (ret)
1081                 return;
1082
1083         if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)))
1084                 equal = false;
1085
1086         if (equal)
1087                 return;
1088
1089         amdgpu_dpm_set_power_state(adev);
1090         amdgpu_dpm_post_set_power_state(adev);
1091
1092         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1093         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1094
1095         if (adev->pm.funcs->force_performance_level) {
1096                 if (adev->pm.dpm.thermal_active) {
1097                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1098                         /* force low perf level for thermal */
1099                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1100                         /* save the user's level */
1101                         adev->pm.dpm.forced_level = level;
1102                 } else {
1103                         /* otherwise, user selected level */
1104                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1105                 }
1106         }
1107 }
1108
1109 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1110 {
1111         if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
1112                 /* enable/disable UVD */
1113                 mutex_lock(&adev->pm.mutex);
1114                 amdgpu_dpm_powergate_uvd(adev, !enable);
1115                 mutex_unlock(&adev->pm.mutex);
1116         } else {
1117                 if (enable) {
1118                         mutex_lock(&adev->pm.mutex);
1119                         adev->pm.dpm.uvd_active = true;
1120                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1121                         mutex_unlock(&adev->pm.mutex);
1122                 } else {
1123                         mutex_lock(&adev->pm.mutex);
1124                         adev->pm.dpm.uvd_active = false;
1125                         mutex_unlock(&adev->pm.mutex);
1126                 }
1127                 amdgpu_pm_compute_clocks(adev);
1128         }
1129 }
1130
1131 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1132 {
1133         if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
1134                 /* enable/disable VCE */
1135                 mutex_lock(&adev->pm.mutex);
1136                 amdgpu_dpm_powergate_vce(adev, !enable);
1137                 mutex_unlock(&adev->pm.mutex);
1138         } else {
1139                 if (enable) {
1140                         mutex_lock(&adev->pm.mutex);
1141                         adev->pm.dpm.vce_active = true;
1142                         /* XXX select vce level based on ring/task */
1143                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1144                         mutex_unlock(&adev->pm.mutex);
1145                         amdgpu_pm_compute_clocks(adev);
1146                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1147                                                         AMD_PG_STATE_UNGATE);
1148                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1149                                                         AMD_CG_STATE_UNGATE);
1150                 } else {
1151                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1152                                                         AMD_PG_STATE_GATE);
1153                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1154                                                         AMD_CG_STATE_GATE);
1155                         mutex_lock(&adev->pm.mutex);
1156                         adev->pm.dpm.vce_active = false;
1157                         mutex_unlock(&adev->pm.mutex);
1158                         amdgpu_pm_compute_clocks(adev);
1159                 }
1160
1161         }
1162 }
1163
1164 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1165 {
1166         int i;
1167
1168         if (adev->pp_enabled)
1169                 /* TO DO */
1170                 return;
1171
1172         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1173                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1174
1175 }
1176
1177 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1178 {
1179         int ret;
1180
1181         if (adev->pm.sysfs_initialized)
1182                 return 0;
1183
1184         if (!adev->pp_enabled) {
1185                 if (adev->pm.funcs->get_temperature == NULL)
1186                         return 0;
1187         }
1188
1189         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1190                                                                    DRIVER_NAME, adev,
1191                                                                    hwmon_groups);
1192         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1193                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1194                 dev_err(adev->dev,
1195                         "Unable to register hwmon device: %d\n", ret);
1196                 return ret;
1197         }
1198
1199         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1200         if (ret) {
1201                 DRM_ERROR("failed to create device file for dpm state\n");
1202                 return ret;
1203         }
1204         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1205         if (ret) {
1206                 DRM_ERROR("failed to create device file for dpm state\n");
1207                 return ret;
1208         }
1209
1210         if (adev->pp_enabled) {
1211                 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1212                 if (ret) {
1213                         DRM_ERROR("failed to create device file pp_num_states\n");
1214                         return ret;
1215                 }
1216                 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1217                 if (ret) {
1218                         DRM_ERROR("failed to create device file pp_cur_state\n");
1219                         return ret;
1220                 }
1221                 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1222                 if (ret) {
1223                         DRM_ERROR("failed to create device file pp_force_state\n");
1224                         return ret;
1225                 }
1226                 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1227                 if (ret) {
1228                         DRM_ERROR("failed to create device file pp_table\n");
1229                         return ret;
1230                 }
1231         }
1232
1233         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1234         if (ret) {
1235                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1236                 return ret;
1237         }
1238         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1239         if (ret) {
1240                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1241                 return ret;
1242         }
1243         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1244         if (ret) {
1245                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1246                 return ret;
1247         }
1248         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1249         if (ret) {
1250                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1251                 return ret;
1252         }
1253         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1254         if (ret) {
1255                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1256                 return ret;
1257         }
1258
1259         ret = amdgpu_debugfs_pm_init(adev);
1260         if (ret) {
1261                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1262                 return ret;
1263         }
1264
1265         adev->pm.sysfs_initialized = true;
1266
1267         return 0;
1268 }
1269
1270 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1271 {
1272         if (adev->pm.int_hwmon_dev)
1273                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1274         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1275         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1276         if (adev->pp_enabled) {
1277                 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1278                 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1279                 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1280                 device_remove_file(adev->dev, &dev_attr_pp_table);
1281         }
1282         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1283         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1284         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1285         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1286         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1287 }
1288
1289 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1290 {
1291         struct drm_device *ddev = adev->ddev;
1292         struct drm_crtc *crtc;
1293         struct amdgpu_crtc *amdgpu_crtc;
1294         int i = 0;
1295
1296         if (!adev->pm.dpm_enabled)
1297                 return;
1298
1299         if (adev->mode_info.num_crtc)
1300                 amdgpu_display_bandwidth_update(adev);
1301
1302         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1303                 struct amdgpu_ring *ring = adev->rings[i];
1304                 if (ring && ring->ready)
1305                         amdgpu_fence_wait_empty(ring);
1306         }
1307
1308         if (adev->pp_enabled) {
1309                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1310         } else {
1311                 mutex_lock(&adev->pm.mutex);
1312                 adev->pm.dpm.new_active_crtcs = 0;
1313                 adev->pm.dpm.new_active_crtc_count = 0;
1314                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1315                         list_for_each_entry(crtc,
1316                                             &ddev->mode_config.crtc_list, head) {
1317                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1318                                 if (crtc->enabled) {
1319                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1320                                         adev->pm.dpm.new_active_crtc_count++;
1321                                 }
1322                         }
1323                 }
1324                 /* update battery/ac status */
1325                 if (power_supply_is_system_supplied() > 0)
1326                         adev->pm.dpm.ac_power = true;
1327                 else
1328                         adev->pm.dpm.ac_power = false;
1329
1330                 amdgpu_dpm_change_power_state_locked(adev);
1331
1332                 mutex_unlock(&adev->pm.mutex);
1333         }
1334 }
1335
1336 /*
1337  * Debugfs info
1338  */
1339 #if defined(CONFIG_DEBUG_FS)
1340
1341 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1342 {
1343         int32_t value;
1344
1345         /* sanity check PP is enabled */
1346         if (!(adev->powerplay.pp_funcs &&
1347               adev->powerplay.pp_funcs->read_sensor))
1348               return -EINVAL;
1349
1350         /* GPU Clocks */
1351         seq_printf(m, "GFX Clocks and Power:\n");
1352         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, &value))
1353                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1354         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, &value))
1355                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1356         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, &value))
1357                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1358         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, &value))
1359                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1360         seq_printf(m, "\n");
1361
1362         /* GPU Temp */
1363         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, &value))
1364                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1365
1366         /* GPU Load */
1367         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value))
1368                 seq_printf(m, "GPU Load: %u %%\n", value);
1369         seq_printf(m, "\n");
1370
1371         /* UVD clocks */
1372         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, &value)) {
1373                 if (!value) {
1374                         seq_printf(m, "UVD: Disabled\n");
1375                 } else {
1376                         seq_printf(m, "UVD: Enabled\n");
1377                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, &value))
1378                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1379                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, &value))
1380                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1381                 }
1382         }
1383         seq_printf(m, "\n");
1384
1385         /* VCE clocks */
1386         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, &value)) {
1387                 if (!value) {
1388                         seq_printf(m, "VCE: Disabled\n");
1389                 } else {
1390                         seq_printf(m, "VCE: Enabled\n");
1391                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, &value))
1392                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1393                 }
1394         }
1395
1396         return 0;
1397 }
1398
1399 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1400 {
1401         int i;
1402
1403         for (i = 0; clocks[i].flag; i++)
1404                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1405                            (flags & clocks[i].flag) ? "On" : "Off");
1406 }
1407
1408 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1409 {
1410         struct drm_info_node *node = (struct drm_info_node *) m->private;
1411         struct drm_device *dev = node->minor->dev;
1412         struct amdgpu_device *adev = dev->dev_private;
1413         struct drm_device *ddev = adev->ddev;
1414         u32 flags = 0;
1415
1416         amdgpu_get_clockgating_state(adev, &flags);
1417         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1418         amdgpu_parse_cg_state(m, flags);
1419         seq_printf(m, "\n");
1420
1421         if (!adev->pm.dpm_enabled) {
1422                 seq_printf(m, "dpm not enabled\n");
1423                 return 0;
1424         }
1425         if  ((adev->flags & AMD_IS_PX) &&
1426              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1427                 seq_printf(m, "PX asic powered off\n");
1428         } else if (adev->pp_enabled) {
1429                 return amdgpu_debugfs_pm_info_pp(m, adev);
1430         } else {
1431                 mutex_lock(&adev->pm.mutex);
1432                 if (adev->pm.funcs->debugfs_print_current_performance_level)
1433                         adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
1434                 else
1435                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1436                 mutex_unlock(&adev->pm.mutex);
1437         }
1438
1439         return 0;
1440 }
1441
1442 static const struct drm_info_list amdgpu_pm_info_list[] = {
1443         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1444 };
1445 #endif
1446
1447 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1448 {
1449 #if defined(CONFIG_DEBUG_FS)
1450         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1451 #else
1452         return 0;
1453 #endif
1454 }