drivers/gpu/drm/sun4i/sun4i_backend.c

   1 /*
   2  * Copyright (C) 2015 Free Electrons
   3  * Copyright (C) 2015 NextThing Co
   4  *
   5  * Maxime Ripard <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <drm/drm_fb_cma_helper.h>
  19 #include <drm/drm_gem_cma_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/component.h>
  23 #include <linux/list.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_graph.h>
  26 #include <linux/reset.h>
  27
  28 #include "sun4i_backend.h"
  29 #include "sun4i_drv.h"
  30 #include "sun4i_frontend.h"
  31 #include "sun4i_layer.h"
  32 #include "sunxi_engine.h"
  33
  34 struct sun4i_backend_quirks {
  35         /* backend <-> TCON muxing selection done in backend */
  36         bool needs_output_muxing;
  37 };
  38
  39 static const u32 sunxi_rgb2yuv_coef[12] = {
  40         0x00000107, 0x00000204, 0x00000064, 0x00000108,
  41         0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
  42         0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
  43 };
  44
  45 /*
  46  * These coefficients are taken from the A33 BSP from Allwinner.
  47  *
  48  * The formula is for each component, each coefficient being multiplied by
  49  * 1024 and each constant being multiplied by 16:
  50  * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
  51  * R = 1.164 * Y + 1.596 * V - 222
  52  * B = 1.164 * Y + 2.018 * U + 276
  53  *
  54  * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
  55  * following the BT601 spec.
  56  */
  57 static const u32 sunxi_bt601_yuv2rgb_coef[12] = {
  58         0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
  59         0x000004a7, 0x00000000, 0x00000662, 0x00003211,
  60         0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
  61 };
  62
  63 static inline bool sun4i_backend_format_is_planar_yuv(uint32_t format)
  64 {
  65         switch (format) {
  66         case DRM_FORMAT_YUV411:
  67         case DRM_FORMAT_YUV422:
  68         case DRM_FORMAT_YUV444:
  69                 return true;
  70         default:
  71                 return false;
  72         }
  73 }
  74
  75 static inline bool sun4i_backend_format_is_packed_yuv422(uint32_t format)
  76 {
  77         switch (format) {
  78         case DRM_FORMAT_YUYV:
  79         case DRM_FORMAT_YVYU:
  80         case DRM_FORMAT_UYVY:
  81         case DRM_FORMAT_VYUY:
  82                 return true;
  83
  84         default:
  85                 return false;
  86         }
  87 }
  88
  89 static inline bool sun4i_backend_format_is_yuv(uint32_t format)
  90 {
  91         return sun4i_backend_format_is_planar_yuv(format) ||
  92                 sun4i_backend_format_is_packed_yuv422(format);
  93 }
  94
  95 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
  96 {
  97         int i;
  98
  99         DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
 100
 101         /* Set color correction */
 102         regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
 103                      SUN4I_BACKEND_OCCTL_ENABLE);
 104
 105         for (i = 0; i < 12; i++)
 106                 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
 107                              sunxi_rgb2yuv_coef[i]);
 108 }
 109
 110 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
 111 {
 112         DRM_DEBUG_DRIVER("Disabling color correction\n");
 113
 114         /* Disable color correction */
 115         regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
 116                            SUN4I_BACKEND_OCCTL_ENABLE, 0);
 117 }
 118
 119 static void sun4i_backend_commit(struct sunxi_engine *engine)
 120 {
 121         DRM_DEBUG_DRIVER("Committing changes\n");
 122
 123         regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 124                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
 125                      SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
 126 }
 127
 128 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
 129                                 int layer, bool enable)
 130 {
 131         u32 val;
 132
 133         DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
 134                          layer);
 135
 136         if (enable)
 137                 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
 138         else
 139                 val = 0;
 140
 141         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 142                            SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
 143 }
 144
 145 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode)
 146 {
 147         switch (format) {
 148         case DRM_FORMAT_ARGB8888:
 149                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
 150                 break;
 151
 152         case DRM_FORMAT_ARGB4444:
 153                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
 154                 break;
 155
 156         case DRM_FORMAT_ARGB1555:
 157                 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
 158                 break;
 159
 160         case DRM_FORMAT_RGBA5551:
 161                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
 162                 break;
 163
 164         case DRM_FORMAT_RGBA4444:
 165                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
 166                 break;
 167
 168         case DRM_FORMAT_XRGB8888:
 169                 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
 170                 break;
 171
 172         case DRM_FORMAT_RGB888:
 173                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
 174                 break;
 175
 176         case DRM_FORMAT_RGB565:
 177                 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
 178                 break;
 179
 180         default:
 181                 return -EINVAL;
 182         }
 183
 184         return 0;
 185 }
 186
 187 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
 188                                      int layer, struct drm_plane *plane)
 189 {
 190         struct drm_plane_state *state = plane->state;
 191
 192         DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
 193
 194         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 195                 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
 196                                  state->crtc_w, state->crtc_h);
 197                 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG,
 198                              SUN4I_BACKEND_DISSIZE(state->crtc_w,
 199                                                    state->crtc_h));
 200         }
 201
 202         /* Set height and width */
 203         DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
 204                          state->crtc_w, state->crtc_h);
 205         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
 206                      SUN4I_BACKEND_LAYSIZE(state->crtc_w,
 207                                            state->crtc_h));
 208
 209         /* Set base coordinates */
 210         DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
 211                          state->crtc_x, state->crtc_y);
 212         regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
 213                      SUN4I_BACKEND_LAYCOOR(state->crtc_x,
 214                                            state->crtc_y));
 215
 216         return 0;
 217 }
 218
 219 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
 220                                            int layer, struct drm_plane *plane)
 221 {
 222         struct drm_plane_state *state = plane->state;
 223         struct drm_framebuffer *fb = state->fb;
 224         uint32_t format = fb->format->format;
 225         u32 val = SUN4I_BACKEND_IYUVCTL_EN;
 226         int i;
 227
 228         for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
 229                 regmap_write(backend->engine.regs,
 230                              SUN4I_BACKEND_YGCOEF_REG(i),
 231                              sunxi_bt601_yuv2rgb_coef[i]);
 232
 233         /*
 234          * We should do that only for a single plane, but the
 235          * framebuffer's atomic_check has our back on this.
 236          */
 237         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 238                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
 239                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
 240
 241         /* TODO: Add support for the multi-planar YUV formats */
 242         if (sun4i_backend_format_is_packed_yuv422(format))
 243                 val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
 244         else
 245                 DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", format);
 246
 247         /*
 248          * Allwinner seems to list the pixel sequence from right to left, while
 249          * DRM lists it from left to right.
 250          */
 251         switch (format) {
 252         case DRM_FORMAT_YUYV:
 253                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
 254                 break;
 255         case DRM_FORMAT_YVYU:
 256                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
 257                 break;
 258         case DRM_FORMAT_UYVY:
 259                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
 260                 break;
 261         case DRM_FORMAT_VYUY:
 262                 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
 263                 break;
 264         default:
 265                 DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
 266                                  format);
 267         }
 268
 269         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
 270
 271         return 0;
 272 }
 273
 274 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
 275                                        int layer, struct drm_plane *plane)
 276 {
 277         struct drm_plane_state *state = plane->state;
 278         struct drm_framebuffer *fb = state->fb;
 279         bool interlaced = false;
 280         u32 val;
 281         int ret;
 282
 283         /* Clear the YUV mode */
 284         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 285                            SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
 286
 287         if (plane->state->crtc)
 288                 interlaced = plane->state->crtc->state->adjusted_mode.flags
 289                         & DRM_MODE_FLAG_INTERLACE;
 290
 291         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 292                            SUN4I_BACKEND_MODCTL_ITLMOD_EN,
 293                            interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
 294
 295         DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
 296                          interlaced ? "on" : "off");
 297
 298         if (sun4i_backend_format_is_yuv(fb->format->format))
 299                 return sun4i_backend_update_yuv_format(backend, layer, plane);
 300
 301         ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
 302         if (ret) {
 303                 DRM_DEBUG_DRIVER("Invalid format\n");
 304                 return ret;
 305         }
 306
 307         regmap_update_bits(backend->engine.regs,
 308                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 309                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 310
 311         return 0;
 312 }
 313
 314 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
 315                                         int layer, uint32_t fmt)
 316 {
 317         u32 val;
 318         int ret;
 319
 320         ret = sun4i_backend_drm_format_to_layer(fmt, &val);
 321         if (ret) {
 322                 DRM_DEBUG_DRIVER("Invalid format\n");
 323                 return ret;
 324         }
 325
 326         regmap_update_bits(backend->engine.regs,
 327                            SUN4I_BACKEND_ATTCTL_REG0(layer),
 328                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
 329                            SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
 330
 331         regmap_update_bits(backend->engine.regs,
 332                            SUN4I_BACKEND_ATTCTL_REG1(layer),
 333                            SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
 334
 335         return 0;
 336 }
 337
 338 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
 339                                            struct drm_framebuffer *fb,
 340                                            dma_addr_t paddr)
 341 {
 342         /* TODO: Add support for the multi-planar YUV formats */
 343         DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
 344         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
 345
 346         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 347         regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
 348                      fb->pitches[0] * 8);
 349
 350         return 0;
 351 }
 352
 353 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
 354                                       int layer, struct drm_plane *plane)
 355 {
 356         struct drm_plane_state *state = plane->state;
 357         struct drm_framebuffer *fb = state->fb;
 358         u32 lo_paddr, hi_paddr;
 359         dma_addr_t paddr;
 360
 361         /* Set the line width */
 362         DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
 363         regmap_write(backend->engine.regs,
 364                      SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
 365                      fb->pitches[0] * 8);
 366
 367         /* Get the start of the displayed memory */
 368         paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
 369         DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
 370
 371         /*
 372          * backend DMA accesses DRAM directly, bypassing the system
 373          * bus. As such, the address range is different and the buffer
 374          * address needs to be corrected.
 375          */
 376         paddr -= PHYS_OFFSET;
 377
 378         if (sun4i_backend_format_is_yuv(fb->format->format))
 379                 return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
 380
 381         /* Write the 32 lower bits of the address (in bits) */
 382         lo_paddr = paddr << 3;
 383         DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
 384         regmap_write(backend->engine.regs,
 385                      SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
 386                      lo_paddr);
 387
 388         /* And the upper bits */
 389         hi_paddr = paddr >> 29;
 390         DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
 391         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
 392                            SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
 393                            SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
 394
 395         return 0;
 396 }
 397
 398 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
 399                                     struct drm_plane *plane)
 400 {
 401         struct drm_plane_state *state = plane->state;
 402         struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state);
 403         unsigned int priority = state->normalized_zpos;
 404         unsigned int pipe = p_state->pipe;
 405
 406         DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n",
 407                          layer, priority, pipe);
 408         regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
 409                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK |
 410                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK,
 411                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) |
 412                            SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority));
 413
 414         return 0;
 415 }
 416
 417 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state)
 418 {
 419         u16 src_h = state->src_h >> 16;
 420         u16 src_w = state->src_w >> 16;
 421
 422         DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n",
 423                          src_w, src_h, state->crtc_w, state->crtc_h);
 424
 425         if ((state->crtc_h != src_h) || (state->crtc_w != src_w))
 426                 return true;
 427
 428         return false;
 429 }
 430
 431 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state)
 432 {
 433         struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane);
 434         struct sun4i_backend *backend = layer->backend;
 435
 436         if (IS_ERR(backend->frontend))
 437                 return false;
 438
 439         return sun4i_backend_plane_uses_scaler(state);
 440 }
 441
 442 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
 443                                        struct drm_crtc_state *old_state)
 444 {
 445         u32 val;
 446
 447         WARN_ON(regmap_read_poll_timeout(engine->regs,
 448                                          SUN4I_BACKEND_REGBUFFCTL_REG,
 449                                          val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL),
 450                                          100, 50000));
 451 }
 452
 453 static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
 454                                       struct drm_crtc_state *crtc_state)
 455 {
 456         struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
 457         struct drm_atomic_state *state = crtc_state->state;
 458         struct drm_device *drm = state->dev;
 459         struct drm_plane *plane;
 460         unsigned int num_planes = 0;
 461         unsigned int num_alpha_planes = 0;
 462         unsigned int num_frontend_planes = 0;
 463         unsigned int num_yuv_planes = 0;
 464         unsigned int current_pipe = 0;
 465         unsigned int i;
 466
 467         DRM_DEBUG_DRIVER("Starting checking our planes\n");
 468
 469         if (!crtc_state->planes_changed)
 470                 return 0;
 471
 472         drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {
 473                 struct drm_plane_state *plane_state =
 474                         drm_atomic_get_plane_state(state, plane);
 475                 struct sun4i_layer_state *layer_state =
 476                         state_to_sun4i_layer_state(plane_state);
 477                 struct drm_framebuffer *fb = plane_state->fb;
 478                 struct drm_format_name_buf format_name;
 479
 480                 if (sun4i_backend_plane_uses_frontend(plane_state)) {
 481                         DRM_DEBUG_DRIVER("Using the frontend for plane %d\n",
 482                                          plane->index);
 483
 484                         layer_state->uses_frontend = true;
 485                         num_frontend_planes++;
 486                 } else {
 487                         layer_state->uses_frontend = false;
 488                 }
 489
 490                 DRM_DEBUG_DRIVER("Plane FB format is %s\n",
 491                                  drm_get_format_name(fb->format->format,
 492                                                      &format_name));
 493                 if (fb->format->has_alpha)
 494                         num_alpha_planes++;
 495
 496                 if (sun4i_backend_format_is_yuv(fb->format->format)) {
 497                         DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
 498                         num_yuv_planes++;
 499                 }
 500
 501                 DRM_DEBUG_DRIVER("Plane zpos is %d\n",
 502                                  plane_state->normalized_zpos);
 503
 504                 /* Sort our planes by Zpos */
 505                 plane_states[plane_state->normalized_zpos] = plane_state;
 506
 507                 num_planes++;
 508         }
 509
 510         /* All our planes were disabled, bail out */
 511         if (!num_planes)
 512                 return 0;
 513
 514         /*
 515          * The hardware is a bit unusual here.
 516          *
 517          * Even though it supports 4 layers, it does the composition
 518          * in two separate steps.
 519          *
 520          * The first one is assigning a layer to one of its two
 521          * pipes. If more that 1 layer is assigned to the same pipe,
 522          * and if pixels overlaps, the pipe will take the pixel from
 523          * the layer with the highest priority.
 524          *
 525          * The second step is the actual alpha blending, that takes
 526          * the two pipes as input, and uses the eventual alpha
 527          * component to do the transparency between the two.
 528          *
 529          * This two steps scenario makes us unable to guarantee a
 530          * robust alpha blending between the 4 layers in all
 531          * situations, since this means that we need to have one layer
 532          * with alpha at the lowest position of our two pipes.
 533          *
 534          * However, we cannot even do that, since the hardware has a
 535          * bug where the lowest plane of the lowest pipe (pipe 0,
 536          * priority 0), if it has any alpha, will discard the pixel
 537          * entirely and just display the pixels in the background
 538          * color (black by default).
 539          *
 540          * This means that we effectively have only three valid
 541          * configurations with alpha, all of them with the alpha being
 542          * on pipe1 with the lowest position, which can be 1, 2 or 3
 543          * depending on the number of planes and their zpos.
 544          */
 545         if (num_alpha_planes > SUN4I_BACKEND_NUM_ALPHA_LAYERS) {
 546                 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n");
 547                 return -EINVAL;
 548         }
 549
 550         /* We can't have an alpha plane at the lowest position */
 551         if (plane_states[0]->fb->format->has_alpha)
 552                 return -EINVAL;
 553
 554         for (i = 1; i < num_planes; i++) {
 555                 struct drm_plane_state *p_state = plane_states[i];
 556                 struct drm_framebuffer *fb = p_state->fb;
 557                 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state);
 558
 559                 /*
 560                  * The only alpha position is the lowest plane of the
 561                  * second pipe.
 562                  */
 563                 if (fb->format->has_alpha)
 564                         current_pipe++;
 565
 566                 s_state->pipe = current_pipe;
 567         }
 568
 569         /* We can only have a single YUV plane at a time */
 570         if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
 571                 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
 572                 return -EINVAL;
 573         }
 574
 575         if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
 576                 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
 577                 return -EINVAL;
 578         }
 579
 580         DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
 581                          num_planes, num_alpha_planes, num_frontend_planes,
 582                          num_yuv_planes);
 583
 584         return 0;
 585 }
 586
 587 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
 588 {
 589         struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
 590         struct sun4i_frontend *frontend = backend->frontend;
 591
 592         if (!frontend)
 593                 return;
 594
 595         /*
 596          * In a teardown scenario with the frontend involved, we have
 597          * to keep the frontend enabled until the next vblank, and
 598          * only then disable it.
 599          *
 600          * This is due to the fact that the backend will not take into
 601          * account the new configuration (with the plane that used to
 602          * be fed by the frontend now disabled) until we write to the
 603          * commit bit and the hardware fetches the new configuration
 604          * during the next vblank.
 605          *
 606          * So we keep the frontend around in order to prevent any
 607          * visual artifacts.
 608          */
 609         spin_lock(&backend->frontend_lock);
 610         if (backend->frontend_teardown) {
 611                 sun4i_frontend_exit(frontend);
 612                 backend->frontend_teardown = false;
 613         }
 614         spin_unlock(&backend->frontend_lock);
 615 };
 616
 617 static int sun4i_backend_init_sat(struct device *dev) {
 618         struct sun4i_backend *backend = dev_get_drvdata(dev);
 619         int ret;
 620
 621         backend->sat_reset = devm_reset_control_get(dev, "sat");
 622         if (IS_ERR(backend->sat_reset)) {
 623                 dev_err(dev, "Couldn't get the SAT reset line\n");
 624                 return PTR_ERR(backend->sat_reset);
 625         }
 626
 627         ret = reset_control_deassert(backend->sat_reset);
 628         if (ret) {
 629                 dev_err(dev, "Couldn't deassert the SAT reset line\n");
 630                 return ret;
 631         }
 632
 633         backend->sat_clk = devm_clk_get(dev, "sat");
 634         if (IS_ERR(backend->sat_clk)) {
 635                 dev_err(dev, "Couldn't get our SAT clock\n");
 636                 ret = PTR_ERR(backend->sat_clk);
 637                 goto err_assert_reset;
 638         }
 639
 640         ret = clk_prepare_enable(backend->sat_clk);
 641         if (ret) {
 642                 dev_err(dev, "Couldn't enable the SAT clock\n");
 643                 return ret;
 644         }
 645
 646         return 0;
 647
 648 err_assert_reset:
 649         reset_control_assert(backend->sat_reset);
 650         return ret;
 651 }
 652
 653 static int sun4i_backend_free_sat(struct device *dev) {
 654         struct sun4i_backend *backend = dev_get_drvdata(dev);
 655
 656         clk_disable_unprepare(backend->sat_clk);
 657         reset_control_assert(backend->sat_reset);
 658
 659         return 0;
 660 }
 661
 662 /*
 663  * The display backend can take video output from the display frontend, or
 664  * the display enhancement unit on the A80, as input for one it its layers.
 665  * This relationship within the display pipeline is encoded in the device
 666  * tree with of_graph, and we use it here to figure out which backend, if
 667  * there are 2 or more, we are currently probing. The number would be in
 668  * the "reg" property of the upstream output port endpoint.
 669  */
 670 static int sun4i_backend_of_get_id(struct device_node *node)
 671 {
 672         struct device_node *port, *ep;
 673         int ret = -EINVAL;
 674
 675         /* input is port 0 */
 676         port = of_graph_get_port_by_id(node, 0);
 677         if (!port)
 678                 return -EINVAL;
 679
 680         /* try finding an upstream endpoint */
 681         for_each_available_child_of_node(port, ep) {
 682                 struct device_node *remote;
 683                 u32 reg;
 684
 685                 remote = of_graph_get_remote_endpoint(ep);
 686                 if (!remote)
 687                         continue;
 688
 689                 ret = of_property_read_u32(remote, "reg", &reg);
 690                 if (ret)
 691                         continue;
 692
 693                 ret = reg;
 694         }
 695
 696         of_node_put(port);
 697
 698         return ret;
 699 }
 700
 701 /* TODO: This needs to take multiple pipelines into account */
 702 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv,
 703                                                           struct device_node *node)
 704 {
 705         struct device_node *port, *ep, *remote;
 706         struct sun4i_frontend *frontend;
 707
 708         port = of_graph_get_port_by_id(node, 0);
 709         if (!port)
 710                 return ERR_PTR(-EINVAL);
 711
 712         for_each_available_child_of_node(port, ep) {
 713                 remote = of_graph_get_remote_port_parent(ep);
 714                 if (!remote)
 715                         continue;
 716
 717                 /* does this node match any registered engines? */
 718                 list_for_each_entry(frontend, &drv->frontend_list, list) {
 719                         if (remote == frontend->node) {
 720                                 of_node_put(remote);
 721                                 of_node_put(port);
 722                                 return frontend;
 723                         }
 724                 }
 725         }
 726
 727         return ERR_PTR(-EINVAL);
 728 }
 729
 730 static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
 731         .atomic_begin                   = sun4i_backend_atomic_begin,
 732         .atomic_check                   = sun4i_backend_atomic_check,
 733         .commit                         = sun4i_backend_commit,
 734         .layers_init                    = sun4i_layers_init,
 735         .apply_color_correction         = sun4i_backend_apply_color_correction,
 736         .disable_color_correction       = sun4i_backend_disable_color_correction,
 737         .vblank_quirk                   = sun4i_backend_vblank_quirk,
 738 };
 739
 740 static struct regmap_config sun4i_backend_regmap_config = {
 741         .reg_bits       = 32,
 742         .val_bits       = 32,
 743         .reg_stride     = 4,
 744         .max_register   = 0x5800,
 745 };
 746
 747 static int sun4i_backend_bind(struct device *dev, struct device *master,
 748                               void *data)
 749 {
 750         struct platform_device *pdev = to_platform_device(dev);
 751         struct drm_device *drm = data;
 752         struct sun4i_drv *drv = drm->dev_private;
 753         struct sun4i_backend *backend;
 754         const struct sun4i_backend_quirks *quirks;
 755         struct resource *res;
 756         void __iomem *regs;
 757         int i, ret;
 758
 759         backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
 760         if (!backend)
 761                 return -ENOMEM;
 762         dev_set_drvdata(dev, backend);
 763         spin_lock_init(&backend->frontend_lock);
 764
 765         backend->engine.node = dev->of_node;
 766         backend->engine.ops = &sun4i_backend_engine_ops;
 767         backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
 768         if (backend->engine.id < 0)
 769                 return backend->engine.id;
 770
 771         backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
 772         if (IS_ERR(backend->frontend))
 773                 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
 774
 775         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 776         regs = devm_ioremap_resource(dev, res);
 777         if (IS_ERR(regs))
 778                 return PTR_ERR(regs);
 779
 780         backend->reset = devm_reset_control_get(dev, NULL);
 781         if (IS_ERR(backend->reset)) {
 782                 dev_err(dev, "Couldn't get our reset line\n");
 783                 return PTR_ERR(backend->reset);
 784         }
 785
 786         ret = reset_control_deassert(backend->reset);
 787         if (ret) {
 788                 dev_err(dev, "Couldn't deassert our reset line\n");
 789                 return ret;
 790         }
 791
 792         backend->bus_clk = devm_clk_get(dev, "ahb");
 793         if (IS_ERR(backend->bus_clk)) {
 794                 dev_err(dev, "Couldn't get the backend bus clock\n");
 795                 ret = PTR_ERR(backend->bus_clk);
 796                 goto err_assert_reset;
 797         }
 798         clk_prepare_enable(backend->bus_clk);
 799
 800         backend->mod_clk = devm_clk_get(dev, "mod");
 801         if (IS_ERR(backend->mod_clk)) {
 802                 dev_err(dev, "Couldn't get the backend module clock\n");
 803                 ret = PTR_ERR(backend->mod_clk);
 804                 goto err_disable_bus_clk;
 805         }
 806         clk_prepare_enable(backend->mod_clk);
 807
 808         backend->ram_clk = devm_clk_get(dev, "ram");
 809         if (IS_ERR(backend->ram_clk)) {
 810                 dev_err(dev, "Couldn't get the backend RAM clock\n");
 811                 ret = PTR_ERR(backend->ram_clk);
 812                 goto err_disable_mod_clk;
 813         }
 814         clk_prepare_enable(backend->ram_clk);
 815
 816         if (of_device_is_compatible(dev->of_node,
 817                                     "allwinner,sun8i-a33-display-backend")) {
 818                 ret = sun4i_backend_init_sat(dev);
 819                 if (ret) {
 820                         dev_err(dev, "Couldn't init SAT resources\n");
 821                         goto err_disable_ram_clk;
 822                 }
 823         }
 824
 825         backend->engine.regs = devm_regmap_init_mmio(dev, regs,
 826                                                      &sun4i_backend_regmap_config);
 827         if (IS_ERR(backend->engine.regs)) {
 828                 dev_err(dev, "Couldn't create the backend regmap\n");
 829                 return PTR_ERR(backend->engine.regs);
 830         }
 831
 832         list_add_tail(&backend->engine.list, &drv->engine_list);
 833
 834         /*
 835          * Many of the backend's layer configuration registers have
 836          * undefined default values. This poses a risk as we use
 837          * regmap_update_bits in some places, and don't overwrite
 838          * the whole register.
 839          *
 840          * Clear the registers here to have something predictable.
 841          */
 842         for (i = 0x800; i < 0x1000; i += 4)
 843                 regmap_write(backend->engine.regs, i, 0);
 844
 845         /* Disable registers autoloading */
 846         regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
 847                      SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
 848
 849         /* Enable the backend */
 850         regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
 851                      SUN4I_BACKEND_MODCTL_DEBE_EN |
 852                      SUN4I_BACKEND_MODCTL_START_CTL);
 853
 854         /* Set output selection if needed */
 855         quirks = of_device_get_match_data(dev);
 856         if (quirks->needs_output_muxing) {
 857                 /*
 858                  * We assume there is no dynamic muxing of backends
 859                  * and TCONs, so we select the backend with same ID.
 860                  *
 861                  * While dynamic selection might be interesting, since
 862                  * the CRTC is tied to the TCON, while the layers are
 863                  * tied to the backends, this means, we will need to
 864                  * switch between groups of layers. There might not be
 865                  * a way to represent this constraint in DRM.
 866                  */
 867                 regmap_update_bits(backend->engine.regs,
 868                                    SUN4I_BACKEND_MODCTL_REG,
 869                                    SUN4I_BACKEND_MODCTL_OUT_SEL,
 870                                    (backend->engine.id
 871                                     ? SUN4I_BACKEND_MODCTL_OUT_LCD1
 872                                     : SUN4I_BACKEND_MODCTL_OUT_LCD0));
 873         }
 874
 875         return 0;
 876
 877 err_disable_ram_clk:
 878         clk_disable_unprepare(backend->ram_clk);
 879 err_disable_mod_clk:
 880         clk_disable_unprepare(backend->mod_clk);
 881 err_disable_bus_clk:
 882         clk_disable_unprepare(backend->bus_clk);
 883 err_assert_reset:
 884         reset_control_assert(backend->reset);
 885         return ret;
 886 }
 887
 888 static void sun4i_backend_unbind(struct device *dev, struct device *master,
 889                                  void *data)
 890 {
 891         struct sun4i_backend *backend = dev_get_drvdata(dev);
 892
 893         list_del(&backend->engine.list);
 894
 895         if (of_device_is_compatible(dev->of_node,
 896                                     "allwinner,sun8i-a33-display-backend"))
 897                 sun4i_backend_free_sat(dev);
 898
 899         clk_disable_unprepare(backend->ram_clk);
 900         clk_disable_unprepare(backend->mod_clk);
 901         clk_disable_unprepare(backend->bus_clk);
 902         reset_control_assert(backend->reset);
 903 }
 904
 905 static const struct component_ops sun4i_backend_ops = {
 906         .bind   = sun4i_backend_bind,
 907         .unbind = sun4i_backend_unbind,
 908 };
 909
 910 static int sun4i_backend_probe(struct platform_device *pdev)
 911 {
 912         return component_add(&pdev->dev, &sun4i_backend_ops);
 913 }
 914
 915 static int sun4i_backend_remove(struct platform_device *pdev)
 916 {
 917         component_del(&pdev->dev, &sun4i_backend_ops);
 918
 919         return 0;
 920 }
 921
 922 static const struct sun4i_backend_quirks sun4i_backend_quirks = {
 923         .needs_output_muxing = true,
 924 };
 925
 926 static const struct sun4i_backend_quirks sun5i_backend_quirks = {
 927 };
 928
 929 static const struct sun4i_backend_quirks sun6i_backend_quirks = {
 930 };
 931
 932 static const struct sun4i_backend_quirks sun7i_backend_quirks = {
 933         .needs_output_muxing = true,
 934 };
 935
 936 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
 937 };
 938
 939 static const struct sun4i_backend_quirks sun9i_backend_quirks = {
 940 };
 941
 942 static const struct of_device_id sun4i_backend_of_table[] = {
 943         {
 944                 .compatible = "allwinner,sun4i-a10-display-backend",
 945                 .data = &sun4i_backend_quirks,
 946         },
 947         {
 948                 .compatible = "allwinner,sun5i-a13-display-backend",
 949                 .data = &sun5i_backend_quirks,
 950         },
 951         {
 952                 .compatible = "allwinner,sun6i-a31-display-backend",
 953                 .data = &sun6i_backend_quirks,
 954         },
 955         {
 956                 .compatible = "allwinner,sun7i-a20-display-backend",
 957                 .data = &sun7i_backend_quirks,
 958         },
 959         {
 960                 .compatible = "allwinner,sun8i-a33-display-backend",
 961                 .data = &sun8i_a33_backend_quirks,
 962         },
 963         {
 964                 .compatible = "allwinner,sun9i-a80-display-backend",
 965                 .data = &sun9i_backend_quirks,
 966         },
 967         { }
 968 };
 969 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
 970
 971 static struct platform_driver sun4i_backend_platform_driver = {
 972         .probe          = sun4i_backend_probe,
 973         .remove         = sun4i_backend_remove,
 974         .driver         = {
 975                 .name           = "sun4i-backend",
 976                 .of_match_table = sun4i_backend_of_table,
 977         },
 978 };
 979 module_platform_driver(sun4i_backend_platform_driver);
 980
 981 MODULE_AUTHOR("Maxime Ripard <[email protected]>");
 982 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
 983 MODULE_LICENSE("GPL");