drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39 #include "amdgpu_amdkfd.h"
  40
  41 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  42 {
  43         if (adev->flags & AMD_IS_APU)
  44                 return false;
  45
  46         if (amdgpu_gpu_recovery == 0 ||
  47             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  48                 return false;
  49
  50         return true;
  51 }
  52
  53 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  54 {
  55         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  56         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  57
  58         if (bo->kfd_bo)
  59                 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
  60
  61         amdgpu_bo_kunmap(bo);
  62
  63         if (bo->gem_base.import_attach)
  64                 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
  65         drm_gem_object_release(&bo->gem_base);
  66         amdgpu_bo_unref(&bo->parent);
  67         if (!list_empty(&bo->shadow_list)) {
  68                 mutex_lock(&adev->shadow_list_lock);
  69                 list_del_init(&bo->shadow_list);
  70                 mutex_unlock(&adev->shadow_list_lock);
  71         }
  72         kfree(bo->metadata);
  73         kfree(bo);
  74 }
  75
  76 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  77 {
  78         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  79                 return true;
  80         return false;
  81 }
  82
  83 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  84 {
  85         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  86         struct ttm_placement *placement = &abo->placement;
  87         struct ttm_place *places = abo->placements;
  88         u64 flags = abo->flags;
  89         u32 c = 0;
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  92                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  93
  94                 places[c].fpfn = 0;
  95                 places[c].lpfn = 0;
  96                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  97                         TTM_PL_FLAG_VRAM;
  98
  99                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
 100                         places[c].lpfn = visible_pfn;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
 103
 104                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
 105                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 106                 c++;
 107         }
 108
 109         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 110                 places[c].fpfn = 0;
 111                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 112                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 113                 else
 114                         places[c].lpfn = 0;
 115                 places[c].flags = TTM_PL_FLAG_TT;
 116                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 117                         places[c].flags |= TTM_PL_FLAG_WC |
 118                                 TTM_PL_FLAG_UNCACHED;
 119                 else
 120                         places[c].flags |= TTM_PL_FLAG_CACHED;
 121                 c++;
 122         }
 123
 124         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 125                 places[c].fpfn = 0;
 126                 places[c].lpfn = 0;
 127                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 128                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 129                         places[c].flags |= TTM_PL_FLAG_WC |
 130                                 TTM_PL_FLAG_UNCACHED;
 131                 else
 132                         places[c].flags |= TTM_PL_FLAG_CACHED;
 133                 c++;
 134         }
 135
 136         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 137                 places[c].fpfn = 0;
 138                 places[c].lpfn = 0;
 139                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 140                 c++;
 141         }
 142
 143         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 144                 places[c].fpfn = 0;
 145                 places[c].lpfn = 0;
 146                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 147                 c++;
 148         }
 149
 150         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 151                 places[c].fpfn = 0;
 152                 places[c].lpfn = 0;
 153                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 154                 c++;
 155         }
 156
 157         if (!c) {
 158                 places[c].fpfn = 0;
 159                 places[c].lpfn = 0;
 160                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 161                 c++;
 162         }
 163
 164         placement->num_placement = c;
 165         placement->placement = places;
 166
 167         placement->num_busy_placement = c;
 168         placement->busy_placement = places;
 169 }
 170
 171 /**
 172  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 173  *
 174  * @adev: amdgpu device object
 175  * @size: size for the new BO
 176  * @align: alignment for the new BO
 177  * @domain: where to place it
 178  * @bo_ptr: used to initialize BOs in structures
 179  * @gpu_addr: GPU addr of the pinned BO
 180  * @cpu_addr: optional CPU address mapping
 181  *
 182  * Allocates and pins a BO for kernel internal use, and returns it still
 183  * reserved.
 184  *
 185  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 186  *
 187  * Returns 0 on success, negative error code otherwise.
 188  */
 189 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 190                               unsigned long size, int align,
 191                               u32 domain, struct amdgpu_bo **bo_ptr,
 192                               u64 *gpu_addr, void **cpu_addr)
 193 {
 194         bool free = false;
 195         int r;
 196
 197         if (!*bo_ptr) {
 198                 r = amdgpu_bo_create(adev, size, align, domain,
 199                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 200                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 201                                      ttm_bo_type_kernel, NULL, bo_ptr);
 202                 if (r) {
 203                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 204                                 r);
 205                         return r;
 206                 }
 207                 free = true;
 208         }
 209
 210         r = amdgpu_bo_reserve(*bo_ptr, false);
 211         if (r) {
 212                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 213                 goto error_free;
 214         }
 215
 216         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 217         if (r) {
 218                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 219                 goto error_unreserve;
 220         }
 221
 222         if (cpu_addr) {
 223                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 224                 if (r) {
 225                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 226                         goto error_unreserve;
 227                 }
 228         }
 229
 230         return 0;
 231
 232 error_unreserve:
 233         amdgpu_bo_unreserve(*bo_ptr);
 234
 235 error_free:
 236         if (free)
 237                 amdgpu_bo_unref(bo_ptr);
 238
 239         return r;
 240 }
 241
 242 /**
 243  * amdgpu_bo_create_kernel - create BO for kernel use
 244  *
 245  * @adev: amdgpu device object
 246  * @size: size for the new BO
 247  * @align: alignment for the new BO
 248  * @domain: where to place it
 249  * @bo_ptr:  used to initialize BOs in structures
 250  * @gpu_addr: GPU addr of the pinned BO
 251  * @cpu_addr: optional CPU address mapping
 252  *
 253  * Allocates and pins a BO for kernel internal use.
 254  *
 255  * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
 256  *
 257  * Returns 0 on success, negative error code otherwise.
 258  */
 259 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 260                             unsigned long size, int align,
 261                             u32 domain, struct amdgpu_bo **bo_ptr,
 262                             u64 *gpu_addr, void **cpu_addr)
 263 {
 264         int r;
 265
 266         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 267                                       gpu_addr, cpu_addr);
 268
 269         if (r)
 270                 return r;
 271
 272         amdgpu_bo_unreserve(*bo_ptr);
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * amdgpu_bo_free_kernel - free BO for kernel use
 279  *
 280  * @bo: amdgpu BO to free
 281  *
 282  * unmaps and unpin a BO for kernel internal use.
 283  */
 284 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 285                            void **cpu_addr)
 286 {
 287         if (*bo == NULL)
 288                 return;
 289
 290         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 291                 if (cpu_addr)
 292                         amdgpu_bo_kunmap(*bo);
 293
 294                 amdgpu_bo_unpin(*bo);
 295                 amdgpu_bo_unreserve(*bo);
 296         }
 297         amdgpu_bo_unref(bo);
 298
 299         if (gpu_addr)
 300                 *gpu_addr = 0;
 301
 302         if (cpu_addr)
 303                 *cpu_addr = NULL;
 304 }
 305
 306 /* Validate bo size is bit bigger then the request domain */
 307 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 308                                           unsigned long size, u32 domain)
 309 {
 310         struct ttm_mem_type_manager *man = NULL;
 311
 312         /*
 313          * If GTT is part of requested domains the check must succeed to
 314          * allow fall back to GTT
 315          */
 316         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 317                 man = &adev->mman.bdev.man[TTM_PL_TT];
 318
 319                 if (size < (man->size << PAGE_SHIFT))
 320                         return true;
 321                 else
 322                         goto fail;
 323         }
 324
 325         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 326                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 327
 328                 if (size < (man->size << PAGE_SHIFT))
 329                         return true;
 330                 else
 331                         goto fail;
 332         }
 333
 334
 335         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 336         return true;
 337
 338 fail:
 339         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 340                   man->size << PAGE_SHIFT);
 341         return false;
 342 }
 343
 344 static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
 345                                int byte_align, u32 domain,
 346                                u64 flags, enum ttm_bo_type type,
 347                                struct reservation_object *resv,
 348                                struct amdgpu_bo **bo_ptr)
 349 {
 350         struct ttm_operation_ctx ctx = {
 351                 .interruptible = (type != ttm_bo_type_kernel),
 352                 .no_wait_gpu = false,
 353                 .resv = resv,
 354                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 355         };
 356         struct amdgpu_bo *bo;
 357         unsigned long page_align;
 358         size_t acc_size;
 359         u32 domains, preferred_domains, allowed_domains;
 360         int r;
 361
 362         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 363         size = ALIGN(size, PAGE_SIZE);
 364
 365         if (!amdgpu_bo_validate_size(adev, size, domain))
 366                 return -ENOMEM;
 367
 368         *bo_ptr = NULL;
 369
 370         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 371                                        sizeof(struct amdgpu_bo));
 372
 373         preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 374                                       AMDGPU_GEM_DOMAIN_GTT |
 375                                       AMDGPU_GEM_DOMAIN_CPU |
 376                                       AMDGPU_GEM_DOMAIN_GDS |
 377                                       AMDGPU_GEM_DOMAIN_GWS |
 378                                       AMDGPU_GEM_DOMAIN_OA);
 379         allowed_domains = preferred_domains;
 380         if (type != ttm_bo_type_kernel &&
 381             allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 382                 allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 383         domains = preferred_domains;
 384 retry:
 385         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 386         if (bo == NULL)
 387                 return -ENOMEM;
 388         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 389         INIT_LIST_HEAD(&bo->shadow_list);
 390         INIT_LIST_HEAD(&bo->va);
 391
 392         bo->flags = flags;
 393
 394 #ifdef CONFIG_X86_32
 395         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 396          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 397          */
 398         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 399 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 400         /* Don't try to enable write-combining when it can't work, or things
 401          * may be slow
 402          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 403          */
 404
 405 #ifndef CONFIG_COMPILE_TEST
 406 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 407          thanks to write-combining
 408 #endif
 409
 410         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 411                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 412                               "better performance thanks to write-combining\n");
 413         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 414 #else
 415         /* For architectures that don't support WC memory,
 416          * mask out the WC flag from the BO
 417          */
 418         if (!drm_arch_can_wc_memory())
 419                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 420 #endif
 421
 422         bo->tbo.bdev = &adev->mman.bdev;
 423         amdgpu_ttm_placement_from_domain(bo, domains);
 424         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 425                                  &bo->placement, page_align, &ctx, acc_size,
 426                                  NULL, resv, &amdgpu_ttm_bo_destroy);
 427         if (unlikely(r && r != -ERESTARTSYS) && type == ttm_bo_type_device) {
 428                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
 429                         flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 430                         goto retry;
 431                 } else if (domains != allowed_domains) {
 432                         domains = allowed_domains;
 433                         goto retry;
 434                 }
 435         }
 436         if (unlikely(r))
 437                 return r;
 438
 439         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 440             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 441             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 442                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 443                                              ctx.bytes_moved);
 444         else
 445                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 446
 447         if (type == ttm_bo_type_kernel)
 448                 bo->tbo.priority = 1;
 449
 450         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 451             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 452                 struct dma_fence *fence;
 453
 454                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 455                 if (unlikely(r))
 456                         goto fail_unreserve;
 457
 458                 amdgpu_bo_fence(bo, fence, false);
 459                 dma_fence_put(bo->tbo.moving);
 460                 bo->tbo.moving = dma_fence_get(fence);
 461                 dma_fence_put(fence);
 462         }
 463         if (!resv)
 464                 amdgpu_bo_unreserve(bo);
 465         *bo_ptr = bo;
 466
 467         trace_amdgpu_bo_create(bo);
 468
 469         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 470         if (type == ttm_bo_type_device)
 471                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 472
 473         return 0;
 474
 475 fail_unreserve:
 476         if (!resv)
 477                 ww_mutex_unlock(&bo->tbo.resv->lock);
 478         amdgpu_bo_unref(&bo);
 479         return r;
 480 }
 481
 482 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 483                                    unsigned long size, int byte_align,
 484                                    struct amdgpu_bo *bo)
 485 {
 486         int r;
 487
 488         if (bo->shadow)
 489                 return 0;
 490
 491         r = amdgpu_bo_do_create(adev, size, byte_align, AMDGPU_GEM_DOMAIN_GTT,
 492                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 493                                 AMDGPU_GEM_CREATE_SHADOW,
 494                                 ttm_bo_type_kernel,
 495                                 bo->tbo.resv, &bo->shadow);
 496         if (!r) {
 497                 bo->shadow->parent = amdgpu_bo_ref(bo);
 498                 mutex_lock(&adev->shadow_list_lock);
 499                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 500                 mutex_unlock(&adev->shadow_list_lock);
 501         }
 502
 503         return r;
 504 }
 505
 506 int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
 507                      int byte_align, u32 domain,
 508                      u64 flags, enum ttm_bo_type type,
 509                      struct reservation_object *resv,
 510                      struct amdgpu_bo **bo_ptr)
 511 {
 512         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 513         int r;
 514
 515         r = amdgpu_bo_do_create(adev, size, byte_align, domain,
 516                                 parent_flags, type, resv, bo_ptr);
 517         if (r)
 518                 return r;
 519
 520         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 521                 if (!resv)
 522                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 523                                                         NULL));
 524
 525                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 526
 527                 if (!resv)
 528                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 529
 530                 if (r)
 531                         amdgpu_bo_unref(bo_ptr);
 532         }
 533
 534         return r;
 535 }
 536
 537 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 538                                struct amdgpu_ring *ring,
 539                                struct amdgpu_bo *bo,
 540                                struct reservation_object *resv,
 541                                struct dma_fence **fence,
 542                                bool direct)
 543
 544 {
 545         struct amdgpu_bo *shadow = bo->shadow;
 546         uint64_t bo_addr, shadow_addr;
 547         int r;
 548
 549         if (!shadow)
 550                 return -EINVAL;
 551
 552         bo_addr = amdgpu_bo_gpu_offset(bo);
 553         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 554
 555         r = reservation_object_reserve_shared(bo->tbo.resv);
 556         if (r)
 557                 goto err;
 558
 559         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 560                                amdgpu_bo_size(bo), resv, fence,
 561                                direct, false);
 562         if (!r)
 563                 amdgpu_bo_fence(bo, *fence, true);
 564
 565 err:
 566         return r;
 567 }
 568
 569 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 570 {
 571         struct ttm_operation_ctx ctx = { false, false };
 572         uint32_t domain;
 573         int r;
 574
 575         if (bo->pin_count)
 576                 return 0;
 577
 578         domain = bo->preferred_domains;
 579
 580 retry:
 581         amdgpu_ttm_placement_from_domain(bo, domain);
 582         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 583         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 584                 domain = bo->allowed_domains;
 585                 goto retry;
 586         }
 587
 588         return r;
 589 }
 590
 591 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 592                                   struct amdgpu_ring *ring,
 593                                   struct amdgpu_bo *bo,
 594                                   struct reservation_object *resv,
 595                                   struct dma_fence **fence,
 596                                   bool direct)
 597
 598 {
 599         struct amdgpu_bo *shadow = bo->shadow;
 600         uint64_t bo_addr, shadow_addr;
 601         int r;
 602
 603         if (!shadow)
 604                 return -EINVAL;
 605
 606         bo_addr = amdgpu_bo_gpu_offset(bo);
 607         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 608
 609         r = reservation_object_reserve_shared(bo->tbo.resv);
 610         if (r)
 611                 goto err;
 612
 613         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 614                                amdgpu_bo_size(bo), resv, fence,
 615                                direct, false);
 616         if (!r)
 617                 amdgpu_bo_fence(bo, *fence, true);
 618
 619 err:
 620         return r;
 621 }
 622
 623 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 624 {
 625         void *kptr;
 626         long r;
 627
 628         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 629                 return -EPERM;
 630
 631         kptr = amdgpu_bo_kptr(bo);
 632         if (kptr) {
 633                 if (ptr)
 634                         *ptr = kptr;
 635                 return 0;
 636         }
 637
 638         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 639                                                 MAX_SCHEDULE_TIMEOUT);
 640         if (r < 0)
 641                 return r;
 642
 643         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 644         if (r)
 645                 return r;
 646
 647         if (ptr)
 648                 *ptr = amdgpu_bo_kptr(bo);
 649
 650         return 0;
 651 }
 652
 653 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 654 {
 655         bool is_iomem;
 656
 657         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 658 }
 659
 660 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 661 {
 662         if (bo->kmap.bo)
 663                 ttm_bo_kunmap(&bo->kmap);
 664 }
 665
 666 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 667 {
 668         if (bo == NULL)
 669                 return NULL;
 670
 671         ttm_bo_reference(&bo->tbo);
 672         return bo;
 673 }
 674
 675 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 676 {
 677         struct ttm_buffer_object *tbo;
 678
 679         if ((*bo) == NULL)
 680                 return;
 681
 682         tbo = &((*bo)->tbo);
 683         ttm_bo_unref(&tbo);
 684         if (tbo == NULL)
 685                 *bo = NULL;
 686 }
 687
 688 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 689                              u64 min_offset, u64 max_offset,
 690                              u64 *gpu_addr)
 691 {
 692         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 693         struct ttm_operation_ctx ctx = { false, false };
 694         int r, i;
 695
 696         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 697                 return -EPERM;
 698
 699         if (WARN_ON_ONCE(min_offset > max_offset))
 700                 return -EINVAL;
 701
 702         /* A shared bo cannot be migrated to VRAM */
 703         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 704                 return -EINVAL;
 705
 706         if (bo->pin_count) {
 707                 uint32_t mem_type = bo->tbo.mem.mem_type;
 708
 709                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 710                         return -EINVAL;
 711
 712                 bo->pin_count++;
 713                 if (gpu_addr)
 714                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 715
 716                 if (max_offset != 0) {
 717                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 718                         WARN_ON_ONCE(max_offset <
 719                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 720                 }
 721
 722                 return 0;
 723         }
 724
 725         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 726         /* force to pin into visible video ram */
 727         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 728                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 729         amdgpu_ttm_placement_from_domain(bo, domain);
 730         for (i = 0; i < bo->placement.num_placement; i++) {
 731                 unsigned fpfn, lpfn;
 732
 733                 fpfn = min_offset >> PAGE_SHIFT;
 734                 lpfn = max_offset >> PAGE_SHIFT;
 735
 736                 if (fpfn > bo->placements[i].fpfn)
 737                         bo->placements[i].fpfn = fpfn;
 738                 if (!bo->placements[i].lpfn ||
 739                     (lpfn && lpfn < bo->placements[i].lpfn))
 740                         bo->placements[i].lpfn = lpfn;
 741                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 742         }
 743
 744         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 745         if (unlikely(r)) {
 746                 dev_err(adev->dev, "%p pin failed\n", bo);
 747                 goto error;
 748         }
 749
 750         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 751         if (unlikely(r)) {
 752                 dev_err(adev->dev, "%p bind failed\n", bo);
 753                 goto error;
 754         }
 755
 756         bo->pin_count = 1;
 757         if (gpu_addr != NULL)
 758                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 759
 760         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 761         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 762                 adev->vram_pin_size += amdgpu_bo_size(bo);
 763                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 764                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 765         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 766                 adev->gart_pin_size += amdgpu_bo_size(bo);
 767         }
 768
 769 error:
 770         return r;
 771 }
 772
 773 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 774 {
 775         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 776 }
 777
 778 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 779 {
 780         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 781         struct ttm_operation_ctx ctx = { false, false };
 782         int r, i;
 783
 784         if (!bo->pin_count) {
 785                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 786                 return 0;
 787         }
 788         bo->pin_count--;
 789         if (bo->pin_count)
 790                 return 0;
 791         for (i = 0; i < bo->placement.num_placement; i++) {
 792                 bo->placements[i].lpfn = 0;
 793                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 794         }
 795         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 796         if (unlikely(r)) {
 797                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 798                 goto error;
 799         }
 800
 801         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 802                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 803                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 804                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 805         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 806                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 807         }
 808
 809 error:
 810         return r;
 811 }
 812
 813 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 814 {
 815         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 816         if (0 && (adev->flags & AMD_IS_APU)) {
 817                 /* Useless to evict on IGP chips */
 818                 return 0;
 819         }
 820         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 821 }
 822
 823 static const char *amdgpu_vram_names[] = {
 824         "UNKNOWN",
 825         "GDDR1",
 826         "DDR2",
 827         "GDDR3",
 828         "GDDR4",
 829         "GDDR5",
 830         "HBM",
 831         "DDR3",
 832         "DDR4",
 833 };
 834
 835 int amdgpu_bo_init(struct amdgpu_device *adev)
 836 {
 837         /* reserve PAT memory space to WC for VRAM */
 838         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 839                                    adev->gmc.aper_size);
 840
 841         /* Add an MTRR for the VRAM */
 842         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 843                                               adev->gmc.aper_size);
 844         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 845                  adev->gmc.mc_vram_size >> 20,
 846                  (unsigned long long)adev->gmc.aper_size >> 20);
 847         DRM_INFO("RAM width %dbits %s\n",
 848                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 849         return amdgpu_ttm_init(adev);
 850 }
 851
 852 int amdgpu_bo_late_init(struct amdgpu_device *adev)
 853 {
 854         amdgpu_ttm_late_init(adev);
 855
 856         return 0;
 857 }
 858
 859 void amdgpu_bo_fini(struct amdgpu_device *adev)
 860 {
 861         amdgpu_ttm_fini(adev);
 862         arch_phys_wc_del(adev->gmc.vram_mtrr);
 863         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 864 }
 865
 866 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 867                              struct vm_area_struct *vma)
 868 {
 869         return ttm_fbdev_mmap(vma, &bo->tbo);
 870 }
 871
 872 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 873 {
 874         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 875
 876         if (adev->family <= AMDGPU_FAMILY_CZ &&
 877             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 878                 return -EINVAL;
 879
 880         bo->tiling_flags = tiling_flags;
 881         return 0;
 882 }
 883
 884 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 885 {
 886         lockdep_assert_held(&bo->tbo.resv->lock.base);
 887
 888         if (tiling_flags)
 889                 *tiling_flags = bo->tiling_flags;
 890 }
 891
 892 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 893                             uint32_t metadata_size, uint64_t flags)
 894 {
 895         void *buffer;
 896
 897         if (!metadata_size) {
 898                 if (bo->metadata_size) {
 899                         kfree(bo->metadata);
 900                         bo->metadata = NULL;
 901                         bo->metadata_size = 0;
 902                 }
 903                 return 0;
 904         }
 905
 906         if (metadata == NULL)
 907                 return -EINVAL;
 908
 909         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 910         if (buffer == NULL)
 911                 return -ENOMEM;
 912
 913         kfree(bo->metadata);
 914         bo->metadata_flags = flags;
 915         bo->metadata = buffer;
 916         bo->metadata_size = metadata_size;
 917
 918         return 0;
 919 }
 920
 921 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 922                            size_t buffer_size, uint32_t *metadata_size,
 923                            uint64_t *flags)
 924 {
 925         if (!buffer && !metadata_size)
 926                 return -EINVAL;
 927
 928         if (buffer) {
 929                 if (buffer_size < bo->metadata_size)
 930                         return -EINVAL;
 931
 932                 if (bo->metadata_size)
 933                         memcpy(buffer, bo->metadata, bo->metadata_size);
 934         }
 935
 936         if (metadata_size)
 937                 *metadata_size = bo->metadata_size;
 938         if (flags)
 939                 *flags = bo->metadata_flags;
 940
 941         return 0;
 942 }
 943
 944 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 945                            bool evict,
 946                            struct ttm_mem_reg *new_mem)
 947 {
 948         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 949         struct amdgpu_bo *abo;
 950         struct ttm_mem_reg *old_mem = &bo->mem;
 951
 952         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 953                 return;
 954
 955         abo = ttm_to_amdgpu_bo(bo);
 956         amdgpu_vm_bo_invalidate(adev, abo, evict);
 957
 958         amdgpu_bo_kunmap(abo);
 959
 960         /* remember the eviction */
 961         if (evict)
 962                 atomic64_inc(&adev->num_evictions);
 963
 964         /* update statistics */
 965         if (!new_mem)
 966                 return;
 967
 968         /* move_notify is called before move happens */
 969         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 970 }
 971
 972 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 973 {
 974         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 975         struct ttm_operation_ctx ctx = { false, false };
 976         struct amdgpu_bo *abo;
 977         unsigned long offset, size;
 978         int r;
 979
 980         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 981                 return 0;
 982
 983         abo = ttm_to_amdgpu_bo(bo);
 984
 985         /* Remember that this BO was accessed by the CPU */
 986         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 987
 988         if (bo->mem.mem_type != TTM_PL_VRAM)
 989                 return 0;
 990
 991         size = bo->mem.num_pages << PAGE_SHIFT;
 992         offset = bo->mem.start << PAGE_SHIFT;
 993         if ((offset + size) <= adev->gmc.visible_vram_size)
 994                 return 0;
 995
 996         /* Can't move a pinned BO to visible VRAM */
 997         if (abo->pin_count > 0)
 998                 return -EINVAL;
 999
1000         /* hurrah the memory is not visible ! */
1001         atomic64_inc(&adev->num_vram_cpu_page_faults);
1002         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1003                                          AMDGPU_GEM_DOMAIN_GTT);
1004
1005         /* Avoid costly evictions; only set GTT as a busy placement */
1006         abo->placement.num_busy_placement = 1;
1007         abo->placement.busy_placement = &abo->placements[1];
1008
1009         r = ttm_bo_validate(bo, &abo->placement, &ctx);
1010         if (unlikely(r != 0))
1011                 return r;
1012
1013         offset = bo->mem.start << PAGE_SHIFT;
1014         /* this should never happen */
1015         if (bo->mem.mem_type == TTM_PL_VRAM &&
1016             (offset + size) > adev->gmc.visible_vram_size)
1017                 return -EINVAL;
1018
1019         return 0;
1020 }
1021
1022 /**
1023  * amdgpu_bo_fence - add fence to buffer object
1024  *
1025  * @bo: buffer object in question
1026  * @fence: fence to add
1027  * @shared: true if fence should be added shared
1028  *
1029  */
1030 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1031                      bool shared)
1032 {
1033         struct reservation_object *resv = bo->tbo.resv;
1034
1035         if (shared)
1036                 reservation_object_add_shared_fence(resv, fence);
1037         else
1038                 reservation_object_add_excl_fence(resv, fence);
1039 }
1040
1041 /**
1042  * amdgpu_bo_gpu_offset - return GPU offset of bo
1043  * @bo: amdgpu object for which we query the offset
1044  *
1045  * Returns current GPU offset of the object.
1046  *
1047  * Note: object should either be pinned or reserved when calling this
1048  * function, it might be useful to add check for this for debugging.
1049  */
1050 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1051 {
1052         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1053         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1054                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1055         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1056                      !bo->pin_count);
1057         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1058         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1059                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1060
1061         return bo->tbo.offset;
1062 }