drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "amdgpu_dm_hdcp.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_dm.h"
  29 #include "dm_helpers.h"
  30 #include <drm/drm_hdcp.h>
  31
  32 static bool
  33 lp_write_i2c(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
  34 {
  35
  36         struct dc_link *link = handle;
  37         struct i2c_payload i2c_payloads[] = {{true, address, size, (void *)data} };
  38         struct i2c_command cmd = {i2c_payloads, 1, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
  39
  40         return dm_helpers_submit_i2c(link->ctx, link, &cmd);
  41 }
  42
  43 static bool
  44 lp_read_i2c(void *handle, uint32_t address, uint8_t offset, uint8_t *data, uint32_t size)
  45 {
  46         struct dc_link *link = handle;
  47
  48         struct i2c_payload i2c_payloads[] = {{true, address, 1, &offset}, {false, address, size, data} };
  49         struct i2c_command cmd = {i2c_payloads, 2, I2C_COMMAND_ENGINE_HW, link->dc->caps.i2c_speed_in_khz};
  50
  51         return dm_helpers_submit_i2c(link->ctx, link, &cmd);
  52 }
  53
  54 static bool
  55 lp_write_dpcd(void *handle, uint32_t address, const uint8_t *data, uint32_t size)
  56 {
  57         struct dc_link *link = handle;
  58
  59         return dm_helpers_dp_write_dpcd(link->ctx, link, address, data, size);
  60 }
  61
  62 static bool
  63 lp_read_dpcd(void *handle, uint32_t address, uint8_t *data, uint32_t size)
  64 {
  65         struct dc_link *link = handle;
  66
  67         return dm_helpers_dp_read_dpcd(link->ctx, link, address, data, size);
  68 }
  69
  70 static void process_output(struct hdcp_workqueue *hdcp_work)
  71 {
  72         struct mod_hdcp_output output = hdcp_work->output;
  73
  74         if (output.callback_stop)
  75                 cancel_delayed_work(&hdcp_work->callback_dwork);
  76
  77         if (output.callback_needed)
  78                 schedule_delayed_work(&hdcp_work->callback_dwork,
  79                                       msecs_to_jiffies(output.callback_delay));
  80
  81         if (output.watchdog_timer_stop)
  82                 cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
  83
  84         if (output.watchdog_timer_needed)
  85                 schedule_delayed_work(&hdcp_work->watchdog_timer_dwork,
  86                                       msecs_to_jiffies(output.watchdog_timer_delay));
  87
  88         schedule_delayed_work(&hdcp_work->property_validate_dwork, msecs_to_jiffies(0));
  89 }
  90
  91 void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
  92                          unsigned int link_index,
  93                          struct amdgpu_dm_connector *aconnector,
  94                          uint8_t content_type,
  95                          bool enable_encryption)
  96 {
  97         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
  98         struct mod_hdcp_display *display = &hdcp_work[link_index].display;
  99         struct mod_hdcp_link *link = &hdcp_work[link_index].link;
 100         struct mod_hdcp_display_query query;
 101
 102         mutex_lock(&hdcp_w->mutex);
 103         hdcp_w->aconnector = aconnector;
 104
 105         query.display = NULL;
 106         mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &query);
 107
 108         if (query.display != NULL) {
 109                 memcpy(display, query.display, sizeof(struct mod_hdcp_display));
 110                 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
 111
 112                 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
 113
 114                 if (enable_encryption) {
 115                         display->adjust.disable = 0;
 116                         if (content_type == DRM_MODE_HDCP_CONTENT_TYPE0)
 117                                 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_0;
 118                         else if (content_type == DRM_MODE_HDCP_CONTENT_TYPE1)
 119                                 hdcp_w->link.adjust.hdcp2.force_type = MOD_HDCP_FORCE_TYPE_1;
 120
 121                         schedule_delayed_work(&hdcp_w->property_validate_dwork,
 122                                               msecs_to_jiffies(DRM_HDCP_CHECK_PERIOD_MS));
 123                 } else {
 124                         display->adjust.disable = 1;
 125                         hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 126                         cancel_delayed_work(&hdcp_w->property_validate_dwork);
 127                 }
 128
 129                 display->state = MOD_HDCP_DISPLAY_ACTIVE;
 130         }
 131
 132         mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output);
 133
 134         process_output(hdcp_w);
 135         mutex_unlock(&hdcp_w->mutex);
 136 }
 137
 138 static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,
 139                          unsigned int link_index,
 140                          struct amdgpu_dm_connector *aconnector)
 141 {
 142         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
 143
 144         mutex_lock(&hdcp_w->mutex);
 145         hdcp_w->aconnector = aconnector;
 146
 147         mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
 148
 149         process_output(hdcp_w);
 150         mutex_unlock(&hdcp_w->mutex);
 151 }
 152 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
 153 {
 154         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
 155
 156         mutex_lock(&hdcp_w->mutex);
 157
 158         mod_hdcp_reset_connection(&hdcp_w->hdcp,  &hdcp_w->output);
 159
 160         cancel_delayed_work(&hdcp_w->property_validate_dwork);
 161         hdcp_w->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 162
 163         process_output(hdcp_w);
 164
 165         mutex_unlock(&hdcp_w->mutex);
 166 }
 167
 168 void hdcp_handle_cpirq(struct hdcp_workqueue *hdcp_work, unsigned int link_index)
 169 {
 170         struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
 171
 172         schedule_work(&hdcp_w->cpirq_work);
 173 }
 174
 175
 176
 177
 178 static void event_callback(struct work_struct *work)
 179 {
 180         struct hdcp_workqueue *hdcp_work;
 181
 182         hdcp_work = container_of(to_delayed_work(work), struct hdcp_workqueue,
 183                                       callback_dwork);
 184
 185         mutex_lock(&hdcp_work->mutex);
 186
 187         cancel_delayed_work(&hdcp_work->watchdog_timer_dwork);
 188
 189         mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CALLBACK,
 190                                &hdcp_work->output);
 191
 192         process_output(hdcp_work);
 193
 194         mutex_unlock(&hdcp_work->mutex);
 195
 196
 197 }
 198 static void event_property_update(struct work_struct *work)
 199 {
 200
 201         struct hdcp_workqueue *hdcp_work = container_of(work, struct hdcp_workqueue, property_update_work);
 202         struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
 203         struct drm_device *dev = hdcp_work->aconnector->base.dev;
 204         long ret;
 205
 206         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 207         mutex_lock(&hdcp_work->mutex);
 208
 209
 210         if (aconnector->base.state->commit) {
 211                 ret = wait_for_completion_interruptible_timeout(&aconnector->base.state->commit->hw_done, 10 * HZ);
 212
 213                 if (ret == 0) {
 214                         DRM_ERROR("HDCP state unknown! Setting it to DESIRED");
 215                         hdcp_work->encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 216                 }
 217         }
 218
 219         if (hdcp_work->encryption_status != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
 220                 if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 &&
 221                     hdcp_work->encryption_status <= MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON)
 222                         drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
 223                 else if (aconnector->base.state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE1 &&
 224                          hdcp_work->encryption_status == MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
 225                         drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED);
 226         } else {
 227                 drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_DESIRED);
 228         }
 229
 230
 231         mutex_unlock(&hdcp_work->mutex);
 232         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 233 }
 234
 235 static void event_property_validate(struct work_struct *work)
 236 {
 237         struct hdcp_workqueue *hdcp_work =
 238                 container_of(to_delayed_work(work), struct hdcp_workqueue, property_validate_dwork);
 239         struct mod_hdcp_display_query query;
 240         struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;
 241
 242         if (!aconnector)
 243                 return;
 244
 245         mutex_lock(&hdcp_work->mutex);
 246
 247         query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
 248         mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, &query);
 249
 250         if (query.encryption_status != hdcp_work->encryption_status) {
 251                 hdcp_work->encryption_status = query.encryption_status;
 252                 schedule_work(&hdcp_work->property_update_work);
 253         }
 254
 255         mutex_unlock(&hdcp_work->mutex);
 256 }
 257
 258 static void event_watchdog_timer(struct work_struct *work)
 259 {
 260         struct hdcp_workqueue *hdcp_work;
 261
 262         hdcp_work = container_of(to_delayed_work(work),
 263                                       struct hdcp_workqueue,
 264                                       watchdog_timer_dwork);
 265
 266         mutex_lock(&hdcp_work->mutex);
 267
 268         mod_hdcp_process_event(&hdcp_work->hdcp,
 269                                MOD_HDCP_EVENT_WATCHDOG_TIMEOUT,
 270                                &hdcp_work->output);
 271
 272         process_output(hdcp_work);
 273
 274         mutex_unlock(&hdcp_work->mutex);
 275
 276 }
 277
 278 static void event_cpirq(struct work_struct *work)
 279 {
 280         struct hdcp_workqueue *hdcp_work;
 281
 282         hdcp_work = container_of(work, struct hdcp_workqueue, cpirq_work);
 283
 284         mutex_lock(&hdcp_work->mutex);
 285
 286         mod_hdcp_process_event(&hdcp_work->hdcp, MOD_HDCP_EVENT_CPIRQ, &hdcp_work->output);
 287
 288         process_output(hdcp_work);
 289
 290         mutex_unlock(&hdcp_work->mutex);
 291
 292 }
 293
 294
 295 void hdcp_destroy(struct hdcp_workqueue *hdcp_work)
 296 {
 297         int i = 0;
 298
 299         for (i = 0; i < hdcp_work->max_link; i++) {
 300                 cancel_delayed_work_sync(&hdcp_work[i].callback_dwork);
 301                 cancel_delayed_work_sync(&hdcp_work[i].watchdog_timer_dwork);
 302         }
 303
 304         kfree(hdcp_work);
 305
 306 }
 307
 308 static void update_config(void *handle, struct cp_psp_stream_config *config)
 309 {
 310         struct hdcp_workqueue *hdcp_work = handle;
 311         struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx;
 312         int link_index = aconnector->dc_link->link_index;
 313         struct mod_hdcp_display *display = &hdcp_work[link_index].display;
 314         struct mod_hdcp_link *link = &hdcp_work[link_index].link;
 315
 316         memset(display, 0, sizeof(*display));
 317         memset(link, 0, sizeof(*link));
 318
 319         display->index = aconnector->base.index;
 320
 321         if (config->dpms_off) {
 322                 hdcp_remove_display(hdcp_work, link_index, aconnector);
 323                 return;
 324         }
 325         display->state = MOD_HDCP_DISPLAY_ACTIVE;
 326
 327         if (aconnector->dc_sink != NULL)
 328                 link->mode = mod_hdcp_signal_type_to_operation_mode(aconnector->dc_sink->sink_signal);
 329
 330         display->controller = CONTROLLER_ID_D0 + config->otg_inst;
 331         display->dig_fe = config->stream_enc_inst;
 332         link->dig_be = config->link_enc_inst;
 333         link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
 334         link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 335         display->adjust.disable = 1;
 336         link->adjust.auth_delay = 2;
 337
 338         hdcp_update_display(hdcp_work, link_index, aconnector, DRM_MODE_HDCP_CONTENT_TYPE0, false);
 339 }
 340
 341 struct hdcp_workqueue *hdcp_create_workqueue(void *psp_context, struct cp_psp *cp_psp, struct dc *dc)
 342 {
 343
 344         int max_caps = dc->caps.max_links;
 345         struct hdcp_workqueue *hdcp_work = kzalloc(max_caps*sizeof(*hdcp_work), GFP_KERNEL);
 346         int i = 0;
 347
 348         if (hdcp_work == NULL)
 349                 goto fail_alloc_context;
 350
 351         hdcp_work->max_link = max_caps;
 352
 353         for (i = 0; i < max_caps; i++) {
 354
 355                 mutex_init(&hdcp_work[i].mutex);
 356
 357                 INIT_WORK(&hdcp_work[i].cpirq_work, event_cpirq);
 358                 INIT_WORK(&hdcp_work[i].property_update_work, event_property_update);
 359                 INIT_DELAYED_WORK(&hdcp_work[i].callback_dwork, event_callback);
 360                 INIT_DELAYED_WORK(&hdcp_work[i].watchdog_timer_dwork, event_watchdog_timer);
 361                 INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
 362
 363                 hdcp_work[i].hdcp.config.psp.handle =  psp_context;
 364                 hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
 365                 hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
 366                 hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
 367                 hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd = lp_write_dpcd;
 368                 hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd = lp_read_dpcd;
 369         }
 370
 371         cp_psp->funcs.update_stream_config = update_config;
 372         cp_psp->handle = hdcp_work;
 373
 374         return hdcp_work;
 375
 376 fail_alloc_context:
 377         kfree(hdcp_work);
 378
 379         return NULL;
 380
 381
 382
 383 }
 384
 385
 386