drivers/gpu/drm/i915/intel_vdsc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2018 Intel Corporation
   4  *
   5  * Author: Gaurav K Singh <[email protected]>
   6  *         Manasi Navare <[email protected]>
   7  */
   8
   9 #include <drm/drmP.h>
  10 #include <drm/i915_drm.h>
  11 #include "i915_drv.h"
  12 #include "intel_drv.h"
  13
  14 enum ROW_INDEX_BPP {
  15         ROW_INDEX_6BPP = 0,
  16         ROW_INDEX_8BPP,
  17         ROW_INDEX_10BPP,
  18         ROW_INDEX_12BPP,
  19         ROW_INDEX_15BPP,
  20         MAX_ROW_INDEX
  21 };
  22
  23 enum COLUMN_INDEX_BPC {
  24         COLUMN_INDEX_8BPC = 0,
  25         COLUMN_INDEX_10BPC,
  26         COLUMN_INDEX_12BPC,
  27         COLUMN_INDEX_14BPC,
  28         COLUMN_INDEX_16BPC,
  29         MAX_COLUMN_INDEX
  30 };
  31
  32 #define DSC_SUPPORTED_VERSION_MIN               1
  33
  34 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
  35 static u16 rc_buf_thresh[] = {
  36         896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
  37         7744, 7872, 8000, 8064
  38 };
  39
  40 struct rc_parameters {
  41         u16 initial_xmit_delay;
  42         u8 first_line_bpg_offset;
  43         u16 initial_offset;
  44         u8 flatness_min_qp;
  45         u8 flatness_max_qp;
  46         u8 rc_quant_incr_limit0;
  47         u8 rc_quant_incr_limit1;
  48         struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
  49 };
  50
  51 /*
  52  * Selected Rate Control Related Parameter Recommended Values
  53  * from DSC_v1.11 spec & C Model release: DSC_model_20161212
  54  */
  55 static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
  56 {
  57         /* 6BPP/8BPC */
  58         { 768, 15, 6144, 3, 13, 11, 11, {
  59                 { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
  60                 { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
  61                 { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
  62                 { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
  63                 }
  64         },
  65         /* 6BPP/10BPC */
  66         { 768, 15, 6144, 7, 17, 15, 15, {
  67                 { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
  68                 { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
  69                 { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
  70                 { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
  71                 { 17, 18, -12 }
  72                 }
  73         },
  74         /* 6BPP/12BPC */
  75         { 768, 15, 6144, 11, 21, 19, 19, {
  76                 { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
  77                 { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
  78                 { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
  79                 { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
  80                 { 21, 22, -12 }
  81                 }
  82         },
  83         /* 6BPP/14BPC */
  84         { 768, 15, 6144, 15, 25, 23, 27, {
  85                 { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
  86                 { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
  87                 { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
  88                 { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
  89                 { 25, 26, -12 }
  90                 }
  91         },
  92         /* 6BPP/16BPC */
  93         { 768, 15, 6144, 19, 29, 27, 27, {
  94                 { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
  95                 { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
  96                 { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
  97                 { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
  98                 { 29, 30, -12 }
  99                 }
 100         },
 101 },
 102 {
 103         /* 8BPP/8BPC */
 104         { 512, 12, 6144, 3, 12, 11, 11, {
 105                 { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 106                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 107                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
 108                 { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 109                 }
 110         },
 111         /* 8BPP/10BPC */
 112         { 512, 12, 6144, 7, 16, 15, 15, {
 113                 { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
 114                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 115                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 116                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 117                 }
 118         },
 119         /* 8BPP/12BPC */
 120         { 512, 12, 6144, 11, 20, 19, 19, {
 121                 { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
 122                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 123                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 124                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 125                 { 21, 23, -12 }
 126                 }
 127         },
 128         /* 8BPP/14BPC */
 129         { 512, 12, 6144, 15, 24, 23, 23, {
 130                 { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
 131                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 132                 { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
 133                 { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
 134                 { 24, 25, -12 }
 135                 }
 136         },
 137         /* 8BPP/16BPC */
 138         { 512, 12, 6144, 19, 28, 27, 27, {
 139                 { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
 140                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 141                 { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
 142                 { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
 143                 { 28, 29, -12 }
 144                 }
 145         },
 146 },
 147 {
 148         /* 10BPP/8BPC */
 149         { 410, 15, 5632, 3, 12, 11, 11, {
 150                 { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
 151                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 152                 { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
 153                 { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
 154                 }
 155         },
 156         /* 10BPP/10BPC */
 157         { 410, 15, 5632, 7, 16, 15, 15, {
 158                 { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
 159                 { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 160                 { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
 161                 { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
 162                 }
 163         },
 164         /* 10BPP/12BPC */
 165         { 410, 15, 5632, 11, 20, 19, 19, {
 166                 { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
 167                 { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 168                 { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
 169                 { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
 170                 { 19, 20, -12 }
 171                 }
 172         },
 173         /* 10BPP/14BPC */
 174         { 410, 15, 5632, 15, 24, 23, 23, {
 175                 { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
 176                 { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 177                 { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
 178                 { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
 179                 { 23, 24, -12 }
 180                 }
 181         },
 182         /* 10BPP/16BPC */
 183         { 410, 15, 5632, 19, 28, 27, 27, {
 184                 { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
 185                 { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 186                 { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
 187                 { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
 188                 { 27, 28, -12 }
 189                 }
 190         },
 191 },
 192 {
 193         /* 12BPP/8BPC */
 194         { 341, 15, 2048, 3, 12, 11, 11, {
 195                 { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
 196                 { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
 197                 { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
 198                 { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
 199                 }
 200         },
 201         /* 12BPP/10BPC */
 202         { 341, 15, 2048, 7, 16, 15, 15, {
 203                 { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
 204                 { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
 205                 { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
 206                 { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
 207                 }
 208         },
 209         /* 12BPP/12BPC */
 210         { 341, 15, 2048, 11, 20, 19, 19, {
 211                 { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
 212                 { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
 213                 { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
 214                 { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
 215                 { 21, 23, -12 }
 216                 }
 217         },
 218         /* 12BPP/14BPC */
 219         { 341, 15, 2048, 15, 24, 23, 23, {
 220                 { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
 221                 { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
 222                 { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
 223                 { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
 224                 { 22, 23, -12 }
 225                 }
 226         },
 227         /* 12BPP/16BPC */
 228         { 341, 15, 2048, 19, 28, 27, 27, {
 229                 { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
 230                 { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
 231                 { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
 232                 { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
 233                 { 26, 27, -12 }
 234                 }
 235         },
 236 },
 237 {
 238         /* 15BPP/8BPC */
 239         { 273, 15, 2048, 3, 12, 11, 11, {
 240                 { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
 241                 { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
 242                 { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
 243                 { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
 244                 }
 245         },
 246         /* 15BPP/10BPC */
 247         { 273, 15, 2048, 7, 16, 15, 15, {
 248                 { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
 249                 { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
 250                 { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
 251                 { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
 252                 }
 253         },
 254         /* 15BPP/12BPC */
 255         { 273, 15, 2048, 11, 20, 19, 19, {
 256                 { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
 257                 { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
 258                 { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
 259                 { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
 260                 { 16, 17, -12 }
 261                 }
 262         },
 263         /* 15BPP/14BPC */
 264         { 273, 15, 2048, 15, 24, 23, 23, {
 265                 { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
 266                 { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
 267                 { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
 268                 { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
 269                 { 20, 21, -12 }
 270                 }
 271         },
 272         /* 15BPP/16BPC */
 273         { 273, 15, 2048, 19, 28, 27, 27, {
 274                 { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
 275                 { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
 276                 { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
 277                 { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
 278                 { 24, 25, -12 }
 279                 }
 280         }
 281 }
 282
 283 };
 284
 285 static int get_row_index_for_rc_params(u16 compressed_bpp)
 286 {
 287         switch (compressed_bpp) {
 288         case 6:
 289                 return ROW_INDEX_6BPP;
 290         case 8:
 291                 return ROW_INDEX_8BPP;
 292         case 10:
 293                 return ROW_INDEX_10BPP;
 294         case 12:
 295                 return ROW_INDEX_12BPP;
 296         case 15:
 297                 return ROW_INDEX_15BPP;
 298         default:
 299                 return -EINVAL;
 300         }
 301 }
 302
 303 static int get_column_index_for_rc_params(u8 bits_per_component)
 304 {
 305         switch (bits_per_component) {
 306         case 8:
 307                 return COLUMN_INDEX_8BPC;
 308         case 10:
 309                 return COLUMN_INDEX_10BPC;
 310         case 12:
 311                 return COLUMN_INDEX_12BPC;
 312         case 14:
 313                 return COLUMN_INDEX_14BPC;
 314         case 16:
 315                 return COLUMN_INDEX_16BPC;
 316         default:
 317                 return -EINVAL;
 318         }
 319 }
 320
 321 static int intel_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg)
 322 {
 323         unsigned long groups_per_line = 0;
 324         unsigned long groups_total = 0;
 325         unsigned long num_extra_mux_bits = 0;
 326         unsigned long slice_bits = 0;
 327         unsigned long hrd_delay = 0;
 328         unsigned long final_scale = 0;
 329         unsigned long rbs_min = 0;
 330
 331         /* Number of groups used to code each line of a slice */
 332         groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width,
 333                                        DSC_RC_PIXELS_PER_GROUP);
 334
 335         /* chunksize in Bytes */
 336         vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
 337                                                   vdsc_cfg->bits_per_pixel,
 338                                                   (8 * 16));
 339
 340         if (vdsc_cfg->convert_rgb)
 341                 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size +
 342                                           (4 * vdsc_cfg->bits_per_component + 4)
 343                                           - 2);
 344         else
 345                 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
 346                         (4 * vdsc_cfg->bits_per_component + 4) +
 347                         2 * (4 * vdsc_cfg->bits_per_component) - 2;
 348         /* Number of bits in one Slice */
 349         slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
 350
 351         while ((num_extra_mux_bits > 0) &&
 352                ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
 353                 num_extra_mux_bits--;
 354
 355         if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
 356                 vdsc_cfg->initial_scale_value = groups_per_line + 8;
 357
 358         /* scale_decrement_interval calculation according to DSC spec 1.11 */
 359         if (vdsc_cfg->initial_scale_value > 8)
 360                 vdsc_cfg->scale_decrement_interval = groups_per_line /
 361                         (vdsc_cfg->initial_scale_value - 8);
 362         else
 363                 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX;
 364
 365         vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
 366                 (vdsc_cfg->initial_xmit_delay *
 367                  vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits;
 368
 369         if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
 370                 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n");
 371                 return -ERANGE;
 372         }
 373
 374         final_scale = (vdsc_cfg->rc_model_size * 8) /
 375                 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
 376         if (vdsc_cfg->slice_height > 1)
 377                 /*
 378                  * NflBpgOffset is 16 bit value with 11 fractional bits
 379                  * hence we multiply by 2^11 for preserving the
 380                  * fractional part
 381                  */
 382                 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11),
 383                                                         (vdsc_cfg->slice_height - 1));
 384         else
 385                 vdsc_cfg->nfl_bpg_offset = 0;
 386
 387         /* 2^16 - 1 */
 388         if (vdsc_cfg->nfl_bpg_offset > 65535) {
 389                 DRM_DEBUG_KMS("NflBpgOffset is too large for this slice height\n");
 390                 return -ERANGE;
 391         }
 392
 393         /* Number of groups used to code the entire slice */
 394         groups_total = groups_per_line * vdsc_cfg->slice_height;
 395
 396         /* slice_bpg_offset is 16 bit value with 11 fractional bits */
 397         vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
 398                                                     vdsc_cfg->initial_offset +
 399                                                     num_extra_mux_bits) << 11),
 400                                                   groups_total);
 401
 402         if (final_scale > 9) {
 403                 /*
 404                  * ScaleIncrementInterval =
 405                  * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
 406                  * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
 407                  * we need divide by 2^11 from pstDscCfg values
 408                  */
 409                 vdsc_cfg->scale_increment_interval =
 410                                 (vdsc_cfg->final_offset * (1 << 11)) /
 411                                 ((vdsc_cfg->nfl_bpg_offset +
 412                                 vdsc_cfg->slice_bpg_offset) *
 413                                 (final_scale - 9));
 414         } else {
 415                 /*
 416                  * If finalScaleValue is less than or equal to 9, a value of 0 should
 417                  * be used to disable the scale increment at the end of the slice
 418                  */
 419                 vdsc_cfg->scale_increment_interval = 0;
 420         }
 421
 422         if (vdsc_cfg->scale_increment_interval > 65535) {
 423                 DRM_DEBUG_KMS("ScaleIncrementInterval is large for slice height\n");
 424                 return -ERANGE;
 425         }
 426
 427         /*
 428          * DSC spec mentions that bits_per_pixel specifies the target
 429          * bits/pixel (bpp) rate that is used by the encoder,
 430          * in steps of 1/16 of a bit per pixel
 431          */
 432         rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
 433                 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay *
 434                              vdsc_cfg->bits_per_pixel, 16) +
 435                 groups_per_line * vdsc_cfg->first_line_bpg_offset;
 436
 437         hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
 438         vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
 439         vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
 440
 441         return 0;
 442 }
 443
 444 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
 445                                 struct intel_crtc_state *pipe_config)
 446 {
 447         struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg;
 448         u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp;
 449         u8 i = 0;
 450         int row_index = 0;
 451         int column_index = 0;
 452         u8 line_buf_depth = 0;
 453
 454         vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
 455         vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
 456         vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 457                                              pipe_config->dsc_params.slice_count);
 458         /*
 459          * Slice Height of 8 works for all currently available panels. So start
 460          * with that if pic_height is an integral multiple of 8.
 461          * Eventually add logic to try multiple slice heights.
 462          */
 463         if (vdsc_cfg->pic_height % 8 == 0)
 464                 vdsc_cfg->slice_height = 8;
 465         else if (vdsc_cfg->pic_height % 4 == 0)
 466                 vdsc_cfg->slice_height = 4;
 467         else
 468                 vdsc_cfg->slice_height = 2;
 469
 470         /* Values filled from DSC Sink DPCD */
 471         vdsc_cfg->dsc_version_major =
 472                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 473                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
 474         vdsc_cfg->dsc_version_minor =
 475                 min(DSC_SUPPORTED_VERSION_MIN,
 476                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 477                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
 478
 479         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
 480                 DP_DSC_RGB;
 481
 482         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 483         if (!line_buf_depth) {
 484                 DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
 485                 return -EINVAL;
 486         }
 487         if (vdsc_cfg->dsc_version_minor == 2)
 488                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
 489                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
 490         else
 491                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
 492                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
 493
 494         /* Gen 11 does not support YCbCr */
 495         vdsc_cfg->enable422 = false;
 496         /* Gen 11 does not support VBR */
 497         vdsc_cfg->vbr_enable = false;
 498         vdsc_cfg->block_pred_enable =
 499                         intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
 500                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
 501
 502         /* Gen 11 only supports integral values of bpp */
 503         vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
 504         vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 505
 506         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 507                 /*
 508                  * six 0s are appended to the lsb of each threshold value
 509                  * internally in h/w.
 510                  * Only 8 bits are allowed for programming RcBufThreshold
 511                  */
 512                 vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
 513         }
 514
 515         /*
 516          * For 6bpp, RC Buffer threshold 12 and 13 need a different value
 517          * as per C Model
 518          */
 519         if (compressed_bpp == 6) {
 520                 vdsc_cfg->rc_buf_thresh[12] = 0x7C;
 521                 vdsc_cfg->rc_buf_thresh[13] = 0x7D;
 522         }
 523
 524         row_index = get_row_index_for_rc_params(compressed_bpp);
 525         column_index =
 526                 get_column_index_for_rc_params(vdsc_cfg->bits_per_component);
 527
 528         if (row_index < 0 || column_index < 0)
 529                 return -EINVAL;
 530
 531         vdsc_cfg->first_line_bpg_offset =
 532                 rc_params[row_index][column_index].first_line_bpg_offset;
 533         vdsc_cfg->initial_xmit_delay =
 534                 rc_params[row_index][column_index].initial_xmit_delay;
 535         vdsc_cfg->initial_offset =
 536                 rc_params[row_index][column_index].initial_offset;
 537         vdsc_cfg->flatness_min_qp =
 538                 rc_params[row_index][column_index].flatness_min_qp;
 539         vdsc_cfg->flatness_max_qp =
 540                 rc_params[row_index][column_index].flatness_max_qp;
 541         vdsc_cfg->rc_quant_incr_limit0 =
 542                 rc_params[row_index][column_index].rc_quant_incr_limit0;
 543         vdsc_cfg->rc_quant_incr_limit1 =
 544                 rc_params[row_index][column_index].rc_quant_incr_limit1;
 545
 546         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 547                 vdsc_cfg->rc_range_params[i].range_min_qp =
 548                         rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
 549                 vdsc_cfg->rc_range_params[i].range_max_qp =
 550                         rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
 551                 /*
 552                  * Range BPG Offset uses 2's complement and is only a 6 bits. So
 553                  * mask it to get only 6 bits.
 554                  */
 555                 vdsc_cfg->rc_range_params[i].range_bpg_offset =
 556                         rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
 557                         DSC_RANGE_BPG_OFFSET_MASK;
 558         }
 559
 560         /*
 561          * BitsPerComponent value determines mux_word_size:
 562          * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
 563          * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
 564          * 48 bits
 565          */
 566         if (vdsc_cfg->bits_per_component == 8 ||
 567             vdsc_cfg->bits_per_component == 10)
 568                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
 569         else if (vdsc_cfg->bits_per_component == 12)
 570                 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 571
 572         /* RC_MODEL_SIZE is a constant across all configurations */
 573         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 574         /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 575         vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 576                 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 577
 578         return intel_compute_rc_parameters(vdsc_cfg);
 579 }
 580
 581 enum intel_display_power_domain
 582 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
 583 {
 584         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 585
 586         /*
 587          * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2
 588          * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
 589          * For any other transcoder, VDSC/joining uses the power well associated
 590          * with the pipe/transcoder in use. Hence another reference on the
 591          * transcoder power domain will suffice.
 592          */
 593         if (cpu_transcoder == TRANSCODER_EDP)
 594                 return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
 595         else
 596                 return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 597 }
 598
 599 static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder,
 600                                                 const struct intel_crtc_state *crtc_state)
 601 {
 602         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 603         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 604         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
 605         enum pipe pipe = crtc->pipe;
 606         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 607         u32 pps_val = 0;
 608         u32 rc_buf_thresh_dword[4];
 609         u32 rc_range_params_dword[8];
 610         u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1;
 611         int i = 0;
 612
 613         /* Populate PICTURE_PARAMETER_SET_0 registers */
 614         pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
 615                 DSC_VER_MIN_SHIFT |
 616                 vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 617                 vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
 618         if (vdsc_cfg->block_pred_enable)
 619                 pps_val |= DSC_BLOCK_PREDICTION;
 620         if (vdsc_cfg->convert_rgb)
 621                 pps_val |= DSC_COLOR_SPACE_CONVERSION;
 622         if (vdsc_cfg->enable422)
 623                 pps_val |= DSC_422_ENABLE;
 624         if (vdsc_cfg->vbr_enable)
 625                 pps_val |= DSC_VBR_ENABLE;
 626         DRM_INFO("PPS0 = 0x%08x\n", pps_val);
 627         if (cpu_transcoder == TRANSCODER_EDP) {
 628                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val);
 629                 /*
 630                  * If 2 VDSC instances are needed, configure PPS for second
 631                  * VDSC
 632                  */
 633                 if (crtc_state->dsc_params.dsc_split)
 634                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val);
 635         } else {
 636                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val);
 637                 if (crtc_state->dsc_params.dsc_split)
 638                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
 639                                    pps_val);
 640         }
 641
 642         /* Populate PICTURE_PARAMETER_SET_1 registers */
 643         pps_val = 0;
 644         pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 645         DRM_INFO("PPS1 = 0x%08x\n", pps_val);
 646         if (cpu_transcoder == TRANSCODER_EDP) {
 647                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val);
 648                 /*
 649                  * If 2 VDSC instances are needed, configure PPS for second
 650                  * VDSC
 651                  */
 652                 if (crtc_state->dsc_params.dsc_split)
 653                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val);
 654         } else {
 655                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val);
 656                 if (crtc_state->dsc_params.dsc_split)
 657                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
 658                                    pps_val);
 659         }
 660
 661         /* Populate PICTURE_PARAMETER_SET_2 registers */
 662         pps_val = 0;
 663         pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 664                 DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 665         DRM_INFO("PPS2 = 0x%08x\n", pps_val);
 666         if (encoder->type == INTEL_OUTPUT_EDP) {
 667                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);
 668                 /*
 669                  * If 2 VDSC instances are needed, configure PPS for second
 670                  * VDSC
 671                  */
 672                 if (crtc_state->dsc_params.dsc_split)
 673                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val);
 674         } else {
 675                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val);
 676                 if (crtc_state->dsc_params.dsc_split)
 677                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
 678                                    pps_val);
 679         }
 680
 681         /* Populate PICTURE_PARAMETER_SET_3 registers */
 682         pps_val = 0;
 683         pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 684                 DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 685         DRM_INFO("PPS3 = 0x%08x\n", pps_val);
 686         if (cpu_transcoder == TRANSCODER_EDP) {
 687                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val);
 688                 /*
 689                  * If 2 VDSC instances are needed, configure PPS for second
 690                  * VDSC
 691                  */
 692                 if (crtc_state->dsc_params.dsc_split)
 693                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val);
 694         } else {
 695                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val);
 696                 if (crtc_state->dsc_params.dsc_split)
 697                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
 698                                    pps_val);
 699         }
 700
 701         /* Populate PICTURE_PARAMETER_SET_4 registers */
 702         pps_val = 0;
 703         pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 704                 DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 705         DRM_INFO("PPS4 = 0x%08x\n", pps_val);
 706         if (cpu_transcoder == TRANSCODER_EDP) {
 707                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val);
 708                 /*
 709                  * If 2 VDSC instances are needed, configure PPS for second
 710                  * VDSC
 711                  */
 712                 if (crtc_state->dsc_params.dsc_split)
 713                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val);
 714         } else {
 715                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val);
 716                 if (crtc_state->dsc_params.dsc_split)
 717                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
 718                                    pps_val);
 719         }
 720
 721         /* Populate PICTURE_PARAMETER_SET_5 registers */
 722         pps_val = 0;
 723         pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 724                 DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 725         DRM_INFO("PPS5 = 0x%08x\n", pps_val);
 726         if (cpu_transcoder == TRANSCODER_EDP) {
 727                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val);
 728                 /*
 729                  * If 2 VDSC instances are needed, configure PPS for second
 730                  * VDSC
 731                  */
 732                 if (crtc_state->dsc_params.dsc_split)
 733                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val);
 734         } else {
 735                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val);
 736                 if (crtc_state->dsc_params.dsc_split)
 737                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
 738                                    pps_val);
 739         }
 740
 741         /* Populate PICTURE_PARAMETER_SET_6 registers */
 742         pps_val = 0;
 743         pps_val |= DSC_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
 744                 DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
 745                 DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 746                 DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 747         DRM_INFO("PPS6 = 0x%08x\n", pps_val);
 748         if (cpu_transcoder == TRANSCODER_EDP) {
 749                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val);
 750                 /*
 751                  * If 2 VDSC instances are needed, configure PPS for second
 752                  * VDSC
 753                  */
 754                 if (crtc_state->dsc_params.dsc_split)
 755                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val);
 756         } else {
 757                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val);
 758                 if (crtc_state->dsc_params.dsc_split)
 759                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
 760                                    pps_val);
 761         }
 762
 763         /* Populate PICTURE_PARAMETER_SET_7 registers */
 764         pps_val = 0;
 765         pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 766                 DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 767         DRM_INFO("PPS7 = 0x%08x\n", pps_val);
 768         if (cpu_transcoder == TRANSCODER_EDP) {
 769                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val);
 770                 /*
 771                  * If 2 VDSC instances are needed, configure PPS for second
 772                  * VDSC
 773                  */
 774                 if (crtc_state->dsc_params.dsc_split)
 775                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val);
 776         } else {
 777                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val);
 778                 if (crtc_state->dsc_params.dsc_split)
 779                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
 780                                    pps_val);
 781         }
 782
 783         /* Populate PICTURE_PARAMETER_SET_8 registers */
 784         pps_val = 0;
 785         pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 786                 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 787         DRM_INFO("PPS8 = 0x%08x\n", pps_val);
 788         if (cpu_transcoder == TRANSCODER_EDP) {
 789                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val);
 790                 /*
 791                  * If 2 VDSC instances are needed, configure PPS for second
 792                  * VDSC
 793                  */
 794                 if (crtc_state->dsc_params.dsc_split)
 795                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val);
 796         } else {
 797                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val);
 798                 if (crtc_state->dsc_params.dsc_split)
 799                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
 800                                    pps_val);
 801         }
 802
 803         /* Populate PICTURE_PARAMETER_SET_9 registers */
 804         pps_val = 0;
 805         pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) |
 806                 DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 807         DRM_INFO("PPS9 = 0x%08x\n", pps_val);
 808         if (cpu_transcoder == TRANSCODER_EDP) {
 809                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val);
 810                 /*
 811                  * If 2 VDSC instances are needed, configure PPS for second
 812                  * VDSC
 813                  */
 814                 if (crtc_state->dsc_params.dsc_split)
 815                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val);
 816         } else {
 817                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val);
 818                 if (crtc_state->dsc_params.dsc_split)
 819                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
 820                                    pps_val);
 821         }
 822
 823         /* Populate PICTURE_PARAMETER_SET_10 registers */
 824         pps_val = 0;
 825         pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
 826                 DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
 827                 DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 828                 DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 829         DRM_INFO("PPS10 = 0x%08x\n", pps_val);
 830         if (cpu_transcoder == TRANSCODER_EDP) {
 831                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val);
 832                 /*
 833                  * If 2 VDSC instances are needed, configure PPS for second
 834                  * VDSC
 835                  */
 836                 if (crtc_state->dsc_params.dsc_split)
 837                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val);
 838         } else {
 839                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val);
 840                 if (crtc_state->dsc_params.dsc_split)
 841                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
 842                                    pps_val);
 843         }
 844
 845         /* Populate Picture parameter set 16 */
 846         pps_val = 0;
 847         pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
 848                 DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
 849                                    vdsc_cfg->slice_width) |
 850                 DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 851                                         vdsc_cfg->slice_height);
 852         DRM_INFO("PPS16 = 0x%08x\n", pps_val);
 853         if (cpu_transcoder == TRANSCODER_EDP) {
 854                 I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val);
 855                 /*
 856                  * If 2 VDSC instances are needed, configure PPS for second
 857                  * VDSC
 858                  */
 859                 if (crtc_state->dsc_params.dsc_split)
 860                         I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val);
 861         } else {
 862                 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val);
 863                 if (crtc_state->dsc_params.dsc_split)
 864                         I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
 865                                    pps_val);
 866         }
 867
 868         /* Populate the RC_BUF_THRESH registers */
 869         memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 870         for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
 871                 rc_buf_thresh_dword[i / 4] |=
 872                         (u32)(vdsc_cfg->rc_buf_thresh[i] <<
 873                               BITS_PER_BYTE * (i % 4));
 874                 DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i,
 875                          rc_buf_thresh_dword[i / 4]);
 876         }
 877         if (cpu_transcoder == TRANSCODER_EDP) {
 878                 I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]);
 879                 I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]);
 880                 I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]);
 881                 I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]);
 882                 if (crtc_state->dsc_params.dsc_split) {
 883                         I915_WRITE(DSCC_RC_BUF_THRESH_0,
 884                                    rc_buf_thresh_dword[0]);
 885                         I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW,
 886                                    rc_buf_thresh_dword[1]);
 887                         I915_WRITE(DSCC_RC_BUF_THRESH_1,
 888                                    rc_buf_thresh_dword[2]);
 889                         I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW,
 890                                    rc_buf_thresh_dword[3]);
 891                 }
 892         } else {
 893                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe),
 894                            rc_buf_thresh_dword[0]);
 895                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
 896                            rc_buf_thresh_dword[1]);
 897                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe),
 898                            rc_buf_thresh_dword[2]);
 899                 I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
 900                            rc_buf_thresh_dword[3]);
 901                 if (crtc_state->dsc_params.dsc_split) {
 902                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe),
 903                                    rc_buf_thresh_dword[0]);
 904                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
 905                                    rc_buf_thresh_dword[1]);
 906                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe),
 907                                    rc_buf_thresh_dword[2]);
 908                         I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
 909                                    rc_buf_thresh_dword[3]);
 910                 }
 911         }
 912
 913         /* Populate the RC_RANGE_PARAMETERS registers */
 914         memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
 915         for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
 916                 rc_range_params_dword[i / 2] |=
 917                         (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
 918                                 RC_BPG_OFFSET_SHIFT) |
 919                                (vdsc_cfg->rc_range_params[i].range_max_qp <<
 920                                 RC_MAX_QP_SHIFT) |
 921                                (vdsc_cfg->rc_range_params[i].range_min_qp <<
 922                                 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
 923                 DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i,
 924                          rc_range_params_dword[i / 2]);
 925         }
 926         if (cpu_transcoder == TRANSCODER_EDP) {
 927                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0,
 928                            rc_range_params_dword[0]);
 929                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW,
 930                            rc_range_params_dword[1]);
 931                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1,
 932                            rc_range_params_dword[2]);
 933                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW,
 934                            rc_range_params_dword[3]);
 935                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2,
 936                            rc_range_params_dword[4]);
 937                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW,
 938                            rc_range_params_dword[5]);
 939                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3,
 940                            rc_range_params_dword[6]);
 941                 I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW,
 942                            rc_range_params_dword[7]);
 943                 if (crtc_state->dsc_params.dsc_split) {
 944                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0,
 945                                    rc_range_params_dword[0]);
 946                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW,
 947                                    rc_range_params_dword[1]);
 948                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1,
 949                                    rc_range_params_dword[2]);
 950                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW,
 951                                    rc_range_params_dword[3]);
 952                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2,
 953                                    rc_range_params_dword[4]);
 954                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW,
 955                                    rc_range_params_dword[5]);
 956                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3,
 957                                    rc_range_params_dword[6]);
 958                         I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW,
 959                                    rc_range_params_dword[7]);
 960                 }
 961         } else {
 962                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
 963                            rc_range_params_dword[0]);
 964                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
 965                            rc_range_params_dword[1]);
 966                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
 967                            rc_range_params_dword[2]);
 968                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
 969                            rc_range_params_dword[3]);
 970                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
 971                            rc_range_params_dword[4]);
 972                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
 973                            rc_range_params_dword[5]);
 974                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
 975                            rc_range_params_dword[6]);
 976                 I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
 977                            rc_range_params_dword[7]);
 978                 if (crtc_state->dsc_params.dsc_split) {
 979                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
 980                                    rc_range_params_dword[0]);
 981                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
 982                                    rc_range_params_dword[1]);
 983                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
 984                                    rc_range_params_dword[2]);
 985                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
 986                                    rc_range_params_dword[3]);
 987                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
 988                                    rc_range_params_dword[4]);
 989                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
 990                                    rc_range_params_dword[5]);
 991                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
 992                                    rc_range_params_dword[6]);
 993                         I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
 994                                    rc_range_params_dword[7]);
 995                 }
 996         }
 997 }
 998
 999 static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder,
1000                                        const struct intel_crtc_state *crtc_state)
1001 {
1002         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1003         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1004         const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg;
1005         struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
1006
1007         /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
1008         drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp);
1009
1010         /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
1011         drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg);
1012
1013         intel_dig_port->write_infoframe(encoder, crtc_state,
1014                                         DP_SDP_PPS, &dp_dsc_pps_sdp,
1015                                         sizeof(dp_dsc_pps_sdp));
1016 }
1017
1018 void intel_dsc_enable(struct intel_encoder *encoder,
1019                       const struct intel_crtc_state *crtc_state)
1020 {
1021         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1022         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1023         enum pipe pipe = crtc->pipe;
1024         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
1025         u32 dss_ctl1_val = 0;
1026         u32 dss_ctl2_val = 0;
1027
1028         if (!crtc_state->dsc_params.compression_enable)
1029                 return;
1030
1031         /* Enable Power wells for VDSC/joining */
1032         intel_display_power_get(dev_priv,
1033                                 intel_dsc_power_domain(crtc_state));
1034
1035         intel_configure_pps_for_dsc_encoder(encoder, crtc_state);
1036
1037         intel_dp_write_dsc_pps_sdp(encoder, crtc_state);
1038
1039         if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
1040                 dss_ctl1_reg = DSS_CTL1;
1041                 dss_ctl2_reg = DSS_CTL2;
1042         } else {
1043                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
1044                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
1045         }
1046         dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
1047         if (crtc_state->dsc_params.dsc_split) {
1048                 dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
1049                 dss_ctl1_val |= JOINER_ENABLE;
1050         }
1051         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
1052         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
1053 }
1054
1055 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
1056 {
1057         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1058         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1059         enum pipe pipe = crtc->pipe;
1060         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
1061         u32 dss_ctl1_val = 0, dss_ctl2_val = 0;
1062
1063         if (!old_crtc_state->dsc_params.compression_enable)
1064                 return;
1065
1066         if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) {
1067                 dss_ctl1_reg = DSS_CTL1;
1068                 dss_ctl2_reg = DSS_CTL2;
1069         } else {
1070                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe);
1071                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe);
1072         }
1073         dss_ctl1_val = I915_READ(dss_ctl1_reg);
1074         if (dss_ctl1_val & JOINER_ENABLE)
1075                 dss_ctl1_val &= ~JOINER_ENABLE;
1076         I915_WRITE(dss_ctl1_reg, dss_ctl1_val);
1077
1078         dss_ctl2_val = I915_READ(dss_ctl2_reg);
1079         if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE ||
1080             dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE)
1081                 dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE |
1082                                   RIGHT_BRANCH_VDSC_ENABLE);
1083         I915_WRITE(dss_ctl2_reg, dss_ctl2_val);
1084
1085         /* Disable Power wells for VDSC/joining */
1086         intel_display_power_put(dev_priv,
1087                                 intel_dsc_power_domain(old_crtc_state));
1088 }