drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68 #include "amdgpu_dm_replay.h"
  69
  70 #include "ivsrcid/ivsrcid_vislands30.h"
  71
  72 #include <linux/backlight.h>
  73 #include <linux/module.h>
  74 #include <linux/moduleparam.h>
  75 #include <linux/types.h>
  76 #include <linux/pm_runtime.h>
  77 #include <linux/pci.h>
  78 #include <linux/firmware.h>
  79 #include <linux/component.h>
  80 #include <linux/dmi.h>
  81
  82 #include <drm/display/drm_dp_mst_helper.h>
  83 #include <drm/display/drm_hdmi_helper.h>
  84 #include <drm/drm_atomic.h>
  85 #include <drm/drm_atomic_uapi.h>
  86 #include <drm/drm_atomic_helper.h>
  87 #include <drm/drm_blend.h>
  88 #include <drm/drm_fixed.h>
  89 #include <drm/drm_fourcc.h>
  90 #include <drm/drm_edid.h>
  91 #include <drm/drm_eld.h>
  92 #include <drm/drm_vblank.h>
  93 #include <drm/drm_audio_component.h>
  94 #include <drm/drm_gem_atomic_helper.h>
  95 #include <drm/drm_plane_helper.h>
  96
  97 #include <acpi/video.h>
  98
  99 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 100
 101 #include "dcn/dcn_1_0_offset.h"
 102 #include "dcn/dcn_1_0_sh_mask.h"
 103 #include "soc15_hw_ip.h"
 104 #include "soc15_common.h"
 105 #include "vega10_ip_offset.h"
 106
 107 #include "gc/gc_11_0_0_offset.h"
 108 #include "gc/gc_11_0_0_sh_mask.h"
 109
 110 #include "modules/inc/mod_freesync.h"
 111 #include "modules/power/power_helpers.h"
 112
 113 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 114 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 115 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 116 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 117 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 118 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 119 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 120 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 121 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 122 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 123 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 124 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 125 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 126 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 127 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 128 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 129 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 130 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 131 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 132 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 133 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 135
 136 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 137 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 138 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 139 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 140
 141 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 143
 144 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 145 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 146
 147 #define FIRMWARE_DCN_35_DMUB "amdgpu/dcn_3_5_dmcub.bin"
 148 MODULE_FIRMWARE(FIRMWARE_DCN_35_DMUB);
 149
 150 /* Number of bytes in PSP header for firmware. */
 151 #define PSP_HEADER_BYTES 0x100
 152
 153 /* Number of bytes in PSP footer for firmware. */
 154 #define PSP_FOOTER_BYTES 0x100
 155
 156 /**
 157  * DOC: overview
 158  *
 159  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 160  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 161  * requests into DC requests, and DC responses into DRM responses.
 162  *
 163  * The root control structure is &struct amdgpu_display_manager.
 164  */
 165
 166 /* basic init/fini API */
 167 static int amdgpu_dm_init(struct amdgpu_device *adev);
 168 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 169 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 170
 171 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 172 {
 173         switch (link->dpcd_caps.dongle_type) {
 174         case DISPLAY_DONGLE_NONE:
 175                 return DRM_MODE_SUBCONNECTOR_Native;
 176         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 177                 return DRM_MODE_SUBCONNECTOR_VGA;
 178         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 179         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 180                 return DRM_MODE_SUBCONNECTOR_DVID;
 181         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 182         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 183                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 184         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 185         default:
 186                 return DRM_MODE_SUBCONNECTOR_Unknown;
 187         }
 188 }
 189
 190 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 191 {
 192         struct dc_link *link = aconnector->dc_link;
 193         struct drm_connector *connector = &aconnector->base;
 194         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 195
 196         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 197                 return;
 198
 199         if (aconnector->dc_sink)
 200                 subconnector = get_subconnector_type(link);
 201
 202         drm_object_property_set_value(&connector->base,
 203                         connector->dev->mode_config.dp_subconnector_property,
 204                         subconnector);
 205 }
 206
 207 /*
 208  * initializes drm_device display related structures, based on the information
 209  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 210  * drm_encoder, drm_mode_config
 211  *
 212  * Returns 0 on success
 213  */
 214 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 215 /* removes and deallocates the drm structures, created by the above function */
 216 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 217
 218 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 219                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 220                                     u32 link_index,
 221                                     struct amdgpu_encoder *amdgpu_encoder);
 222 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 223                                   struct amdgpu_encoder *aencoder,
 224                                   uint32_t link_index);
 225
 226 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 227
 228 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 229
 230 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 231                                   struct drm_atomic_state *state);
 232
 233 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 234 static void handle_hpd_rx_irq(void *param);
 235
 236 static bool
 237 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 238                                  struct drm_crtc_state *new_crtc_state);
 239 /*
 240  * dm_vblank_get_counter
 241  *
 242  * @brief
 243  * Get counter for number of vertical blanks
 244  *
 245  * @param
 246  * struct amdgpu_device *adev - [in] desired amdgpu device
 247  * int disp_idx - [in] which CRTC to get the counter from
 248  *
 249  * @return
 250  * Counter for vertical blanks
 251  */
 252 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 253 {
 254         struct amdgpu_crtc *acrtc = NULL;
 255
 256         if (crtc >= adev->mode_info.num_crtc)
 257                 return 0;
 258
 259         acrtc = adev->mode_info.crtcs[crtc];
 260
 261         if (!acrtc->dm_irq_params.stream) {
 262                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 263                           crtc);
 264                 return 0;
 265         }
 266
 267         return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 268 }
 269
 270 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 271                                   u32 *vbl, u32 *position)
 272 {
 273         u32 v_blank_start, v_blank_end, h_position, v_position;
 274         struct amdgpu_crtc *acrtc = NULL;
 275
 276         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 277                 return -EINVAL;
 278
 279         acrtc = adev->mode_info.crtcs[crtc];
 280
 281         if (!acrtc->dm_irq_params.stream) {
 282                 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 283                           crtc);
 284                 return 0;
 285         }
 286
 287         /*
 288          * TODO rework base driver to use values directly.
 289          * for now parse it back into reg-format
 290          */
 291         dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 292                                  &v_blank_start,
 293                                  &v_blank_end,
 294                                  &h_position,
 295                                  &v_position);
 296
 297         *position = v_position | (h_position << 16);
 298         *vbl = v_blank_start | (v_blank_end << 16);
 299
 300         return 0;
 301 }
 302
 303 static bool dm_is_idle(void *handle)
 304 {
 305         /* XXX todo */
 306         return true;
 307 }
 308
 309 static int dm_wait_for_idle(void *handle)
 310 {
 311         /* XXX todo */
 312         return 0;
 313 }
 314
 315 static bool dm_check_soft_reset(void *handle)
 316 {
 317         return false;
 318 }
 319
 320 static int dm_soft_reset(void *handle)
 321 {
 322         /* XXX todo */
 323         return 0;
 324 }
 325
 326 static struct amdgpu_crtc *
 327 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 328                      int otg_inst)
 329 {
 330         struct drm_device *dev = adev_to_drm(adev);
 331         struct drm_crtc *crtc;
 332         struct amdgpu_crtc *amdgpu_crtc;
 333
 334         if (WARN_ON(otg_inst == -1))
 335                 return adev->mode_info.crtcs[0];
 336
 337         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 338                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 339
 340                 if (amdgpu_crtc->otg_inst == otg_inst)
 341                         return amdgpu_crtc;
 342         }
 343
 344         return NULL;
 345 }
 346
 347 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 348                                               struct dm_crtc_state *new_state)
 349 {
 350         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 351                 return true;
 352         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 353                 return true;
 354         else
 355                 return false;
 356 }
 357
 358 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 359                                         int planes_count)
 360 {
 361         int i, j;
 362
 363         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 364                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 365 }
 366
 367 /**
 368  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 369  *
 370  * DC has a generic way to update planes and stream via
 371  * dc_update_planes_and_stream function; however, DM might need some
 372  * adjustments and preparation before calling it. This function is a wrapper
 373  * for the dc_update_planes_and_stream that does any required configuration
 374  * before passing control to DC.
 375  *
 376  * @dc: Display Core control structure
 377  * @update_type: specify whether it is FULL/MEDIUM/FAST update
 378  * @planes_count: planes count to update
 379  * @stream: stream state
 380  * @stream_update: stream update
 381  * @array_of_surface_update: dc surface update pointer
 382  *
 383  */
 384 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 385                                                     int update_type,
 386                                                     int planes_count,
 387                                                     struct dc_stream_state *stream,
 388                                                     struct dc_stream_update *stream_update,
 389                                                     struct dc_surface_update *array_of_surface_update)
 390 {
 391         reverse_planes_order(array_of_surface_update, planes_count);
 392
 393         /*
 394          * Previous frame finished and HW is ready for optimization.
 395          */
 396         if (update_type == UPDATE_TYPE_FAST)
 397                 dc_post_update_surfaces_to_stream(dc);
 398
 399         return dc_update_planes_and_stream(dc,
 400                                            array_of_surface_update,
 401                                            planes_count,
 402                                            stream,
 403                                            stream_update);
 404 }
 405
 406 /**
 407  * dm_pflip_high_irq() - Handle pageflip interrupt
 408  * @interrupt_params: ignored
 409  *
 410  * Handles the pageflip interrupt by notifying all interested parties
 411  * that the pageflip has been completed.
 412  */
 413 static void dm_pflip_high_irq(void *interrupt_params)
 414 {
 415         struct amdgpu_crtc *amdgpu_crtc;
 416         struct common_irq_params *irq_params = interrupt_params;
 417         struct amdgpu_device *adev = irq_params->adev;
 418         struct drm_device *dev = adev_to_drm(adev);
 419         unsigned long flags;
 420         struct drm_pending_vblank_event *e;
 421         u32 vpos, hpos, v_blank_start, v_blank_end;
 422         bool vrr_active;
 423
 424         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 425
 426         /* IRQ could occur when in initial stage */
 427         /* TODO work and BO cleanup */
 428         if (amdgpu_crtc == NULL) {
 429                 drm_dbg_state(dev, "CRTC is null, returning.\n");
 430                 return;
 431         }
 432
 433         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 434
 435         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 436                 drm_dbg_state(dev,
 437                               "amdgpu_crtc->pflip_status = %d != AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",
 438                               amdgpu_crtc->pflip_status, AMDGPU_FLIP_SUBMITTED,
 439                               amdgpu_crtc->crtc_id, amdgpu_crtc);
 440                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 441                 return;
 442         }
 443
 444         /* page flip completed. */
 445         e = amdgpu_crtc->event;
 446         amdgpu_crtc->event = NULL;
 447
 448         WARN_ON(!e);
 449
 450         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 451
 452         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 453         if (!vrr_active ||
 454             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 455                                       &v_blank_end, &hpos, &vpos) ||
 456             (vpos < v_blank_start)) {
 457                 /* Update to correct count and vblank timestamp if racing with
 458                  * vblank irq. This also updates to the correct vblank timestamp
 459                  * even in VRR mode, as scanout is past the front-porch atm.
 460                  */
 461                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 462
 463                 /* Wake up userspace by sending the pageflip event with proper
 464                  * count and timestamp of vblank of flip completion.
 465                  */
 466                 if (e) {
 467                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 468
 469                         /* Event sent, so done with vblank for this flip */
 470                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 471                 }
 472         } else if (e) {
 473                 /* VRR active and inside front-porch: vblank count and
 474                  * timestamp for pageflip event will only be up to date after
 475                  * drm_crtc_handle_vblank() has been executed from late vblank
 476                  * irq handler after start of back-porch (vline 0). We queue the
 477                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 478                  * updated timestamp and count, once it runs after us.
 479                  *
 480                  * We need to open-code this instead of using the helper
 481                  * drm_crtc_arm_vblank_event(), as that helper would
 482                  * call drm_crtc_accurate_vblank_count(), which we must
 483                  * not call in VRR mode while we are in front-porch!
 484                  */
 485
 486                 /* sequence will be replaced by real count during send-out. */
 487                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 488                 e->pipe = amdgpu_crtc->crtc_id;
 489
 490                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 491                 e = NULL;
 492         }
 493
 494         /* Keep track of vblank of this flip for flip throttling. We use the
 495          * cooked hw counter, as that one incremented at start of this vblank
 496          * of pageflip completion, so last_flip_vblank is the forbidden count
 497          * for queueing new pageflips if vsync + VRR is enabled.
 498          */
 499         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 500                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 501
 502         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 503         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 504
 505         drm_dbg_state(dev,
 506                       "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 507                       amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e);
 508 }
 509
 510 static void dm_vupdate_high_irq(void *interrupt_params)
 511 {
 512         struct common_irq_params *irq_params = interrupt_params;
 513         struct amdgpu_device *adev = irq_params->adev;
 514         struct amdgpu_crtc *acrtc;
 515         struct drm_device *drm_dev;
 516         struct drm_vblank_crtc *vblank;
 517         ktime_t frame_duration_ns, previous_timestamp;
 518         unsigned long flags;
 519         int vrr_active;
 520
 521         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 522
 523         if (acrtc) {
 524                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 525                 drm_dev = acrtc->base.dev;
 526                 vblank = &drm_dev->vblank[acrtc->base.index];
 527                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 528                 frame_duration_ns = vblank->time - previous_timestamp;
 529
 530                 if (frame_duration_ns > 0) {
 531                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 532                                                 frame_duration_ns,
 533                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 534                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 535                 }
 536
 537                 drm_dbg_vbl(drm_dev,
 538                             "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 539                             vrr_active);
 540
 541                 /* Core vblank handling is done here after end of front-porch in
 542                  * vrr mode, as vblank timestamping will give valid results
 543                  * while now done after front-porch. This will also deliver
 544                  * page-flip completion events that have been queued to us
 545                  * if a pageflip happened inside front-porch.
 546                  */
 547                 if (vrr_active) {
 548                         amdgpu_dm_crtc_handle_vblank(acrtc);
 549
 550                         /* BTR processing for pre-DCE12 ASICs */
 551                         if (acrtc->dm_irq_params.stream &&
 552                             adev->family < AMDGPU_FAMILY_AI) {
 553                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 554                                 mod_freesync_handle_v_update(
 555                                     adev->dm.freesync_module,
 556                                     acrtc->dm_irq_params.stream,
 557                                     &acrtc->dm_irq_params.vrr_params);
 558
 559                                 dc_stream_adjust_vmin_vmax(
 560                                     adev->dm.dc,
 561                                     acrtc->dm_irq_params.stream,
 562                                     &acrtc->dm_irq_params.vrr_params.adjust);
 563                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 564                         }
 565                 }
 566         }
 567 }
 568
 569 /**
 570  * dm_crtc_high_irq() - Handles CRTC interrupt
 571  * @interrupt_params: used for determining the CRTC instance
 572  *
 573  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 574  * event handler.
 575  */
 576 static void dm_crtc_high_irq(void *interrupt_params)
 577 {
 578         struct common_irq_params *irq_params = interrupt_params;
 579         struct amdgpu_device *adev = irq_params->adev;
 580         struct amdgpu_crtc *acrtc;
 581         unsigned long flags;
 582         int vrr_active;
 583
 584         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 585         if (!acrtc)
 586                 return;
 587
 588         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 589
 590         drm_dbg_vbl(adev_to_drm(adev),
 591                     "crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 592                     vrr_active, acrtc->dm_irq_params.active_planes);
 593
 594         /**
 595          * Core vblank handling at start of front-porch is only possible
 596          * in non-vrr mode, as only there vblank timestamping will give
 597          * valid results while done in front-porch. Otherwise defer it
 598          * to dm_vupdate_high_irq after end of front-porch.
 599          */
 600         if (!vrr_active)
 601                 amdgpu_dm_crtc_handle_vblank(acrtc);
 602
 603         /**
 604          * Following stuff must happen at start of vblank, for crc
 605          * computation and below-the-range btr support in vrr mode.
 606          */
 607         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 608
 609         /* BTR updates need to happen before VUPDATE on Vega and above. */
 610         if (adev->family < AMDGPU_FAMILY_AI)
 611                 return;
 612
 613         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 614
 615         if (acrtc->dm_irq_params.stream &&
 616             acrtc->dm_irq_params.vrr_params.supported &&
 617             acrtc->dm_irq_params.freesync_config.state ==
 618                     VRR_STATE_ACTIVE_VARIABLE) {
 619                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 620                                              acrtc->dm_irq_params.stream,
 621                                              &acrtc->dm_irq_params.vrr_params);
 622
 623                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 624                                            &acrtc->dm_irq_params.vrr_params.adjust);
 625         }
 626
 627         /*
 628          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 629          * In that case, pageflip completion interrupts won't fire and pageflip
 630          * completion events won't get delivered. Prevent this by sending
 631          * pending pageflip events from here if a flip is still pending.
 632          *
 633          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 634          * avoid race conditions between flip programming and completion,
 635          * which could cause too early flip completion events.
 636          */
 637         if (adev->family >= AMDGPU_FAMILY_RV &&
 638             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 639             acrtc->dm_irq_params.active_planes == 0) {
 640                 if (acrtc->event) {
 641                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 642                         acrtc->event = NULL;
 643                         drm_crtc_vblank_put(&acrtc->base);
 644                 }
 645                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 646         }
 647
 648         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 649 }
 650
 651 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 652 /**
 653  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 654  * DCN generation ASICs
 655  * @interrupt_params: interrupt parameters
 656  *
 657  * Used to set crc window/read out crc value at vertical line 0 position
 658  */
 659 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 660 {
 661         struct common_irq_params *irq_params = interrupt_params;
 662         struct amdgpu_device *adev = irq_params->adev;
 663         struct amdgpu_crtc *acrtc;
 664
 665         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 666
 667         if (!acrtc)
 668                 return;
 669
 670         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 671 }
 672 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 673
 674 /**
 675  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 676  * @adev: amdgpu_device pointer
 677  * @notify: dmub notification structure
 678  *
 679  * Dmub AUX or SET_CONFIG command completion processing callback
 680  * Copies dmub notification to DM which is to be read by AUX command.
 681  * issuing thread and also signals the event to wake up the thread.
 682  */
 683 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 684                                         struct dmub_notification *notify)
 685 {
 686         if (adev->dm.dmub_notify)
 687                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 688         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 689                 complete(&adev->dm.dmub_aux_transfer_done);
 690 }
 691
 692 /**
 693  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 694  * @adev: amdgpu_device pointer
 695  * @notify: dmub notification structure
 696  *
 697  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 698  * ink index and calls helper to do the processing.
 699  */
 700 static void dmub_hpd_callback(struct amdgpu_device *adev,
 701                               struct dmub_notification *notify)
 702 {
 703         struct amdgpu_dm_connector *aconnector;
 704         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 705         struct drm_connector *connector;
 706         struct drm_connector_list_iter iter;
 707         struct dc_link *link;
 708         u8 link_index = 0;
 709         struct drm_device *dev;
 710
 711         if (adev == NULL)
 712                 return;
 713
 714         if (notify == NULL) {
 715                 DRM_ERROR("DMUB HPD callback notification was NULL");
 716                 return;
 717         }
 718
 719         if (notify->link_index > adev->dm.dc->link_count) {
 720                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 721                 return;
 722         }
 723
 724         link_index = notify->link_index;
 725         link = adev->dm.dc->links[link_index];
 726         dev = adev->dm.ddev;
 727
 728         drm_connector_list_iter_begin(dev, &iter);
 729         drm_for_each_connector_iter(connector, &iter) {
 730                 aconnector = to_amdgpu_dm_connector(connector);
 731                 if (link && aconnector->dc_link == link) {
 732                         if (notify->type == DMUB_NOTIFICATION_HPD)
 733                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 734                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 735                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 736                         else
 737                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 738                                                 notify->type, link_index);
 739
 740                         hpd_aconnector = aconnector;
 741                         break;
 742                 }
 743         }
 744         drm_connector_list_iter_end(&iter);
 745
 746         if (hpd_aconnector) {
 747                 if (notify->type == DMUB_NOTIFICATION_HPD)
 748                         handle_hpd_irq_helper(hpd_aconnector);
 749                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 750                         handle_hpd_rx_irq(hpd_aconnector);
 751         }
 752 }
 753
 754 /**
 755  * register_dmub_notify_callback - Sets callback for DMUB notify
 756  * @adev: amdgpu_device pointer
 757  * @type: Type of dmub notification
 758  * @callback: Dmub interrupt callback function
 759  * @dmub_int_thread_offload: offload indicator
 760  *
 761  * API to register a dmub callback handler for a dmub notification
 762  * Also sets indicator whether callback processing to be offloaded.
 763  * to dmub interrupt handling thread
 764  * Return: true if successfully registered, false if there is existing registration
 765  */
 766 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 767                                           enum dmub_notification_type type,
 768                                           dmub_notify_interrupt_callback_t callback,
 769                                           bool dmub_int_thread_offload)
 770 {
 771         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 772                 adev->dm.dmub_callback[type] = callback;
 773                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 774         } else
 775                 return false;
 776
 777         return true;
 778 }
 779
 780 static void dm_handle_hpd_work(struct work_struct *work)
 781 {
 782         struct dmub_hpd_work *dmub_hpd_wrk;
 783
 784         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 785
 786         if (!dmub_hpd_wrk->dmub_notify) {
 787                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 788                 return;
 789         }
 790
 791         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 792                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 793                 dmub_hpd_wrk->dmub_notify);
 794         }
 795
 796         kfree(dmub_hpd_wrk->dmub_notify);
 797         kfree(dmub_hpd_wrk);
 798
 799 }
 800
 801 #define DMUB_TRACE_MAX_READ 64
 802 /**
 803  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 804  * @interrupt_params: used for determining the Outbox instance
 805  *
 806  * Handles the Outbox Interrupt
 807  * event handler.
 808  */
 809 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 810 {
 811         struct dmub_notification notify;
 812         struct common_irq_params *irq_params = interrupt_params;
 813         struct amdgpu_device *adev = irq_params->adev;
 814         struct amdgpu_display_manager *dm = &adev->dm;
 815         struct dmcub_trace_buf_entry entry = { 0 };
 816         u32 count = 0;
 817         struct dmub_hpd_work *dmub_hpd_wrk;
 818         struct dc_link *plink = NULL;
 819
 820         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 821                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 822
 823                 do {
 824                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 825                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 826                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 827                                 continue;
 828                         }
 829                         if (!dm->dmub_callback[notify.type]) {
 830                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 831                                 continue;
 832                         }
 833                         if (dm->dmub_thread_offload[notify.type] == true) {
 834                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 835                                 if (!dmub_hpd_wrk) {
 836                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 837                                         return;
 838                                 }
 839                                 dmub_hpd_wrk->dmub_notify = kmemdup(&notify, sizeof(struct dmub_notification),
 840                                                                     GFP_ATOMIC);
 841                                 if (!dmub_hpd_wrk->dmub_notify) {
 842                                         kfree(dmub_hpd_wrk);
 843                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 844                                         return;
 845                                 }
 846                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 847                                 dmub_hpd_wrk->adev = adev;
 848                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 849                                         plink = adev->dm.dc->links[notify.link_index];
 850                                         if (plink) {
 851                                                 plink->hpd_status =
 852                                                         notify.hpd_status == DP_HPD_PLUG;
 853                                         }
 854                                 }
 855                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 856                         } else {
 857                                 dm->dmub_callback[notify.type](adev, &notify);
 858                         }
 859                 } while (notify.pending_notification);
 860         }
 861
 862
 863         do {
 864                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 865                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 866                                                         entry.param0, entry.param1);
 867
 868                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 869                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 870                 } else
 871                         break;
 872
 873                 count++;
 874
 875         } while (count <= DMUB_TRACE_MAX_READ);
 876
 877         if (count > DMUB_TRACE_MAX_READ)
 878                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 879 }
 880
 881 static int dm_set_clockgating_state(void *handle,
 882                   enum amd_clockgating_state state)
 883 {
 884         return 0;
 885 }
 886
 887 static int dm_set_powergating_state(void *handle,
 888                   enum amd_powergating_state state)
 889 {
 890         return 0;
 891 }
 892
 893 /* Prototypes of private functions */
 894 static int dm_early_init(void *handle);
 895
 896 /* Allocate memory for FBC compressed data  */
 897 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 898 {
 899         struct amdgpu_device *adev = drm_to_adev(connector->dev);
 900         struct dm_compressor_info *compressor = &adev->dm.compressor;
 901         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 902         struct drm_display_mode *mode;
 903         unsigned long max_size = 0;
 904
 905         if (adev->dm.dc->fbc_compressor == NULL)
 906                 return;
 907
 908         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 909                 return;
 910
 911         if (compressor->bo_ptr)
 912                 return;
 913
 914
 915         list_for_each_entry(mode, &connector->modes, head) {
 916                 if (max_size < mode->htotal * mode->vtotal)
 917                         max_size = mode->htotal * mode->vtotal;
 918         }
 919
 920         if (max_size) {
 921                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 922                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 923                             &compressor->gpu_addr, &compressor->cpu_addr);
 924
 925                 if (r)
 926                         DRM_ERROR("DM: Failed to initialize FBC\n");
 927                 else {
 928                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 929                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 930                 }
 931
 932         }
 933
 934 }
 935
 936 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 937                                           int pipe, bool *enabled,
 938                                           unsigned char *buf, int max_bytes)
 939 {
 940         struct drm_device *dev = dev_get_drvdata(kdev);
 941         struct amdgpu_device *adev = drm_to_adev(dev);
 942         struct drm_connector *connector;
 943         struct drm_connector_list_iter conn_iter;
 944         struct amdgpu_dm_connector *aconnector;
 945         int ret = 0;
 946
 947         *enabled = false;
 948
 949         mutex_lock(&adev->dm.audio_lock);
 950
 951         drm_connector_list_iter_begin(dev, &conn_iter);
 952         drm_for_each_connector_iter(connector, &conn_iter) {
 953                 aconnector = to_amdgpu_dm_connector(connector);
 954                 if (aconnector->audio_inst != port)
 955                         continue;
 956
 957                 *enabled = true;
 958                 ret = drm_eld_size(connector->eld);
 959                 memcpy(buf, connector->eld, min(max_bytes, ret));
 960
 961                 break;
 962         }
 963         drm_connector_list_iter_end(&conn_iter);
 964
 965         mutex_unlock(&adev->dm.audio_lock);
 966
 967         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 968
 969         return ret;
 970 }
 971
 972 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 973         .get_eld = amdgpu_dm_audio_component_get_eld,
 974 };
 975
 976 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 977                                        struct device *hda_kdev, void *data)
 978 {
 979         struct drm_device *dev = dev_get_drvdata(kdev);
 980         struct amdgpu_device *adev = drm_to_adev(dev);
 981         struct drm_audio_component *acomp = data;
 982
 983         acomp->ops = &amdgpu_dm_audio_component_ops;
 984         acomp->dev = kdev;
 985         adev->dm.audio_component = acomp;
 986
 987         return 0;
 988 }
 989
 990 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 991                                           struct device *hda_kdev, void *data)
 992 {
 993         struct amdgpu_device *adev = drm_to_adev(dev_get_drvdata(kdev));
 994         struct drm_audio_component *acomp = data;
 995
 996         acomp->ops = NULL;
 997         acomp->dev = NULL;
 998         adev->dm.audio_component = NULL;
 999 }
1000
1001 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
1002         .bind   = amdgpu_dm_audio_component_bind,
1003         .unbind = amdgpu_dm_audio_component_unbind,
1004 };
1005
1006 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1007 {
1008         int i, ret;
1009
1010         if (!amdgpu_audio)
1011                 return 0;
1012
1013         adev->mode_info.audio.enabled = true;
1014
1015         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1016
1017         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1018                 adev->mode_info.audio.pin[i].channels = -1;
1019                 adev->mode_info.audio.pin[i].rate = -1;
1020                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1021                 adev->mode_info.audio.pin[i].status_bits = 0;
1022                 adev->mode_info.audio.pin[i].category_code = 0;
1023                 adev->mode_info.audio.pin[i].connected = false;
1024                 adev->mode_info.audio.pin[i].id =
1025                         adev->dm.dc->res_pool->audios[i]->inst;
1026                 adev->mode_info.audio.pin[i].offset = 0;
1027         }
1028
1029         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1030         if (ret < 0)
1031                 return ret;
1032
1033         adev->dm.audio_registered = true;
1034
1035         return 0;
1036 }
1037
1038 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1039 {
1040         if (!amdgpu_audio)
1041                 return;
1042
1043         if (!adev->mode_info.audio.enabled)
1044                 return;
1045
1046         if (adev->dm.audio_registered) {
1047                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1048                 adev->dm.audio_registered = false;
1049         }
1050
1051         /* TODO: Disable audio? */
1052
1053         adev->mode_info.audio.enabled = false;
1054 }
1055
1056 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1057 {
1058         struct drm_audio_component *acomp = adev->dm.audio_component;
1059
1060         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1061                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1062
1063                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1064                                                  pin, -1);
1065         }
1066 }
1067
1068 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1069 {
1070         const struct dmcub_firmware_header_v1_0 *hdr;
1071         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1072         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1073         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1074         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1075         struct abm *abm = adev->dm.dc->res_pool->abm;
1076         struct dc_context *ctx = adev->dm.dc->ctx;
1077         struct dmub_srv_hw_params hw_params;
1078         enum dmub_status status;
1079         const unsigned char *fw_inst_const, *fw_bss_data;
1080         u32 i, fw_inst_const_size, fw_bss_data_size;
1081         bool has_hw_support;
1082
1083         if (!dmub_srv)
1084                 /* DMUB isn't supported on the ASIC. */
1085                 return 0;
1086
1087         if (!fb_info) {
1088                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1089                 return -EINVAL;
1090         }
1091
1092         if (!dmub_fw) {
1093                 /* Firmware required for DMUB support. */
1094                 DRM_ERROR("No firmware provided for DMUB.\n");
1095                 return -EINVAL;
1096         }
1097
1098         /* initialize register offsets for ASICs with runtime initialization available */
1099         if (dmub_srv->hw_funcs.init_reg_offsets)
1100                 dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);
1101
1102         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1103         if (status != DMUB_STATUS_OK) {
1104                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1105                 return -EINVAL;
1106         }
1107
1108         if (!has_hw_support) {
1109                 DRM_INFO("DMUB unsupported on ASIC\n");
1110                 return 0;
1111         }
1112
1113         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1114         status = dmub_srv_hw_reset(dmub_srv);
1115         if (status != DMUB_STATUS_OK)
1116                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1117
1118         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1119
1120         fw_inst_const = dmub_fw->data +
1121                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1122                         PSP_HEADER_BYTES;
1123
1124         fw_bss_data = dmub_fw->data +
1125                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1126                       le32_to_cpu(hdr->inst_const_bytes);
1127
1128         /* Copy firmware and bios info into FB memory. */
1129         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1130                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1131
1132         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1133
1134         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1135          * amdgpu_ucode_init_single_fw will load dmub firmware
1136          * fw_inst_const part to cw0; otherwise, the firmware back door load
1137          * will be done by dm_dmub_hw_init
1138          */
1139         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1140                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1141                                 fw_inst_const_size);
1142         }
1143
1144         if (fw_bss_data_size)
1145                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1146                        fw_bss_data, fw_bss_data_size);
1147
1148         /* Copy firmware bios info into FB memory. */
1149         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1150                adev->bios_size);
1151
1152         /* Reset regions that need to be reset. */
1153         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1154         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1155
1156         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1157                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1158
1159         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1160                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1161
1162         /* Initialize hardware. */
1163         memset(&hw_params, 0, sizeof(hw_params));
1164         hw_params.fb_base = adev->gmc.fb_start;
1165         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1166
1167         /* backdoor load firmware and trigger dmub running */
1168         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1169                 hw_params.load_inst_const = true;
1170
1171         if (dmcu)
1172                 hw_params.psp_version = dmcu->psp_version;
1173
1174         for (i = 0; i < fb_info->num_fb; ++i)
1175                 hw_params.fb[i] = &fb_info->fb[i];
1176
1177         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1178         case IP_VERSION(3, 1, 3):
1179         case IP_VERSION(3, 1, 4):
1180         case IP_VERSION(3, 5, 0):
1181                 hw_params.dpia_supported = true;
1182                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1183                 break;
1184         default:
1185                 break;
1186         }
1187
1188         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1189         if (status != DMUB_STATUS_OK) {
1190                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1191                 return -EINVAL;
1192         }
1193
1194         /* Wait for firmware load to finish. */
1195         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1196         if (status != DMUB_STATUS_OK)
1197                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1198
1199         /* Init DMCU and ABM if available. */
1200         if (dmcu && abm) {
1201                 dmcu->funcs->dmcu_init(dmcu);
1202                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1203         }
1204
1205         if (!adev->dm.dc->ctx->dmub_srv)
1206                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1207         if (!adev->dm.dc->ctx->dmub_srv) {
1208                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1209                 return -ENOMEM;
1210         }
1211
1212         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1213                  adev->dm.dmcub_fw_version);
1214
1215         return 0;
1216 }
1217
1218 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1219 {
1220         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1221         enum dmub_status status;
1222         bool init;
1223
1224         if (!dmub_srv) {
1225                 /* DMUB isn't supported on the ASIC. */
1226                 return;
1227         }
1228
1229         status = dmub_srv_is_hw_init(dmub_srv, &init);
1230         if (status != DMUB_STATUS_OK)
1231                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1232
1233         if (status == DMUB_STATUS_OK && init) {
1234                 /* Wait for firmware load to finish. */
1235                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1236                 if (status != DMUB_STATUS_OK)
1237                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1238         } else {
1239                 /* Perform the full hardware initialization. */
1240                 dm_dmub_hw_init(adev);
1241         }
1242 }
1243
1244 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1245 {
1246         u64 pt_base;
1247         u32 logical_addr_low;
1248         u32 logical_addr_high;
1249         u32 agp_base, agp_bot, agp_top;
1250         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1251
1252         memset(pa_config, 0, sizeof(*pa_config));
1253
1254         agp_base = 0;
1255         agp_bot = adev->gmc.agp_start >> 24;
1256         agp_top = adev->gmc.agp_end >> 24;
1257
1258         /* AGP aperture is disabled */
1259         if (agp_bot > agp_top) {
1260                 logical_addr_low = adev->gmc.fb_start >> 18;
1261                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1262                         /*
1263                          * Raven2 has a HW issue that it is unable to use the vram which
1264                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1265                          * workaround that increase system aperture high address (add 1)
1266                          * to get rid of the VM fault and hardware hang.
1267                          */
1268                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1269                 else
1270                         logical_addr_high = adev->gmc.fb_end >> 18;
1271         } else {
1272                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1273                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1274                         /*
1275                          * Raven2 has a HW issue that it is unable to use the vram which
1276                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1277                          * workaround that increase system aperture high address (add 1)
1278                          * to get rid of the VM fault and hardware hang.
1279                          */
1280                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1281                 else
1282                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1283         }
1284
1285         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1286
1287         page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
1288                                                    AMDGPU_GPU_PAGE_SHIFT);
1289         page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
1290                                                   AMDGPU_GPU_PAGE_SHIFT);
1291         page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
1292                                                  AMDGPU_GPU_PAGE_SHIFT);
1293         page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
1294                                                 AMDGPU_GPU_PAGE_SHIFT);
1295         page_table_base.high_part = upper_32_bits(pt_base);
1296         page_table_base.low_part = lower_32_bits(pt_base);
1297
1298         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1299         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1300
1301         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
1302         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1303         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1304
1305         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1306         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1307         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1308
1309         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1310         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1311         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1312
1313         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1314
1315 }
1316
1317 static void force_connector_state(
1318         struct amdgpu_dm_connector *aconnector,
1319         enum drm_connector_force force_state)
1320 {
1321         struct drm_connector *connector = &aconnector->base;
1322
1323         mutex_lock(&connector->dev->mode_config.mutex);
1324         aconnector->base.force = force_state;
1325         mutex_unlock(&connector->dev->mode_config.mutex);
1326
1327         mutex_lock(&aconnector->hpd_lock);
1328         drm_kms_helper_connector_hotplug_event(connector);
1329         mutex_unlock(&aconnector->hpd_lock);
1330 }
1331
1332 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1333 {
1334         struct hpd_rx_irq_offload_work *offload_work;
1335         struct amdgpu_dm_connector *aconnector;
1336         struct dc_link *dc_link;
1337         struct amdgpu_device *adev;
1338         enum dc_connection_type new_connection_type = dc_connection_none;
1339         unsigned long flags;
1340         union test_response test_response;
1341
1342         memset(&test_response, 0, sizeof(test_response));
1343
1344         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1345         aconnector = offload_work->offload_wq->aconnector;
1346
1347         if (!aconnector) {
1348                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1349                 goto skip;
1350         }
1351
1352         adev = drm_to_adev(aconnector->base.dev);
1353         dc_link = aconnector->dc_link;
1354
1355         mutex_lock(&aconnector->hpd_lock);
1356         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1357                 DRM_ERROR("KMS: Failed to detect connector\n");
1358         mutex_unlock(&aconnector->hpd_lock);
1359
1360         if (new_connection_type == dc_connection_none)
1361                 goto skip;
1362
1363         if (amdgpu_in_reset(adev))
1364                 goto skip;
1365
1366         if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
1367                 offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
1368                 dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
1369                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1370                 offload_work->offload_wq->is_handling_mst_msg_rdy_event = false;
1371                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1372                 goto skip;
1373         }
1374
1375         mutex_lock(&adev->dm.dc_lock);
1376         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1377                 dc_link_dp_handle_automated_test(dc_link);
1378
1379                 if (aconnector->timing_changed) {
1380                         /* force connector disconnect and reconnect */
1381                         force_connector_state(aconnector, DRM_FORCE_OFF);
1382                         msleep(100);
1383                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1384                 }
1385
1386                 test_response.bits.ACK = 1;
1387
1388                 core_link_write_dpcd(
1389                 dc_link,
1390                 DP_TEST_RESPONSE,
1391                 &test_response.raw,
1392                 sizeof(test_response));
1393         } else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1394                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1395                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1396                 /* offload_work->data is from handle_hpd_rx_irq->
1397                  * schedule_hpd_rx_offload_work.this is defer handle
1398                  * for hpd short pulse. upon here, link status may be
1399                  * changed, need get latest link status from dpcd
1400                  * registers. if link status is good, skip run link
1401                  * training again.
1402                  */
1403                 union hpd_irq_data irq_data;
1404
1405                 memset(&irq_data, 0, sizeof(irq_data));
1406
1407                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1408                  * request be added to work queue if link lost at end of dc_link_
1409                  * dp_handle_link_loss
1410                  */
1411                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1412                 offload_work->offload_wq->is_handling_link_loss = false;
1413                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1414
1415                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1416                         dc_link_check_link_loss_status(dc_link, &irq_data))
1417                         dc_link_dp_handle_link_loss(dc_link);
1418         }
1419         mutex_unlock(&adev->dm.dc_lock);
1420
1421 skip:
1422         kfree(offload_work);
1423
1424 }
1425
1426 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1427 {
1428         int max_caps = dc->caps.max_links;
1429         int i = 0;
1430         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1431
1432         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1433
1434         if (!hpd_rx_offload_wq)
1435                 return NULL;
1436
1437
1438         for (i = 0; i < max_caps; i++) {
1439                 hpd_rx_offload_wq[i].wq =
1440                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1441
1442                 if (hpd_rx_offload_wq[i].wq == NULL) {
1443                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1444                         goto out_err;
1445                 }
1446
1447                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1448         }
1449
1450         return hpd_rx_offload_wq;
1451
1452 out_err:
1453         for (i = 0; i < max_caps; i++) {
1454                 if (hpd_rx_offload_wq[i].wq)
1455                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1456         }
1457         kfree(hpd_rx_offload_wq);
1458         return NULL;
1459 }
1460
1461 struct amdgpu_stutter_quirk {
1462         u16 chip_vendor;
1463         u16 chip_device;
1464         u16 subsys_vendor;
1465         u16 subsys_device;
1466         u8 revision;
1467 };
1468
1469 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1470         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1471         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1472         { 0, 0, 0, 0, 0 },
1473 };
1474
1475 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1476 {
1477         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1478
1479         while (p && p->chip_device != 0) {
1480                 if (pdev->vendor == p->chip_vendor &&
1481                     pdev->device == p->chip_device &&
1482                     pdev->subsystem_vendor == p->subsys_vendor &&
1483                     pdev->subsystem_device == p->subsys_device &&
1484                     pdev->revision == p->revision) {
1485                         return true;
1486                 }
1487                 ++p;
1488         }
1489         return false;
1490 }
1491
1492 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1493         {
1494                 .matches = {
1495                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1496                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1497                 },
1498         },
1499         {
1500                 .matches = {
1501                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1502                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1503                 },
1504         },
1505         {
1506                 .matches = {
1507                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1508                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1509                 },
1510         },
1511         {
1512                 .matches = {
1513                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1514                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1515                 },
1516         },
1517         {
1518                 .matches = {
1519                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1520                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1521                 },
1522         },
1523         {
1524                 .matches = {
1525                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1526                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1527                 },
1528         },
1529         {
1530                 .matches = {
1531                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1532                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1533                 },
1534         },
1535         {
1536                 .matches = {
1537                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1538                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1539                 },
1540         },
1541         {
1542                 .matches = {
1543                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1544                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1545                 },
1546         },
1547         {}
1548         /* TODO: refactor this from a fixed table to a dynamic option */
1549 };
1550
1551 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1552 {
1553         const struct dmi_system_id *dmi_id;
1554
1555         dm->aux_hpd_discon_quirk = false;
1556
1557         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1558         if (dmi_id) {
1559                 dm->aux_hpd_discon_quirk = true;
1560                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1561         }
1562 }
1563
1564 static int amdgpu_dm_init(struct amdgpu_device *adev)
1565 {
1566         struct dc_init_data init_data;
1567         struct dc_callback_init init_params;
1568         int r;
1569
1570         adev->dm.ddev = adev_to_drm(adev);
1571         adev->dm.adev = adev;
1572
1573         /* Zero all the fields */
1574         memset(&init_data, 0, sizeof(init_data));
1575         memset(&init_params, 0, sizeof(init_params));
1576
1577         mutex_init(&adev->dm.dpia_aux_lock);
1578         mutex_init(&adev->dm.dc_lock);
1579         mutex_init(&adev->dm.audio_lock);
1580
1581         if (amdgpu_dm_irq_init(adev)) {
1582                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1583                 goto error;
1584         }
1585
1586         init_data.asic_id.chip_family = adev->family;
1587
1588         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1589         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1590         init_data.asic_id.chip_id = adev->pdev->device;
1591
1592         init_data.asic_id.vram_width = adev->gmc.vram_width;
1593         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1594         init_data.asic_id.atombios_base_address =
1595                 adev->mode_info.atom_context->bios;
1596
1597         init_data.driver = adev;
1598
1599         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1600
1601         if (!adev->dm.cgs_device) {
1602                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1603                 goto error;
1604         }
1605
1606         init_data.cgs_device = adev->dm.cgs_device;
1607
1608         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1609
1610         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1611         case IP_VERSION(2, 1, 0):
1612                 switch (adev->dm.dmcub_fw_version) {
1613                 case 0: /* development */
1614                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1615                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1616                         init_data.flags.disable_dmcu = false;
1617                         break;
1618                 default:
1619                         init_data.flags.disable_dmcu = true;
1620                 }
1621                 break;
1622         case IP_VERSION(2, 0, 3):
1623                 init_data.flags.disable_dmcu = true;
1624                 break;
1625         default:
1626                 break;
1627         }
1628
1629         /* APU support S/G display by default except:
1630          * ASICs before Carrizo,
1631          * RAVEN1 (Users reported stability issue)
1632          */
1633
1634         if (adev->asic_type < CHIP_CARRIZO) {
1635                 init_data.flags.gpu_vm_support = false;
1636         } else if (adev->asic_type == CHIP_RAVEN) {
1637                 if (adev->apu_flags & AMD_APU_IS_RAVEN)
1638                         init_data.flags.gpu_vm_support = false;
1639                 else
1640                         init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0);
1641         } else {
1642                 init_data.flags.gpu_vm_support = (amdgpu_sg_display != 0) && (adev->flags & AMD_IS_APU);
1643         }
1644
1645         adev->mode_info.gpu_vm_support = init_data.flags.gpu_vm_support;
1646
1647         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1648                 init_data.flags.fbc_support = true;
1649
1650         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1651                 init_data.flags.multi_mon_pp_mclk_switch = true;
1652
1653         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1654                 init_data.flags.disable_fractional_pwm = true;
1655
1656         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1657                 init_data.flags.edp_no_power_sequencing = true;
1658
1659         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1660                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1661         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1662                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1663
1664         init_data.flags.seamless_boot_edp_requested = false;
1665
1666         if (amdgpu_device_seamless_boot_supported(adev)) {
1667                 init_data.flags.seamless_boot_edp_requested = true;
1668                 init_data.flags.allow_seamless_boot_optimization = true;
1669                 DRM_INFO("Seamless boot condition check passed\n");
1670         }
1671
1672         init_data.flags.enable_mipi_converter_optimization = true;
1673
1674         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1675         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1676         init_data.clk_reg_offsets = adev->reg_offset[CLK_HWIP][0];
1677
1678         /* Enable DWB for tested platforms only */
1679         if (adev->ip_versions[DCE_HWIP][0] >= IP_VERSION(3, 0, 0))
1680                 init_data.num_virtual_links = 1;
1681
1682         INIT_LIST_HEAD(&adev->dm.da_list);
1683
1684         retrieve_dmi_info(&adev->dm);
1685
1686         /* Display Core create. */
1687         adev->dm.dc = dc_create(&init_data);
1688
1689         if (adev->dm.dc) {
1690                 DRM_INFO("Display Core v%s initialized on %s\n", DC_VER,
1691                          dce_version_to_string(adev->dm.dc->ctx->dce_version));
1692         } else {
1693                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1694                 goto error;
1695         }
1696
1697         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1698                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1699                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1700         }
1701
1702         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1703                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1704         if (dm_should_disable_stutter(adev->pdev))
1705                 adev->dm.dc->debug.disable_stutter = true;
1706
1707         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1708                 adev->dm.dc->debug.disable_stutter = true;
1709
1710         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
1711                 adev->dm.dc->debug.disable_dsc = true;
1712
1713         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1714                 adev->dm.dc->debug.disable_clock_gate = true;
1715
1716         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1717                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1718
1719         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1720
1721         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1722         adev->dm.dc->debug.ignore_cable_id = true;
1723
1724         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1725                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1726
1727         r = dm_dmub_hw_init(adev);
1728         if (r) {
1729                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1730                 goto error;
1731         }
1732
1733         dc_hardware_init(adev->dm.dc);
1734
1735         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1736         if (!adev->dm.hpd_rx_offload_wq) {
1737                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1738                 goto error;
1739         }
1740
1741         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1742                 struct dc_phy_addr_space_config pa_config;
1743
1744                 mmhub_read_system_context(adev, &pa_config);
1745
1746                 // Call the DC init_memory func
1747                 dc_setup_system_context(adev->dm.dc, &pa_config);
1748         }
1749
1750         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1751         if (!adev->dm.freesync_module) {
1752                 DRM_ERROR(
1753                 "amdgpu: failed to initialize freesync_module.\n");
1754         } else
1755                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1756                                 adev->dm.freesync_module);
1757
1758         amdgpu_dm_init_color_mod();
1759
1760         if (adev->dm.dc->caps.max_links > 0) {
1761                 adev->dm.vblank_control_workqueue =
1762                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1763                 if (!adev->dm.vblank_control_workqueue)
1764                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1765         }
1766
1767         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1768                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1769
1770                 if (!adev->dm.hdcp_workqueue)
1771                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1772                 else
1773                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1774
1775                 dc_init_callbacks(adev->dm.dc, &init_params);
1776         }
1777         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1778                 init_completion(&adev->dm.dmub_aux_transfer_done);
1779                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1780                 if (!adev->dm.dmub_notify) {
1781                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1782                         goto error;
1783                 }
1784
1785                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1786                 if (!adev->dm.delayed_hpd_wq) {
1787                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1788                         goto error;
1789                 }
1790
1791                 amdgpu_dm_outbox_init(adev);
1792                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1793                         dmub_aux_setconfig_callback, false)) {
1794                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1795                         goto error;
1796                 }
1797                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1798                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1799                         goto error;
1800                 }
1801                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1802                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1803                         goto error;
1804                 }
1805         }
1806
1807         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1808          * It is expected that DMUB will resend any pending notifications at this point, for
1809          * example HPD from DPIA.
1810          */
1811         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1812                 dc_enable_dmub_outbox(adev->dm.dc);
1813
1814                 /* DPIA trace goes to dmesg logs only if outbox is enabled */
1815                 if (amdgpu_dc_debug_mask & DC_ENABLE_DPIA_TRACE)
1816                         dc_dmub_srv_enable_dpia_trace(adev->dm.dc);
1817         }
1818
1819         if (amdgpu_dm_initialize_drm_device(adev)) {
1820                 DRM_ERROR(
1821                 "amdgpu: failed to initialize sw for display support.\n");
1822                 goto error;
1823         }
1824
1825         /* create fake encoders for MST */
1826         dm_dp_create_fake_mst_encoders(adev);
1827
1828         /* TODO: Add_display_info? */
1829
1830         /* TODO use dynamic cursor width */
1831         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1832         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1833
1834         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1835                 DRM_ERROR(
1836                 "amdgpu: failed to initialize sw for display support.\n");
1837                 goto error;
1838         }
1839
1840 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1841         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1842         if (!adev->dm.secure_display_ctxs)
1843                 DRM_ERROR("amdgpu: failed to initialize secure display contexts.\n");
1844 #endif
1845
1846         DRM_DEBUG_DRIVER("KMS initialized.\n");
1847
1848         return 0;
1849 error:
1850         amdgpu_dm_fini(adev);
1851
1852         return -EINVAL;
1853 }
1854
1855 static int amdgpu_dm_early_fini(void *handle)
1856 {
1857         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1858
1859         amdgpu_dm_audio_fini(adev);
1860
1861         return 0;
1862 }
1863
1864 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1865 {
1866         int i;
1867
1868         if (adev->dm.vblank_control_workqueue) {
1869                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1870                 adev->dm.vblank_control_workqueue = NULL;
1871         }
1872
1873         amdgpu_dm_destroy_drm_device(&adev->dm);
1874
1875 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1876         if (adev->dm.secure_display_ctxs) {
1877                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1878                         if (adev->dm.secure_display_ctxs[i].crtc) {
1879                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1880                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1881                         }
1882                 }
1883                 kfree(adev->dm.secure_display_ctxs);
1884                 adev->dm.secure_display_ctxs = NULL;
1885         }
1886 #endif
1887         if (adev->dm.hdcp_workqueue) {
1888                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1889                 adev->dm.hdcp_workqueue = NULL;
1890         }
1891
1892         if (adev->dm.dc)
1893                 dc_deinit_callbacks(adev->dm.dc);
1894
1895         if (adev->dm.dc)
1896                 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1897
1898         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1899                 kfree(adev->dm.dmub_notify);
1900                 adev->dm.dmub_notify = NULL;
1901                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1902                 adev->dm.delayed_hpd_wq = NULL;
1903         }
1904
1905         if (adev->dm.dmub_bo)
1906                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1907                                       &adev->dm.dmub_bo_gpu_addr,
1908                                       &adev->dm.dmub_bo_cpu_addr);
1909
1910         if (adev->dm.hpd_rx_offload_wq) {
1911                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1912                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1913                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1914                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1915                         }
1916                 }
1917
1918                 kfree(adev->dm.hpd_rx_offload_wq);
1919                 adev->dm.hpd_rx_offload_wq = NULL;
1920         }
1921
1922         /* DC Destroy TODO: Replace destroy DAL */
1923         if (adev->dm.dc)
1924                 dc_destroy(&adev->dm.dc);
1925         /*
1926          * TODO: pageflip, vlank interrupt
1927          *
1928          * amdgpu_dm_irq_fini(adev);
1929          */
1930
1931         if (adev->dm.cgs_device) {
1932                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1933                 adev->dm.cgs_device = NULL;
1934         }
1935         if (adev->dm.freesync_module) {
1936                 mod_freesync_destroy(adev->dm.freesync_module);
1937                 adev->dm.freesync_module = NULL;
1938         }
1939
1940         mutex_destroy(&adev->dm.audio_lock);
1941         mutex_destroy(&adev->dm.dc_lock);
1942         mutex_destroy(&adev->dm.dpia_aux_lock);
1943 }
1944
1945 static int load_dmcu_fw(struct amdgpu_device *adev)
1946 {
1947         const char *fw_name_dmcu = NULL;
1948         int r;
1949         const struct dmcu_firmware_header_v1_0 *hdr;
1950
1951         switch (adev->asic_type) {
1952 #if defined(CONFIG_DRM_AMD_DC_SI)
1953         case CHIP_TAHITI:
1954         case CHIP_PITCAIRN:
1955         case CHIP_VERDE:
1956         case CHIP_OLAND:
1957 #endif
1958         case CHIP_BONAIRE:
1959         case CHIP_HAWAII:
1960         case CHIP_KAVERI:
1961         case CHIP_KABINI:
1962         case CHIP_MULLINS:
1963         case CHIP_TONGA:
1964         case CHIP_FIJI:
1965         case CHIP_CARRIZO:
1966         case CHIP_STONEY:
1967         case CHIP_POLARIS11:
1968         case CHIP_POLARIS10:
1969         case CHIP_POLARIS12:
1970         case CHIP_VEGAM:
1971         case CHIP_VEGA10:
1972         case CHIP_VEGA12:
1973         case CHIP_VEGA20:
1974                 return 0;
1975         case CHIP_NAVI12:
1976                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1977                 break;
1978         case CHIP_RAVEN:
1979                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1980                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1981                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1982                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1983                 else
1984                         return 0;
1985                 break;
1986         default:
1987                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1988                 case IP_VERSION(2, 0, 2):
1989                 case IP_VERSION(2, 0, 3):
1990                 case IP_VERSION(2, 0, 0):
1991                 case IP_VERSION(2, 1, 0):
1992                 case IP_VERSION(3, 0, 0):
1993                 case IP_VERSION(3, 0, 2):
1994                 case IP_VERSION(3, 0, 3):
1995                 case IP_VERSION(3, 0, 1):
1996                 case IP_VERSION(3, 1, 2):
1997                 case IP_VERSION(3, 1, 3):
1998                 case IP_VERSION(3, 1, 4):
1999                 case IP_VERSION(3, 1, 5):
2000                 case IP_VERSION(3, 1, 6):
2001                 case IP_VERSION(3, 2, 0):
2002                 case IP_VERSION(3, 2, 1):
2003                 case IP_VERSION(3, 5, 0):
2004                         return 0;
2005                 default:
2006                         break;
2007                 }
2008                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2009                 return -EINVAL;
2010         }
2011
2012         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2013                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2014                 return 0;
2015         }
2016
2017         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2018         if (r == -ENODEV) {
2019                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2020                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2021                 adev->dm.fw_dmcu = NULL;
2022                 return 0;
2023         }
2024         if (r) {
2025                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2026                         fw_name_dmcu);
2027                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2028                 return r;
2029         }
2030
2031         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2032         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2033         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2034         adev->firmware.fw_size +=
2035                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2036
2037         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2038         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2039         adev->firmware.fw_size +=
2040                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2041
2042         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2043
2044         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2045
2046         return 0;
2047 }
2048
2049 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2050 {
2051         struct amdgpu_device *adev = ctx;
2052
2053         return dm_read_reg(adev->dm.dc->ctx, address);
2054 }
2055
2056 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2057                                      uint32_t value)
2058 {
2059         struct amdgpu_device *adev = ctx;
2060
2061         return dm_write_reg(adev->dm.dc->ctx, address, value);
2062 }
2063
2064 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2065 {
2066         struct dmub_srv_create_params create_params;
2067         struct dmub_srv_region_params region_params;
2068         struct dmub_srv_region_info region_info;
2069         struct dmub_srv_memory_params memory_params;
2070         struct dmub_srv_fb_info *fb_info;
2071         struct dmub_srv *dmub_srv;
2072         const struct dmcub_firmware_header_v1_0 *hdr;
2073         enum dmub_asic dmub_asic;
2074         enum dmub_status status;
2075         int r;
2076
2077         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2078         case IP_VERSION(2, 1, 0):
2079                 dmub_asic = DMUB_ASIC_DCN21;
2080                 break;
2081         case IP_VERSION(3, 0, 0):
2082                 dmub_asic = DMUB_ASIC_DCN30;
2083                 break;
2084         case IP_VERSION(3, 0, 1):
2085                 dmub_asic = DMUB_ASIC_DCN301;
2086                 break;
2087         case IP_VERSION(3, 0, 2):
2088                 dmub_asic = DMUB_ASIC_DCN302;
2089                 break;
2090         case IP_VERSION(3, 0, 3):
2091                 dmub_asic = DMUB_ASIC_DCN303;
2092                 break;
2093         case IP_VERSION(3, 1, 2):
2094         case IP_VERSION(3, 1, 3):
2095                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2096                 break;
2097         case IP_VERSION(3, 1, 4):
2098                 dmub_asic = DMUB_ASIC_DCN314;
2099                 break;
2100         case IP_VERSION(3, 1, 5):
2101                 dmub_asic = DMUB_ASIC_DCN315;
2102                 break;
2103         case IP_VERSION(3, 1, 6):
2104                 dmub_asic = DMUB_ASIC_DCN316;
2105                 break;
2106         case IP_VERSION(3, 2, 0):
2107                 dmub_asic = DMUB_ASIC_DCN32;
2108                 break;
2109         case IP_VERSION(3, 2, 1):
2110                 dmub_asic = DMUB_ASIC_DCN321;
2111                 break;
2112         case IP_VERSION(3, 5, 0):
2113                 dmub_asic = DMUB_ASIC_DCN35;
2114                 break;
2115         default:
2116                 /* ASIC doesn't support DMUB. */
2117                 return 0;
2118         }
2119
2120         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2121         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2122
2123         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2124                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2125                         AMDGPU_UCODE_ID_DMCUB;
2126                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2127                         adev->dm.dmub_fw;
2128                 adev->firmware.fw_size +=
2129                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2130
2131                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2132                          adev->dm.dmcub_fw_version);
2133         }
2134
2135
2136         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2137         dmub_srv = adev->dm.dmub_srv;
2138
2139         if (!dmub_srv) {
2140                 DRM_ERROR("Failed to allocate DMUB service!\n");
2141                 return -ENOMEM;
2142         }
2143
2144         memset(&create_params, 0, sizeof(create_params));
2145         create_params.user_ctx = adev;
2146         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2147         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2148         create_params.asic = dmub_asic;
2149
2150         /* Create the DMUB service. */
2151         status = dmub_srv_create(dmub_srv, &create_params);
2152         if (status != DMUB_STATUS_OK) {
2153                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2154                 return -EINVAL;
2155         }
2156
2157         /* Calculate the size of all the regions for the DMUB service. */
2158         memset(&region_params, 0, sizeof(region_params));
2159
2160         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2161                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2162         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2163         region_params.vbios_size = adev->bios_size;
2164         region_params.fw_bss_data = region_params.bss_data_size ?
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2168         region_params.fw_inst_const =
2169                 adev->dm.dmub_fw->data +
2170                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2171                 PSP_HEADER_BYTES;
2172         region_params.is_mailbox_in_inbox = false;
2173
2174         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2175                                            &region_info);
2176
2177         if (status != DMUB_STATUS_OK) {
2178                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2179                 return -EINVAL;
2180         }
2181
2182         /*
2183          * Allocate a framebuffer based on the total size of all the regions.
2184          * TODO: Move this into GART.
2185          */
2186         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2187                                     AMDGPU_GEM_DOMAIN_VRAM |
2188                                     AMDGPU_GEM_DOMAIN_GTT,
2189                                     &adev->dm.dmub_bo,
2190                                     &adev->dm.dmub_bo_gpu_addr,
2191                                     &adev->dm.dmub_bo_cpu_addr);
2192         if (r)
2193                 return r;
2194
2195         /* Rebase the regions on the framebuffer address. */
2196         memset(&memory_params, 0, sizeof(memory_params));
2197         memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
2198         memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
2199         memory_params.region_info = &region_info;
2200
2201         adev->dm.dmub_fb_info =
2202                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2203         fb_info = adev->dm.dmub_fb_info;
2204
2205         if (!fb_info) {
2206                 DRM_ERROR(
2207                         "Failed to allocate framebuffer info for DMUB service!\n");
2208                 return -ENOMEM;
2209         }
2210
2211         status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
2212         if (status != DMUB_STATUS_OK) {
2213                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2214                 return -EINVAL;
2215         }
2216
2217         return 0;
2218 }
2219
2220 static int dm_sw_init(void *handle)
2221 {
2222         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2223         int r;
2224
2225         r = dm_dmub_sw_init(adev);
2226         if (r)
2227                 return r;
2228
2229         return load_dmcu_fw(adev);
2230 }
2231
2232 static int dm_sw_fini(void *handle)
2233 {
2234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2235
2236         kfree(adev->dm.dmub_fb_info);
2237         adev->dm.dmub_fb_info = NULL;
2238
2239         if (adev->dm.dmub_srv) {
2240                 dmub_srv_destroy(adev->dm.dmub_srv);
2241                 adev->dm.dmub_srv = NULL;
2242         }
2243
2244         amdgpu_ucode_release(&adev->dm.dmub_fw);
2245         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2246
2247         return 0;
2248 }
2249
2250 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2251 {
2252         struct amdgpu_dm_connector *aconnector;
2253         struct drm_connector *connector;
2254         struct drm_connector_list_iter iter;
2255         int ret = 0;
2256
2257         drm_connector_list_iter_begin(dev, &iter);
2258         drm_for_each_connector_iter(connector, &iter) {
2259                 aconnector = to_amdgpu_dm_connector(connector);
2260                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2261                     aconnector->mst_mgr.aux) {
2262                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2263                                          aconnector,
2264                                          aconnector->base.base.id);
2265
2266                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2267                         if (ret < 0) {
2268                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2269                                 aconnector->dc_link->type =
2270                                         dc_connection_single;
2271                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2272                                                                      aconnector->dc_link);
2273                                 break;
2274                         }
2275                 }
2276         }
2277         drm_connector_list_iter_end(&iter);
2278
2279         return ret;
2280 }
2281
2282 static int dm_late_init(void *handle)
2283 {
2284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2285
2286         struct dmcu_iram_parameters params;
2287         unsigned int linear_lut[16];
2288         int i;
2289         struct dmcu *dmcu = NULL;
2290
2291         dmcu = adev->dm.dc->res_pool->dmcu;
2292
2293         for (i = 0; i < 16; i++)
2294                 linear_lut[i] = 0xFFFF * i / 15;
2295
2296         params.set = 0;
2297         params.backlight_ramping_override = false;
2298         params.backlight_ramping_start = 0xCCCC;
2299         params.backlight_ramping_reduction = 0xCCCCCCCC;
2300         params.backlight_lut_array_size = 16;
2301         params.backlight_lut_array = linear_lut;
2302
2303         /* Min backlight level after ABM reduction,  Don't allow below 1%
2304          * 0xFFFF x 0.01 = 0x28F
2305          */
2306         params.min_abm_backlight = 0x28F;
2307         /* In the case where abm is implemented on dmcub,
2308          * dmcu object will be null.
2309          * ABM 2.4 and up are implemented on dmcub.
2310          */
2311         if (dmcu) {
2312                 if (!dmcu_load_iram(dmcu, params))
2313                         return -EINVAL;
2314         } else if (adev->dm.dc->ctx->dmub_srv) {
2315                 struct dc_link *edp_links[MAX_NUM_EDP];
2316                 int edp_num;
2317
2318                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2319                 for (i = 0; i < edp_num; i++) {
2320                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2321                                 return -EINVAL;
2322                 }
2323         }
2324
2325         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2326 }
2327
2328 static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2329 {
2330         int ret;
2331         u8 guid[16];
2332         u64 tmp64;
2333
2334         mutex_lock(&mgr->lock);
2335         if (!mgr->mst_primary)
2336                 goto out_fail;
2337
2338         if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
2339                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2340                 goto out_fail;
2341         }
2342
2343         ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2344                                  DP_MST_EN |
2345                                  DP_UP_REQ_EN |
2346                                  DP_UPSTREAM_IS_SRC);
2347         if (ret < 0) {
2348                 drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n");
2349                 goto out_fail;
2350         }
2351
2352         /* Some hubs forget their guids after they resume */
2353         ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
2354         if (ret != 16) {
2355                 drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n");
2356                 goto out_fail;
2357         }
2358
2359         if (memchr_inv(guid, 0, 16) == NULL) {
2360                 tmp64 = get_jiffies_64();
2361                 memcpy(&guid[0], &tmp64, sizeof(u64));
2362                 memcpy(&guid[8], &tmp64, sizeof(u64));
2363
2364                 ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
2365
2366                 if (ret != 16) {
2367                         drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n");
2368                         goto out_fail;
2369                 }
2370         }
2371
2372         memcpy(mgr->mst_primary->guid, guid, 16);
2373
2374 out_fail:
2375         mutex_unlock(&mgr->lock);
2376 }
2377
2378 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2379 {
2380         struct amdgpu_dm_connector *aconnector;
2381         struct drm_connector *connector;
2382         struct drm_connector_list_iter iter;
2383         struct drm_dp_mst_topology_mgr *mgr;
2384
2385         drm_connector_list_iter_begin(dev, &iter);
2386         drm_for_each_connector_iter(connector, &iter) {
2387                 aconnector = to_amdgpu_dm_connector(connector);
2388                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2389                     aconnector->mst_root)
2390                         continue;
2391
2392                 mgr = &aconnector->mst_mgr;
2393
2394                 if (suspend) {
2395                         drm_dp_mst_topology_mgr_suspend(mgr);
2396                 } else {
2397                         /* if extended timeout is supported in hardware,
2398                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2399                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2400                          */
2401                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2402                         if (!dp_is_lttpr_present(aconnector->dc_link))
2403                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2404
2405                         /* TODO: move resume_mst_branch_status() into drm mst resume again
2406                          * once topology probing work is pulled out from mst resume into mst
2407                          * resume 2nd step. mst resume 2nd step should be called after old
2408                          * state getting restored (i.e. drm_atomic_helper_resume()).
2409                          */
2410                         resume_mst_branch_status(mgr);
2411                 }
2412         }
2413         drm_connector_list_iter_end(&iter);
2414 }
2415
2416 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2417 {
2418         int ret = 0;
2419
2420         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2421          * on window driver dc implementation.
2422          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2423          * should be passed to smu during boot up and resume from s3.
2424          * boot up: dc calculate dcn watermark clock settings within dc_create,
2425          * dcn20_resource_construct
2426          * then call pplib functions below to pass the settings to smu:
2427          * smu_set_watermarks_for_clock_ranges
2428          * smu_set_watermarks_table
2429          * navi10_set_watermarks_table
2430          * smu_write_watermarks_table
2431          *
2432          * For Renoir, clock settings of dcn watermark are also fixed values.
2433          * dc has implemented different flow for window driver:
2434          * dc_hardware_init / dc_set_power_state
2435          * dcn10_init_hw
2436          * notify_wm_ranges
2437          * set_wm_ranges
2438          * -- Linux
2439          * smu_set_watermarks_for_clock_ranges
2440          * renoir_set_watermarks_table
2441          * smu_write_watermarks_table
2442          *
2443          * For Linux,
2444          * dc_hardware_init -> amdgpu_dm_init
2445          * dc_set_power_state --> dm_resume
2446          *
2447          * therefore, this function apply to navi10/12/14 but not Renoir
2448          * *
2449          */
2450         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
2451         case IP_VERSION(2, 0, 2):
2452         case IP_VERSION(2, 0, 0):
2453                 break;
2454         default:
2455                 return 0;
2456         }
2457
2458         ret = amdgpu_dpm_write_watermarks_table(adev);
2459         if (ret) {
2460                 DRM_ERROR("Failed to update WMTABLE!\n");
2461                 return ret;
2462         }
2463
2464         return 0;
2465 }
2466
2467 /**
2468  * dm_hw_init() - Initialize DC device
2469  * @handle: The base driver device containing the amdgpu_dm device.
2470  *
2471  * Initialize the &struct amdgpu_display_manager device. This involves calling
2472  * the initializers of each DM component, then populating the struct with them.
2473  *
2474  * Although the function implies hardware initialization, both hardware and
2475  * software are initialized here. Splitting them out to their relevant init
2476  * hooks is a future TODO item.
2477  *
2478  * Some notable things that are initialized here:
2479  *
2480  * - Display Core, both software and hardware
2481  * - DC modules that we need (freesync and color management)
2482  * - DRM software states
2483  * - Interrupt sources and handlers
2484  * - Vblank support
2485  * - Debug FS entries, if enabled
2486  */
2487 static int dm_hw_init(void *handle)
2488 {
2489         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2490         /* Create DAL display manager */
2491         amdgpu_dm_init(adev);
2492         amdgpu_dm_hpd_init(adev);
2493
2494         return 0;
2495 }
2496
2497 /**
2498  * dm_hw_fini() - Teardown DC device
2499  * @handle: The base driver device containing the amdgpu_dm device.
2500  *
2501  * Teardown components within &struct amdgpu_display_manager that require
2502  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2503  * were loaded. Also flush IRQ workqueues and disable them.
2504  */
2505 static int dm_hw_fini(void *handle)
2506 {
2507         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2508
2509         amdgpu_dm_hpd_fini(adev);
2510
2511         amdgpu_dm_irq_fini(adev);
2512         amdgpu_dm_fini(adev);
2513         return 0;
2514 }
2515
2516
2517 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2518                                  struct dc_state *state, bool enable)
2519 {
2520         enum dc_irq_source irq_source;
2521         struct amdgpu_crtc *acrtc;
2522         int rc = -EBUSY;
2523         int i = 0;
2524
2525         for (i = 0; i < state->stream_count; i++) {
2526                 acrtc = get_crtc_by_otg_inst(
2527                                 adev, state->stream_status[i].primary_otg_inst);
2528
2529                 if (acrtc && state->stream_status[i].plane_count != 0) {
2530                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2531                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2532                         if (rc)
2533                                 DRM_WARN("Failed to %s pflip interrupts\n",
2534                                          enable ? "enable" : "disable");
2535
2536                         if (enable) {
2537                                 if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
2538                                         rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
2539                         } else
2540                                 rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
2541
2542                         if (rc)
2543                                 DRM_WARN("Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
2544
2545                         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
2546                         /* During gpu-reset we disable and then enable vblank irq, so
2547                          * don't use amdgpu_irq_get/put() to avoid refcount change.
2548                          */
2549                         if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
2550                                 DRM_WARN("Failed to %sable vblank interrupt\n", enable ? "en" : "dis");
2551                 }
2552         }
2553
2554 }
2555
2556 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2557 {
2558         struct dc_state *context = NULL;
2559         enum dc_status res = DC_ERROR_UNEXPECTED;
2560         int i;
2561         struct dc_stream_state *del_streams[MAX_PIPES];
2562         int del_streams_count = 0;
2563
2564         memset(del_streams, 0, sizeof(del_streams));
2565
2566         context = dc_create_state(dc);
2567         if (context == NULL)
2568                 goto context_alloc_fail;
2569
2570         dc_resource_state_copy_construct_current(dc, context);
2571
2572         /* First remove from context all streams */
2573         for (i = 0; i < context->stream_count; i++) {
2574                 struct dc_stream_state *stream = context->streams[i];
2575
2576                 del_streams[del_streams_count++] = stream;
2577         }
2578
2579         /* Remove all planes for removed streams and then remove the streams */
2580         for (i = 0; i < del_streams_count; i++) {
2581                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2582                         res = DC_FAIL_DETACH_SURFACES;
2583                         goto fail;
2584                 }
2585
2586                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2587                 if (res != DC_OK)
2588                         goto fail;
2589         }
2590
2591         res = dc_commit_streams(dc, context->streams, context->stream_count);
2592
2593 fail:
2594         dc_release_state(context);
2595
2596 context_alloc_fail:
2597         return res;
2598 }
2599
2600 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2601 {
2602         int i;
2603
2604         if (dm->hpd_rx_offload_wq) {
2605                 for (i = 0; i < dm->dc->caps.max_links; i++)
2606                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2607         }
2608 }
2609
2610 static int dm_suspend(void *handle)
2611 {
2612         struct amdgpu_device *adev = handle;
2613         struct amdgpu_display_manager *dm = &adev->dm;
2614         int ret = 0;
2615
2616         if (amdgpu_in_reset(adev)) {
2617                 mutex_lock(&dm->dc_lock);
2618
2619                 dc_allow_idle_optimizations(adev->dm.dc, false);
2620
2621                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2622
2623                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2624
2625                 amdgpu_dm_commit_zero_streams(dm->dc);
2626
2627                 amdgpu_dm_irq_suspend(adev);
2628
2629                 hpd_rx_irq_work_suspend(dm);
2630
2631                 return ret;
2632         }
2633
2634         WARN_ON(adev->dm.cached_state);
2635         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2636         if (IS_ERR(adev->dm.cached_state))
2637                 return PTR_ERR(adev->dm.cached_state);
2638
2639         s3_handle_mst(adev_to_drm(adev), true);
2640
2641         amdgpu_dm_irq_suspend(adev);
2642
2643         hpd_rx_irq_work_suspend(dm);
2644
2645         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2646
2647         return 0;
2648 }
2649
2650 struct amdgpu_dm_connector *
2651 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2652                                              struct drm_crtc *crtc)
2653 {
2654         u32 i;
2655         struct drm_connector_state *new_con_state;
2656         struct drm_connector *connector;
2657         struct drm_crtc *crtc_from_state;
2658
2659         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2660                 crtc_from_state = new_con_state->crtc;
2661
2662                 if (crtc_from_state == crtc)
2663                         return to_amdgpu_dm_connector(connector);
2664         }
2665
2666         return NULL;
2667 }
2668
2669 static void emulated_link_detect(struct dc_link *link)
2670 {
2671         struct dc_sink_init_data sink_init_data = { 0 };
2672         struct display_sink_capability sink_caps = { 0 };
2673         enum dc_edid_status edid_status;
2674         struct dc_context *dc_ctx = link->ctx;
2675         struct drm_device *dev = adev_to_drm(dc_ctx->driver_context);
2676         struct dc_sink *sink = NULL;
2677         struct dc_sink *prev_sink = NULL;
2678
2679         link->type = dc_connection_none;
2680         prev_sink = link->local_sink;
2681
2682         if (prev_sink)
2683                 dc_sink_release(prev_sink);
2684
2685         switch (link->connector_signal) {
2686         case SIGNAL_TYPE_HDMI_TYPE_A: {
2687                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2688                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2689                 break;
2690         }
2691
2692         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2693                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2694                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2695                 break;
2696         }
2697
2698         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2699                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2700                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2701                 break;
2702         }
2703
2704         case SIGNAL_TYPE_LVDS: {
2705                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2706                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2707                 break;
2708         }
2709
2710         case SIGNAL_TYPE_EDP: {
2711                 sink_caps.transaction_type =
2712                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2713                 sink_caps.signal = SIGNAL_TYPE_EDP;
2714                 break;
2715         }
2716
2717         case SIGNAL_TYPE_DISPLAY_PORT: {
2718                 sink_caps.transaction_type =
2719                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2720                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2721                 break;
2722         }
2723
2724         default:
2725                 drm_err(dev, "Invalid connector type! signal:%d\n",
2726                         link->connector_signal);
2727                 return;
2728         }
2729
2730         sink_init_data.link = link;
2731         sink_init_data.sink_signal = sink_caps.signal;
2732
2733         sink = dc_sink_create(&sink_init_data);
2734         if (!sink) {
2735                 drm_err(dev, "Failed to create sink!\n");
2736                 return;
2737         }
2738
2739         /* dc_sink_create returns a new reference */
2740         link->local_sink = sink;
2741
2742         edid_status = dm_helpers_read_local_edid(
2743                         link->ctx,
2744                         link,
2745                         sink);
2746
2747         if (edid_status != EDID_OK)
2748                 drm_err(dev, "Failed to read EDID\n");
2749
2750 }
2751
2752 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2753                                      struct amdgpu_display_manager *dm)
2754 {
2755         struct {
2756                 struct dc_surface_update surface_updates[MAX_SURFACES];
2757                 struct dc_plane_info plane_infos[MAX_SURFACES];
2758                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2759                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2760                 struct dc_stream_update stream_update;
2761         } *bundle;
2762         int k, m;
2763
2764         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2765
2766         if (!bundle) {
2767                 drm_err(dm->ddev, "Failed to allocate update bundle\n");
2768                 goto cleanup;
2769         }
2770
2771         for (k = 0; k < dc_state->stream_count; k++) {
2772                 bundle->stream_update.stream = dc_state->streams[k];
2773
2774                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2775                         bundle->surface_updates[m].surface =
2776                                 dc_state->stream_status->plane_states[m];
2777                         bundle->surface_updates[m].surface->force_full_update =
2778                                 true;
2779                 }
2780
2781                 update_planes_and_stream_adapter(dm->dc,
2782                                          UPDATE_TYPE_FULL,
2783                                          dc_state->stream_status->plane_count,
2784                                          dc_state->streams[k],
2785                                          &bundle->stream_update,
2786                                          bundle->surface_updates);
2787         }
2788
2789 cleanup:
2790         kfree(bundle);
2791 }
2792
2793 static int dm_resume(void *handle)
2794 {
2795         struct amdgpu_device *adev = handle;
2796         struct drm_device *ddev = adev_to_drm(adev);
2797         struct amdgpu_display_manager *dm = &adev->dm;
2798         struct amdgpu_dm_connector *aconnector;
2799         struct drm_connector *connector;
2800         struct drm_connector_list_iter iter;
2801         struct drm_crtc *crtc;
2802         struct drm_crtc_state *new_crtc_state;
2803         struct dm_crtc_state *dm_new_crtc_state;
2804         struct drm_plane *plane;
2805         struct drm_plane_state *new_plane_state;
2806         struct dm_plane_state *dm_new_plane_state;
2807         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2808         enum dc_connection_type new_connection_type = dc_connection_none;
2809         struct dc_state *dc_state;
2810         int i, r, j, ret;
2811         bool need_hotplug = false;
2812
2813         if (dm->dc->caps.ips_support) {
2814                 dc_dmub_srv_exit_low_power_state(dm->dc);
2815         }
2816
2817         if (amdgpu_in_reset(adev)) {
2818                 dc_state = dm->cached_dc_state;
2819
2820                 /*
2821                  * The dc->current_state is backed up into dm->cached_dc_state
2822                  * before we commit 0 streams.
2823                  *
2824                  * DC will clear link encoder assignments on the real state
2825                  * but the changes won't propagate over to the copy we made
2826                  * before the 0 streams commit.
2827                  *
2828                  * DC expects that link encoder assignments are *not* valid
2829                  * when committing a state, so as a workaround we can copy
2830                  * off of the current state.
2831                  *
2832                  * We lose the previous assignments, but we had already
2833                  * commit 0 streams anyway.
2834                  */
2835                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2836
2837                 r = dm_dmub_hw_init(adev);
2838                 if (r)
2839                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2840
2841                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2842
2843                 dc_resume(dm->dc);
2844
2845                 amdgpu_dm_irq_resume_early(adev);
2846
2847                 for (i = 0; i < dc_state->stream_count; i++) {
2848                         dc_state->streams[i]->mode_changed = true;
2849                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2850                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2851                                         = 0xffffffff;
2852                         }
2853                 }
2854
2855                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2856                         amdgpu_dm_outbox_init(adev);
2857                         dc_enable_dmub_outbox(adev->dm.dc);
2858                 }
2859
2860                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2861
2862                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2863
2864                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2865
2866                 dc_release_state(dm->cached_dc_state);
2867                 dm->cached_dc_state = NULL;
2868
2869                 amdgpu_dm_irq_resume_late(adev);
2870
2871                 mutex_unlock(&dm->dc_lock);
2872
2873                 return 0;
2874         }
2875         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2876         dc_release_state(dm_state->context);
2877         dm_state->context = dc_create_state(dm->dc);
2878         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2879         dc_resource_state_construct(dm->dc, dm_state->context);
2880
2881         /* Before powering on DC we need to re-initialize DMUB. */
2882         dm_dmub_hw_resume(adev);
2883
2884         /* Re-enable outbox interrupts for DPIA. */
2885         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2886                 amdgpu_dm_outbox_init(adev);
2887                 dc_enable_dmub_outbox(adev->dm.dc);
2888         }
2889
2890         /* power on hardware */
2891         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2892
2893         /* program HPD filter */
2894         dc_resume(dm->dc);
2895
2896         /*
2897          * early enable HPD Rx IRQ, should be done before set mode as short
2898          * pulse interrupts are used for MST
2899          */
2900         amdgpu_dm_irq_resume_early(adev);
2901
2902         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2903         s3_handle_mst(ddev, false);
2904
2905         /* Do detection*/
2906         drm_connector_list_iter_begin(ddev, &iter);
2907         drm_for_each_connector_iter(connector, &iter) {
2908                 aconnector = to_amdgpu_dm_connector(connector);
2909
2910                 if (!aconnector->dc_link)
2911                         continue;
2912
2913                 /*
2914                  * this is the case when traversing through already created end sink
2915                  * MST connectors, should be skipped
2916                  */
2917                 if (aconnector && aconnector->mst_root)
2918                         continue;
2919
2920                 mutex_lock(&aconnector->hpd_lock);
2921                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2922                         DRM_ERROR("KMS: Failed to detect connector\n");
2923
2924                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2925                         emulated_link_detect(aconnector->dc_link);
2926                 } else {
2927                         mutex_lock(&dm->dc_lock);
2928                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2929                         mutex_unlock(&dm->dc_lock);
2930                 }
2931
2932                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2933                         aconnector->fake_enable = false;
2934
2935                 if (aconnector->dc_sink)
2936                         dc_sink_release(aconnector->dc_sink);
2937                 aconnector->dc_sink = NULL;
2938                 amdgpu_dm_update_connector_after_detect(aconnector);
2939                 mutex_unlock(&aconnector->hpd_lock);
2940         }
2941         drm_connector_list_iter_end(&iter);
2942
2943         /* Force mode set in atomic commit */
2944         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2945                 new_crtc_state->active_changed = true;
2946
2947         /*
2948          * atomic_check is expected to create the dc states. We need to release
2949          * them here, since they were duplicated as part of the suspend
2950          * procedure.
2951          */
2952         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2953                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2954                 if (dm_new_crtc_state->stream) {
2955                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2956                         dc_stream_release(dm_new_crtc_state->stream);
2957                         dm_new_crtc_state->stream = NULL;
2958                 }
2959         }
2960
2961         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2962                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2963                 if (dm_new_plane_state->dc_state) {
2964                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2965                         dc_plane_state_release(dm_new_plane_state->dc_state);
2966                         dm_new_plane_state->dc_state = NULL;
2967                 }
2968         }
2969
2970         drm_atomic_helper_resume(ddev, dm->cached_state);
2971
2972         dm->cached_state = NULL;
2973
2974         /* Do mst topology probing after resuming cached state*/
2975         drm_connector_list_iter_begin(ddev, &iter);
2976         drm_for_each_connector_iter(connector, &iter) {
2977                 aconnector = to_amdgpu_dm_connector(connector);
2978                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2979                     aconnector->mst_root)
2980                         continue;
2981
2982                 ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true);
2983
2984                 if (ret < 0) {
2985                         dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2986                                         aconnector->dc_link);
2987                         need_hotplug = true;
2988                 }
2989         }
2990         drm_connector_list_iter_end(&iter);
2991
2992         if (need_hotplug)
2993                 drm_kms_helper_hotplug_event(ddev);
2994
2995         amdgpu_dm_irq_resume_late(adev);
2996
2997         amdgpu_dm_smu_write_watermarks_table(adev);
2998
2999         return 0;
3000 }
3001
3002 /**
3003  * DOC: DM Lifecycle
3004  *
3005  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
3006  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
3007  * the base driver's device list to be initialized and torn down accordingly.
3008  *
3009  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
3010  */
3011
3012 static const struct amd_ip_funcs amdgpu_dm_funcs = {
3013         .name = "dm",
3014         .early_init = dm_early_init,
3015         .late_init = dm_late_init,
3016         .sw_init = dm_sw_init,
3017         .sw_fini = dm_sw_fini,
3018         .early_fini = amdgpu_dm_early_fini,
3019         .hw_init = dm_hw_init,
3020         .hw_fini = dm_hw_fini,
3021         .suspend = dm_suspend,
3022         .resume = dm_resume,
3023         .is_idle = dm_is_idle,
3024         .wait_for_idle = dm_wait_for_idle,
3025         .check_soft_reset = dm_check_soft_reset,
3026         .soft_reset = dm_soft_reset,
3027         .set_clockgating_state = dm_set_clockgating_state,
3028         .set_powergating_state = dm_set_powergating_state,
3029 };
3030
3031 const struct amdgpu_ip_block_version dm_ip_block = {
3032         .type = AMD_IP_BLOCK_TYPE_DCE,
3033         .major = 1,
3034         .minor = 0,
3035         .rev = 0,
3036         .funcs = &amdgpu_dm_funcs,
3037 };
3038
3039
3040 /**
3041  * DOC: atomic
3042  *
3043  * *WIP*
3044  */
3045
3046 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
3047         .fb_create = amdgpu_display_user_framebuffer_create,
3048         .get_format_info = amdgpu_dm_plane_get_format_info,
3049         .atomic_check = amdgpu_dm_atomic_check,
3050         .atomic_commit = drm_atomic_helper_commit,
3051 };
3052
3053 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
3054         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
3055         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3056 };
3057
3058 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3059 {
3060         struct amdgpu_dm_backlight_caps *caps;
3061         struct drm_connector *conn_base;
3062         struct amdgpu_device *adev;
3063         struct drm_luminance_range_info *luminance_range;
3064
3065         if (aconnector->bl_idx == -1 ||
3066             aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
3067                 return;
3068
3069         conn_base = &aconnector->base;
3070         adev = drm_to_adev(conn_base->dev);
3071
3072         caps = &adev->dm.backlight_caps[aconnector->bl_idx];
3073         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3074         caps->aux_support = false;
3075
3076         if (caps->ext_caps->bits.oled == 1
3077             /*
3078              * ||
3079              * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3080              * caps->ext_caps->bits.hdr_aux_backlight_control == 1
3081              */)
3082                 caps->aux_support = true;
3083
3084         if (amdgpu_backlight == 0)
3085                 caps->aux_support = false;
3086         else if (amdgpu_backlight == 1)
3087                 caps->aux_support = true;
3088
3089         luminance_range = &conn_base->display_info.luminance_range;
3090
3091         if (luminance_range->max_luminance) {
3092                 caps->aux_min_input_signal = luminance_range->min_luminance;
3093                 caps->aux_max_input_signal = luminance_range->max_luminance;
3094         } else {
3095                 caps->aux_min_input_signal = 0;
3096                 caps->aux_max_input_signal = 512;
3097         }
3098 }
3099
3100 void amdgpu_dm_update_connector_after_detect(
3101                 struct amdgpu_dm_connector *aconnector)
3102 {
3103         struct drm_connector *connector = &aconnector->base;
3104         struct drm_device *dev = connector->dev;
3105         struct dc_sink *sink;
3106
3107         /* MST handled by drm_mst framework */
3108         if (aconnector->mst_mgr.mst_state == true)
3109                 return;
3110
3111         sink = aconnector->dc_link->local_sink;
3112         if (sink)
3113                 dc_sink_retain(sink);
3114
3115         /*
3116          * Edid mgmt connector gets first update only in mode_valid hook and then
3117          * the connector sink is set to either fake or physical sink depends on link status.
3118          * Skip if already done during boot.
3119          */
3120         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3121                         && aconnector->dc_em_sink) {
3122
3123                 /*
3124                  * For S3 resume with headless use eml_sink to fake stream
3125                  * because on resume connector->sink is set to NULL
3126                  */
3127                 mutex_lock(&dev->mode_config.mutex);
3128
3129                 if (sink) {
3130                         if (aconnector->dc_sink) {
3131                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3132                                 /*
3133                                  * retain and release below are used to
3134                                  * bump up refcount for sink because the link doesn't point
3135                                  * to it anymore after disconnect, so on next crtc to connector
3136                                  * reshuffle by UMD we will get into unwanted dc_sink release
3137                                  */
3138                                 dc_sink_release(aconnector->dc_sink);
3139                         }
3140                         aconnector->dc_sink = sink;
3141                         dc_sink_retain(aconnector->dc_sink);
3142                         amdgpu_dm_update_freesync_caps(connector,
3143                                         aconnector->edid);
3144                 } else {
3145                         amdgpu_dm_update_freesync_caps(connector, NULL);
3146                         if (!aconnector->dc_sink) {
3147                                 aconnector->dc_sink = aconnector->dc_em_sink;
3148                                 dc_sink_retain(aconnector->dc_sink);
3149                         }
3150                 }
3151
3152                 mutex_unlock(&dev->mode_config.mutex);
3153
3154                 if (sink)
3155                         dc_sink_release(sink);
3156                 return;
3157         }
3158
3159         /*
3160          * TODO: temporary guard to look for proper fix
3161          * if this sink is MST sink, we should not do anything
3162          */
3163         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3164                 dc_sink_release(sink);
3165                 return;
3166         }
3167
3168         if (aconnector->dc_sink == sink) {
3169                 /*
3170                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3171                  * Do nothing!!
3172                  */
3173                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3174                                 aconnector->connector_id);
3175                 if (sink)
3176                         dc_sink_release(sink);
3177                 return;
3178         }
3179
3180         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3181                 aconnector->connector_id, aconnector->dc_sink, sink);
3182
3183         mutex_lock(&dev->mode_config.mutex);
3184
3185         /*
3186          * 1. Update status of the drm connector
3187          * 2. Send an event and let userspace tell us what to do
3188          */
3189         if (sink) {
3190                 /*
3191                  * TODO: check if we still need the S3 mode update workaround.
3192                  * If yes, put it here.
3193                  */
3194                 if (aconnector->dc_sink) {
3195                         amdgpu_dm_update_freesync_caps(connector, NULL);
3196                         dc_sink_release(aconnector->dc_sink);
3197                 }
3198
3199                 aconnector->dc_sink = sink;
3200                 dc_sink_retain(aconnector->dc_sink);
3201                 if (sink->dc_edid.length == 0) {
3202                         aconnector->edid = NULL;
3203                         if (aconnector->dc_link->aux_mode) {
3204                                 drm_dp_cec_unset_edid(
3205                                         &aconnector->dm_dp_aux.aux);
3206                         }
3207                 } else {
3208                         aconnector->edid =
3209                                 (struct edid *)sink->dc_edid.raw_edid;
3210
3211                         if (aconnector->dc_link->aux_mode)
3212                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3213                                                     aconnector->edid);
3214                 }
3215
3216                 if (!aconnector->timing_requested) {
3217                         aconnector->timing_requested =
3218                                 kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3219                         if (!aconnector->timing_requested)
3220                                 drm_err(dev,
3221                                         "failed to create aconnector->requested_timing\n");
3222                 }
3223
3224                 drm_connector_update_edid_property(connector, aconnector->edid);
3225                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3226                 update_connector_ext_caps(aconnector);
3227         } else {
3228                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3229                 amdgpu_dm_update_freesync_caps(connector, NULL);
3230                 drm_connector_update_edid_property(connector, NULL);
3231                 aconnector->num_modes = 0;
3232                 dc_sink_release(aconnector->dc_sink);
3233                 aconnector->dc_sink = NULL;
3234                 aconnector->edid = NULL;
3235                 kfree(aconnector->timing_requested);
3236                 aconnector->timing_requested = NULL;
3237                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3238                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3239                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3240         }
3241
3242         mutex_unlock(&dev->mode_config.mutex);
3243
3244         update_subconnector_property(aconnector);
3245
3246         if (sink)
3247                 dc_sink_release(sink);
3248 }
3249
3250 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3251 {
3252         struct drm_connector *connector = &aconnector->base;
3253         struct drm_device *dev = connector->dev;
3254         enum dc_connection_type new_connection_type = dc_connection_none;
3255         struct amdgpu_device *adev = drm_to_adev(dev);
3256         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3257         bool ret = false;
3258
3259         if (adev->dm.disable_hpd_irq)
3260                 return;
3261
3262         /*
3263          * In case of failure or MST no need to update connector status or notify the OS
3264          * since (for MST case) MST does this in its own context.
3265          */
3266         mutex_lock(&aconnector->hpd_lock);
3267
3268         if (adev->dm.hdcp_workqueue) {
3269                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3270                 dm_con_state->update_hdcp = true;
3271         }
3272         if (aconnector->fake_enable)
3273                 aconnector->fake_enable = false;
3274
3275         aconnector->timing_changed = false;
3276
3277         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3278                 DRM_ERROR("KMS: Failed to detect connector\n");
3279
3280         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3281                 emulated_link_detect(aconnector->dc_link);
3282
3283                 drm_modeset_lock_all(dev);
3284                 dm_restore_drm_connector_state(dev, connector);
3285                 drm_modeset_unlock_all(dev);
3286
3287                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3288                         drm_kms_helper_connector_hotplug_event(connector);
3289         } else {
3290                 mutex_lock(&adev->dm.dc_lock);
3291                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3292                 mutex_unlock(&adev->dm.dc_lock);
3293                 if (ret) {
3294                         amdgpu_dm_update_connector_after_detect(aconnector);
3295
3296                         drm_modeset_lock_all(dev);
3297                         dm_restore_drm_connector_state(dev, connector);
3298                         drm_modeset_unlock_all(dev);
3299
3300                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3301                                 drm_kms_helper_connector_hotplug_event(connector);
3302                 }
3303         }
3304         mutex_unlock(&aconnector->hpd_lock);
3305
3306 }
3307
3308 static void handle_hpd_irq(void *param)
3309 {
3310         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3311
3312         handle_hpd_irq_helper(aconnector);
3313
3314 }
3315
3316 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3317                                                         union hpd_irq_data hpd_irq_data)
3318 {
3319         struct hpd_rx_irq_offload_work *offload_work =
3320                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3321
3322         if (!offload_work) {
3323                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3324                 return;
3325         }
3326
3327         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3328         offload_work->data = hpd_irq_data;
3329         offload_work->offload_wq = offload_wq;
3330
3331         queue_work(offload_wq->wq, &offload_work->work);
3332         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3333 }
3334
3335 static void handle_hpd_rx_irq(void *param)
3336 {
3337         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3338         struct drm_connector *connector = &aconnector->base;
3339         struct drm_device *dev = connector->dev;
3340         struct dc_link *dc_link = aconnector->dc_link;
3341         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3342         bool result = false;
3343         enum dc_connection_type new_connection_type = dc_connection_none;
3344         struct amdgpu_device *adev = drm_to_adev(dev);
3345         union hpd_irq_data hpd_irq_data;
3346         bool link_loss = false;
3347         bool has_left_work = false;
3348         int idx = dc_link->link_index;
3349         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3350
3351         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3352
3353         if (adev->dm.disable_hpd_irq)
3354                 return;
3355
3356         /*
3357          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3358          * conflict, after implement i2c helper, this mutex should be
3359          * retired.
3360          */
3361         mutex_lock(&aconnector->hpd_lock);
3362
3363         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3364                                                 &link_loss, true, &has_left_work);
3365
3366         if (!has_left_work)
3367                 goto out;
3368
3369         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3370                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3371                 goto out;
3372         }
3373
3374         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3375                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3376                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3377                         bool skip = false;
3378
3379                         /*
3380                          * DOWN_REP_MSG_RDY is also handled by polling method
3381                          * mgr->cbs->poll_hpd_irq()
3382                          */
3383                         spin_lock(&offload_wq->offload_lock);
3384                         skip = offload_wq->is_handling_mst_msg_rdy_event;
3385
3386                         if (!skip)
3387                                 offload_wq->is_handling_mst_msg_rdy_event = true;
3388
3389                         spin_unlock(&offload_wq->offload_lock);
3390
3391                         if (!skip)
3392                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3393
3394                         goto out;
3395                 }
3396
3397                 if (link_loss) {
3398                         bool skip = false;
3399
3400                         spin_lock(&offload_wq->offload_lock);
3401                         skip = offload_wq->is_handling_link_loss;
3402
3403                         if (!skip)
3404                                 offload_wq->is_handling_link_loss = true;
3405
3406                         spin_unlock(&offload_wq->offload_lock);
3407
3408                         if (!skip)
3409                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3410
3411                         goto out;
3412                 }
3413         }
3414
3415 out:
3416         if (result && !is_mst_root_connector) {
3417                 /* Downstream Port status changed. */
3418                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3419                         DRM_ERROR("KMS: Failed to detect connector\n");
3420
3421                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3422                         emulated_link_detect(dc_link);
3423
3424                         if (aconnector->fake_enable)
3425                                 aconnector->fake_enable = false;
3426
3427                         amdgpu_dm_update_connector_after_detect(aconnector);
3428
3429
3430                         drm_modeset_lock_all(dev);
3431                         dm_restore_drm_connector_state(dev, connector);
3432                         drm_modeset_unlock_all(dev);
3433
3434                         drm_kms_helper_connector_hotplug_event(connector);
3435                 } else {
3436                         bool ret = false;
3437
3438                         mutex_lock(&adev->dm.dc_lock);
3439                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3440                         mutex_unlock(&adev->dm.dc_lock);
3441
3442                         if (ret) {
3443                                 if (aconnector->fake_enable)
3444                                         aconnector->fake_enable = false;
3445
3446                                 amdgpu_dm_update_connector_after_detect(aconnector);
3447
3448                                 drm_modeset_lock_all(dev);
3449                                 dm_restore_drm_connector_state(dev, connector);
3450                                 drm_modeset_unlock_all(dev);
3451
3452                                 drm_kms_helper_connector_hotplug_event(connector);
3453                         }
3454                 }
3455         }
3456         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3457                 if (adev->dm.hdcp_workqueue)
3458                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3459         }
3460
3461         if (dc_link->type != dc_connection_mst_branch)
3462                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3463
3464         mutex_unlock(&aconnector->hpd_lock);
3465 }
3466
3467 static void register_hpd_handlers(struct amdgpu_device *adev)
3468 {
3469         struct drm_device *dev = adev_to_drm(adev);
3470         struct drm_connector *connector;
3471         struct amdgpu_dm_connector *aconnector;
3472         const struct dc_link *dc_link;
3473         struct dc_interrupt_params int_params = {0};
3474
3475         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3476         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3477
3478         list_for_each_entry(connector,
3479                         &dev->mode_config.connector_list, head) {
3480
3481                 aconnector = to_amdgpu_dm_connector(connector);
3482                 dc_link = aconnector->dc_link;
3483
3484                 if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
3485                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3486                         int_params.irq_source = dc_link->irq_source_hpd;
3487
3488                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3489                                         handle_hpd_irq,
3490                                         (void *) aconnector);
3491                 }
3492
3493                 if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
3494
3495                         /* Also register for DP short pulse (hpd_rx). */
3496                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3497                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3498
3499                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3500                                         handle_hpd_rx_irq,
3501                                         (void *) aconnector);
3502                 }
3503
3504                 if (adev->dm.hpd_rx_offload_wq)
3505                         adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3506                                 aconnector;
3507         }
3508 }
3509
3510 #if defined(CONFIG_DRM_AMD_DC_SI)
3511 /* Register IRQ sources and initialize IRQ callbacks */
3512 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3513 {
3514         struct dc *dc = adev->dm.dc;
3515         struct common_irq_params *c_irq_params;
3516         struct dc_interrupt_params int_params = {0};
3517         int r;
3518         int i;
3519         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3520
3521         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3522         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3523
3524         /*
3525          * Actions of amdgpu_irq_add_id():
3526          * 1. Register a set() function with base driver.
3527          *    Base driver will call set() function to enable/disable an
3528          *    interrupt in DC hardware.
3529          * 2. Register amdgpu_dm_irq_handler().
3530          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3531          *    coming from DC hardware.
3532          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3533          *    for acknowledging and handling.
3534          */
3535
3536         /* Use VBLANK interrupt */
3537         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3538                 r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
3539                 if (r) {
3540                         DRM_ERROR("Failed to add crtc irq id!\n");
3541                         return r;
3542                 }
3543
3544                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3545                 int_params.irq_source =
3546                         dc_interrupt_to_irq_source(dc, i + 1, 0);
3547
3548                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3549
3550                 c_irq_params->adev = adev;
3551                 c_irq_params->irq_src = int_params.irq_source;
3552
3553                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3554                                 dm_crtc_high_irq, c_irq_params);
3555         }
3556
3557         /* Use GRPH_PFLIP interrupt */
3558         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3559                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3560                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3561                 if (r) {
3562                         DRM_ERROR("Failed to add page flip irq id!\n");
3563                         return r;
3564                 }
3565
3566                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3567                 int_params.irq_source =
3568                         dc_interrupt_to_irq_source(dc, i, 0);
3569
3570                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3571
3572                 c_irq_params->adev = adev;
3573                 c_irq_params->irq_src = int_params.irq_source;
3574
3575                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3576                                 dm_pflip_high_irq, c_irq_params);
3577
3578         }
3579
3580         /* HPD */
3581         r = amdgpu_irq_add_id(adev, client_id,
3582                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3583         if (r) {
3584                 DRM_ERROR("Failed to add hpd irq id!\n");
3585                 return r;
3586         }
3587
3588         register_hpd_handlers(adev);
3589
3590         return 0;
3591 }
3592 #endif
3593
3594 /* Register IRQ sources and initialize IRQ callbacks */
3595 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3596 {
3597         struct dc *dc = adev->dm.dc;
3598         struct common_irq_params *c_irq_params;
3599         struct dc_interrupt_params int_params = {0};
3600         int r;
3601         int i;
3602         unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3603
3604         if (adev->family >= AMDGPU_FAMILY_AI)
3605                 client_id = SOC15_IH_CLIENTID_DCE;
3606
3607         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3608         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3609
3610         /*
3611          * Actions of amdgpu_irq_add_id():
3612          * 1. Register a set() function with base driver.
3613          *    Base driver will call set() function to enable/disable an
3614          *    interrupt in DC hardware.
3615          * 2. Register amdgpu_dm_irq_handler().
3616          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3617          *    coming from DC hardware.
3618          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3619          *    for acknowledging and handling.
3620          */
3621
3622         /* Use VBLANK interrupt */
3623         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3624                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3625                 if (r) {
3626                         DRM_ERROR("Failed to add crtc irq id!\n");
3627                         return r;
3628                 }
3629
3630                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3631                 int_params.irq_source =
3632                         dc_interrupt_to_irq_source(dc, i, 0);
3633
3634                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3635
3636                 c_irq_params->adev = adev;
3637                 c_irq_params->irq_src = int_params.irq_source;
3638
3639                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3640                                 dm_crtc_high_irq, c_irq_params);
3641         }
3642
3643         /* Use VUPDATE interrupt */
3644         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3645                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3646                 if (r) {
3647                         DRM_ERROR("Failed to add vupdate irq id!\n");
3648                         return r;
3649                 }
3650
3651                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3652                 int_params.irq_source =
3653                         dc_interrupt_to_irq_source(dc, i, 0);
3654
3655                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3656
3657                 c_irq_params->adev = adev;
3658                 c_irq_params->irq_src = int_params.irq_source;
3659
3660                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3661                                 dm_vupdate_high_irq, c_irq_params);
3662         }
3663
3664         /* Use GRPH_PFLIP interrupt */
3665         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3666                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3667                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3668                 if (r) {
3669                         DRM_ERROR("Failed to add page flip irq id!\n");
3670                         return r;
3671                 }
3672
3673                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3674                 int_params.irq_source =
3675                         dc_interrupt_to_irq_source(dc, i, 0);
3676
3677                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3678
3679                 c_irq_params->adev = adev;
3680                 c_irq_params->irq_src = int_params.irq_source;
3681
3682                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3683                                 dm_pflip_high_irq, c_irq_params);
3684
3685         }
3686
3687         /* HPD */
3688         r = amdgpu_irq_add_id(adev, client_id,
3689                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3690         if (r) {
3691                 DRM_ERROR("Failed to add hpd irq id!\n");
3692                 return r;
3693         }
3694
3695         register_hpd_handlers(adev);
3696
3697         return 0;
3698 }
3699
3700 /* Register IRQ sources and initialize IRQ callbacks */
3701 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3702 {
3703         struct dc *dc = adev->dm.dc;
3704         struct common_irq_params *c_irq_params;
3705         struct dc_interrupt_params int_params = {0};
3706         int r;
3707         int i;
3708 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3709         static const unsigned int vrtl_int_srcid[] = {
3710                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3711                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3712                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3713                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3714                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3715                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3716         };
3717 #endif
3718
3719         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3720         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3721
3722         /*
3723          * Actions of amdgpu_irq_add_id():
3724          * 1. Register a set() function with base driver.
3725          *    Base driver will call set() function to enable/disable an
3726          *    interrupt in DC hardware.
3727          * 2. Register amdgpu_dm_irq_handler().
3728          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3729          *    coming from DC hardware.
3730          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3731          *    for acknowledging and handling.
3732          */
3733
3734         /* Use VSTARTUP interrupt */
3735         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3736                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3737                         i++) {
3738                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3739
3740                 if (r) {
3741                         DRM_ERROR("Failed to add crtc irq id!\n");
3742                         return r;
3743                 }
3744
3745                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3746                 int_params.irq_source =
3747                         dc_interrupt_to_irq_source(dc, i, 0);
3748
3749                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3750
3751                 c_irq_params->adev = adev;
3752                 c_irq_params->irq_src = int_params.irq_source;
3753
3754                 amdgpu_dm_irq_register_interrupt(
3755                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3756         }
3757
3758         /* Use otg vertical line interrupt */
3759 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3760         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3761                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3762                                 vrtl_int_srcid[i], &adev->vline0_irq);
3763
3764                 if (r) {
3765                         DRM_ERROR("Failed to add vline0 irq id!\n");
3766                         return r;
3767                 }
3768
3769                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3770                 int_params.irq_source =
3771                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3772
3773                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3774                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3775                         break;
3776                 }
3777
3778                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3779                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3780
3781                 c_irq_params->adev = adev;
3782                 c_irq_params->irq_src = int_params.irq_source;
3783
3784                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3785                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3786         }
3787 #endif
3788
3789         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3790          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3791          * to trigger at end of each vblank, regardless of state of the lock,
3792          * matching DCE behaviour.
3793          */
3794         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3795              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3796              i++) {
3797                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3798
3799                 if (r) {
3800                         DRM_ERROR("Failed to add vupdate irq id!\n");
3801                         return r;
3802                 }
3803
3804                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3805                 int_params.irq_source =
3806                         dc_interrupt_to_irq_source(dc, i, 0);
3807
3808                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3809
3810                 c_irq_params->adev = adev;
3811                 c_irq_params->irq_src = int_params.irq_source;
3812
3813                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3814                                 dm_vupdate_high_irq, c_irq_params);
3815         }
3816
3817         /* Use GRPH_PFLIP interrupt */
3818         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3819                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3820                         i++) {
3821                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3822                 if (r) {
3823                         DRM_ERROR("Failed to add page flip irq id!\n");
3824                         return r;
3825                 }
3826
3827                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3828                 int_params.irq_source =
3829                         dc_interrupt_to_irq_source(dc, i, 0);
3830
3831                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3832
3833                 c_irq_params->adev = adev;
3834                 c_irq_params->irq_src = int_params.irq_source;
3835
3836                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3837                                 dm_pflip_high_irq, c_irq_params);
3838
3839         }
3840
3841         /* HPD */
3842         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3843                         &adev->hpd_irq);
3844         if (r) {
3845                 DRM_ERROR("Failed to add hpd irq id!\n");
3846                 return r;
3847         }
3848
3849         register_hpd_handlers(adev);
3850
3851         return 0;
3852 }
3853 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3854 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3855 {
3856         struct dc *dc = adev->dm.dc;
3857         struct common_irq_params *c_irq_params;
3858         struct dc_interrupt_params int_params = {0};
3859         int r, i;
3860
3861         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3862         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3863
3864         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3865                         &adev->dmub_outbox_irq);
3866         if (r) {
3867                 DRM_ERROR("Failed to add outbox irq id!\n");
3868                 return r;
3869         }
3870
3871         if (dc->ctx->dmub_srv) {
3872                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3873                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3874                 int_params.irq_source =
3875                 dc_interrupt_to_irq_source(dc, i, 0);
3876
3877                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3878
3879                 c_irq_params->adev = adev;
3880                 c_irq_params->irq_src = int_params.irq_source;
3881
3882                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3883                                 dm_dmub_outbox1_low_irq, c_irq_params);
3884         }
3885
3886         return 0;
3887 }
3888
3889 /*
3890  * Acquires the lock for the atomic state object and returns
3891  * the new atomic state.
3892  *
3893  * This should only be called during atomic check.
3894  */
3895 int dm_atomic_get_state(struct drm_atomic_state *state,
3896                         struct dm_atomic_state **dm_state)
3897 {
3898         struct drm_device *dev = state->dev;
3899         struct amdgpu_device *adev = drm_to_adev(dev);
3900         struct amdgpu_display_manager *dm = &adev->dm;
3901         struct drm_private_state *priv_state;
3902
3903         if (*dm_state)
3904                 return 0;
3905
3906         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3907         if (IS_ERR(priv_state))
3908                 return PTR_ERR(priv_state);
3909
3910         *dm_state = to_dm_atomic_state(priv_state);
3911
3912         return 0;
3913 }
3914
3915 static struct dm_atomic_state *
3916 dm_atomic_get_new_state(struct drm_atomic_state *state)
3917 {
3918         struct drm_device *dev = state->dev;
3919         struct amdgpu_device *adev = drm_to_adev(dev);
3920         struct amdgpu_display_manager *dm = &adev->dm;
3921         struct drm_private_obj *obj;
3922         struct drm_private_state *new_obj_state;
3923         int i;
3924
3925         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3926                 if (obj->funcs == dm->atomic_obj.funcs)
3927                         return to_dm_atomic_state(new_obj_state);
3928         }
3929
3930         return NULL;
3931 }
3932
3933 static struct drm_private_state *
3934 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3935 {
3936         struct dm_atomic_state *old_state, *new_state;
3937
3938         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3939         if (!new_state)
3940                 return NULL;
3941
3942         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3943
3944         old_state = to_dm_atomic_state(obj->state);
3945
3946         if (old_state && old_state->context)
3947                 new_state->context = dc_copy_state(old_state->context);
3948
3949         if (!new_state->context) {
3950                 kfree(new_state);
3951                 return NULL;
3952         }
3953
3954         return &new_state->base;
3955 }
3956
3957 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3958                                     struct drm_private_state *state)
3959 {
3960         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3961
3962         if (dm_state && dm_state->context)
3963                 dc_release_state(dm_state->context);
3964
3965         kfree(dm_state);
3966 }
3967
3968 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3969         .atomic_duplicate_state = dm_atomic_duplicate_state,
3970         .atomic_destroy_state = dm_atomic_destroy_state,
3971 };
3972
3973 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3974 {
3975         struct dm_atomic_state *state;
3976         int r;
3977
3978         adev->mode_info.mode_config_initialized = true;
3979
3980         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3981         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3982
3983         adev_to_drm(adev)->mode_config.max_width = 16384;
3984         adev_to_drm(adev)->mode_config.max_height = 16384;
3985
3986         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3987         if (adev->asic_type == CHIP_HAWAII)
3988                 /* disable prefer shadow for now due to hibernation issues */
3989                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3990         else
3991                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3992         /* indicates support for immediate flip */
3993         adev_to_drm(adev)->mode_config.async_page_flip = true;
3994
3995         state = kzalloc(sizeof(*state), GFP_KERNEL);
3996         if (!state)
3997                 return -ENOMEM;
3998
3999         state->context = dc_create_state(adev->dm.dc);
4000         if (!state->context) {
4001                 kfree(state);
4002                 return -ENOMEM;
4003         }
4004
4005         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
4006
4007         drm_atomic_private_obj_init(adev_to_drm(adev),
4008                                     &adev->dm.atomic_obj,
4009                                     &state->base,
4010                                     &dm_atomic_state_funcs);
4011
4012         r = amdgpu_display_modeset_create_props(adev);
4013         if (r) {
4014                 dc_release_state(state->context);
4015                 kfree(state);
4016                 return r;
4017         }
4018
4019         r = amdgpu_dm_audio_init(adev);
4020         if (r) {
4021                 dc_release_state(state->context);
4022                 kfree(state);
4023                 return r;
4024         }
4025
4026         return 0;
4027 }
4028
4029 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4030 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4031 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4032
4033 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4034                                             int bl_idx)
4035 {
4036 #if defined(CONFIG_ACPI)
4037         struct amdgpu_dm_backlight_caps caps;
4038
4039         memset(&caps, 0, sizeof(caps));
4040
4041         if (dm->backlight_caps[bl_idx].caps_valid)
4042                 return;
4043
4044         amdgpu_acpi_get_backlight_caps(&caps);
4045         if (caps.caps_valid) {
4046                 dm->backlight_caps[bl_idx].caps_valid = true;
4047                 if (caps.aux_support)
4048                         return;
4049                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4050                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4051         } else {
4052                 dm->backlight_caps[bl_idx].min_input_signal =
4053                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4054                 dm->backlight_caps[bl_idx].max_input_signal =
4055                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4056         }
4057 #else
4058         if (dm->backlight_caps[bl_idx].aux_support)
4059                 return;
4060
4061         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4062         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4063 #endif
4064 }
4065
4066 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4067                                 unsigned int *min, unsigned int *max)
4068 {
4069         if (!caps)
4070                 return 0;
4071
4072         if (caps->aux_support) {
4073                 // Firmware limits are in nits, DC API wants millinits.
4074                 *max = 1000 * caps->aux_max_input_signal;
4075                 *min = 1000 * caps->aux_min_input_signal;
4076         } else {
4077                 // Firmware limits are 8-bit, PWM control is 16-bit.
4078                 *max = 0x101 * caps->max_input_signal;
4079                 *min = 0x101 * caps->min_input_signal;
4080         }
4081         return 1;
4082 }
4083
4084 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4085                                         uint32_t brightness)
4086 {
4087         unsigned int min, max;
4088
4089         if (!get_brightness_range(caps, &min, &max))
4090                 return brightness;
4091
4092         // Rescale 0..255 to min..max
4093         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4094                                        AMDGPU_MAX_BL_LEVEL);
4095 }
4096
4097 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4098                                       uint32_t brightness)
4099 {
4100         unsigned int min, max;
4101
4102         if (!get_brightness_range(caps, &min, &max))
4103                 return brightness;
4104
4105         if (brightness < min)
4106                 return 0;
4107         // Rescale min..max to 0..255
4108         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4109                                  max - min);
4110 }
4111
4112 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4113                                          int bl_idx,
4114                                          u32 user_brightness)
4115 {
4116         struct amdgpu_dm_backlight_caps caps;
4117         struct dc_link *link;
4118         u32 brightness;
4119         bool rc;
4120
4121         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4122         caps = dm->backlight_caps[bl_idx];
4123
4124         dm->brightness[bl_idx] = user_brightness;
4125         /* update scratch register */
4126         if (bl_idx == 0)
4127                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4128         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4129         link = (struct dc_link *)dm->backlight_link[bl_idx];
4130
4131         /* Change brightness based on AUX property */
4132         if (caps.aux_support) {
4133                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4134                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4135                 if (!rc)
4136                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4137         } else {
4138                 rc = dc_link_set_backlight_level(link, brightness, 0);
4139                 if (!rc)
4140                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4141         }
4142
4143         if (rc)
4144                 dm->actual_brightness[bl_idx] = user_brightness;
4145 }
4146
4147 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4148 {
4149         struct amdgpu_display_manager *dm = bl_get_data(bd);
4150         int i;
4151
4152         for (i = 0; i < dm->num_of_edps; i++) {
4153                 if (bd == dm->backlight_dev[i])
4154                         break;
4155         }
4156         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4157                 i = 0;
4158         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4159
4160         return 0;
4161 }
4162
4163 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4164                                          int bl_idx)
4165 {
4166         int ret;
4167         struct amdgpu_dm_backlight_caps caps;
4168         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4169
4170         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4171         caps = dm->backlight_caps[bl_idx];
4172
4173         if (caps.aux_support) {
4174                 u32 avg, peak;
4175                 bool rc;
4176
4177                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4178                 if (!rc)
4179                         return dm->brightness[bl_idx];
4180                 return convert_brightness_to_user(&caps, avg);
4181         }
4182
4183         ret = dc_link_get_backlight_level(link);
4184
4185         if (ret == DC_ERROR_UNEXPECTED)
4186                 return dm->brightness[bl_idx];
4187
4188         return convert_brightness_to_user(&caps, ret);
4189 }
4190
4191 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4192 {
4193         struct amdgpu_display_manager *dm = bl_get_data(bd);
4194         int i;
4195
4196         for (i = 0; i < dm->num_of_edps; i++) {
4197                 if (bd == dm->backlight_dev[i])
4198                         break;
4199         }
4200         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4201                 i = 0;
4202         return amdgpu_dm_backlight_get_level(dm, i);
4203 }
4204
4205 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4206         .options = BL_CORE_SUSPENDRESUME,
4207         .get_brightness = amdgpu_dm_backlight_get_brightness,
4208         .update_status  = amdgpu_dm_backlight_update_status,
4209 };
4210
4211 static void
4212 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4213 {
4214         struct drm_device *drm = aconnector->base.dev;
4215         struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4216         struct backlight_properties props = { 0 };
4217         char bl_name[16];
4218
4219         if (aconnector->bl_idx == -1)
4220                 return;
4221
4222         if (!acpi_video_backlight_use_native()) {
4223                 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4224                 /* Try registering an ACPI video backlight device instead. */
4225                 acpi_video_register_backlight();
4226                 return;
4227         }
4228
4229         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4230         props.brightness = AMDGPU_MAX_BL_LEVEL;
4231         props.type = BACKLIGHT_RAW;
4232
4233         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4234                  drm->primary->index + aconnector->bl_idx);
4235
4236         dm->backlight_dev[aconnector->bl_idx] =
4237                 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4238                                           &amdgpu_dm_backlight_ops, &props);
4239
4240         if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4241                 DRM_ERROR("DM: Backlight registration failed!\n");
4242                 dm->backlight_dev[aconnector->bl_idx] = NULL;
4243         } else
4244                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4245 }
4246
4247 static int initialize_plane(struct amdgpu_display_manager *dm,
4248                             struct amdgpu_mode_info *mode_info, int plane_id,
4249                             enum drm_plane_type plane_type,
4250                             const struct dc_plane_cap *plane_cap)
4251 {
4252         struct drm_plane *plane;
4253         unsigned long possible_crtcs;
4254         int ret = 0;
4255
4256         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4257         if (!plane) {
4258                 DRM_ERROR("KMS: Failed to allocate plane\n");
4259                 return -ENOMEM;
4260         }
4261         plane->type = plane_type;
4262
4263         /*
4264          * HACK: IGT tests expect that the primary plane for a CRTC
4265          * can only have one possible CRTC. Only expose support for
4266          * any CRTC if they're not going to be used as a primary plane
4267          * for a CRTC - like overlay or underlay planes.
4268          */
4269         possible_crtcs = 1 << plane_id;
4270         if (plane_id >= dm->dc->caps.max_streams)
4271                 possible_crtcs = 0xff;
4272
4273         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4274
4275         if (ret) {
4276                 DRM_ERROR("KMS: Failed to initialize plane\n");
4277                 kfree(plane);
4278                 return ret;
4279         }
4280
4281         if (mode_info)
4282                 mode_info->planes[plane_id] = plane;
4283
4284         return ret;
4285 }
4286
4287
4288 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4289                                    struct amdgpu_dm_connector *aconnector)
4290 {
4291         struct dc_link *link = aconnector->dc_link;
4292         int bl_idx = dm->num_of_edps;
4293
4294         if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4295             link->type == dc_connection_none)
4296                 return;
4297
4298         if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4299                 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4300                 return;
4301         }
4302
4303         aconnector->bl_idx = bl_idx;
4304
4305         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4306         dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4307         dm->backlight_link[bl_idx] = link;
4308         dm->num_of_edps++;
4309
4310         update_connector_ext_caps(aconnector);
4311 }
4312
4313 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4314
4315 /*
4316  * In this architecture, the association
4317  * connector -> encoder -> crtc
4318  * id not really requried. The crtc and connector will hold the
4319  * display_index as an abstraction to use with DAL component
4320  *
4321  * Returns 0 on success
4322  */
4323 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4324 {
4325         struct amdgpu_display_manager *dm = &adev->dm;
4326         s32 i;
4327         struct amdgpu_dm_connector *aconnector = NULL;
4328         struct amdgpu_encoder *aencoder = NULL;
4329         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4330         u32 link_cnt;
4331         s32 primary_planes;
4332         enum dc_connection_type new_connection_type = dc_connection_none;
4333         const struct dc_plane_cap *plane;
4334         bool psr_feature_enabled = false;
4335         bool replay_feature_enabled = false;
4336         int max_overlay = dm->dc->caps.max_slave_planes;
4337
4338         dm->display_indexes_num = dm->dc->caps.max_streams;
4339         /* Update the actual used number of crtc */
4340         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4341
4342         amdgpu_dm_set_irq_funcs(adev);
4343
4344         link_cnt = dm->dc->caps.max_links;
4345         if (amdgpu_dm_mode_config_init(dm->adev)) {
4346                 DRM_ERROR("DM: Failed to initialize mode config\n");
4347                 return -EINVAL;
4348         }
4349
4350         /* There is one primary plane per CRTC */
4351         primary_planes = dm->dc->caps.max_streams;
4352         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4353
4354         /*
4355          * Initialize primary planes, implicit planes for legacy IOCTLS.
4356          * Order is reversed to match iteration order in atomic check.
4357          */
4358         for (i = (primary_planes - 1); i >= 0; i--) {
4359                 plane = &dm->dc->caps.planes[i];
4360
4361                 if (initialize_plane(dm, mode_info, i,
4362                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4363                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4364                         goto fail;
4365                 }
4366         }
4367
4368         /*
4369          * Initialize overlay planes, index starting after primary planes.
4370          * These planes have a higher DRM index than the primary planes since
4371          * they should be considered as having a higher z-order.
4372          * Order is reversed to match iteration order in atomic check.
4373          *
4374          * Only support DCN for now, and only expose one so we don't encourage
4375          * userspace to use up all the pipes.
4376          */
4377         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4378                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4379
4380                 /* Do not create overlay if MPO disabled */
4381                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4382                         break;
4383
4384                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4385                         continue;
4386
4387                 if (!plane->pixel_format_support.argb8888)
4388                         continue;
4389
4390                 if (max_overlay-- == 0)
4391                         break;
4392
4393                 if (initialize_plane(dm, NULL, primary_planes + i,
4394                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4395                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4396                         goto fail;
4397                 }
4398         }
4399
4400         for (i = 0; i < dm->dc->caps.max_streams; i++)
4401                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4402                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4403                         goto fail;
4404                 }
4405
4406         /* Use Outbox interrupt */
4407         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4408         case IP_VERSION(3, 0, 0):
4409         case IP_VERSION(3, 1, 2):
4410         case IP_VERSION(3, 1, 3):
4411         case IP_VERSION(3, 1, 4):
4412         case IP_VERSION(3, 1, 5):
4413         case IP_VERSION(3, 1, 6):
4414         case IP_VERSION(3, 2, 0):
4415         case IP_VERSION(3, 2, 1):
4416         case IP_VERSION(2, 1, 0):
4417         case IP_VERSION(3, 5, 0):
4418                 if (register_outbox_irq_handlers(dm->adev)) {
4419                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4420                         goto fail;
4421                 }
4422                 break;
4423         default:
4424                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4425                               amdgpu_ip_version(adev, DCE_HWIP, 0));
4426         }
4427
4428         /* Determine whether to enable PSR support by default. */
4429         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4430                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4431                 case IP_VERSION(3, 1, 2):
4432                 case IP_VERSION(3, 1, 3):
4433                 case IP_VERSION(3, 1, 4):
4434                 case IP_VERSION(3, 1, 5):
4435                 case IP_VERSION(3, 1, 6):
4436                 case IP_VERSION(3, 2, 0):
4437                 case IP_VERSION(3, 2, 1):
4438                 case IP_VERSION(3, 5, 0):
4439                         psr_feature_enabled = true;
4440                         break;
4441                 default:
4442                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4443                         break;
4444                 }
4445         }
4446
4447         if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
4448                 switch (adev->ip_versions[DCE_HWIP][0]) {
4449                 case IP_VERSION(3, 1, 4):
4450                 case IP_VERSION(3, 1, 5):
4451                 case IP_VERSION(3, 1, 6):
4452                 case IP_VERSION(3, 2, 0):
4453                 case IP_VERSION(3, 2, 1):
4454                         replay_feature_enabled = true;
4455                         break;
4456                 default:
4457                         replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK;
4458                         break;
4459                 }
4460         }
4461         /* loops over all connectors on the board */
4462         for (i = 0; i < link_cnt; i++) {
4463                 struct dc_link *link = NULL;
4464
4465                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4466                         DRM_ERROR(
4467                                 "KMS: Cannot support more than %d display indexes\n",
4468                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4469                         continue;
4470                 }
4471
4472                 link = dc_get_link_at_index(dm->dc, i);
4473
4474                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
4475                         continue;
4476
4477                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4478                 if (!aconnector)
4479                         goto fail;
4480
4481                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4482                 if (!aencoder)
4483                         goto fail;
4484
4485                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4486                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4487                         goto fail;
4488                 }
4489
4490                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4491                         DRM_ERROR("KMS: Failed to initialize connector\n");
4492                         goto fail;
4493                 }
4494
4495                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4496                         DRM_ERROR("KMS: Failed to detect connector\n");
4497
4498                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4499                         emulated_link_detect(link);
4500                         amdgpu_dm_update_connector_after_detect(aconnector);
4501                 } else {
4502                         bool ret = false;
4503
4504                         mutex_lock(&dm->dc_lock);
4505                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4506                         mutex_unlock(&dm->dc_lock);
4507
4508                         if (ret) {
4509                                 amdgpu_dm_update_connector_after_detect(aconnector);
4510                                 setup_backlight_device(dm, aconnector);
4511
4512                                 /*
4513                                  * Disable psr if replay can be enabled
4514                                  */
4515                                 if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector))
4516                                         psr_feature_enabled = false;
4517
4518                                 if (psr_feature_enabled)
4519                                         amdgpu_dm_set_psr_caps(link);
4520
4521                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4522                                  * PSR is also supported.
4523                                  */
4524                                 if (link->psr_settings.psr_feature_enabled)
4525                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4526                         }
4527                 }
4528                 amdgpu_set_panel_orientation(&aconnector->base);
4529         }
4530
4531         /* Software is initialized. Now we can register interrupt handlers. */
4532         switch (adev->asic_type) {
4533 #if defined(CONFIG_DRM_AMD_DC_SI)
4534         case CHIP_TAHITI:
4535         case CHIP_PITCAIRN:
4536         case CHIP_VERDE:
4537         case CHIP_OLAND:
4538                 if (dce60_register_irq_handlers(dm->adev)) {
4539                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4540                         goto fail;
4541                 }
4542                 break;
4543 #endif
4544         case CHIP_BONAIRE:
4545         case CHIP_HAWAII:
4546         case CHIP_KAVERI:
4547         case CHIP_KABINI:
4548         case CHIP_MULLINS:
4549         case CHIP_TONGA:
4550         case CHIP_FIJI:
4551         case CHIP_CARRIZO:
4552         case CHIP_STONEY:
4553         case CHIP_POLARIS11:
4554         case CHIP_POLARIS10:
4555         case CHIP_POLARIS12:
4556         case CHIP_VEGAM:
4557         case CHIP_VEGA10:
4558         case CHIP_VEGA12:
4559         case CHIP_VEGA20:
4560                 if (dce110_register_irq_handlers(dm->adev)) {
4561                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4562                         goto fail;
4563                 }
4564                 break;
4565         default:
4566                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4567                 case IP_VERSION(1, 0, 0):
4568                 case IP_VERSION(1, 0, 1):
4569                 case IP_VERSION(2, 0, 2):
4570                 case IP_VERSION(2, 0, 3):
4571                 case IP_VERSION(2, 0, 0):
4572                 case IP_VERSION(2, 1, 0):
4573                 case IP_VERSION(3, 0, 0):
4574                 case IP_VERSION(3, 0, 2):
4575                 case IP_VERSION(3, 0, 3):
4576                 case IP_VERSION(3, 0, 1):
4577                 case IP_VERSION(3, 1, 2):
4578                 case IP_VERSION(3, 1, 3):
4579                 case IP_VERSION(3, 1, 4):
4580                 case IP_VERSION(3, 1, 5):
4581                 case IP_VERSION(3, 1, 6):
4582                 case IP_VERSION(3, 2, 0):
4583                 case IP_VERSION(3, 2, 1):
4584                 case IP_VERSION(3, 5, 0):
4585                         if (dcn10_register_irq_handlers(dm->adev)) {
4586                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4587                                 goto fail;
4588                         }
4589                         break;
4590                 default:
4591                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4592                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4593                         goto fail;
4594                 }
4595                 break;
4596         }
4597
4598         return 0;
4599 fail:
4600         kfree(aencoder);
4601         kfree(aconnector);
4602
4603         return -EINVAL;
4604 }
4605
4606 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4607 {
4608         drm_atomic_private_obj_fini(&dm->atomic_obj);
4609 }
4610
4611 /******************************************************************************
4612  * amdgpu_display_funcs functions
4613  *****************************************************************************/
4614
4615 /*
4616  * dm_bandwidth_update - program display watermarks
4617  *
4618  * @adev: amdgpu_device pointer
4619  *
4620  * Calculate and program the display watermarks and line buffer allocation.
4621  */
4622 static void dm_bandwidth_update(struct amdgpu_device *adev)
4623 {
4624         /* TODO: implement later */
4625 }
4626
4627 static const struct amdgpu_display_funcs dm_display_funcs = {
4628         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4629         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4630         .backlight_set_level = NULL, /* never called for DC */
4631         .backlight_get_level = NULL, /* never called for DC */
4632         .hpd_sense = NULL,/* called unconditionally */
4633         .hpd_set_polarity = NULL, /* called unconditionally */
4634         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4635         .page_flip_get_scanoutpos =
4636                 dm_crtc_get_scanoutpos,/* called unconditionally */
4637         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4638         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4639 };
4640
4641 #if defined(CONFIG_DEBUG_KERNEL_DC)
4642
4643 static ssize_t s3_debug_store(struct device *device,
4644                               struct device_attribute *attr,
4645                               const char *buf,
4646                               size_t count)
4647 {
4648         int ret;
4649         int s3_state;
4650         struct drm_device *drm_dev = dev_get_drvdata(device);
4651         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4652
4653         ret = kstrtoint(buf, 0, &s3_state);
4654
4655         if (ret == 0) {
4656                 if (s3_state) {
4657                         dm_resume(adev);
4658                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4659                 } else
4660                         dm_suspend(adev);
4661         }
4662
4663         return ret == 0 ? count : 0;
4664 }
4665
4666 DEVICE_ATTR_WO(s3_debug);
4667
4668 #endif
4669
4670 static int dm_init_microcode(struct amdgpu_device *adev)
4671 {
4672         char *fw_name_dmub;
4673         int r;
4674
4675         switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4676         case IP_VERSION(2, 1, 0):
4677                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4678                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4679                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4680                 break;
4681         case IP_VERSION(3, 0, 0):
4682                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 0))
4683                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4684                 else
4685                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4686                 break;
4687         case IP_VERSION(3, 0, 1):
4688                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4689                 break;
4690         case IP_VERSION(3, 0, 2):
4691                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4692                 break;
4693         case IP_VERSION(3, 0, 3):
4694                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4695                 break;
4696         case IP_VERSION(3, 1, 2):
4697         case IP_VERSION(3, 1, 3):
4698                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4699                 break;
4700         case IP_VERSION(3, 1, 4):
4701                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4702                 break;
4703         case IP_VERSION(3, 1, 5):
4704                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4705                 break;
4706         case IP_VERSION(3, 1, 6):
4707                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4708                 break;
4709         case IP_VERSION(3, 2, 0):
4710                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4711                 break;
4712         case IP_VERSION(3, 2, 1):
4713                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4714                 break;
4715         case IP_VERSION(3, 5, 0):
4716                 fw_name_dmub = FIRMWARE_DCN_35_DMUB;
4717                 break;
4718         default:
4719                 /* ASIC doesn't support DMUB. */
4720                 return 0;
4721         }
4722         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4723         return r;
4724 }
4725
4726 static int dm_early_init(void *handle)
4727 {
4728         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4729         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4730         struct atom_context *ctx = mode_info->atom_context;
4731         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4732         u16 data_offset;
4733
4734         /* if there is no object header, skip DM */
4735         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4736                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4737                 dev_info(adev->dev, "No object header, skipping DM\n");
4738                 return -ENOENT;
4739         }
4740
4741         switch (adev->asic_type) {
4742 #if defined(CONFIG_DRM_AMD_DC_SI)
4743         case CHIP_TAHITI:
4744         case CHIP_PITCAIRN:
4745         case CHIP_VERDE:
4746                 adev->mode_info.num_crtc = 6;
4747                 adev->mode_info.num_hpd = 6;
4748                 adev->mode_info.num_dig = 6;
4749                 break;
4750         case CHIP_OLAND:
4751                 adev->mode_info.num_crtc = 2;
4752                 adev->mode_info.num_hpd = 2;
4753                 adev->mode_info.num_dig = 2;
4754                 break;
4755 #endif
4756         case CHIP_BONAIRE:
4757         case CHIP_HAWAII:
4758                 adev->mode_info.num_crtc = 6;
4759                 adev->mode_info.num_hpd = 6;
4760                 adev->mode_info.num_dig = 6;
4761                 break;
4762         case CHIP_KAVERI:
4763                 adev->mode_info.num_crtc = 4;
4764                 adev->mode_info.num_hpd = 6;
4765                 adev->mode_info.num_dig = 7;
4766                 break;
4767         case CHIP_KABINI:
4768         case CHIP_MULLINS:
4769                 adev->mode_info.num_crtc = 2;
4770                 adev->mode_info.num_hpd = 6;
4771                 adev->mode_info.num_dig = 6;
4772                 break;
4773         case CHIP_FIJI:
4774         case CHIP_TONGA:
4775                 adev->mode_info.num_crtc = 6;
4776                 adev->mode_info.num_hpd = 6;
4777                 adev->mode_info.num_dig = 7;
4778                 break;
4779         case CHIP_CARRIZO:
4780                 adev->mode_info.num_crtc = 3;
4781                 adev->mode_info.num_hpd = 6;
4782                 adev->mode_info.num_dig = 9;
4783                 break;
4784         case CHIP_STONEY:
4785                 adev->mode_info.num_crtc = 2;
4786                 adev->mode_info.num_hpd = 6;
4787                 adev->mode_info.num_dig = 9;
4788                 break;
4789         case CHIP_POLARIS11:
4790         case CHIP_POLARIS12:
4791                 adev->mode_info.num_crtc = 5;
4792                 adev->mode_info.num_hpd = 5;
4793                 adev->mode_info.num_dig = 5;
4794                 break;
4795         case CHIP_POLARIS10:
4796         case CHIP_VEGAM:
4797                 adev->mode_info.num_crtc = 6;
4798                 adev->mode_info.num_hpd = 6;
4799                 adev->mode_info.num_dig = 6;
4800                 break;
4801         case CHIP_VEGA10:
4802         case CHIP_VEGA12:
4803         case CHIP_VEGA20:
4804                 adev->mode_info.num_crtc = 6;
4805                 adev->mode_info.num_hpd = 6;
4806                 adev->mode_info.num_dig = 6;
4807                 break;
4808         default:
4809
4810                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
4811                 case IP_VERSION(2, 0, 2):
4812                 case IP_VERSION(3, 0, 0):
4813                         adev->mode_info.num_crtc = 6;
4814                         adev->mode_info.num_hpd = 6;
4815                         adev->mode_info.num_dig = 6;
4816                         break;
4817                 case IP_VERSION(2, 0, 0):
4818                 case IP_VERSION(3, 0, 2):
4819                         adev->mode_info.num_crtc = 5;
4820                         adev->mode_info.num_hpd = 5;
4821                         adev->mode_info.num_dig = 5;
4822                         break;
4823                 case IP_VERSION(2, 0, 3):
4824                 case IP_VERSION(3, 0, 3):
4825                         adev->mode_info.num_crtc = 2;
4826                         adev->mode_info.num_hpd = 2;
4827                         adev->mode_info.num_dig = 2;
4828                         break;
4829                 case IP_VERSION(1, 0, 0):
4830                 case IP_VERSION(1, 0, 1):
4831                 case IP_VERSION(3, 0, 1):
4832                 case IP_VERSION(2, 1, 0):
4833                 case IP_VERSION(3, 1, 2):
4834                 case IP_VERSION(3, 1, 3):
4835                 case IP_VERSION(3, 1, 4):
4836                 case IP_VERSION(3, 1, 5):
4837                 case IP_VERSION(3, 1, 6):
4838                 case IP_VERSION(3, 2, 0):
4839                 case IP_VERSION(3, 2, 1):
4840                 case IP_VERSION(3, 5, 0):
4841                         adev->mode_info.num_crtc = 4;
4842                         adev->mode_info.num_hpd = 4;
4843                         adev->mode_info.num_dig = 4;
4844                         break;
4845                 default:
4846                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4847                                         amdgpu_ip_version(adev, DCE_HWIP, 0));
4848                         return -EINVAL;
4849                 }
4850                 break;
4851         }
4852
4853         if (adev->mode_info.funcs == NULL)
4854                 adev->mode_info.funcs = &dm_display_funcs;
4855
4856         /*
4857          * Note: Do NOT change adev->audio_endpt_rreg and
4858          * adev->audio_endpt_wreg because they are initialised in
4859          * amdgpu_device_init()
4860          */
4861 #if defined(CONFIG_DEBUG_KERNEL_DC)
4862         device_create_file(
4863                 adev_to_drm(adev)->dev,
4864                 &dev_attr_s3_debug);
4865 #endif
4866         adev->dc_enabled = true;
4867
4868         return dm_init_microcode(adev);
4869 }
4870
4871 static bool modereset_required(struct drm_crtc_state *crtc_state)
4872 {
4873         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4874 }
4875
4876 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4877 {
4878         drm_encoder_cleanup(encoder);
4879         kfree(encoder);
4880 }
4881
4882 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4883         .destroy = amdgpu_dm_encoder_destroy,
4884 };
4885
4886 static int
4887 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4888                             const enum surface_pixel_format format,
4889                             enum dc_color_space *color_space)
4890 {
4891         bool full_range;
4892
4893         *color_space = COLOR_SPACE_SRGB;
4894
4895         /* DRM color properties only affect non-RGB formats. */
4896         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4897                 return 0;
4898
4899         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4900
4901         switch (plane_state->color_encoding) {
4902         case DRM_COLOR_YCBCR_BT601:
4903                 if (full_range)
4904                         *color_space = COLOR_SPACE_YCBCR601;
4905                 else
4906                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4907                 break;
4908
4909         case DRM_COLOR_YCBCR_BT709:
4910                 if (full_range)
4911                         *color_space = COLOR_SPACE_YCBCR709;
4912                 else
4913                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4914                 break;
4915
4916         case DRM_COLOR_YCBCR_BT2020:
4917                 if (full_range)
4918                         *color_space = COLOR_SPACE_2020_YCBCR;
4919                 else
4920                         return -EINVAL;
4921                 break;
4922
4923         default:
4924                 return -EINVAL;
4925         }
4926
4927         return 0;
4928 }
4929
4930 static int
4931 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4932                             const struct drm_plane_state *plane_state,
4933                             const u64 tiling_flags,
4934                             struct dc_plane_info *plane_info,
4935                             struct dc_plane_address *address,
4936                             bool tmz_surface,
4937                             bool force_disable_dcc)
4938 {
4939         const struct drm_framebuffer *fb = plane_state->fb;
4940         const struct amdgpu_framebuffer *afb =
4941                 to_amdgpu_framebuffer(plane_state->fb);
4942         int ret;
4943
4944         memset(plane_info, 0, sizeof(*plane_info));
4945
4946         switch (fb->format->format) {
4947         case DRM_FORMAT_C8:
4948                 plane_info->format =
4949                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4950                 break;
4951         case DRM_FORMAT_RGB565:
4952                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4953                 break;
4954         case DRM_FORMAT_XRGB8888:
4955         case DRM_FORMAT_ARGB8888:
4956                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4957                 break;
4958         case DRM_FORMAT_XRGB2101010:
4959         case DRM_FORMAT_ARGB2101010:
4960                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4961                 break;
4962         case DRM_FORMAT_XBGR2101010:
4963         case DRM_FORMAT_ABGR2101010:
4964                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4965                 break;
4966         case DRM_FORMAT_XBGR8888:
4967         case DRM_FORMAT_ABGR8888:
4968                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4969                 break;
4970         case DRM_FORMAT_NV21:
4971                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4972                 break;
4973         case DRM_FORMAT_NV12:
4974                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4975                 break;
4976         case DRM_FORMAT_P010:
4977                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4978                 break;
4979         case DRM_FORMAT_XRGB16161616F:
4980         case DRM_FORMAT_ARGB16161616F:
4981                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4982                 break;
4983         case DRM_FORMAT_XBGR16161616F:
4984         case DRM_FORMAT_ABGR16161616F:
4985                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4986                 break;
4987         case DRM_FORMAT_XRGB16161616:
4988         case DRM_FORMAT_ARGB16161616:
4989                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4990                 break;
4991         case DRM_FORMAT_XBGR16161616:
4992         case DRM_FORMAT_ABGR16161616:
4993                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4994                 break;
4995         default:
4996                 DRM_ERROR(
4997                         "Unsupported screen format %p4cc\n",
4998                         &fb->format->format);
4999                 return -EINVAL;
5000         }
5001
5002         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
5003         case DRM_MODE_ROTATE_0:
5004                 plane_info->rotation = ROTATION_ANGLE_0;
5005                 break;
5006         case DRM_MODE_ROTATE_90:
5007                 plane_info->rotation = ROTATION_ANGLE_90;
5008                 break;
5009         case DRM_MODE_ROTATE_180:
5010                 plane_info->rotation = ROTATION_ANGLE_180;
5011                 break;
5012         case DRM_MODE_ROTATE_270:
5013                 plane_info->rotation = ROTATION_ANGLE_270;
5014                 break;
5015         default:
5016                 plane_info->rotation = ROTATION_ANGLE_0;
5017                 break;
5018         }
5019
5020
5021         plane_info->visible = true;
5022         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
5023
5024         plane_info->layer_index = plane_state->normalized_zpos;
5025
5026         ret = fill_plane_color_attributes(plane_state, plane_info->format,
5027                                           &plane_info->color_space);
5028         if (ret)
5029                 return ret;
5030
5031         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
5032                                            plane_info->rotation, tiling_flags,
5033                                            &plane_info->tiling_info,
5034                                            &plane_info->plane_size,
5035                                            &plane_info->dcc, address,
5036                                            tmz_surface, force_disable_dcc);
5037         if (ret)
5038                 return ret;
5039
5040         amdgpu_dm_plane_fill_blending_from_plane_state(
5041                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
5042                 &plane_info->global_alpha, &plane_info->global_alpha_value);
5043
5044         return 0;
5045 }
5046
5047 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5048                                     struct dc_plane_state *dc_plane_state,
5049                                     struct drm_plane_state *plane_state,
5050                                     struct drm_crtc_state *crtc_state)
5051 {
5052         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5053         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5054         struct dc_scaling_info scaling_info;
5055         struct dc_plane_info plane_info;
5056         int ret;
5057         bool force_disable_dcc = false;
5058
5059         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5060         if (ret)
5061                 return ret;
5062
5063         dc_plane_state->src_rect = scaling_info.src_rect;
5064         dc_plane_state->dst_rect = scaling_info.dst_rect;
5065         dc_plane_state->clip_rect = scaling_info.clip_rect;
5066         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5067
5068         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5069         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5070                                           afb->tiling_flags,
5071                                           &plane_info,
5072                                           &dc_plane_state->address,
5073                                           afb->tmz_surface,
5074                                           force_disable_dcc);
5075         if (ret)
5076                 return ret;
5077
5078         dc_plane_state->format = plane_info.format;
5079         dc_plane_state->color_space = plane_info.color_space;
5080         dc_plane_state->format = plane_info.format;
5081         dc_plane_state->plane_size = plane_info.plane_size;
5082         dc_plane_state->rotation = plane_info.rotation;
5083         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5084         dc_plane_state->stereo_format = plane_info.stereo_format;
5085         dc_plane_state->tiling_info = plane_info.tiling_info;
5086         dc_plane_state->visible = plane_info.visible;
5087         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5088         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5089         dc_plane_state->global_alpha = plane_info.global_alpha;
5090         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5091         dc_plane_state->dcc = plane_info.dcc;
5092         dc_plane_state->layer_index = plane_info.layer_index;
5093         dc_plane_state->flip_int_enabled = true;
5094
5095         /*
5096          * Always set input transfer function, since plane state is refreshed
5097          * every time.
5098          */
5099         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5100         if (ret)
5101                 return ret;
5102
5103         return 0;
5104 }
5105
5106 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5107                                       struct rect *dirty_rect, int32_t x,
5108                                       s32 y, s32 width, s32 height,
5109                                       int *i, bool ffu)
5110 {
5111         WARN_ON(*i >= DC_MAX_DIRTY_RECTS);
5112
5113         dirty_rect->x = x;
5114         dirty_rect->y = y;
5115         dirty_rect->width = width;
5116         dirty_rect->height = height;
5117
5118         if (ffu)
5119                 drm_dbg(plane->dev,
5120                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5121                         plane->base.id, width, height);
5122         else
5123                 drm_dbg(plane->dev,
5124                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5125                         plane->base.id, x, y, width, height);
5126
5127         (*i)++;
5128 }
5129
5130 /**
5131  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5132  *
5133  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5134  *         remote fb
5135  * @old_plane_state: Old state of @plane
5136  * @new_plane_state: New state of @plane
5137  * @crtc_state: New state of CRTC connected to the @plane
5138  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5139  * @dirty_regions_changed: dirty regions changed
5140  *
5141  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5142  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5143  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5144  * amdgpu_dm's.
5145  *
5146  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5147  * plane with regions that require flushing to the eDP remote buffer. In
5148  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5149  * implicitly provide damage clips without any client support via the plane
5150  * bounds.
5151  */
5152 static void fill_dc_dirty_rects(struct drm_plane *plane,
5153                                 struct drm_plane_state *old_plane_state,
5154                                 struct drm_plane_state *new_plane_state,
5155                                 struct drm_crtc_state *crtc_state,
5156                                 struct dc_flip_addrs *flip_addrs,
5157                                 bool *dirty_regions_changed)
5158 {
5159         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5160         struct rect *dirty_rects = flip_addrs->dirty_rects;
5161         u32 num_clips;
5162         struct drm_mode_rect *clips;
5163         bool bb_changed;
5164         bool fb_changed;
5165         u32 i = 0;
5166         *dirty_regions_changed = false;
5167
5168         /*
5169          * Cursor plane has it's own dirty rect update interface. See
5170          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5171          */
5172         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5173                 return;
5174
5175         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5176         clips = drm_plane_get_damage_clips(new_plane_state);
5177
5178         if (!dm_crtc_state->mpo_requested) {
5179                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5180                         goto ffu;
5181
5182                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5183                         fill_dc_dirty_rect(new_plane_state->plane,
5184                                            &dirty_rects[flip_addrs->dirty_rect_count],
5185                                            clips->x1, clips->y1,
5186                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5187                                            &flip_addrs->dirty_rect_count,
5188                                            false);
5189                 return;
5190         }
5191
5192         /*
5193          * MPO is requested. Add entire plane bounding box to dirty rects if
5194          * flipped to or damaged.
5195          *
5196          * If plane is moved or resized, also add old bounding box to dirty
5197          * rects.
5198          */
5199         fb_changed = old_plane_state->fb->base.id !=
5200                      new_plane_state->fb->base.id;
5201         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5202                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5203                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5204                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5205
5206         drm_dbg(plane->dev,
5207                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5208                 new_plane_state->plane->base.id,
5209                 bb_changed, fb_changed, num_clips);
5210
5211         *dirty_regions_changed = bb_changed;
5212
5213         if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS)
5214                 goto ffu;
5215
5216         if (bb_changed) {
5217                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5218                                    new_plane_state->crtc_x,
5219                                    new_plane_state->crtc_y,
5220                                    new_plane_state->crtc_w,
5221                                    new_plane_state->crtc_h, &i, false);
5222
5223                 /* Add old plane bounding-box if plane is moved or resized */
5224                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5225                                    old_plane_state->crtc_x,
5226                                    old_plane_state->crtc_y,
5227                                    old_plane_state->crtc_w,
5228                                    old_plane_state->crtc_h, &i, false);
5229         }
5230
5231         if (num_clips) {
5232                 for (; i < num_clips; clips++)
5233                         fill_dc_dirty_rect(new_plane_state->plane,
5234                                            &dirty_rects[i], clips->x1,
5235                                            clips->y1, clips->x2 - clips->x1,
5236                                            clips->y2 - clips->y1, &i, false);
5237         } else if (fb_changed && !bb_changed) {
5238                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5239                                    new_plane_state->crtc_x,
5240                                    new_plane_state->crtc_y,
5241                                    new_plane_state->crtc_w,
5242                                    new_plane_state->crtc_h, &i, false);
5243         }
5244
5245         flip_addrs->dirty_rect_count = i;
5246         return;
5247
5248 ffu:
5249         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5250                            dm_crtc_state->base.mode.crtc_hdisplay,
5251                            dm_crtc_state->base.mode.crtc_vdisplay,
5252                            &flip_addrs->dirty_rect_count, true);
5253 }
5254
5255 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5256                                            const struct dm_connector_state *dm_state,
5257                                            struct dc_stream_state *stream)
5258 {
5259         enum amdgpu_rmx_type rmx_type;
5260
5261         struct rect src = { 0 }; /* viewport in composition space*/
5262         struct rect dst = { 0 }; /* stream addressable area */
5263
5264         /* no mode. nothing to be done */
5265         if (!mode)
5266                 return;
5267
5268         /* Full screen scaling by default */
5269         src.width = mode->hdisplay;
5270         src.height = mode->vdisplay;
5271         dst.width = stream->timing.h_addressable;
5272         dst.height = stream->timing.v_addressable;
5273
5274         if (dm_state) {
5275                 rmx_type = dm_state->scaling;
5276                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5277                         if (src.width * dst.height <
5278                                         src.height * dst.width) {
5279                                 /* height needs less upscaling/more downscaling */
5280                                 dst.width = src.width *
5281                                                 dst.height / src.height;
5282                         } else {
5283                                 /* width needs less upscaling/more downscaling */
5284                                 dst.height = src.height *
5285                                                 dst.width / src.width;
5286                         }
5287                 } else if (rmx_type == RMX_CENTER) {
5288                         dst = src;
5289                 }
5290
5291                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5292                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5293
5294                 if (dm_state->underscan_enable) {
5295                         dst.x += dm_state->underscan_hborder / 2;
5296                         dst.y += dm_state->underscan_vborder / 2;
5297                         dst.width -= dm_state->underscan_hborder;
5298                         dst.height -= dm_state->underscan_vborder;
5299                 }
5300         }
5301
5302         stream->src = src;
5303         stream->dst = dst;
5304
5305         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5306                       dst.x, dst.y, dst.width, dst.height);
5307
5308 }
5309
5310 static enum dc_color_depth
5311 convert_color_depth_from_display_info(const struct drm_connector *connector,
5312                                       bool is_y420, int requested_bpc)
5313 {
5314         u8 bpc;
5315
5316         if (is_y420) {
5317                 bpc = 8;
5318
5319                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5320                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5321                         bpc = 16;
5322                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5323                         bpc = 12;
5324                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5325                         bpc = 10;
5326         } else {
5327                 bpc = (uint8_t)connector->display_info.bpc;
5328                 /* Assume 8 bpc by default if no bpc is specified. */
5329                 bpc = bpc ? bpc : 8;
5330         }
5331
5332         if (requested_bpc > 0) {
5333                 /*
5334                  * Cap display bpc based on the user requested value.
5335                  *
5336                  * The value for state->max_bpc may not correctly updated
5337                  * depending on when the connector gets added to the state
5338                  * or if this was called outside of atomic check, so it
5339                  * can't be used directly.
5340                  */
5341                 bpc = min_t(u8, bpc, requested_bpc);
5342
5343                 /* Round down to the nearest even number. */
5344                 bpc = bpc - (bpc & 1);
5345         }
5346
5347         switch (bpc) {
5348         case 0:
5349                 /*
5350                  * Temporary Work around, DRM doesn't parse color depth for
5351                  * EDID revision before 1.4
5352                  * TODO: Fix edid parsing
5353                  */
5354                 return COLOR_DEPTH_888;
5355         case 6:
5356                 return COLOR_DEPTH_666;
5357         case 8:
5358                 return COLOR_DEPTH_888;
5359         case 10:
5360                 return COLOR_DEPTH_101010;
5361         case 12:
5362                 return COLOR_DEPTH_121212;
5363         case 14:
5364                 return COLOR_DEPTH_141414;
5365         case 16:
5366                 return COLOR_DEPTH_161616;
5367         default:
5368                 return COLOR_DEPTH_UNDEFINED;
5369         }
5370 }
5371
5372 static enum dc_aspect_ratio
5373 get_aspect_ratio(const struct drm_display_mode *mode_in)
5374 {
5375         /* 1-1 mapping, since both enums follow the HDMI spec. */
5376         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5377 }
5378
5379 static enum dc_color_space
5380 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing,
5381                        const struct drm_connector_state *connector_state)
5382 {
5383         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5384
5385         switch (connector_state->colorspace) {
5386         case DRM_MODE_COLORIMETRY_BT601_YCC:
5387                 if (dc_crtc_timing->flags.Y_ONLY)
5388                         color_space = COLOR_SPACE_YCBCR601_LIMITED;
5389                 else
5390                         color_space = COLOR_SPACE_YCBCR601;
5391                 break;
5392         case DRM_MODE_COLORIMETRY_BT709_YCC:
5393                 if (dc_crtc_timing->flags.Y_ONLY)
5394                         color_space = COLOR_SPACE_YCBCR709_LIMITED;
5395                 else
5396                         color_space = COLOR_SPACE_YCBCR709;
5397                 break;
5398         case DRM_MODE_COLORIMETRY_OPRGB:
5399                 color_space = COLOR_SPACE_ADOBERGB;
5400                 break;
5401         case DRM_MODE_COLORIMETRY_BT2020_RGB:
5402         case DRM_MODE_COLORIMETRY_BT2020_YCC:
5403                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
5404                         color_space = COLOR_SPACE_2020_RGB_FULLRANGE;
5405                 else
5406                         color_space = COLOR_SPACE_2020_YCBCR;
5407                 break;
5408         case DRM_MODE_COLORIMETRY_DEFAULT: // ITU601
5409         default:
5410                 if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) {
5411                         color_space = COLOR_SPACE_SRGB;
5412                 /*
5413                  * 27030khz is the separation point between HDTV and SDTV
5414                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5415                  * respectively
5416                  */
5417                 } else if (dc_crtc_timing->pix_clk_100hz > 270300) {
5418                         if (dc_crtc_timing->flags.Y_ONLY)
5419                                 color_space =
5420                                         COLOR_SPACE_YCBCR709_LIMITED;
5421                         else
5422                                 color_space = COLOR_SPACE_YCBCR709;
5423                 } else {
5424                         if (dc_crtc_timing->flags.Y_ONLY)
5425                                 color_space =
5426                                         COLOR_SPACE_YCBCR601_LIMITED;
5427                         else
5428                                 color_space = COLOR_SPACE_YCBCR601;
5429                 }
5430                 break;
5431         }
5432
5433         return color_space;
5434 }
5435
5436 static enum display_content_type
5437 get_output_content_type(const struct drm_connector_state *connector_state)
5438 {
5439         switch (connector_state->content_type) {
5440         default:
5441         case DRM_MODE_CONTENT_TYPE_NO_DATA:
5442                 return DISPLAY_CONTENT_TYPE_NO_DATA;
5443         case DRM_MODE_CONTENT_TYPE_GRAPHICS:
5444                 return DISPLAY_CONTENT_TYPE_GRAPHICS;
5445         case DRM_MODE_CONTENT_TYPE_PHOTO:
5446                 return DISPLAY_CONTENT_TYPE_PHOTO;
5447         case DRM_MODE_CONTENT_TYPE_CINEMA:
5448                 return DISPLAY_CONTENT_TYPE_CINEMA;
5449         case DRM_MODE_CONTENT_TYPE_GAME:
5450                 return DISPLAY_CONTENT_TYPE_GAME;
5451         }
5452 }
5453
5454 static bool adjust_colour_depth_from_display_info(
5455         struct dc_crtc_timing *timing_out,
5456         const struct drm_display_info *info)
5457 {
5458         enum dc_color_depth depth = timing_out->display_color_depth;
5459         int normalized_clk;
5460
5461         do {
5462                 normalized_clk = timing_out->pix_clk_100hz / 10;
5463                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5464                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5465                         normalized_clk /= 2;
5466                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5467                 switch (depth) {
5468                 case COLOR_DEPTH_888:
5469                         break;
5470                 case COLOR_DEPTH_101010:
5471                         normalized_clk = (normalized_clk * 30) / 24;
5472                         break;
5473                 case COLOR_DEPTH_121212:
5474                         normalized_clk = (normalized_clk * 36) / 24;
5475                         break;
5476                 case COLOR_DEPTH_161616:
5477                         normalized_clk = (normalized_clk * 48) / 24;
5478                         break;
5479                 default:
5480                         /* The above depths are the only ones valid for HDMI. */
5481                         return false;
5482                 }
5483                 if (normalized_clk <= info->max_tmds_clock) {
5484                         timing_out->display_color_depth = depth;
5485                         return true;
5486                 }
5487         } while (--depth > COLOR_DEPTH_666);
5488         return false;
5489 }
5490
5491 static void fill_stream_properties_from_drm_display_mode(
5492         struct dc_stream_state *stream,
5493         const struct drm_display_mode *mode_in,
5494         const struct drm_connector *connector,
5495         const struct drm_connector_state *connector_state,
5496         const struct dc_stream_state *old_stream,
5497         int requested_bpc)
5498 {
5499         struct dc_crtc_timing *timing_out = &stream->timing;
5500         const struct drm_display_info *info = &connector->display_info;
5501         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5502         struct hdmi_vendor_infoframe hv_frame;
5503         struct hdmi_avi_infoframe avi_frame;
5504
5505         memset(&hv_frame, 0, sizeof(hv_frame));
5506         memset(&avi_frame, 0, sizeof(avi_frame));
5507
5508         timing_out->h_border_left = 0;
5509         timing_out->h_border_right = 0;
5510         timing_out->v_border_top = 0;
5511         timing_out->v_border_bottom = 0;
5512         /* TODO: un-hardcode */
5513         if (drm_mode_is_420_only(info, mode_in)
5514                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5515                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5516         else if (drm_mode_is_420_also(info, mode_in)
5517                         && aconnector->force_yuv420_output)
5518                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5519         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5520                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5521                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5522         else
5523                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5524
5525         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5526         timing_out->display_color_depth = convert_color_depth_from_display_info(
5527                 connector,
5528                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5529                 requested_bpc);
5530         timing_out->scan_type = SCANNING_TYPE_NODATA;
5531         timing_out->hdmi_vic = 0;
5532
5533         if (old_stream) {
5534                 timing_out->vic = old_stream->timing.vic;
5535                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5536                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5537         } else {
5538                 timing_out->vic = drm_match_cea_mode(mode_in);
5539                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5540                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5541                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5542                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5543         }
5544
5545         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5546                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5547                 timing_out->vic = avi_frame.video_code;
5548                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5549                 timing_out->hdmi_vic = hv_frame.vic;
5550         }
5551
5552         if (is_freesync_video_mode(mode_in, aconnector)) {
5553                 timing_out->h_addressable = mode_in->hdisplay;
5554                 timing_out->h_total = mode_in->htotal;
5555                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5556                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5557                 timing_out->v_total = mode_in->vtotal;
5558                 timing_out->v_addressable = mode_in->vdisplay;
5559                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5560                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5561                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5562         } else {
5563                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5564                 timing_out->h_total = mode_in->crtc_htotal;
5565                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5566                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5567                 timing_out->v_total = mode_in->crtc_vtotal;
5568                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5569                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5570                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5571                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5572         }
5573
5574         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5575
5576         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5577         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5578         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5579                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5580                     drm_mode_is_420_also(info, mode_in) &&
5581                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5582                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5583                         adjust_colour_depth_from_display_info(timing_out, info);
5584                 }
5585         }
5586
5587         stream->output_color_space = get_output_color_space(timing_out, connector_state);
5588         stream->content_type = get_output_content_type(connector_state);
5589 }
5590
5591 static void fill_audio_info(struct audio_info *audio_info,
5592                             const struct drm_connector *drm_connector,
5593                             const struct dc_sink *dc_sink)
5594 {
5595         int i = 0;
5596         int cea_revision = 0;
5597         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5598
5599         audio_info->manufacture_id = edid_caps->manufacturer_id;
5600         audio_info->product_id = edid_caps->product_id;
5601
5602         cea_revision = drm_connector->display_info.cea_rev;
5603
5604         strscpy(audio_info->display_name,
5605                 edid_caps->display_name,
5606                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5607
5608         if (cea_revision >= 3) {
5609                 audio_info->mode_count = edid_caps->audio_mode_count;
5610
5611                 for (i = 0; i < audio_info->mode_count; ++i) {
5612                         audio_info->modes[i].format_code =
5613                                         (enum audio_format_code)
5614                                         (edid_caps->audio_modes[i].format_code);
5615                         audio_info->modes[i].channel_count =
5616                                         edid_caps->audio_modes[i].channel_count;
5617                         audio_info->modes[i].sample_rates.all =
5618                                         edid_caps->audio_modes[i].sample_rate;
5619                         audio_info->modes[i].sample_size =
5620                                         edid_caps->audio_modes[i].sample_size;
5621                 }
5622         }
5623
5624         audio_info->flags.all = edid_caps->speaker_flags;
5625
5626         /* TODO: We only check for the progressive mode, check for interlace mode too */
5627         if (drm_connector->latency_present[0]) {
5628                 audio_info->video_latency = drm_connector->video_latency[0];
5629                 audio_info->audio_latency = drm_connector->audio_latency[0];
5630         }
5631
5632         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5633
5634 }
5635
5636 static void
5637 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5638                                       struct drm_display_mode *dst_mode)
5639 {
5640         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5641         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5642         dst_mode->crtc_clock = src_mode->crtc_clock;
5643         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5644         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5645         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5646         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5647         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5648         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5649         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5650         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5651         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5652         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5653         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5654 }
5655
5656 static void
5657 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5658                                         const struct drm_display_mode *native_mode,
5659                                         bool scale_enabled)
5660 {
5661         if (scale_enabled) {
5662                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5663         } else if (native_mode->clock == drm_mode->clock &&
5664                         native_mode->htotal == drm_mode->htotal &&
5665                         native_mode->vtotal == drm_mode->vtotal) {
5666                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5667         } else {
5668                 /* no scaling nor amdgpu inserted, no need to patch */
5669         }
5670 }
5671
5672 static struct dc_sink *
5673 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5674 {
5675         struct dc_sink_init_data sink_init_data = { 0 };
5676         struct dc_sink *sink = NULL;
5677
5678         sink_init_data.link = aconnector->dc_link;
5679         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5680
5681         sink = dc_sink_create(&sink_init_data);
5682         if (!sink) {
5683                 DRM_ERROR("Failed to create sink!\n");
5684                 return NULL;
5685         }
5686         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5687
5688         return sink;
5689 }
5690
5691 static void set_multisync_trigger_params(
5692                 struct dc_stream_state *stream)
5693 {
5694         struct dc_stream_state *master = NULL;
5695
5696         if (stream->triggered_crtc_reset.enabled) {
5697                 master = stream->triggered_crtc_reset.event_source;
5698                 stream->triggered_crtc_reset.event =
5699                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5700                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5701                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5702         }
5703 }
5704
5705 static void set_master_stream(struct dc_stream_state *stream_set[],
5706                               int stream_count)
5707 {
5708         int j, highest_rfr = 0, master_stream = 0;
5709
5710         for (j = 0;  j < stream_count; j++) {
5711                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5712                         int refresh_rate = 0;
5713
5714                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5715                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5716                         if (refresh_rate > highest_rfr) {
5717                                 highest_rfr = refresh_rate;
5718                                 master_stream = j;
5719                         }
5720                 }
5721         }
5722         for (j = 0;  j < stream_count; j++) {
5723                 if (stream_set[j])
5724                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5725         }
5726 }
5727
5728 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5729 {
5730         int i = 0;
5731         struct dc_stream_state *stream;
5732
5733         if (context->stream_count < 2)
5734                 return;
5735         for (i = 0; i < context->stream_count ; i++) {
5736                 if (!context->streams[i])
5737                         continue;
5738                 /*
5739                  * TODO: add a function to read AMD VSDB bits and set
5740                  * crtc_sync_master.multi_sync_enabled flag
5741                  * For now it's set to false
5742                  */
5743         }
5744
5745         set_master_stream(context->streams, context->stream_count);
5746
5747         for (i = 0; i < context->stream_count ; i++) {
5748                 stream = context->streams[i];
5749
5750                 if (!stream)
5751                         continue;
5752
5753                 set_multisync_trigger_params(stream);
5754         }
5755 }
5756
5757 /**
5758  * DOC: FreeSync Video
5759  *
5760  * When a userspace application wants to play a video, the content follows a
5761  * standard format definition that usually specifies the FPS for that format.
5762  * The below list illustrates some video format and the expected FPS,
5763  * respectively:
5764  *
5765  * - TV/NTSC (23.976 FPS)
5766  * - Cinema (24 FPS)
5767  * - TV/PAL (25 FPS)
5768  * - TV/NTSC (29.97 FPS)
5769  * - TV/NTSC (30 FPS)
5770  * - Cinema HFR (48 FPS)
5771  * - TV/PAL (50 FPS)
5772  * - Commonly used (60 FPS)
5773  * - Multiples of 24 (48,72,96 FPS)
5774  *
5775  * The list of standards video format is not huge and can be added to the
5776  * connector modeset list beforehand. With that, userspace can leverage
5777  * FreeSync to extends the front porch in order to attain the target refresh
5778  * rate. Such a switch will happen seamlessly, without screen blanking or
5779  * reprogramming of the output in any other way. If the userspace requests a
5780  * modesetting change compatible with FreeSync modes that only differ in the
5781  * refresh rate, DC will skip the full update and avoid blink during the
5782  * transition. For example, the video player can change the modesetting from
5783  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5784  * causing any display blink. This same concept can be applied to a mode
5785  * setting change.
5786  */
5787 static struct drm_display_mode *
5788 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5789                 bool use_probed_modes)
5790 {
5791         struct drm_display_mode *m, *m_pref = NULL;
5792         u16 current_refresh, highest_refresh;
5793         struct list_head *list_head = use_probed_modes ?
5794                 &aconnector->base.probed_modes :
5795                 &aconnector->base.modes;
5796
5797         if (aconnector->freesync_vid_base.clock != 0)
5798                 return &aconnector->freesync_vid_base;
5799
5800         /* Find the preferred mode */
5801         list_for_each_entry(m, list_head, head) {
5802                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5803                         m_pref = m;
5804                         break;
5805                 }
5806         }
5807
5808         if (!m_pref) {
5809                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5810                 m_pref = list_first_entry_or_null(
5811                                 &aconnector->base.modes, struct drm_display_mode, head);
5812                 if (!m_pref) {
5813                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5814                         return NULL;
5815                 }
5816         }
5817
5818         highest_refresh = drm_mode_vrefresh(m_pref);
5819
5820         /*
5821          * Find the mode with highest refresh rate with same resolution.
5822          * For some monitors, preferred mode is not the mode with highest
5823          * supported refresh rate.
5824          */
5825         list_for_each_entry(m, list_head, head) {
5826                 current_refresh  = drm_mode_vrefresh(m);
5827
5828                 if (m->hdisplay == m_pref->hdisplay &&
5829                     m->vdisplay == m_pref->vdisplay &&
5830                     highest_refresh < current_refresh) {
5831                         highest_refresh = current_refresh;
5832                         m_pref = m;
5833                 }
5834         }
5835
5836         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5837         return m_pref;
5838 }
5839
5840 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5841                 struct amdgpu_dm_connector *aconnector)
5842 {
5843         struct drm_display_mode *high_mode;
5844         int timing_diff;
5845
5846         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5847         if (!high_mode || !mode)
5848                 return false;
5849
5850         timing_diff = high_mode->vtotal - mode->vtotal;
5851
5852         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5853             high_mode->hdisplay != mode->hdisplay ||
5854             high_mode->vdisplay != mode->vdisplay ||
5855             high_mode->hsync_start != mode->hsync_start ||
5856             high_mode->hsync_end != mode->hsync_end ||
5857             high_mode->htotal != mode->htotal ||
5858             high_mode->hskew != mode->hskew ||
5859             high_mode->vscan != mode->vscan ||
5860             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5861             high_mode->vsync_end - mode->vsync_end != timing_diff)
5862                 return false;
5863         else
5864                 return true;
5865 }
5866
5867 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5868                             struct dc_sink *sink, struct dc_stream_state *stream,
5869                             struct dsc_dec_dpcd_caps *dsc_caps)
5870 {
5871         stream->timing.flags.DSC = 0;
5872         dsc_caps->is_dsc_supported = false;
5873
5874         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5875             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5876                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5877                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5878                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5879                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5880                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5881                                 dsc_caps);
5882         }
5883 }
5884
5885
5886 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5887                                     struct dc_sink *sink, struct dc_stream_state *stream,
5888                                     struct dsc_dec_dpcd_caps *dsc_caps,
5889                                     uint32_t max_dsc_target_bpp_limit_override)
5890 {
5891         const struct dc_link_settings *verified_link_cap = NULL;
5892         u32 link_bw_in_kbps;
5893         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5894         struct dc *dc = sink->ctx->dc;
5895         struct dc_dsc_bw_range bw_range = {0};
5896         struct dc_dsc_config dsc_cfg = {0};
5897         struct dc_dsc_config_options dsc_options = {0};
5898
5899         dc_dsc_get_default_config_option(dc, &dsc_options);
5900         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5901
5902         verified_link_cap = dc_link_get_link_cap(stream->link);
5903         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5904         edp_min_bpp_x16 = 8 * 16;
5905         edp_max_bpp_x16 = 8 * 16;
5906
5907         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5908                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5909
5910         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5911                 edp_min_bpp_x16 = edp_max_bpp_x16;
5912
5913         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5914                                 dc->debug.dsc_min_slice_height_override,
5915                                 edp_min_bpp_x16, edp_max_bpp_x16,
5916                                 dsc_caps,
5917                                 &stream->timing,
5918                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5919                                 &bw_range)) {
5920
5921                 if (bw_range.max_kbps < link_bw_in_kbps) {
5922                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5923                                         dsc_caps,
5924                                         &dsc_options,
5925                                         0,
5926                                         &stream->timing,
5927                                         dc_link_get_highest_encoding_format(aconnector->dc_link),
5928                                         &dsc_cfg)) {
5929                                 stream->timing.dsc_cfg = dsc_cfg;
5930                                 stream->timing.flags.DSC = 1;
5931                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5932                         }
5933                         return;
5934                 }
5935         }
5936
5937         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5938                                 dsc_caps,
5939                                 &dsc_options,
5940                                 link_bw_in_kbps,
5941                                 &stream->timing,
5942                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5943                                 &dsc_cfg)) {
5944                 stream->timing.dsc_cfg = dsc_cfg;
5945                 stream->timing.flags.DSC = 1;
5946         }
5947 }
5948
5949
5950 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5951                                         struct dc_sink *sink, struct dc_stream_state *stream,
5952                                         struct dsc_dec_dpcd_caps *dsc_caps)
5953 {
5954         struct drm_connector *drm_connector = &aconnector->base;
5955         u32 link_bandwidth_kbps;
5956         struct dc *dc = sink->ctx->dc;
5957         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5958         u32 dsc_max_supported_bw_in_kbps;
5959         u32 max_dsc_target_bpp_limit_override =
5960                 drm_connector->display_info.max_dsc_bpp;
5961         struct dc_dsc_config_options dsc_options = {0};
5962
5963         dc_dsc_get_default_config_option(dc, &dsc_options);
5964         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5965
5966         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5967                                                         dc_link_get_link_cap(aconnector->dc_link));
5968
5969         /* Set DSC policy according to dsc_clock_en */
5970         dc_dsc_policy_set_enable_dsc_when_not_needed(
5971                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5972
5973         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5974             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5975             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5976
5977                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5978
5979         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5980                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5981                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5982                                                 dsc_caps,
5983                                                 &dsc_options,
5984                                                 link_bandwidth_kbps,
5985                                                 &stream->timing,
5986                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
5987                                                 &stream->timing.dsc_cfg)) {
5988                                 stream->timing.flags.DSC = 1;
5989                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5990                         }
5991                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5992                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing,
5993                                         dc_link_get_highest_encoding_format(aconnector->dc_link));
5994                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5995                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5996
5997                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5998                                         max_supported_bw_in_kbps > 0 &&
5999                                         dsc_max_supported_bw_in_kbps > 0)
6000                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
6001                                                 dsc_caps,
6002                                                 &dsc_options,
6003                                                 dsc_max_supported_bw_in_kbps,
6004                                                 &stream->timing,
6005                                                 dc_link_get_highest_encoding_format(aconnector->dc_link),
6006                                                 &stream->timing.dsc_cfg)) {
6007                                         stream->timing.flags.DSC = 1;
6008                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
6009                                                                          __func__, drm_connector->name);
6010                                 }
6011                 }
6012         }
6013
6014         /* Overwrite the stream flag if DSC is enabled through debugfs */
6015         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
6016                 stream->timing.flags.DSC = 1;
6017
6018         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
6019                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
6020
6021         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
6022                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
6023
6024         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
6025                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
6026 }
6027
6028 static struct dc_stream_state *
6029 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6030                        const struct drm_display_mode *drm_mode,
6031                        const struct dm_connector_state *dm_state,
6032                        const struct dc_stream_state *old_stream,
6033                        int requested_bpc)
6034 {
6035         struct drm_display_mode *preferred_mode = NULL;
6036         struct drm_connector *drm_connector;
6037         const struct drm_connector_state *con_state = &dm_state->base;
6038         struct dc_stream_state *stream = NULL;
6039         struct drm_display_mode mode;
6040         struct drm_display_mode saved_mode;
6041         struct drm_display_mode *freesync_mode = NULL;
6042         bool native_mode_found = false;
6043         bool recalculate_timing = false;
6044         bool scale = dm_state->scaling != RMX_OFF;
6045         int mode_refresh;
6046         int preferred_refresh = 0;
6047         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
6048         struct dsc_dec_dpcd_caps dsc_caps;
6049
6050         struct dc_sink *sink = NULL;
6051
6052         drm_mode_init(&mode, drm_mode);
6053         memset(&saved_mode, 0, sizeof(saved_mode));
6054
6055         if (aconnector == NULL) {
6056                 DRM_ERROR("aconnector is NULL!\n");
6057                 return stream;
6058         }
6059
6060         drm_connector = &aconnector->base;
6061
6062         if (!aconnector->dc_sink) {
6063                 sink = create_fake_sink(aconnector);
6064                 if (!sink)
6065                         return stream;
6066         } else {
6067                 sink = aconnector->dc_sink;
6068                 dc_sink_retain(sink);
6069         }
6070
6071         stream = dc_create_stream_for_sink(sink);
6072
6073         if (stream == NULL) {
6074                 DRM_ERROR("Failed to create stream for sink!\n");
6075                 goto finish;
6076         }
6077
6078         stream->dm_stream_context = aconnector;
6079
6080         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6081                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6082
6083         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6084                 /* Search for preferred mode */
6085                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6086                         native_mode_found = true;
6087                         break;
6088                 }
6089         }
6090         if (!native_mode_found)
6091                 preferred_mode = list_first_entry_or_null(
6092                                 &aconnector->base.modes,
6093                                 struct drm_display_mode,
6094                                 head);
6095
6096         mode_refresh = drm_mode_vrefresh(&mode);
6097
6098         if (preferred_mode == NULL) {
6099                 /*
6100                  * This may not be an error, the use case is when we have no
6101                  * usermode calls to reset and set mode upon hotplug. In this
6102                  * case, we call set mode ourselves to restore the previous mode
6103                  * and the modelist may not be filled in time.
6104                  */
6105                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6106         } else {
6107                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
6108                 if (recalculate_timing) {
6109                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6110                         drm_mode_copy(&saved_mode, &mode);
6111                         drm_mode_copy(&mode, freesync_mode);
6112                 } else {
6113                         decide_crtc_timing_for_drm_display_mode(
6114                                         &mode, preferred_mode, scale);
6115
6116                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6117                 }
6118         }
6119
6120         if (recalculate_timing)
6121                 drm_mode_set_crtcinfo(&saved_mode, 0);
6122
6123         /*
6124          * If scaling is enabled and refresh rate didn't change
6125          * we copy the vic and polarities of the old timings
6126          */
6127         if (!scale || mode_refresh != preferred_refresh)
6128                 fill_stream_properties_from_drm_display_mode(
6129                         stream, &mode, &aconnector->base, con_state, NULL,
6130                         requested_bpc);
6131         else
6132                 fill_stream_properties_from_drm_display_mode(
6133                         stream, &mode, &aconnector->base, con_state, old_stream,
6134                         requested_bpc);
6135
6136         if (aconnector->timing_changed) {
6137                 drm_dbg(aconnector->base.dev,
6138                         "overriding timing for automated test, bpc %d, changing to %d\n",
6139                         stream->timing.display_color_depth,
6140                         aconnector->timing_requested->display_color_depth);
6141                 stream->timing = *aconnector->timing_requested;
6142         }
6143
6144         /* SST DSC determination policy */
6145         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6146         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6147                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6148
6149         update_stream_scaling_settings(&mode, dm_state, stream);
6150
6151         fill_audio_info(
6152                 &stream->audio_info,
6153                 drm_connector,
6154                 sink);
6155
6156         update_stream_signal(stream, sink);
6157
6158         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6159                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6160
6161         if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
6162                 //
6163                 // should decide stream support vsc sdp colorimetry capability
6164                 // before building vsc info packet
6165                 //
6166                 stream->use_vsc_sdp_for_colorimetry = false;
6167                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6168                         stream->use_vsc_sdp_for_colorimetry =
6169                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6170                 } else {
6171                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6172                                 stream->use_vsc_sdp_for_colorimetry = true;
6173                 }
6174                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6175                         tf = TRANSFER_FUNC_GAMMA_22;
6176                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6177                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6178
6179         }
6180 finish:
6181         dc_sink_release(sink);
6182
6183         return stream;
6184 }
6185
6186 static enum drm_connector_status
6187 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6188 {
6189         bool connected;
6190         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6191
6192         /*
6193          * Notes:
6194          * 1. This interface is NOT called in context of HPD irq.
6195          * 2. This interface *is called* in context of user-mode ioctl. Which
6196          * makes it a bad place for *any* MST-related activity.
6197          */
6198
6199         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6200             !aconnector->fake_enable)
6201                 connected = (aconnector->dc_sink != NULL);
6202         else
6203                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6204                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6205
6206         update_subconnector_property(aconnector);
6207
6208         return (connected ? connector_status_connected :
6209                         connector_status_disconnected);
6210 }
6211
6212 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6213                                             struct drm_connector_state *connector_state,
6214                                             struct drm_property *property,
6215                                             uint64_t val)
6216 {
6217         struct drm_device *dev = connector->dev;
6218         struct amdgpu_device *adev = drm_to_adev(dev);
6219         struct dm_connector_state *dm_old_state =
6220                 to_dm_connector_state(connector->state);
6221         struct dm_connector_state *dm_new_state =
6222                 to_dm_connector_state(connector_state);
6223
6224         int ret = -EINVAL;
6225
6226         if (property == dev->mode_config.scaling_mode_property) {
6227                 enum amdgpu_rmx_type rmx_type;
6228
6229                 switch (val) {
6230                 case DRM_MODE_SCALE_CENTER:
6231                         rmx_type = RMX_CENTER;
6232                         break;
6233                 case DRM_MODE_SCALE_ASPECT:
6234                         rmx_type = RMX_ASPECT;
6235                         break;
6236                 case DRM_MODE_SCALE_FULLSCREEN:
6237                         rmx_type = RMX_FULL;
6238                         break;
6239                 case DRM_MODE_SCALE_NONE:
6240                 default:
6241                         rmx_type = RMX_OFF;
6242                         break;
6243                 }
6244
6245                 if (dm_old_state->scaling == rmx_type)
6246                         return 0;
6247
6248                 dm_new_state->scaling = rmx_type;
6249                 ret = 0;
6250         } else if (property == adev->mode_info.underscan_hborder_property) {
6251                 dm_new_state->underscan_hborder = val;
6252                 ret = 0;
6253         } else if (property == adev->mode_info.underscan_vborder_property) {
6254                 dm_new_state->underscan_vborder = val;
6255                 ret = 0;
6256         } else if (property == adev->mode_info.underscan_property) {
6257                 dm_new_state->underscan_enable = val;
6258                 ret = 0;
6259         } else if (property == adev->mode_info.abm_level_property) {
6260                 dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE;
6261                 ret = 0;
6262         }
6263
6264         return ret;
6265 }
6266
6267 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6268                                             const struct drm_connector_state *state,
6269                                             struct drm_property *property,
6270                                             uint64_t *val)
6271 {
6272         struct drm_device *dev = connector->dev;
6273         struct amdgpu_device *adev = drm_to_adev(dev);
6274         struct dm_connector_state *dm_state =
6275                 to_dm_connector_state(state);
6276         int ret = -EINVAL;
6277
6278         if (property == dev->mode_config.scaling_mode_property) {
6279                 switch (dm_state->scaling) {
6280                 case RMX_CENTER:
6281                         *val = DRM_MODE_SCALE_CENTER;
6282                         break;
6283                 case RMX_ASPECT:
6284                         *val = DRM_MODE_SCALE_ASPECT;
6285                         break;
6286                 case RMX_FULL:
6287                         *val = DRM_MODE_SCALE_FULLSCREEN;
6288                         break;
6289                 case RMX_OFF:
6290                 default:
6291                         *val = DRM_MODE_SCALE_NONE;
6292                         break;
6293                 }
6294                 ret = 0;
6295         } else if (property == adev->mode_info.underscan_hborder_property) {
6296                 *val = dm_state->underscan_hborder;
6297                 ret = 0;
6298         } else if (property == adev->mode_info.underscan_vborder_property) {
6299                 *val = dm_state->underscan_vborder;
6300                 ret = 0;
6301         } else if (property == adev->mode_info.underscan_property) {
6302                 *val = dm_state->underscan_enable;
6303                 ret = 0;
6304         } else if (property == adev->mode_info.abm_level_property) {
6305                 *val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE) ?
6306                         dm_state->abm_level : 0;
6307                 ret = 0;
6308         }
6309
6310         return ret;
6311 }
6312
6313 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6314 {
6315         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6316
6317         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6318 }
6319
6320 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6321 {
6322         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6323         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6324         struct amdgpu_display_manager *dm = &adev->dm;
6325
6326         /*
6327          * Call only if mst_mgr was initialized before since it's not done
6328          * for all connector types.
6329          */
6330         if (aconnector->mst_mgr.dev)
6331                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6332
6333         if (aconnector->bl_idx != -1) {
6334                 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6335                 dm->backlight_dev[aconnector->bl_idx] = NULL;
6336         }
6337
6338         if (aconnector->dc_em_sink)
6339                 dc_sink_release(aconnector->dc_em_sink);
6340         aconnector->dc_em_sink = NULL;
6341         if (aconnector->dc_sink)
6342                 dc_sink_release(aconnector->dc_sink);
6343         aconnector->dc_sink = NULL;
6344
6345         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6346         drm_connector_unregister(connector);
6347         drm_connector_cleanup(connector);
6348         if (aconnector->i2c) {
6349                 i2c_del_adapter(&aconnector->i2c->base);
6350                 kfree(aconnector->i2c);
6351         }
6352         kfree(aconnector->dm_dp_aux.aux.name);
6353
6354         kfree(connector);
6355 }
6356
6357 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6358 {
6359         struct dm_connector_state *state =
6360                 to_dm_connector_state(connector->state);
6361
6362         if (connector->state)
6363                 __drm_atomic_helper_connector_destroy_state(connector->state);
6364
6365         kfree(state);
6366
6367         state = kzalloc(sizeof(*state), GFP_KERNEL);
6368
6369         if (state) {
6370                 state->scaling = RMX_OFF;
6371                 state->underscan_enable = false;
6372                 state->underscan_hborder = 0;
6373                 state->underscan_vborder = 0;
6374                 state->base.max_requested_bpc = 8;
6375                 state->vcpi_slots = 0;
6376                 state->pbn = 0;
6377
6378                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6379                         state->abm_level = amdgpu_dm_abm_level ?:
6380                                 ABM_LEVEL_IMMEDIATE_DISABLE;
6381
6382                 __drm_atomic_helper_connector_reset(connector, &state->base);
6383         }
6384 }
6385
6386 struct drm_connector_state *
6387 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6388 {
6389         struct dm_connector_state *state =
6390                 to_dm_connector_state(connector->state);
6391
6392         struct dm_connector_state *new_state =
6393                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6394
6395         if (!new_state)
6396                 return NULL;
6397
6398         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6399
6400         new_state->freesync_capable = state->freesync_capable;
6401         new_state->abm_level = state->abm_level;
6402         new_state->scaling = state->scaling;
6403         new_state->underscan_enable = state->underscan_enable;
6404         new_state->underscan_hborder = state->underscan_hborder;
6405         new_state->underscan_vborder = state->underscan_vborder;
6406         new_state->vcpi_slots = state->vcpi_slots;
6407         new_state->pbn = state->pbn;
6408         return &new_state->base;
6409 }
6410
6411 static int
6412 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6413 {
6414         struct amdgpu_dm_connector *amdgpu_dm_connector =
6415                 to_amdgpu_dm_connector(connector);
6416         int r;
6417
6418         amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6419
6420         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6421             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6422                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6423                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6424                 if (r)
6425                         return r;
6426         }
6427
6428 #if defined(CONFIG_DEBUG_FS)
6429         connector_debugfs_init(amdgpu_dm_connector);
6430 #endif
6431
6432         return 0;
6433 }
6434
6435 static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector)
6436 {
6437         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6438         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
6439         struct dc_link *dc_link = aconnector->dc_link;
6440         struct dc_sink *dc_em_sink = aconnector->dc_em_sink;
6441         struct edid *edid;
6442
6443         /*
6444          * Note: drm_get_edid gets edid in the following order:
6445          * 1) override EDID if set via edid_override debugfs,
6446          * 2) firmware EDID if set via edid_firmware module parameter
6447          * 3) regular DDC read.
6448          */
6449         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6450         if (!edid) {
6451                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6452                 return;
6453         }
6454
6455         aconnector->edid = edid;
6456
6457         /* Update emulated (virtual) sink's EDID */
6458         if (dc_em_sink && dc_link) {
6459                 memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps));
6460                 memmove(dc_em_sink->dc_edid.raw_edid, edid, (edid->extensions + 1) * EDID_LENGTH);
6461                 dm_helpers_parse_edid_caps(
6462                         dc_link,
6463                         &dc_em_sink->dc_edid,
6464                         &dc_em_sink->edid_caps);
6465         }
6466 }
6467
6468 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6469         .reset = amdgpu_dm_connector_funcs_reset,
6470         .detect = amdgpu_dm_connector_detect,
6471         .fill_modes = drm_helper_probe_single_connector_modes,
6472         .destroy = amdgpu_dm_connector_destroy,
6473         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6474         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6475         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6476         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6477         .late_register = amdgpu_dm_connector_late_register,
6478         .early_unregister = amdgpu_dm_connector_unregister,
6479         .force = amdgpu_dm_connector_funcs_force
6480 };
6481
6482 static int get_modes(struct drm_connector *connector)
6483 {
6484         return amdgpu_dm_connector_get_modes(connector);
6485 }
6486
6487 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6488 {
6489         struct drm_connector *connector = &aconnector->base;
6490         struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(&aconnector->base);
6491         struct dc_sink_init_data init_params = {
6492                         .link = aconnector->dc_link,
6493                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6494         };
6495         struct edid *edid;
6496
6497         /*
6498          * Note: drm_get_edid gets edid in the following order:
6499          * 1) override EDID if set via edid_override debugfs,
6500          * 2) firmware EDID if set via edid_firmware module parameter
6501          * 3) regular DDC read.
6502          */
6503         edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc);
6504         if (!edid) {
6505                 DRM_ERROR("No EDID found on connector: %s.\n", connector->name);
6506                 return;
6507         }
6508
6509         if (drm_detect_hdmi_monitor(edid))
6510                 init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A;
6511
6512         aconnector->edid = edid;
6513
6514         aconnector->dc_em_sink = dc_link_add_remote_sink(
6515                 aconnector->dc_link,
6516                 (uint8_t *)edid,
6517                 (edid->extensions + 1) * EDID_LENGTH,
6518                 &init_params);
6519
6520         if (aconnector->base.force == DRM_FORCE_ON) {
6521                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6522                 aconnector->dc_link->local_sink :
6523                 aconnector->dc_em_sink;
6524                 dc_sink_retain(aconnector->dc_sink);
6525         }
6526 }
6527
6528 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6529 {
6530         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6531
6532         /*
6533          * In case of headless boot with force on for DP managed connector
6534          * Those settings have to be != 0 to get initial modeset
6535          */
6536         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6537                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6538                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6539         }
6540
6541         create_eml_sink(aconnector);
6542 }
6543
6544 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6545                                                 struct dc_stream_state *stream)
6546 {
6547         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6548         struct dc_plane_state *dc_plane_state = NULL;
6549         struct dc_state *dc_state = NULL;
6550
6551         if (!stream)
6552                 goto cleanup;
6553
6554         dc_plane_state = dc_create_plane_state(dc);
6555         if (!dc_plane_state)
6556                 goto cleanup;
6557
6558         dc_state = dc_create_state(dc);
6559         if (!dc_state)
6560                 goto cleanup;
6561
6562         /* populate stream to plane */
6563         dc_plane_state->src_rect.height  = stream->src.height;
6564         dc_plane_state->src_rect.width   = stream->src.width;
6565         dc_plane_state->dst_rect.height  = stream->src.height;
6566         dc_plane_state->dst_rect.width   = stream->src.width;
6567         dc_plane_state->clip_rect.height = stream->src.height;
6568         dc_plane_state->clip_rect.width  = stream->src.width;
6569         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6570         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6571         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6572         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6573         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6574         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6575         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6576         dc_plane_state->rotation = ROTATION_ANGLE_0;
6577         dc_plane_state->is_tiling_rotated = false;
6578         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6579
6580         dc_result = dc_validate_stream(dc, stream);
6581         if (dc_result == DC_OK)
6582                 dc_result = dc_validate_plane(dc, dc_plane_state);
6583
6584         if (dc_result == DC_OK)
6585                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6586
6587         if (dc_result == DC_OK && !dc_add_plane_to_context(
6588                                                 dc,
6589                                                 stream,
6590                                                 dc_plane_state,
6591                                                 dc_state))
6592                 dc_result = DC_FAIL_ATTACH_SURFACES;
6593
6594         if (dc_result == DC_OK)
6595                 dc_result = dc_validate_global_state(dc, dc_state, true);
6596
6597 cleanup:
6598         if (dc_state)
6599                 dc_release_state(dc_state);
6600
6601         if (dc_plane_state)
6602                 dc_plane_state_release(dc_plane_state);
6603
6604         return dc_result;
6605 }
6606
6607 struct dc_stream_state *
6608 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6609                                 const struct drm_display_mode *drm_mode,
6610                                 const struct dm_connector_state *dm_state,
6611                                 const struct dc_stream_state *old_stream)
6612 {
6613         struct drm_connector *connector = &aconnector->base;
6614         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6615         struct dc_stream_state *stream;
6616         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6617         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6618         enum dc_status dc_result = DC_OK;
6619
6620         do {
6621                 stream = create_stream_for_sink(aconnector, drm_mode,
6622                                                 dm_state, old_stream,
6623                                                 requested_bpc);
6624                 if (stream == NULL) {
6625                         DRM_ERROR("Failed to create stream for sink!\n");
6626                         break;
6627                 }
6628
6629                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6630                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6631                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6632
6633                 if (dc_result == DC_OK)
6634                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6635
6636                 if (dc_result != DC_OK) {
6637                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6638                                       drm_mode->hdisplay,
6639                                       drm_mode->vdisplay,
6640                                       drm_mode->clock,
6641                                       dc_result,
6642                                       dc_status_to_str(dc_result));
6643
6644                         dc_stream_release(stream);
6645                         stream = NULL;
6646                         requested_bpc -= 2; /* lower bpc to retry validation */
6647                 }
6648
6649         } while (stream == NULL && requested_bpc >= 6);
6650
6651         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6652                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6653
6654                 aconnector->force_yuv420_output = true;
6655                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6656                                                 dm_state, old_stream);
6657                 aconnector->force_yuv420_output = false;
6658         }
6659
6660         return stream;
6661 }
6662
6663 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6664                                    struct drm_display_mode *mode)
6665 {
6666         int result = MODE_ERROR;
6667         struct dc_sink *dc_sink;
6668         /* TODO: Unhardcode stream count */
6669         struct dc_stream_state *stream;
6670         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6671
6672         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6673                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6674                 return result;
6675
6676         /*
6677          * Only run this the first time mode_valid is called to initilialize
6678          * EDID mgmt
6679          */
6680         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6681                 !aconnector->dc_em_sink)
6682                 handle_edid_mgmt(aconnector);
6683
6684         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6685
6686         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6687                                 aconnector->base.force != DRM_FORCE_ON) {
6688                 DRM_ERROR("dc_sink is NULL!\n");
6689                 goto fail;
6690         }
6691
6692         drm_mode_set_crtcinfo(mode, 0);
6693
6694         stream = create_validate_stream_for_sink(aconnector, mode,
6695                                                  to_dm_connector_state(connector->state),
6696                                                  NULL);
6697         if (stream) {
6698                 dc_stream_release(stream);
6699                 result = MODE_OK;
6700         }
6701
6702 fail:
6703         /* TODO: error handling*/
6704         return result;
6705 }
6706
6707 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6708                                 struct dc_info_packet *out)
6709 {
6710         struct hdmi_drm_infoframe frame;
6711         unsigned char buf[30]; /* 26 + 4 */
6712         ssize_t len;
6713         int ret, i;
6714
6715         memset(out, 0, sizeof(*out));
6716
6717         if (!state->hdr_output_metadata)
6718                 return 0;
6719
6720         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6721         if (ret)
6722                 return ret;
6723
6724         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6725         if (len < 0)
6726                 return (int)len;
6727
6728         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6729         if (len != 30)
6730                 return -EINVAL;
6731
6732         /* Prepare the infopacket for DC. */
6733         switch (state->connector->connector_type) {
6734         case DRM_MODE_CONNECTOR_HDMIA:
6735                 out->hb0 = 0x87; /* type */
6736                 out->hb1 = 0x01; /* version */
6737                 out->hb2 = 0x1A; /* length */
6738                 out->sb[0] = buf[3]; /* checksum */
6739                 i = 1;
6740                 break;
6741
6742         case DRM_MODE_CONNECTOR_DisplayPort:
6743         case DRM_MODE_CONNECTOR_eDP:
6744                 out->hb0 = 0x00; /* sdp id, zero */
6745                 out->hb1 = 0x87; /* type */
6746                 out->hb2 = 0x1D; /* payload len - 1 */
6747                 out->hb3 = (0x13 << 2); /* sdp version */
6748                 out->sb[0] = 0x01; /* version */
6749                 out->sb[1] = 0x1A; /* length */
6750                 i = 2;
6751                 break;
6752
6753         default:
6754                 return -EINVAL;
6755         }
6756
6757         memcpy(&out->sb[i], &buf[4], 26);
6758         out->valid = true;
6759
6760         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6761                        sizeof(out->sb), false);
6762
6763         return 0;
6764 }
6765
6766 static int
6767 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6768                                  struct drm_atomic_state *state)
6769 {
6770         struct drm_connector_state *new_con_state =
6771                 drm_atomic_get_new_connector_state(state, conn);
6772         struct drm_connector_state *old_con_state =
6773                 drm_atomic_get_old_connector_state(state, conn);
6774         struct drm_crtc *crtc = new_con_state->crtc;
6775         struct drm_crtc_state *new_crtc_state;
6776         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6777         int ret;
6778
6779         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6780
6781         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6782                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6783                 if (ret < 0)
6784                         return ret;
6785         }
6786
6787         if (!crtc)
6788                 return 0;
6789
6790         if (new_con_state->colorspace != old_con_state->colorspace) {
6791                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6792                 if (IS_ERR(new_crtc_state))
6793                         return PTR_ERR(new_crtc_state);
6794
6795                 new_crtc_state->mode_changed = true;
6796         }
6797
6798         if (new_con_state->content_type != old_con_state->content_type) {
6799                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6800                 if (IS_ERR(new_crtc_state))
6801                         return PTR_ERR(new_crtc_state);
6802
6803                 new_crtc_state->mode_changed = true;
6804         }
6805
6806         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6807                 struct dc_info_packet hdr_infopacket;
6808
6809                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6810                 if (ret)
6811                         return ret;
6812
6813                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6814                 if (IS_ERR(new_crtc_state))
6815                         return PTR_ERR(new_crtc_state);
6816
6817                 /*
6818                  * DC considers the stream backends changed if the
6819                  * static metadata changes. Forcing the modeset also
6820                  * gives a simple way for userspace to switch from
6821                  * 8bpc to 10bpc when setting the metadata to enter
6822                  * or exit HDR.
6823                  *
6824                  * Changing the static metadata after it's been
6825                  * set is permissible, however. So only force a
6826                  * modeset if we're entering or exiting HDR.
6827                  */
6828                 new_crtc_state->mode_changed = new_crtc_state->mode_changed ||
6829                         !old_con_state->hdr_output_metadata ||
6830                         !new_con_state->hdr_output_metadata;
6831         }
6832
6833         return 0;
6834 }
6835
6836 static const struct drm_connector_helper_funcs
6837 amdgpu_dm_connector_helper_funcs = {
6838         /*
6839          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6840          * modes will be filtered by drm_mode_validate_size(), and those modes
6841          * are missing after user start lightdm. So we need to renew modes list.
6842          * in get_modes call back, not just return the modes count
6843          */
6844         .get_modes = get_modes,
6845         .mode_valid = amdgpu_dm_connector_mode_valid,
6846         .atomic_check = amdgpu_dm_connector_atomic_check,
6847 };
6848
6849 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6850 {
6851
6852 }
6853
6854 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6855 {
6856         switch (display_color_depth) {
6857         case COLOR_DEPTH_666:
6858                 return 6;
6859         case COLOR_DEPTH_888:
6860                 return 8;
6861         case COLOR_DEPTH_101010:
6862                 return 10;
6863         case COLOR_DEPTH_121212:
6864                 return 12;
6865         case COLOR_DEPTH_141414:
6866                 return 14;
6867         case COLOR_DEPTH_161616:
6868                 return 16;
6869         default:
6870                 break;
6871         }
6872         return 0;
6873 }
6874
6875 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6876                                           struct drm_crtc_state *crtc_state,
6877                                           struct drm_connector_state *conn_state)
6878 {
6879         struct drm_atomic_state *state = crtc_state->state;
6880         struct drm_connector *connector = conn_state->connector;
6881         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6882         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6883         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6884         struct drm_dp_mst_topology_mgr *mst_mgr;
6885         struct drm_dp_mst_port *mst_port;
6886         struct drm_dp_mst_topology_state *mst_state;
6887         enum dc_color_depth color_depth;
6888         int clock, bpp = 0;
6889         bool is_y420 = false;
6890
6891         if (!aconnector->mst_output_port)
6892                 return 0;
6893
6894         mst_port = aconnector->mst_output_port;
6895         mst_mgr = &aconnector->mst_root->mst_mgr;
6896
6897         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6898                 return 0;
6899
6900         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6901         if (IS_ERR(mst_state))
6902                 return PTR_ERR(mst_state);
6903
6904         if (!mst_state->pbn_div.full)
6905                 mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link));
6906
6907         if (!state->duplicated) {
6908                 int max_bpc = conn_state->max_requested_bpc;
6909
6910                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6911                           aconnector->force_yuv420_output;
6912                 color_depth = convert_color_depth_from_display_info(connector,
6913                                                                     is_y420,
6914                                                                     max_bpc);
6915                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6916                 clock = adjusted_mode->clock;
6917                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
6918         }
6919
6920         dm_new_connector_state->vcpi_slots =
6921                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6922                                               dm_new_connector_state->pbn);
6923         if (dm_new_connector_state->vcpi_slots < 0) {
6924                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6925                 return dm_new_connector_state->vcpi_slots;
6926         }
6927         return 0;
6928 }
6929
6930 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6931         .disable = dm_encoder_helper_disable,
6932         .atomic_check = dm_encoder_helper_atomic_check
6933 };
6934
6935 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6936                                             struct dc_state *dc_state,
6937                                             struct dsc_mst_fairness_vars *vars)
6938 {
6939         struct dc_stream_state *stream = NULL;
6940         struct drm_connector *connector;
6941         struct drm_connector_state *new_con_state;
6942         struct amdgpu_dm_connector *aconnector;
6943         struct dm_connector_state *dm_conn_state;
6944         int i, j, ret;
6945         int vcpi, pbn_div, pbn, slot_num = 0;
6946
6947         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6948
6949                 aconnector = to_amdgpu_dm_connector(connector);
6950
6951                 if (!aconnector->mst_output_port)
6952                         continue;
6953
6954                 if (!new_con_state || !new_con_state->crtc)
6955                         continue;
6956
6957                 dm_conn_state = to_dm_connector_state(new_con_state);
6958
6959                 for (j = 0; j < dc_state->stream_count; j++) {
6960                         stream = dc_state->streams[j];
6961                         if (!stream)
6962                                 continue;
6963
6964                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6965                                 break;
6966
6967                         stream = NULL;
6968                 }
6969
6970                 if (!stream)
6971                         continue;
6972
6973                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6974                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6975                 for (j = 0; j < dc_state->stream_count; j++) {
6976                         if (vars[j].aconnector == aconnector) {
6977                                 pbn = vars[j].pbn;
6978                                 break;
6979                         }
6980                 }
6981
6982                 if (j == dc_state->stream_count)
6983                         continue;
6984
6985                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6986
6987                 if (stream->timing.flags.DSC != 1) {
6988                         dm_conn_state->pbn = pbn;
6989                         dm_conn_state->vcpi_slots = slot_num;
6990
6991                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6992                                                            dm_conn_state->pbn, false);
6993                         if (ret < 0)
6994                                 return ret;
6995
6996                         continue;
6997                 }
6998
6999                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
7000                 if (vcpi < 0)
7001                         return vcpi;
7002
7003                 dm_conn_state->pbn = pbn;
7004                 dm_conn_state->vcpi_slots = vcpi;
7005         }
7006         return 0;
7007 }
7008
7009 static int to_drm_connector_type(enum signal_type st)
7010 {
7011         switch (st) {
7012         case SIGNAL_TYPE_HDMI_TYPE_A:
7013                 return DRM_MODE_CONNECTOR_HDMIA;
7014         case SIGNAL_TYPE_EDP:
7015                 return DRM_MODE_CONNECTOR_eDP;
7016         case SIGNAL_TYPE_LVDS:
7017                 return DRM_MODE_CONNECTOR_LVDS;
7018         case SIGNAL_TYPE_RGB:
7019                 return DRM_MODE_CONNECTOR_VGA;
7020         case SIGNAL_TYPE_DISPLAY_PORT:
7021         case SIGNAL_TYPE_DISPLAY_PORT_MST:
7022                 return DRM_MODE_CONNECTOR_DisplayPort;
7023         case SIGNAL_TYPE_DVI_DUAL_LINK:
7024         case SIGNAL_TYPE_DVI_SINGLE_LINK:
7025                 return DRM_MODE_CONNECTOR_DVID;
7026         case SIGNAL_TYPE_VIRTUAL:
7027                 return DRM_MODE_CONNECTOR_VIRTUAL;
7028
7029         default:
7030                 return DRM_MODE_CONNECTOR_Unknown;
7031         }
7032 }
7033
7034 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
7035 {
7036         struct drm_encoder *encoder;
7037
7038         /* There is only one encoder per connector */
7039         drm_connector_for_each_possible_encoder(connector, encoder)
7040                 return encoder;
7041
7042         return NULL;
7043 }
7044
7045 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
7046 {
7047         struct drm_encoder *encoder;
7048         struct amdgpu_encoder *amdgpu_encoder;
7049
7050         encoder = amdgpu_dm_connector_to_encoder(connector);
7051
7052         if (encoder == NULL)
7053                 return;
7054
7055         amdgpu_encoder = to_amdgpu_encoder(encoder);
7056
7057         amdgpu_encoder->native_mode.clock = 0;
7058
7059         if (!list_empty(&connector->probed_modes)) {
7060                 struct drm_display_mode *preferred_mode = NULL;
7061
7062                 list_for_each_entry(preferred_mode,
7063                                     &connector->probed_modes,
7064                                     head) {
7065                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
7066                                 amdgpu_encoder->native_mode = *preferred_mode;
7067
7068                         break;
7069                 }
7070
7071         }
7072 }
7073
7074 static struct drm_display_mode *
7075 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
7076                              char *name,
7077                              int hdisplay, int vdisplay)
7078 {
7079         struct drm_device *dev = encoder->dev;
7080         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7081         struct drm_display_mode *mode = NULL;
7082         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7083
7084         mode = drm_mode_duplicate(dev, native_mode);
7085
7086         if (mode == NULL)
7087                 return NULL;
7088
7089         mode->hdisplay = hdisplay;
7090         mode->vdisplay = vdisplay;
7091         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7092         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
7093
7094         return mode;
7095
7096 }
7097
7098 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
7099                                                  struct drm_connector *connector)
7100 {
7101         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
7102         struct drm_display_mode *mode = NULL;
7103         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
7104         struct amdgpu_dm_connector *amdgpu_dm_connector =
7105                                 to_amdgpu_dm_connector(connector);
7106         int i;
7107         int n;
7108         struct mode_size {
7109                 char name[DRM_DISPLAY_MODE_LEN];
7110                 int w;
7111                 int h;
7112         } common_modes[] = {
7113                 {  "640x480",  640,  480},
7114                 {  "800x600",  800,  600},
7115                 { "1024x768", 1024,  768},
7116                 { "1280x720", 1280,  720},
7117                 { "1280x800", 1280,  800},
7118                 {"1280x1024", 1280, 1024},
7119                 { "1440x900", 1440,  900},
7120                 {"1680x1050", 1680, 1050},
7121                 {"1600x1200", 1600, 1200},
7122                 {"1920x1080", 1920, 1080},
7123                 {"1920x1200", 1920, 1200}
7124         };
7125
7126         n = ARRAY_SIZE(common_modes);
7127
7128         for (i = 0; i < n; i++) {
7129                 struct drm_display_mode *curmode = NULL;
7130                 bool mode_existed = false;
7131
7132                 if (common_modes[i].w > native_mode->hdisplay ||
7133                     common_modes[i].h > native_mode->vdisplay ||
7134                    (common_modes[i].w == native_mode->hdisplay &&
7135                     common_modes[i].h == native_mode->vdisplay))
7136                         continue;
7137
7138                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7139                         if (common_modes[i].w == curmode->hdisplay &&
7140                             common_modes[i].h == curmode->vdisplay) {
7141                                 mode_existed = true;
7142                                 break;
7143                         }
7144                 }
7145
7146                 if (mode_existed)
7147                         continue;
7148
7149                 mode = amdgpu_dm_create_common_mode(encoder,
7150                                 common_modes[i].name, common_modes[i].w,
7151                                 common_modes[i].h);
7152                 if (!mode)
7153                         continue;
7154
7155                 drm_mode_probed_add(connector, mode);
7156                 amdgpu_dm_connector->num_modes++;
7157         }
7158 }
7159
7160 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7161 {
7162         struct drm_encoder *encoder;
7163         struct amdgpu_encoder *amdgpu_encoder;
7164         const struct drm_display_mode *native_mode;
7165
7166         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7167             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7168                 return;
7169
7170         mutex_lock(&connector->dev->mode_config.mutex);
7171         amdgpu_dm_connector_get_modes(connector);
7172         mutex_unlock(&connector->dev->mode_config.mutex);
7173
7174         encoder = amdgpu_dm_connector_to_encoder(connector);
7175         if (!encoder)
7176                 return;
7177
7178         amdgpu_encoder = to_amdgpu_encoder(encoder);
7179
7180         native_mode = &amdgpu_encoder->native_mode;
7181         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7182                 return;
7183
7184         drm_connector_set_panel_orientation_with_quirk(connector,
7185                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7186                                                        native_mode->hdisplay,
7187                                                        native_mode->vdisplay);
7188 }
7189
7190 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7191                                               struct edid *edid)
7192 {
7193         struct amdgpu_dm_connector *amdgpu_dm_connector =
7194                         to_amdgpu_dm_connector(connector);
7195
7196         if (edid) {
7197                 /* empty probed_modes */
7198                 INIT_LIST_HEAD(&connector->probed_modes);
7199                 amdgpu_dm_connector->num_modes =
7200                                 drm_add_edid_modes(connector, edid);
7201
7202                 /* sorting the probed modes before calling function
7203                  * amdgpu_dm_get_native_mode() since EDID can have
7204                  * more than one preferred mode. The modes that are
7205                  * later in the probed mode list could be of higher
7206                  * and preferred resolution. For example, 3840x2160
7207                  * resolution in base EDID preferred timing and 4096x2160
7208                  * preferred resolution in DID extension block later.
7209                  */
7210                 drm_mode_sort(&connector->probed_modes);
7211                 amdgpu_dm_get_native_mode(connector);
7212
7213                 /* Freesync capabilities are reset by calling
7214                  * drm_add_edid_modes() and need to be
7215                  * restored here.
7216                  */
7217                 amdgpu_dm_update_freesync_caps(connector, edid);
7218         } else {
7219                 amdgpu_dm_connector->num_modes = 0;
7220         }
7221 }
7222
7223 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7224                               struct drm_display_mode *mode)
7225 {
7226         struct drm_display_mode *m;
7227
7228         list_for_each_entry(m, &aconnector->base.probed_modes, head) {
7229                 if (drm_mode_equal(m, mode))
7230                         return true;
7231         }
7232
7233         return false;
7234 }
7235
7236 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7237 {
7238         const struct drm_display_mode *m;
7239         struct drm_display_mode *new_mode;
7240         uint i;
7241         u32 new_modes_count = 0;
7242
7243         /* Standard FPS values
7244          *
7245          * 23.976       - TV/NTSC
7246          * 24           - Cinema
7247          * 25           - TV/PAL
7248          * 29.97        - TV/NTSC
7249          * 30           - TV/NTSC
7250          * 48           - Cinema HFR
7251          * 50           - TV/PAL
7252          * 60           - Commonly used
7253          * 48,72,96,120 - Multiples of 24
7254          */
7255         static const u32 common_rates[] = {
7256                 23976, 24000, 25000, 29970, 30000,
7257                 48000, 50000, 60000, 72000, 96000, 120000
7258         };
7259
7260         /*
7261          * Find mode with highest refresh rate with the same resolution
7262          * as the preferred mode. Some monitors report a preferred mode
7263          * with lower resolution than the highest refresh rate supported.
7264          */
7265
7266         m = get_highest_refresh_rate_mode(aconnector, true);
7267         if (!m)
7268                 return 0;
7269
7270         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7271                 u64 target_vtotal, target_vtotal_diff;
7272                 u64 num, den;
7273
7274                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7275                         continue;
7276
7277                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7278                     common_rates[i] > aconnector->max_vfreq * 1000)
7279                         continue;
7280
7281                 num = (unsigned long long)m->clock * 1000 * 1000;
7282                 den = common_rates[i] * (unsigned long long)m->htotal;
7283                 target_vtotal = div_u64(num, den);
7284                 target_vtotal_diff = target_vtotal - m->vtotal;
7285
7286                 /* Check for illegal modes */
7287                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7288                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7289                     m->vtotal + target_vtotal_diff < m->vsync_end)
7290                         continue;
7291
7292                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7293                 if (!new_mode)
7294                         goto out;
7295
7296                 new_mode->vtotal += (u16)target_vtotal_diff;
7297                 new_mode->vsync_start += (u16)target_vtotal_diff;
7298                 new_mode->vsync_end += (u16)target_vtotal_diff;
7299                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7300                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7301
7302                 if (!is_duplicate_mode(aconnector, new_mode)) {
7303                         drm_mode_probed_add(&aconnector->base, new_mode);
7304                         new_modes_count += 1;
7305                 } else
7306                         drm_mode_destroy(aconnector->base.dev, new_mode);
7307         }
7308  out:
7309         return new_modes_count;
7310 }
7311
7312 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7313                                                    struct edid *edid)
7314 {
7315         struct amdgpu_dm_connector *amdgpu_dm_connector =
7316                 to_amdgpu_dm_connector(connector);
7317
7318         if (!edid)
7319                 return;
7320
7321         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7322                 amdgpu_dm_connector->num_modes +=
7323                         add_fs_modes(amdgpu_dm_connector);
7324 }
7325
7326 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7327 {
7328         struct amdgpu_dm_connector *amdgpu_dm_connector =
7329                         to_amdgpu_dm_connector(connector);
7330         struct drm_encoder *encoder;
7331         struct edid *edid = amdgpu_dm_connector->edid;
7332         struct dc_link_settings *verified_link_cap =
7333                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7334         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7335
7336         encoder = amdgpu_dm_connector_to_encoder(connector);
7337
7338         if (!drm_edid_is_valid(edid)) {
7339                 amdgpu_dm_connector->num_modes =
7340                                 drm_add_modes_noedid(connector, 640, 480);
7341                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7342                         amdgpu_dm_connector->num_modes +=
7343                                 drm_add_modes_noedid(connector, 1920, 1080);
7344         } else {
7345                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7346                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7347                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7348         }
7349         amdgpu_dm_fbc_init(connector);
7350
7351         return amdgpu_dm_connector->num_modes;
7352 }
7353
7354 static const u32 supported_colorspaces =
7355         BIT(DRM_MODE_COLORIMETRY_BT709_YCC) |
7356         BIT(DRM_MODE_COLORIMETRY_OPRGB) |
7357         BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
7358         BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
7359
7360 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7361                                      struct amdgpu_dm_connector *aconnector,
7362                                      int connector_type,
7363                                      struct dc_link *link,
7364                                      int link_index)
7365 {
7366         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7367
7368         /*
7369          * Some of the properties below require access to state, like bpc.
7370          * Allocate some default initial connector state with our reset helper.
7371          */
7372         if (aconnector->base.funcs->reset)
7373                 aconnector->base.funcs->reset(&aconnector->base);
7374
7375         aconnector->connector_id = link_index;
7376         aconnector->bl_idx = -1;
7377         aconnector->dc_link = link;
7378         aconnector->base.interlace_allowed = false;
7379         aconnector->base.doublescan_allowed = false;
7380         aconnector->base.stereo_allowed = false;
7381         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7382         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7383         aconnector->audio_inst = -1;
7384         aconnector->pack_sdp_v1_3 = false;
7385         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7386         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7387         mutex_init(&aconnector->hpd_lock);
7388         mutex_init(&aconnector->handle_mst_msg_ready);
7389
7390         /*
7391          * configure support HPD hot plug connector_>polled default value is 0
7392          * which means HPD hot plug not supported
7393          */
7394         switch (connector_type) {
7395         case DRM_MODE_CONNECTOR_HDMIA:
7396                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7397                 aconnector->base.ycbcr_420_allowed =
7398                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7399                 break;
7400         case DRM_MODE_CONNECTOR_DisplayPort:
7401                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7402                 link->link_enc = link_enc_cfg_get_link_enc(link);
7403                 ASSERT(link->link_enc);
7404                 if (link->link_enc)
7405                         aconnector->base.ycbcr_420_allowed =
7406                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7407                 break;
7408         case DRM_MODE_CONNECTOR_DVID:
7409                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7410                 break;
7411         default:
7412                 break;
7413         }
7414
7415         drm_object_attach_property(&aconnector->base.base,
7416                                 dm->ddev->mode_config.scaling_mode_property,
7417                                 DRM_MODE_SCALE_NONE);
7418
7419         drm_object_attach_property(&aconnector->base.base,
7420                                 adev->mode_info.underscan_property,
7421                                 UNDERSCAN_OFF);
7422         drm_object_attach_property(&aconnector->base.base,
7423                                 adev->mode_info.underscan_hborder_property,
7424                                 0);
7425         drm_object_attach_property(&aconnector->base.base,
7426                                 adev->mode_info.underscan_vborder_property,
7427                                 0);
7428
7429         if (!aconnector->mst_root)
7430                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7431
7432         aconnector->base.state->max_bpc = 16;
7433         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7434
7435         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7436             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7437                 drm_object_attach_property(&aconnector->base.base,
7438                                 adev->mode_info.abm_level_property, 0);
7439         }
7440
7441         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7442                 /* Content Type is currently only implemented for HDMI. */
7443                 drm_connector_attach_content_type_property(&aconnector->base);
7444         }
7445
7446         if (connector_type == DRM_MODE_CONNECTOR_HDMIA) {
7447                 if (!drm_mode_create_hdmi_colorspace_property(&aconnector->base, supported_colorspaces))
7448                         drm_connector_attach_colorspace_property(&aconnector->base);
7449         } else if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root) ||
7450                    connector_type == DRM_MODE_CONNECTOR_eDP) {
7451                 if (!drm_mode_create_dp_colorspace_property(&aconnector->base, supported_colorspaces))
7452                         drm_connector_attach_colorspace_property(&aconnector->base);
7453         }
7454
7455         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7456             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7457             connector_type == DRM_MODE_CONNECTOR_eDP) {
7458                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7459
7460                 if (!aconnector->mst_root)
7461                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7462
7463                 if (adev->dm.hdcp_workqueue)
7464                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7465         }
7466 }
7467
7468 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7469                               struct i2c_msg *msgs, int num)
7470 {
7471         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7472         struct ddc_service *ddc_service = i2c->ddc_service;
7473         struct i2c_command cmd;
7474         int i;
7475         int result = -EIO;
7476
7477         if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
7478                 return result;
7479
7480         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7481
7482         if (!cmd.payloads)
7483                 return result;
7484
7485         cmd.number_of_payloads = num;
7486         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7487         cmd.speed = 100;
7488
7489         for (i = 0; i < num; i++) {
7490                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7491                 cmd.payloads[i].address = msgs[i].addr;
7492                 cmd.payloads[i].length = msgs[i].len;
7493                 cmd.payloads[i].data = msgs[i].buf;
7494         }
7495
7496         if (dc_submit_i2c(
7497                         ddc_service->ctx->dc,
7498                         ddc_service->link->link_index,
7499                         &cmd))
7500                 result = num;
7501
7502         kfree(cmd.payloads);
7503         return result;
7504 }
7505
7506 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7507 {
7508         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7509 }
7510
7511 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7512         .master_xfer = amdgpu_dm_i2c_xfer,
7513         .functionality = amdgpu_dm_i2c_func,
7514 };
7515
7516 static struct amdgpu_i2c_adapter *
7517 create_i2c(struct ddc_service *ddc_service,
7518            int link_index,
7519            int *res)
7520 {
7521         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7522         struct amdgpu_i2c_adapter *i2c;
7523
7524         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7525         if (!i2c)
7526                 return NULL;
7527         i2c->base.owner = THIS_MODULE;
7528         i2c->base.class = I2C_CLASS_DDC;
7529         i2c->base.dev.parent = &adev->pdev->dev;
7530         i2c->base.algo = &amdgpu_dm_i2c_algo;
7531         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7532         i2c_set_adapdata(&i2c->base, i2c);
7533         i2c->ddc_service = ddc_service;
7534
7535         return i2c;
7536 }
7537
7538
7539 /*
7540  * Note: this function assumes that dc_link_detect() was called for the
7541  * dc_link which will be represented by this aconnector.
7542  */
7543 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7544                                     struct amdgpu_dm_connector *aconnector,
7545                                     u32 link_index,
7546                                     struct amdgpu_encoder *aencoder)
7547 {
7548         int res = 0;
7549         int connector_type;
7550         struct dc *dc = dm->dc;
7551         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7552         struct amdgpu_i2c_adapter *i2c;
7553
7554         link->priv = aconnector;
7555
7556
7557         i2c = create_i2c(link->ddc, link->link_index, &res);
7558         if (!i2c) {
7559                 DRM_ERROR("Failed to create i2c adapter data\n");
7560                 return -ENOMEM;
7561         }
7562
7563         aconnector->i2c = i2c;
7564         res = i2c_add_adapter(&i2c->base);
7565
7566         if (res) {
7567                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7568                 goto out_free;
7569         }
7570
7571         connector_type = to_drm_connector_type(link->connector_signal);
7572
7573         res = drm_connector_init_with_ddc(
7574                         dm->ddev,
7575                         &aconnector->base,
7576                         &amdgpu_dm_connector_funcs,
7577                         connector_type,
7578                         &i2c->base);
7579
7580         if (res) {
7581                 DRM_ERROR("connector_init failed\n");
7582                 aconnector->connector_id = -1;
7583                 goto out_free;
7584         }
7585
7586         drm_connector_helper_add(
7587                         &aconnector->base,
7588                         &amdgpu_dm_connector_helper_funcs);
7589
7590         amdgpu_dm_connector_init_helper(
7591                 dm,
7592                 aconnector,
7593                 connector_type,
7594                 link,
7595                 link_index);
7596
7597         drm_connector_attach_encoder(
7598                 &aconnector->base, &aencoder->base);
7599
7600         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7601                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7602                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7603
7604 out_free:
7605         if (res) {
7606                 kfree(i2c);
7607                 aconnector->i2c = NULL;
7608         }
7609         return res;
7610 }
7611
7612 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7613 {
7614         switch (adev->mode_info.num_crtc) {
7615         case 1:
7616                 return 0x1;
7617         case 2:
7618                 return 0x3;
7619         case 3:
7620                 return 0x7;
7621         case 4:
7622                 return 0xf;
7623         case 5:
7624                 return 0x1f;
7625         case 6:
7626         default:
7627                 return 0x3f;
7628         }
7629 }
7630
7631 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7632                                   struct amdgpu_encoder *aencoder,
7633                                   uint32_t link_index)
7634 {
7635         struct amdgpu_device *adev = drm_to_adev(dev);
7636
7637         int res = drm_encoder_init(dev,
7638                                    &aencoder->base,
7639                                    &amdgpu_dm_encoder_funcs,
7640                                    DRM_MODE_ENCODER_TMDS,
7641                                    NULL);
7642
7643         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7644
7645         if (!res)
7646                 aencoder->encoder_id = link_index;
7647         else
7648                 aencoder->encoder_id = -1;
7649
7650         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7651
7652         return res;
7653 }
7654
7655 static void manage_dm_interrupts(struct amdgpu_device *adev,
7656                                  struct amdgpu_crtc *acrtc,
7657                                  bool enable)
7658 {
7659         /*
7660          * We have no guarantee that the frontend index maps to the same
7661          * backend index - some even map to more than one.
7662          *
7663          * TODO: Use a different interrupt or check DC itself for the mapping.
7664          */
7665         int irq_type =
7666                 amdgpu_display_crtc_idx_to_irq_type(
7667                         adev,
7668                         acrtc->crtc_id);
7669
7670         if (enable) {
7671                 drm_crtc_vblank_on(&acrtc->base);
7672                 amdgpu_irq_get(
7673                         adev,
7674                         &adev->pageflip_irq,
7675                         irq_type);
7676 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7677                 amdgpu_irq_get(
7678                         adev,
7679                         &adev->vline0_irq,
7680                         irq_type);
7681 #endif
7682         } else {
7683 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7684                 amdgpu_irq_put(
7685                         adev,
7686                         &adev->vline0_irq,
7687                         irq_type);
7688 #endif
7689                 amdgpu_irq_put(
7690                         adev,
7691                         &adev->pageflip_irq,
7692                         irq_type);
7693                 drm_crtc_vblank_off(&acrtc->base);
7694         }
7695 }
7696
7697 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7698                                       struct amdgpu_crtc *acrtc)
7699 {
7700         int irq_type =
7701                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7702
7703         /**
7704          * This reads the current state for the IRQ and force reapplies
7705          * the setting to hardware.
7706          */
7707         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7708 }
7709
7710 static bool
7711 is_scaling_state_different(const struct dm_connector_state *dm_state,
7712                            const struct dm_connector_state *old_dm_state)
7713 {
7714         if (dm_state->scaling != old_dm_state->scaling)
7715                 return true;
7716         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7717                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7718                         return true;
7719         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7720                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7721                         return true;
7722         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7723                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7724                 return true;
7725         return false;
7726 }
7727
7728 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7729                                             struct drm_crtc_state *old_crtc_state,
7730                                             struct drm_connector_state *new_conn_state,
7731                                             struct drm_connector_state *old_conn_state,
7732                                             const struct drm_connector *connector,
7733                                             struct hdcp_workqueue *hdcp_w)
7734 {
7735         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7736         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7737
7738         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7739                 connector->index, connector->status, connector->dpms);
7740         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7741                 old_conn_state->content_protection, new_conn_state->content_protection);
7742
7743         if (old_crtc_state)
7744                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7745                 old_crtc_state->enable,
7746                 old_crtc_state->active,
7747                 old_crtc_state->mode_changed,
7748                 old_crtc_state->active_changed,
7749                 old_crtc_state->connectors_changed);
7750
7751         if (new_crtc_state)
7752                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7753                 new_crtc_state->enable,
7754                 new_crtc_state->active,
7755                 new_crtc_state->mode_changed,
7756                 new_crtc_state->active_changed,
7757                 new_crtc_state->connectors_changed);
7758
7759         /* hdcp content type change */
7760         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7761             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7762                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7763                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7764                 return true;
7765         }
7766
7767         /* CP is being re enabled, ignore this */
7768         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7769             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7770                 if (new_crtc_state && new_crtc_state->mode_changed) {
7771                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7772                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7773                         return true;
7774                 }
7775                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7776                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7777                 return false;
7778         }
7779
7780         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7781          *
7782          * Handles:     UNDESIRED -> ENABLED
7783          */
7784         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7785             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7786                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7787
7788         /* Stream removed and re-enabled
7789          *
7790          * Can sometimes overlap with the HPD case,
7791          * thus set update_hdcp to false to avoid
7792          * setting HDCP multiple times.
7793          *
7794          * Handles:     DESIRED -> DESIRED (Special case)
7795          */
7796         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7797                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7798                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7799                 dm_con_state->update_hdcp = false;
7800                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7801                         __func__);
7802                 return true;
7803         }
7804
7805         /* Hot-plug, headless s3, dpms
7806          *
7807          * Only start HDCP if the display is connected/enabled.
7808          * update_hdcp flag will be set to false until the next
7809          * HPD comes in.
7810          *
7811          * Handles:     DESIRED -> DESIRED (Special case)
7812          */
7813         if (dm_con_state->update_hdcp &&
7814         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7815         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7816                 dm_con_state->update_hdcp = false;
7817                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7818                         __func__);
7819                 return true;
7820         }
7821
7822         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7823                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7824                         if (new_crtc_state && new_crtc_state->mode_changed) {
7825                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7826                                         __func__);
7827                                 return true;
7828                         }
7829                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7830                                 __func__);
7831                         return false;
7832                 }
7833
7834                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7835                 return false;
7836         }
7837
7838         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7839                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7840                         __func__);
7841                 return true;
7842         }
7843
7844         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7845         return false;
7846 }
7847
7848 static void remove_stream(struct amdgpu_device *adev,
7849                           struct amdgpu_crtc *acrtc,
7850                           struct dc_stream_state *stream)
7851 {
7852         /* this is the update mode case */
7853
7854         acrtc->otg_inst = -1;
7855         acrtc->enabled = false;
7856 }
7857
7858 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7859 {
7860
7861         assert_spin_locked(&acrtc->base.dev->event_lock);
7862         WARN_ON(acrtc->event);
7863
7864         acrtc->event = acrtc->base.state->event;
7865
7866         /* Set the flip status */
7867         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7868
7869         /* Mark this event as consumed */
7870         acrtc->base.state->event = NULL;
7871
7872         drm_dbg_state(acrtc->base.dev,
7873                       "crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7874                       acrtc->crtc_id);
7875 }
7876
7877 static void update_freesync_state_on_stream(
7878         struct amdgpu_display_manager *dm,
7879         struct dm_crtc_state *new_crtc_state,
7880         struct dc_stream_state *new_stream,
7881         struct dc_plane_state *surface,
7882         u32 flip_timestamp_in_us)
7883 {
7884         struct mod_vrr_params vrr_params;
7885         struct dc_info_packet vrr_infopacket = {0};
7886         struct amdgpu_device *adev = dm->adev;
7887         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7888         unsigned long flags;
7889         bool pack_sdp_v1_3 = false;
7890         struct amdgpu_dm_connector *aconn;
7891         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7892
7893         if (!new_stream)
7894                 return;
7895
7896         /*
7897          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7898          * For now it's sufficient to just guard against these conditions.
7899          */
7900
7901         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7902                 return;
7903
7904         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7905         vrr_params = acrtc->dm_irq_params.vrr_params;
7906
7907         if (surface) {
7908                 mod_freesync_handle_preflip(
7909                         dm->freesync_module,
7910                         surface,
7911                         new_stream,
7912                         flip_timestamp_in_us,
7913                         &vrr_params);
7914
7915                 if (adev->family < AMDGPU_FAMILY_AI &&
7916                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7917                         mod_freesync_handle_v_update(dm->freesync_module,
7918                                                      new_stream, &vrr_params);
7919
7920                         /* Need to call this before the frame ends. */
7921                         dc_stream_adjust_vmin_vmax(dm->dc,
7922                                                    new_crtc_state->stream,
7923                                                    &vrr_params.adjust);
7924                 }
7925         }
7926
7927         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7928
7929         if (aconn && (aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST || aconn->vsdb_info.replay_mode)) {
7930                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7931
7932                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7933                         packet_type = PACKET_TYPE_FS_V1;
7934                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7935                         packet_type = PACKET_TYPE_FS_V2;
7936                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7937                         packet_type = PACKET_TYPE_FS_V3;
7938
7939                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7940                                         &new_stream->adaptive_sync_infopacket);
7941         }
7942
7943         mod_freesync_build_vrr_infopacket(
7944                 dm->freesync_module,
7945                 new_stream,
7946                 &vrr_params,
7947                 packet_type,
7948                 TRANSFER_FUNC_UNKNOWN,
7949                 &vrr_infopacket,
7950                 pack_sdp_v1_3);
7951
7952         new_crtc_state->freesync_vrr_info_changed |=
7953                 (memcmp(&new_crtc_state->vrr_infopacket,
7954                         &vrr_infopacket,
7955                         sizeof(vrr_infopacket)) != 0);
7956
7957         acrtc->dm_irq_params.vrr_params = vrr_params;
7958         new_crtc_state->vrr_infopacket = vrr_infopacket;
7959
7960         new_stream->vrr_infopacket = vrr_infopacket;
7961         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7962
7963         if (new_crtc_state->freesync_vrr_info_changed)
7964                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7965                               new_crtc_state->base.crtc->base.id,
7966                               (int)new_crtc_state->base.vrr_enabled,
7967                               (int)vrr_params.state);
7968
7969         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7970 }
7971
7972 static void update_stream_irq_parameters(
7973         struct amdgpu_display_manager *dm,
7974         struct dm_crtc_state *new_crtc_state)
7975 {
7976         struct dc_stream_state *new_stream = new_crtc_state->stream;
7977         struct mod_vrr_params vrr_params;
7978         struct mod_freesync_config config = new_crtc_state->freesync_config;
7979         struct amdgpu_device *adev = dm->adev;
7980         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7981         unsigned long flags;
7982
7983         if (!new_stream)
7984                 return;
7985
7986         /*
7987          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7988          * For now it's sufficient to just guard against these conditions.
7989          */
7990         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7991                 return;
7992
7993         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7994         vrr_params = acrtc->dm_irq_params.vrr_params;
7995
7996         if (new_crtc_state->vrr_supported &&
7997             config.min_refresh_in_uhz &&
7998             config.max_refresh_in_uhz) {
7999                 /*
8000                  * if freesync compatible mode was set, config.state will be set
8001                  * in atomic check
8002                  */
8003                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
8004                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
8005                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
8006                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
8007                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
8008                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
8009                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
8010                 } else {
8011                         config.state = new_crtc_state->base.vrr_enabled ?
8012                                                      VRR_STATE_ACTIVE_VARIABLE :
8013                                                      VRR_STATE_INACTIVE;
8014                 }
8015         } else {
8016                 config.state = VRR_STATE_UNSUPPORTED;
8017         }
8018
8019         mod_freesync_build_vrr_params(dm->freesync_module,
8020                                       new_stream,
8021                                       &config, &vrr_params);
8022
8023         new_crtc_state->freesync_config = config;
8024         /* Copy state for access from DM IRQ handler */
8025         acrtc->dm_irq_params.freesync_config = config;
8026         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
8027         acrtc->dm_irq_params.vrr_params = vrr_params;
8028         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8029 }
8030
8031 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
8032                                             struct dm_crtc_state *new_state)
8033 {
8034         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
8035         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
8036
8037         if (!old_vrr_active && new_vrr_active) {
8038                 /* Transition VRR inactive -> active:
8039                  * While VRR is active, we must not disable vblank irq, as a
8040                  * reenable after disable would compute bogus vblank/pflip
8041                  * timestamps if it likely happened inside display front-porch.
8042                  *
8043                  * We also need vupdate irq for the actual core vblank handling
8044                  * at end of vblank.
8045                  */
8046                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
8047                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
8048                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
8049                                  __func__, new_state->base.crtc->base.id);
8050         } else if (old_vrr_active && !new_vrr_active) {
8051                 /* Transition VRR active -> inactive:
8052                  * Allow vblank irq disable again for fixed refresh rate.
8053                  */
8054                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
8055                 drm_crtc_vblank_put(new_state->base.crtc);
8056                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
8057                                  __func__, new_state->base.crtc->base.id);
8058         }
8059 }
8060
8061 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
8062 {
8063         struct drm_plane *plane;
8064         struct drm_plane_state *old_plane_state;
8065         int i;
8066
8067         /*
8068          * TODO: Make this per-stream so we don't issue redundant updates for
8069          * commits with multiple streams.
8070          */
8071         for_each_old_plane_in_state(state, plane, old_plane_state, i)
8072                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
8073                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
8074 }
8075
8076 static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
8077 {
8078         struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0]);
8079
8080         return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
8081 }
8082
8083 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
8084                                     struct drm_device *dev,
8085                                     struct amdgpu_display_manager *dm,
8086                                     struct drm_crtc *pcrtc,
8087                                     bool wait_for_vblank)
8088 {
8089         u32 i;
8090         u64 timestamp_ns = ktime_get_ns();
8091         struct drm_plane *plane;
8092         struct drm_plane_state *old_plane_state, *new_plane_state;
8093         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
8094         struct drm_crtc_state *new_pcrtc_state =
8095                         drm_atomic_get_new_crtc_state(state, pcrtc);
8096         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
8097         struct dm_crtc_state *dm_old_crtc_state =
8098                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
8099         int planes_count = 0, vpos, hpos;
8100         unsigned long flags;
8101         u32 target_vblank, last_flip_vblank;
8102         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8103         bool cursor_update = false;
8104         bool pflip_present = false;
8105         bool dirty_rects_changed = false;
8106         struct {
8107                 struct dc_surface_update surface_updates[MAX_SURFACES];
8108                 struct dc_plane_info plane_infos[MAX_SURFACES];
8109                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
8110                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
8111                 struct dc_stream_update stream_update;
8112         } *bundle;
8113
8114         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
8115
8116         if (!bundle) {
8117                 drm_err(dev, "Failed to allocate update bundle\n");
8118                 goto cleanup;
8119         }
8120
8121         /*
8122          * Disable the cursor first if we're disabling all the planes.
8123          * It'll remain on the screen after the planes are re-enabled
8124          * if we don't.
8125          */
8126         if (acrtc_state->active_planes == 0)
8127                 amdgpu_dm_commit_cursors(state);
8128
8129         /* update planes when needed */
8130         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
8131                 struct drm_crtc *crtc = new_plane_state->crtc;
8132                 struct drm_crtc_state *new_crtc_state;
8133                 struct drm_framebuffer *fb = new_plane_state->fb;
8134                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
8135                 bool plane_needs_flip;
8136                 struct dc_plane_state *dc_plane;
8137                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
8138
8139                 /* Cursor plane is handled after stream updates */
8140                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
8141                         if ((fb && crtc == pcrtc) ||
8142                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
8143                                 cursor_update = true;
8144
8145                         continue;
8146                 }
8147
8148                 if (!fb || !crtc || pcrtc != crtc)
8149                         continue;
8150
8151                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
8152                 if (!new_crtc_state->active)
8153                         continue;
8154
8155                 dc_plane = dm_new_plane_state->dc_state;
8156                 if (!dc_plane)
8157                         continue;
8158
8159                 bundle->surface_updates[planes_count].surface = dc_plane;
8160                 if (new_pcrtc_state->color_mgmt_changed) {
8161                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
8162                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
8163                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
8164                 }
8165
8166                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
8167                                      &bundle->scaling_infos[planes_count]);
8168
8169                 bundle->surface_updates[planes_count].scaling_info =
8170                         &bundle->scaling_infos[planes_count];
8171
8172                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8173
8174                 pflip_present = pflip_present || plane_needs_flip;
8175
8176                 if (!plane_needs_flip) {
8177                         planes_count += 1;
8178                         continue;
8179                 }
8180
8181                 fill_dc_plane_info_and_addr(
8182                         dm->adev, new_plane_state,
8183                         afb->tiling_flags,
8184                         &bundle->plane_infos[planes_count],
8185                         &bundle->flip_addrs[planes_count].address,
8186                         afb->tmz_surface, false);
8187
8188                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8189                                  new_plane_state->plane->index,
8190                                  bundle->plane_infos[planes_count].dcc.enable);
8191
8192                 bundle->surface_updates[planes_count].plane_info =
8193                         &bundle->plane_infos[planes_count];
8194
8195                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled ||
8196                     acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
8197                         fill_dc_dirty_rects(plane, old_plane_state,
8198                                             new_plane_state, new_crtc_state,
8199                                             &bundle->flip_addrs[planes_count],
8200                                             &dirty_rects_changed);
8201
8202                         /*
8203                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8204                          * and enabled it again after dirty regions are stable to avoid video glitch.
8205                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8206                          * during the PSR-SU was disabled.
8207                          */
8208                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8209                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8210 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8211                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8212 #endif
8213                             dirty_rects_changed) {
8214                                 mutex_lock(&dm->dc_lock);
8215                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8216                                 timestamp_ns;
8217                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8218                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8219                                 mutex_unlock(&dm->dc_lock);
8220                         }
8221                 }
8222
8223                 /*
8224                  * Only allow immediate flips for fast updates that don't
8225                  * change memory domain, FB pitch, DCC state, rotation or
8226                  * mirroring.
8227                  *
8228                  * dm_crtc_helper_atomic_check() only accepts async flips with
8229                  * fast updates.
8230                  */
8231                 if (crtc->state->async_flip &&
8232                     (acrtc_state->update_type != UPDATE_TYPE_FAST ||
8233                      get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
8234                         drm_warn_once(state->dev,
8235                                       "[PLANE:%d:%s] async flip with non-fast update\n",
8236                                       plane->base.id, plane->name);
8237
8238                 bundle->flip_addrs[planes_count].flip_immediate =
8239                         crtc->state->async_flip &&
8240                         acrtc_state->update_type == UPDATE_TYPE_FAST &&
8241                         get_mem_type(old_plane_state->fb) == get_mem_type(fb);
8242
8243                 timestamp_ns = ktime_get_ns();
8244                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8245                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8246                 bundle->surface_updates[planes_count].surface = dc_plane;
8247
8248                 if (!bundle->surface_updates[planes_count].surface) {
8249                         DRM_ERROR("No surface for CRTC: id=%d\n",
8250                                         acrtc_attach->crtc_id);
8251                         continue;
8252                 }
8253
8254                 if (plane == pcrtc->primary)
8255                         update_freesync_state_on_stream(
8256                                 dm,
8257                                 acrtc_state,
8258                                 acrtc_state->stream,
8259                                 dc_plane,
8260                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8261
8262                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8263                                  __func__,
8264                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8265                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8266
8267                 planes_count += 1;
8268
8269         }
8270
8271         if (pflip_present) {
8272                 if (!vrr_active) {
8273                         /* Use old throttling in non-vrr fixed refresh rate mode
8274                          * to keep flip scheduling based on target vblank counts
8275                          * working in a backwards compatible way, e.g., for
8276                          * clients using the GLX_OML_sync_control extension or
8277                          * DRI3/Present extension with defined target_msc.
8278                          */
8279                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8280                 } else {
8281                         /* For variable refresh rate mode only:
8282                          * Get vblank of last completed flip to avoid > 1 vrr
8283                          * flips per video frame by use of throttling, but allow
8284                          * flip programming anywhere in the possibly large
8285                          * variable vrr vblank interval for fine-grained flip
8286                          * timing control and more opportunity to avoid stutter
8287                          * on late submission of flips.
8288                          */
8289                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8290                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8291                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8292                 }
8293
8294                 target_vblank = last_flip_vblank + wait_for_vblank;
8295
8296                 /*
8297                  * Wait until we're out of the vertical blank period before the one
8298                  * targeted by the flip
8299                  */
8300                 while ((acrtc_attach->enabled &&
8301                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8302                                                             0, &vpos, &hpos, NULL,
8303                                                             NULL, &pcrtc->hwmode)
8304                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8305                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8306                         (int)(target_vblank -
8307                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8308                         usleep_range(1000, 1100);
8309                 }
8310
8311                 /**
8312                  * Prepare the flip event for the pageflip interrupt to handle.
8313                  *
8314                  * This only works in the case where we've already turned on the
8315                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8316                  * from 0 -> n planes we have to skip a hardware generated event
8317                  * and rely on sending it from software.
8318                  */
8319                 if (acrtc_attach->base.state->event &&
8320                     acrtc_state->active_planes > 0) {
8321                         drm_crtc_vblank_get(pcrtc);
8322
8323                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8324
8325                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8326                         prepare_flip_isr(acrtc_attach);
8327
8328                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8329                 }
8330
8331                 if (acrtc_state->stream) {
8332                         if (acrtc_state->freesync_vrr_info_changed)
8333                                 bundle->stream_update.vrr_infopacket =
8334                                         &acrtc_state->stream->vrr_infopacket;
8335                 }
8336         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8337                    acrtc_attach->base.state->event) {
8338                 drm_crtc_vblank_get(pcrtc);
8339
8340                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8341
8342                 acrtc_attach->event = acrtc_attach->base.state->event;
8343                 acrtc_attach->base.state->event = NULL;
8344
8345                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8346         }
8347
8348         /* Update the planes if changed or disable if we don't have any. */
8349         if ((planes_count || acrtc_state->active_planes == 0) &&
8350                 acrtc_state->stream) {
8351                 /*
8352                  * If PSR or idle optimizations are enabled then flush out
8353                  * any pending work before hardware programming.
8354                  */
8355                 if (dm->vblank_control_workqueue)
8356                         flush_workqueue(dm->vblank_control_workqueue);
8357
8358                 bundle->stream_update.stream = acrtc_state->stream;
8359                 if (new_pcrtc_state->mode_changed) {
8360                         bundle->stream_update.src = acrtc_state->stream->src;
8361                         bundle->stream_update.dst = acrtc_state->stream->dst;
8362                 }
8363
8364                 if (new_pcrtc_state->color_mgmt_changed) {
8365                         /*
8366                          * TODO: This isn't fully correct since we've actually
8367                          * already modified the stream in place.
8368                          */
8369                         bundle->stream_update.gamut_remap =
8370                                 &acrtc_state->stream->gamut_remap_matrix;
8371                         bundle->stream_update.output_csc_transform =
8372                                 &acrtc_state->stream->csc_color_matrix;
8373                         bundle->stream_update.out_transfer_func =
8374                                 acrtc_state->stream->out_transfer_func;
8375                 }
8376
8377                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8378                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8379                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8380
8381                 mutex_lock(&dm->dc_lock);
8382                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8383                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8384                         amdgpu_dm_psr_disable(acrtc_state->stream);
8385                 mutex_unlock(&dm->dc_lock);
8386
8387                 /*
8388                  * If FreeSync state on the stream has changed then we need to
8389                  * re-adjust the min/max bounds now that DC doesn't handle this
8390                  * as part of commit.
8391                  */
8392                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8393                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8394                         dc_stream_adjust_vmin_vmax(
8395                                 dm->dc, acrtc_state->stream,
8396                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8397                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8398                 }
8399                 mutex_lock(&dm->dc_lock);
8400                 update_planes_and_stream_adapter(dm->dc,
8401                                          acrtc_state->update_type,
8402                                          planes_count,
8403                                          acrtc_state->stream,
8404                                          &bundle->stream_update,
8405                                          bundle->surface_updates);
8406
8407                 /**
8408                  * Enable or disable the interrupts on the backend.
8409                  *
8410                  * Most pipes are put into power gating when unused.
8411                  *
8412                  * When power gating is enabled on a pipe we lose the
8413                  * interrupt enablement state when power gating is disabled.
8414                  *
8415                  * So we need to update the IRQ control state in hardware
8416                  * whenever the pipe turns on (since it could be previously
8417                  * power gated) or off (since some pipes can't be power gated
8418                  * on some ASICs).
8419                  */
8420                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8421                         dm_update_pflip_irq_state(drm_to_adev(dev),
8422                                                   acrtc_attach);
8423
8424                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8425                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8426                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8427                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8428
8429                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8430                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8431                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8432                         struct amdgpu_dm_connector *aconn =
8433                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8434
8435                         if (aconn->psr_skip_count > 0)
8436                                 aconn->psr_skip_count--;
8437
8438                         /* Allow PSR when skip count is 0. */
8439                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8440
8441                         /*
8442                          * If sink supports PSR SU, there is no need to rely on
8443                          * a vblank event disable request to enable PSR. PSR SU
8444                          * can be enabled immediately once OS demonstrates an
8445                          * adequate number of fast atomic commits to notify KMD
8446                          * of update events. See `vblank_control_worker()`.
8447                          */
8448                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8449                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8450 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8451                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8452 #endif
8453                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8454                             (timestamp_ns -
8455                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8456                             500000000)
8457                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8458                 } else {
8459                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8460                 }
8461
8462                 mutex_unlock(&dm->dc_lock);
8463         }
8464
8465         /*
8466          * Update cursor state *after* programming all the planes.
8467          * This avoids redundant programming in the case where we're going
8468          * to be disabling a single plane - those pipes are being disabled.
8469          */
8470         if (acrtc_state->active_planes)
8471                 amdgpu_dm_commit_cursors(state);
8472
8473 cleanup:
8474         kfree(bundle);
8475 }
8476
8477 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8478                                    struct drm_atomic_state *state)
8479 {
8480         struct amdgpu_device *adev = drm_to_adev(dev);
8481         struct amdgpu_dm_connector *aconnector;
8482         struct drm_connector *connector;
8483         struct drm_connector_state *old_con_state, *new_con_state;
8484         struct drm_crtc_state *new_crtc_state;
8485         struct dm_crtc_state *new_dm_crtc_state;
8486         const struct dc_stream_status *status;
8487         int i, inst;
8488
8489         /* Notify device removals. */
8490         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8491                 if (old_con_state->crtc != new_con_state->crtc) {
8492                         /* CRTC changes require notification. */
8493                         goto notify;
8494                 }
8495
8496                 if (!new_con_state->crtc)
8497                         continue;
8498
8499                 new_crtc_state = drm_atomic_get_new_crtc_state(
8500                         state, new_con_state->crtc);
8501
8502                 if (!new_crtc_state)
8503                         continue;
8504
8505                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8506                         continue;
8507
8508 notify:
8509                 aconnector = to_amdgpu_dm_connector(connector);
8510
8511                 mutex_lock(&adev->dm.audio_lock);
8512                 inst = aconnector->audio_inst;
8513                 aconnector->audio_inst = -1;
8514                 mutex_unlock(&adev->dm.audio_lock);
8515
8516                 amdgpu_dm_audio_eld_notify(adev, inst);
8517         }
8518
8519         /* Notify audio device additions. */
8520         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8521                 if (!new_con_state->crtc)
8522                         continue;
8523
8524                 new_crtc_state = drm_atomic_get_new_crtc_state(
8525                         state, new_con_state->crtc);
8526
8527                 if (!new_crtc_state)
8528                         continue;
8529
8530                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8531                         continue;
8532
8533                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8534                 if (!new_dm_crtc_state->stream)
8535                         continue;
8536
8537                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8538                 if (!status)
8539                         continue;
8540
8541                 aconnector = to_amdgpu_dm_connector(connector);
8542
8543                 mutex_lock(&adev->dm.audio_lock);
8544                 inst = status->audio_inst;
8545                 aconnector->audio_inst = inst;
8546                 mutex_unlock(&adev->dm.audio_lock);
8547
8548                 amdgpu_dm_audio_eld_notify(adev, inst);
8549         }
8550 }
8551
8552 /*
8553  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8554  * @crtc_state: the DRM CRTC state
8555  * @stream_state: the DC stream state.
8556  *
8557  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8558  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8559  */
8560 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8561                                                 struct dc_stream_state *stream_state)
8562 {
8563         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8564 }
8565
8566 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
8567                                         struct dc_state *dc_state)
8568 {
8569         struct drm_device *dev = state->dev;
8570         struct amdgpu_device *adev = drm_to_adev(dev);
8571         struct amdgpu_display_manager *dm = &adev->dm;
8572         struct drm_crtc *crtc;
8573         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8574         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8575         bool mode_set_reset_required = false;
8576         u32 i;
8577
8578         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8579                                       new_crtc_state, i) {
8580                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8581
8582                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8583
8584                 if (old_crtc_state->active &&
8585                     (!new_crtc_state->active ||
8586                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8587                         manage_dm_interrupts(adev, acrtc, false);
8588                         dc_stream_release(dm_old_crtc_state->stream);
8589                 }
8590         }
8591
8592         drm_atomic_helper_calc_timestamping_constants(state);
8593
8594         /* update changed items */
8595         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8596                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8597
8598                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8599                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8600
8601                 drm_dbg_state(state->dev,
8602                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
8603                         acrtc->crtc_id,
8604                         new_crtc_state->enable,
8605                         new_crtc_state->active,
8606                         new_crtc_state->planes_changed,
8607                         new_crtc_state->mode_changed,
8608                         new_crtc_state->active_changed,
8609                         new_crtc_state->connectors_changed);
8610
8611                 /* Disable cursor if disabling crtc */
8612                 if (old_crtc_state->active && !new_crtc_state->active) {
8613                         struct dc_cursor_position position;
8614
8615                         memset(&position, 0, sizeof(position));
8616                         mutex_lock(&dm->dc_lock);
8617                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8618                         mutex_unlock(&dm->dc_lock);
8619                 }
8620
8621                 /* Copy all transient state flags into dc state */
8622                 if (dm_new_crtc_state->stream) {
8623                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8624                                                             dm_new_crtc_state->stream);
8625                 }
8626
8627                 /* handles headless hotplug case, updating new_state and
8628                  * aconnector as needed
8629                  */
8630
8631                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8632
8633                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8634
8635                         if (!dm_new_crtc_state->stream) {
8636                                 /*
8637                                  * this could happen because of issues with
8638                                  * userspace notifications delivery.
8639                                  * In this case userspace tries to set mode on
8640                                  * display which is disconnected in fact.
8641                                  * dc_sink is NULL in this case on aconnector.
8642                                  * We expect reset mode will come soon.
8643                                  *
8644                                  * This can also happen when unplug is done
8645                                  * during resume sequence ended
8646                                  *
8647                                  * In this case, we want to pretend we still
8648                                  * have a sink to keep the pipe running so that
8649                                  * hw state is consistent with the sw state
8650                                  */
8651                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8652                                                 __func__, acrtc->base.base.id);
8653                                 continue;
8654                         }
8655
8656                         if (dm_old_crtc_state->stream)
8657                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8658
8659                         pm_runtime_get_noresume(dev->dev);
8660
8661                         acrtc->enabled = true;
8662                         acrtc->hw_mode = new_crtc_state->mode;
8663                         crtc->hwmode = new_crtc_state->mode;
8664                         mode_set_reset_required = true;
8665                 } else if (modereset_required(new_crtc_state)) {
8666                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8667                         /* i.e. reset mode */
8668                         if (dm_old_crtc_state->stream)
8669                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8670
8671                         mode_set_reset_required = true;
8672                 }
8673         } /* for_each_crtc_in_state() */
8674
8675         /* if there mode set or reset, disable eDP PSR */
8676         if (mode_set_reset_required) {
8677                 if (dm->vblank_control_workqueue)
8678                         flush_workqueue(dm->vblank_control_workqueue);
8679
8680                 amdgpu_dm_psr_disable_all(dm);
8681         }
8682
8683         dm_enable_per_frame_crtc_master_sync(dc_state);
8684         mutex_lock(&dm->dc_lock);
8685         WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8686
8687         /* Allow idle optimization when vblank count is 0 for display off */
8688         if (dm->active_vblank_irq_count == 0)
8689                 dc_allow_idle_optimizations(dm->dc, true);
8690         mutex_unlock(&dm->dc_lock);
8691
8692         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8693                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8694
8695                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8696
8697                 if (dm_new_crtc_state->stream != NULL) {
8698                         const struct dc_stream_status *status =
8699                                         dc_stream_get_status(dm_new_crtc_state->stream);
8700
8701                         if (!status)
8702                                 status = dc_stream_get_status_from_state(dc_state,
8703                                                                          dm_new_crtc_state->stream);
8704                         if (!status)
8705                                 drm_err(dev,
8706                                         "got no status for stream %p on acrtc%p\n",
8707                                         dm_new_crtc_state->stream, acrtc);
8708                         else
8709                                 acrtc->otg_inst = status->primary_otg_inst;
8710                 }
8711         }
8712 }
8713
8714 /**
8715  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8716  * @state: The atomic state to commit
8717  *
8718  * This will tell DC to commit the constructed DC state from atomic_check,
8719  * programming the hardware. Any failures here implies a hardware failure, since
8720  * atomic check should have filtered anything non-kosher.
8721  */
8722 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8723 {
8724         struct drm_device *dev = state->dev;
8725         struct amdgpu_device *adev = drm_to_adev(dev);
8726         struct amdgpu_display_manager *dm = &adev->dm;
8727         struct dm_atomic_state *dm_state;
8728         struct dc_state *dc_state = NULL;
8729         u32 i, j;
8730         struct drm_crtc *crtc;
8731         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8732         unsigned long flags;
8733         bool wait_for_vblank = true;
8734         struct drm_connector *connector;
8735         struct drm_connector_state *old_con_state, *new_con_state;
8736         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8737         int crtc_disable_count = 0;
8738
8739         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8740
8741         if (dm->dc->caps.ips_support) {
8742                 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8743                         if (new_con_state->crtc &&
8744                                 new_con_state->crtc->state->active &&
8745                                 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
8746                                 dc_dmub_srv_exit_low_power_state(dm->dc);
8747                                 break;
8748                         }
8749                 }
8750         }
8751
8752         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8753         drm_dp_mst_atomic_wait_for_dependencies(state);
8754
8755         dm_state = dm_atomic_get_new_state(state);
8756         if (dm_state && dm_state->context) {
8757                 dc_state = dm_state->context;
8758                 amdgpu_dm_commit_streams(state, dc_state);
8759         }
8760
8761         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8762                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8763                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8764                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8765
8766                 if (!adev->dm.hdcp_workqueue)
8767                         continue;
8768
8769                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8770
8771                 if (!connector)
8772                         continue;
8773
8774                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8775                         connector->index, connector->status, connector->dpms);
8776                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8777                         old_con_state->content_protection, new_con_state->content_protection);
8778
8779                 if (aconnector->dc_sink) {
8780                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8781                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8782                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8783                                 aconnector->dc_sink->edid_caps.display_name);
8784                         }
8785                 }
8786
8787                 new_crtc_state = NULL;
8788                 old_crtc_state = NULL;
8789
8790                 if (acrtc) {
8791                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8792                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8793                 }
8794
8795                 if (old_crtc_state)
8796                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8797                         old_crtc_state->enable,
8798                         old_crtc_state->active,
8799                         old_crtc_state->mode_changed,
8800                         old_crtc_state->active_changed,
8801                         old_crtc_state->connectors_changed);
8802
8803                 if (new_crtc_state)
8804                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8805                         new_crtc_state->enable,
8806                         new_crtc_state->active,
8807                         new_crtc_state->mode_changed,
8808                         new_crtc_state->active_changed,
8809                         new_crtc_state->connectors_changed);
8810         }
8811
8812         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8813                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8814                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8815                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8816
8817                 if (!adev->dm.hdcp_workqueue)
8818                         continue;
8819
8820                 new_crtc_state = NULL;
8821                 old_crtc_state = NULL;
8822
8823                 if (acrtc) {
8824                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8825                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8826                 }
8827
8828                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8829
8830                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8831                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8832                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8833                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8834                         dm_new_con_state->update_hdcp = true;
8835                         continue;
8836                 }
8837
8838                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8839                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8840                         /* when display is unplugged from mst hub, connctor will
8841                          * be destroyed within dm_dp_mst_connector_destroy. connector
8842                          * hdcp perperties, like type, undesired, desired, enabled,
8843                          * will be lost. So, save hdcp properties into hdcp_work within
8844                          * amdgpu_dm_atomic_commit_tail. if the same display is
8845                          * plugged back with same display index, its hdcp properties
8846                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8847                          */
8848
8849                         bool enable_encryption = false;
8850
8851                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8852                                 enable_encryption = true;
8853
8854                         if (aconnector->dc_link && aconnector->dc_sink &&
8855                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8856                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8857                                 struct hdcp_workqueue *hdcp_w =
8858                                         &hdcp_work[aconnector->dc_link->link_index];
8859
8860                                 hdcp_w->hdcp_content_type[connector->index] =
8861                                         new_con_state->hdcp_content_type;
8862                                 hdcp_w->content_protection[connector->index] =
8863                                         new_con_state->content_protection;
8864                         }
8865
8866                         if (new_crtc_state && new_crtc_state->mode_changed &&
8867                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8868                                 enable_encryption = true;
8869
8870                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8871
8872                         hdcp_update_display(
8873                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8874                                 new_con_state->hdcp_content_type, enable_encryption);
8875                 }
8876         }
8877
8878         /* Handle connector state changes */
8879         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8880                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8881                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8882                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8883                 struct dc_surface_update *dummy_updates;
8884                 struct dc_stream_update stream_update;
8885                 struct dc_info_packet hdr_packet;
8886                 struct dc_stream_status *status = NULL;
8887                 bool abm_changed, hdr_changed, scaling_changed;
8888
8889                 memset(&stream_update, 0, sizeof(stream_update));
8890
8891                 if (acrtc) {
8892                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8893                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8894                 }
8895
8896                 /* Skip any modesets/resets */
8897                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8898                         continue;
8899
8900                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8901                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8902
8903                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8904                                                              dm_old_con_state);
8905
8906                 abm_changed = dm_new_crtc_state->abm_level !=
8907                               dm_old_crtc_state->abm_level;
8908
8909                 hdr_changed =
8910                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8911
8912                 if (!scaling_changed && !abm_changed && !hdr_changed)
8913                         continue;
8914
8915                 stream_update.stream = dm_new_crtc_state->stream;
8916                 if (scaling_changed) {
8917                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8918                                         dm_new_con_state, dm_new_crtc_state->stream);
8919
8920                         stream_update.src = dm_new_crtc_state->stream->src;
8921                         stream_update.dst = dm_new_crtc_state->stream->dst;
8922                 }
8923
8924                 if (abm_changed) {
8925                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8926
8927                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8928                 }
8929
8930                 if (hdr_changed) {
8931                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8932                         stream_update.hdr_static_metadata = &hdr_packet;
8933                 }
8934
8935                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8936
8937                 if (WARN_ON(!status))
8938                         continue;
8939
8940                 WARN_ON(!status->plane_count);
8941
8942                 /*
8943                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8944                  * Here we create an empty update on each plane.
8945                  * To fix this, DC should permit updating only stream properties.
8946                  */
8947                 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
8948                 for (j = 0; j < status->plane_count; j++)
8949                         dummy_updates[j].surface = status->plane_states[0];
8950
8951
8952                 mutex_lock(&dm->dc_lock);
8953                 dc_update_planes_and_stream(dm->dc,
8954                                             dummy_updates,
8955                                             status->plane_count,
8956                                             dm_new_crtc_state->stream,
8957                                             &stream_update);
8958                 mutex_unlock(&dm->dc_lock);
8959                 kfree(dummy_updates);
8960         }
8961
8962         /**
8963          * Enable interrupts for CRTCs that are newly enabled or went through
8964          * a modeset. It was intentionally deferred until after the front end
8965          * state was modified to wait until the OTG was on and so the IRQ
8966          * handlers didn't access stale or invalid state.
8967          */
8968         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8969                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8970 #ifdef CONFIG_DEBUG_FS
8971                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8972 #endif
8973                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8974                 if (old_crtc_state->active && !new_crtc_state->active)
8975                         crtc_disable_count++;
8976
8977                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8978                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8979
8980                 /* For freesync config update on crtc state and params for irq */
8981                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8982
8983 #ifdef CONFIG_DEBUG_FS
8984                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8985                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8986                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8987 #endif
8988
8989                 if (new_crtc_state->active &&
8990                     (!old_crtc_state->active ||
8991                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8992                         dc_stream_retain(dm_new_crtc_state->stream);
8993                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8994                         manage_dm_interrupts(adev, acrtc, true);
8995                 }
8996                 /* Handle vrr on->off / off->on transitions */
8997                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8998
8999 #ifdef CONFIG_DEBUG_FS
9000                 if (new_crtc_state->active &&
9001                     (!old_crtc_state->active ||
9002                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
9003                         /**
9004                          * Frontend may have changed so reapply the CRC capture
9005                          * settings for the stream.
9006                          */
9007                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
9008 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
9009                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
9010                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9011                                         acrtc->dm_irq_params.window_param.update_win = true;
9012
9013                                         /**
9014                                          * It takes 2 frames for HW to stably generate CRC when
9015                                          * resuming from suspend, so we set skip_frame_cnt 2.
9016                                          */
9017                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
9018                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9019                                 }
9020 #endif
9021                                 if (amdgpu_dm_crtc_configure_crc_source(
9022                                         crtc, dm_new_crtc_state, cur_crc_src))
9023                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
9024                         }
9025                 }
9026 #endif
9027         }
9028
9029         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
9030                 if (new_crtc_state->async_flip)
9031                         wait_for_vblank = false;
9032
9033         /* update planes when needed per crtc*/
9034         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
9035                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9036
9037                 if (dm_new_crtc_state->stream)
9038                         amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
9039         }
9040
9041         /* Update audio instances for each connector. */
9042         amdgpu_dm_commit_audio(dev, state);
9043
9044         /* restore the backlight level */
9045         for (i = 0; i < dm->num_of_edps; i++) {
9046                 if (dm->backlight_dev[i] &&
9047                     (dm->actual_brightness[i] != dm->brightness[i]))
9048                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
9049         }
9050
9051         /*
9052          * send vblank event on all events not handled in flip and
9053          * mark consumed event for drm_atomic_helper_commit_hw_done
9054          */
9055         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
9056         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9057
9058                 if (new_crtc_state->event)
9059                         drm_send_event_locked(dev, &new_crtc_state->event->base);
9060
9061                 new_crtc_state->event = NULL;
9062         }
9063         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
9064
9065         /* Signal HW programming completion */
9066         drm_atomic_helper_commit_hw_done(state);
9067
9068         if (wait_for_vblank)
9069                 drm_atomic_helper_wait_for_flip_done(dev, state);
9070
9071         drm_atomic_helper_cleanup_planes(dev, state);
9072
9073         /* Don't free the memory if we are hitting this as part of suspend.
9074          * This way we don't free any memory during suspend; see
9075          * amdgpu_bo_free_kernel().  The memory will be freed in the first
9076          * non-suspend modeset or when the driver is torn down.
9077          */
9078         if (!adev->in_suspend) {
9079                 /* return the stolen vga memory back to VRAM */
9080                 if (!adev->mman.keep_stolen_vga_memory)
9081                         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
9082                 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
9083         }
9084
9085         /*
9086          * Finally, drop a runtime PM reference for each newly disabled CRTC,
9087          * so we can put the GPU into runtime suspend if we're not driving any
9088          * displays anymore
9089          */
9090         for (i = 0; i < crtc_disable_count; i++)
9091                 pm_runtime_put_autosuspend(dev->dev);
9092         pm_runtime_mark_last_busy(dev->dev);
9093 }
9094
9095 static int dm_force_atomic_commit(struct drm_connector *connector)
9096 {
9097         int ret = 0;
9098         struct drm_device *ddev = connector->dev;
9099         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
9100         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9101         struct drm_plane *plane = disconnected_acrtc->base.primary;
9102         struct drm_connector_state *conn_state;
9103         struct drm_crtc_state *crtc_state;
9104         struct drm_plane_state *plane_state;
9105
9106         if (!state)
9107                 return -ENOMEM;
9108
9109         state->acquire_ctx = ddev->mode_config.acquire_ctx;
9110
9111         /* Construct an atomic state to restore previous display setting */
9112
9113         /*
9114          * Attach connectors to drm_atomic_state
9115          */
9116         conn_state = drm_atomic_get_connector_state(state, connector);
9117
9118         ret = PTR_ERR_OR_ZERO(conn_state);
9119         if (ret)
9120                 goto out;
9121
9122         /* Attach crtc to drm_atomic_state*/
9123         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
9124
9125         ret = PTR_ERR_OR_ZERO(crtc_state);
9126         if (ret)
9127                 goto out;
9128
9129         /* force a restore */
9130         crtc_state->mode_changed = true;
9131
9132         /* Attach plane to drm_atomic_state */
9133         plane_state = drm_atomic_get_plane_state(state, plane);
9134
9135         ret = PTR_ERR_OR_ZERO(plane_state);
9136         if (ret)
9137                 goto out;
9138
9139         /* Call commit internally with the state we just constructed */
9140         ret = drm_atomic_commit(state);
9141
9142 out:
9143         drm_atomic_state_put(state);
9144         if (ret)
9145                 DRM_ERROR("Restoring old state failed with %i\n", ret);
9146
9147         return ret;
9148 }
9149
9150 /*
9151  * This function handles all cases when set mode does not come upon hotplug.
9152  * This includes when a display is unplugged then plugged back into the
9153  * same port and when running without usermode desktop manager supprot
9154  */
9155 void dm_restore_drm_connector_state(struct drm_device *dev,
9156                                     struct drm_connector *connector)
9157 {
9158         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
9159         struct amdgpu_crtc *disconnected_acrtc;
9160         struct dm_crtc_state *acrtc_state;
9161
9162         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
9163                 return;
9164
9165         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
9166         if (!disconnected_acrtc)
9167                 return;
9168
9169         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
9170         if (!acrtc_state->stream)
9171                 return;
9172
9173         /*
9174          * If the previous sink is not released and different from the current,
9175          * we deduce we are in a state where we can not rely on usermode call
9176          * to turn on the display, so we do it here
9177          */
9178         if (acrtc_state->stream->sink != aconnector->dc_sink)
9179                 dm_force_atomic_commit(&aconnector->base);
9180 }
9181
9182 /*
9183  * Grabs all modesetting locks to serialize against any blocking commits,
9184  * Waits for completion of all non blocking commits.
9185  */
9186 static int do_aquire_global_lock(struct drm_device *dev,
9187                                  struct drm_atomic_state *state)
9188 {
9189         struct drm_crtc *crtc;
9190         struct drm_crtc_commit *commit;
9191         long ret;
9192
9193         /*
9194          * Adding all modeset locks to aquire_ctx will
9195          * ensure that when the framework release it the
9196          * extra locks we are locking here will get released to
9197          */
9198         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
9199         if (ret)
9200                 return ret;
9201
9202         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9203                 spin_lock(&crtc->commit_lock);
9204                 commit = list_first_entry_or_null(&crtc->commit_list,
9205                                 struct drm_crtc_commit, commit_entry);
9206                 if (commit)
9207                         drm_crtc_commit_get(commit);
9208                 spin_unlock(&crtc->commit_lock);
9209
9210                 if (!commit)
9211                         continue;
9212
9213                 /*
9214                  * Make sure all pending HW programming completed and
9215                  * page flips done
9216                  */
9217                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9218
9219                 if (ret > 0)
9220                         ret = wait_for_completion_interruptible_timeout(
9221                                         &commit->flip_done, 10*HZ);
9222
9223                 if (ret == 0)
9224                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",
9225                                   crtc->base.id, crtc->name);
9226
9227                 drm_crtc_commit_put(commit);
9228         }
9229
9230         return ret < 0 ? ret : 0;
9231 }
9232
9233 static void get_freesync_config_for_crtc(
9234         struct dm_crtc_state *new_crtc_state,
9235         struct dm_connector_state *new_con_state)
9236 {
9237         struct mod_freesync_config config = {0};
9238         struct amdgpu_dm_connector *aconnector =
9239                         to_amdgpu_dm_connector(new_con_state->base.connector);
9240         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9241         int vrefresh = drm_mode_vrefresh(mode);
9242         bool fs_vid_mode = false;
9243
9244         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9245                                         vrefresh >= aconnector->min_vfreq &&
9246                                         vrefresh <= aconnector->max_vfreq;
9247
9248         if (new_crtc_state->vrr_supported) {
9249                 new_crtc_state->stream->ignore_msa_timing_param = true;
9250                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9251
9252                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9253                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9254                 config.vsif_supported = true;
9255                 config.btr = true;
9256
9257                 if (fs_vid_mode) {
9258                         config.state = VRR_STATE_ACTIVE_FIXED;
9259                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9260                         goto out;
9261                 } else if (new_crtc_state->base.vrr_enabled) {
9262                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9263                 } else {
9264                         config.state = VRR_STATE_INACTIVE;
9265                 }
9266         }
9267 out:
9268         new_crtc_state->freesync_config = config;
9269 }
9270
9271 static void reset_freesync_config_for_crtc(
9272         struct dm_crtc_state *new_crtc_state)
9273 {
9274         new_crtc_state->vrr_supported = false;
9275
9276         memset(&new_crtc_state->vrr_infopacket, 0,
9277                sizeof(new_crtc_state->vrr_infopacket));
9278 }
9279
9280 static bool
9281 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9282                                  struct drm_crtc_state *new_crtc_state)
9283 {
9284         const struct drm_display_mode *old_mode, *new_mode;
9285
9286         if (!old_crtc_state || !new_crtc_state)
9287                 return false;
9288
9289         old_mode = &old_crtc_state->mode;
9290         new_mode = &new_crtc_state->mode;
9291
9292         if (old_mode->clock       == new_mode->clock &&
9293             old_mode->hdisplay    == new_mode->hdisplay &&
9294             old_mode->vdisplay    == new_mode->vdisplay &&
9295             old_mode->htotal      == new_mode->htotal &&
9296             old_mode->vtotal      != new_mode->vtotal &&
9297             old_mode->hsync_start == new_mode->hsync_start &&
9298             old_mode->vsync_start != new_mode->vsync_start &&
9299             old_mode->hsync_end   == new_mode->hsync_end &&
9300             old_mode->vsync_end   != new_mode->vsync_end &&
9301             old_mode->hskew       == new_mode->hskew &&
9302             old_mode->vscan       == new_mode->vscan &&
9303             (old_mode->vsync_end - old_mode->vsync_start) ==
9304             (new_mode->vsync_end - new_mode->vsync_start))
9305                 return true;
9306
9307         return false;
9308 }
9309
9310 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9311 {
9312         u64 num, den, res;
9313         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9314
9315         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9316
9317         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9318         den = (unsigned long long)new_crtc_state->mode.htotal *
9319               (unsigned long long)new_crtc_state->mode.vtotal;
9320
9321         res = div_u64(num, den);
9322         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9323 }
9324
9325 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9326                          struct drm_atomic_state *state,
9327                          struct drm_crtc *crtc,
9328                          struct drm_crtc_state *old_crtc_state,
9329                          struct drm_crtc_state *new_crtc_state,
9330                          bool enable,
9331                          bool *lock_and_validation_needed)
9332 {
9333         struct dm_atomic_state *dm_state = NULL;
9334         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9335         struct dc_stream_state *new_stream;
9336         int ret = 0;
9337
9338         /*
9339          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9340          * update changed items
9341          */
9342         struct amdgpu_crtc *acrtc = NULL;
9343         struct amdgpu_dm_connector *aconnector = NULL;
9344         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9345         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9346
9347         new_stream = NULL;
9348
9349         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9350         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9351         acrtc = to_amdgpu_crtc(crtc);
9352         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9353
9354         /* TODO This hack should go away */
9355         if (aconnector && enable) {
9356                 /* Make sure fake sink is created in plug-in scenario */
9357                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9358                                                             &aconnector->base);
9359                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9360                                                             &aconnector->base);
9361
9362                 if (IS_ERR(drm_new_conn_state)) {
9363                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9364                         goto fail;
9365                 }
9366
9367                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9368                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9369
9370                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9371                         goto skip_modeset;
9372
9373                 new_stream = create_validate_stream_for_sink(aconnector,
9374                                                              &new_crtc_state->mode,
9375                                                              dm_new_conn_state,
9376                                                              dm_old_crtc_state->stream);
9377
9378                 /*
9379                  * we can have no stream on ACTION_SET if a display
9380                  * was disconnected during S3, in this case it is not an
9381                  * error, the OS will be updated after detection, and
9382                  * will do the right thing on next atomic commit
9383                  */
9384
9385                 if (!new_stream) {
9386                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9387                                         __func__, acrtc->base.base.id);
9388                         ret = -ENOMEM;
9389                         goto fail;
9390                 }
9391
9392                 /*
9393                  * TODO: Check VSDB bits to decide whether this should
9394                  * be enabled or not.
9395                  */
9396                 new_stream->triggered_crtc_reset.enabled =
9397                         dm->force_timing_sync;
9398
9399                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9400
9401                 ret = fill_hdr_info_packet(drm_new_conn_state,
9402                                            &new_stream->hdr_static_metadata);
9403                 if (ret)
9404                         goto fail;
9405
9406                 /*
9407                  * If we already removed the old stream from the context
9408                  * (and set the new stream to NULL) then we can't reuse
9409                  * the old stream even if the stream and scaling are unchanged.
9410                  * We'll hit the BUG_ON and black screen.
9411                  *
9412                  * TODO: Refactor this function to allow this check to work
9413                  * in all conditions.
9414                  */
9415                 if (dm_new_crtc_state->stream &&
9416                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9417                         goto skip_modeset;
9418
9419                 if (dm_new_crtc_state->stream &&
9420                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9421                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9422                         new_crtc_state->mode_changed = false;
9423                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9424                                          new_crtc_state->mode_changed);
9425                 }
9426         }
9427
9428         /* mode_changed flag may get updated above, need to check again */
9429         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9430                 goto skip_modeset;
9431
9432         drm_dbg_state(state->dev,
9433                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",
9434                 acrtc->crtc_id,
9435                 new_crtc_state->enable,
9436                 new_crtc_state->active,
9437                 new_crtc_state->planes_changed,
9438                 new_crtc_state->mode_changed,
9439                 new_crtc_state->active_changed,
9440                 new_crtc_state->connectors_changed);
9441
9442         /* Remove stream for any changed/disabled CRTC */
9443         if (!enable) {
9444
9445                 if (!dm_old_crtc_state->stream)
9446                         goto skip_modeset;
9447
9448                 /* Unset freesync video if it was active before */
9449                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9450                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9451                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9452                 }
9453
9454                 /* Now check if we should set freesync video mode */
9455                 if (dm_new_crtc_state->stream &&
9456                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9457                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
9458                     is_timing_unchanged_for_freesync(new_crtc_state,
9459                                                      old_crtc_state)) {
9460                         new_crtc_state->mode_changed = false;
9461                         DRM_DEBUG_DRIVER(
9462                                 "Mode change not required for front porch change, setting mode_changed to %d",
9463                                 new_crtc_state->mode_changed);
9464
9465                         set_freesync_fixed_config(dm_new_crtc_state);
9466
9467                         goto skip_modeset;
9468                 } else if (aconnector &&
9469                            is_freesync_video_mode(&new_crtc_state->mode,
9470                                                   aconnector)) {
9471                         struct drm_display_mode *high_mode;
9472
9473                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9474                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
9475                                 set_freesync_fixed_config(dm_new_crtc_state);
9476                 }
9477
9478                 ret = dm_atomic_get_state(state, &dm_state);
9479                 if (ret)
9480                         goto fail;
9481
9482                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9483                                 crtc->base.id);
9484
9485                 /* i.e. reset mode */
9486                 if (dc_remove_stream_from_ctx(
9487                                 dm->dc,
9488                                 dm_state->context,
9489                                 dm_old_crtc_state->stream) != DC_OK) {
9490                         ret = -EINVAL;
9491                         goto fail;
9492                 }
9493
9494                 dc_stream_release(dm_old_crtc_state->stream);
9495                 dm_new_crtc_state->stream = NULL;
9496
9497                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9498
9499                 *lock_and_validation_needed = true;
9500
9501         } else {/* Add stream for any updated/enabled CRTC */
9502                 /*
9503                  * Quick fix to prevent NULL pointer on new_stream when
9504                  * added MST connectors not found in existing crtc_state in the chained mode
9505                  * TODO: need to dig out the root cause of that
9506                  */
9507                 if (!aconnector)
9508                         goto skip_modeset;
9509
9510                 if (modereset_required(new_crtc_state))
9511                         goto skip_modeset;
9512
9513                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9514                                      dm_old_crtc_state->stream)) {
9515
9516                         WARN_ON(dm_new_crtc_state->stream);
9517
9518                         ret = dm_atomic_get_state(state, &dm_state);
9519                         if (ret)
9520                                 goto fail;
9521
9522                         dm_new_crtc_state->stream = new_stream;
9523
9524                         dc_stream_retain(new_stream);
9525
9526                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9527                                          crtc->base.id);
9528
9529                         if (dc_add_stream_to_ctx(
9530                                         dm->dc,
9531                                         dm_state->context,
9532                                         dm_new_crtc_state->stream) != DC_OK) {
9533                                 ret = -EINVAL;
9534                                 goto fail;
9535                         }
9536
9537                         *lock_and_validation_needed = true;
9538                 }
9539         }
9540
9541 skip_modeset:
9542         /* Release extra reference */
9543         if (new_stream)
9544                 dc_stream_release(new_stream);
9545
9546         /*
9547          * We want to do dc stream updates that do not require a
9548          * full modeset below.
9549          */
9550         if (!(enable && aconnector && new_crtc_state->active))
9551                 return 0;
9552         /*
9553          * Given above conditions, the dc state cannot be NULL because:
9554          * 1. We're in the process of enabling CRTCs (just been added
9555          *    to the dc context, or already is on the context)
9556          * 2. Has a valid connector attached, and
9557          * 3. Is currently active and enabled.
9558          * => The dc stream state currently exists.
9559          */
9560         BUG_ON(dm_new_crtc_state->stream == NULL);
9561
9562         /* Scaling or underscan settings */
9563         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9564                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9565                 update_stream_scaling_settings(
9566                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9567
9568         /* ABM settings */
9569         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9570
9571         /*
9572          * Color management settings. We also update color properties
9573          * when a modeset is needed, to ensure it gets reprogrammed.
9574          */
9575         if (dm_new_crtc_state->base.color_mgmt_changed ||
9576             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9577                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9578                 if (ret)
9579                         goto fail;
9580         }
9581
9582         /* Update Freesync settings. */
9583         get_freesync_config_for_crtc(dm_new_crtc_state,
9584                                      dm_new_conn_state);
9585
9586         return ret;
9587
9588 fail:
9589         if (new_stream)
9590                 dc_stream_release(new_stream);
9591         return ret;
9592 }
9593
9594 static bool should_reset_plane(struct drm_atomic_state *state,
9595                                struct drm_plane *plane,
9596                                struct drm_plane_state *old_plane_state,
9597                                struct drm_plane_state *new_plane_state)
9598 {
9599         struct drm_plane *other;
9600         struct drm_plane_state *old_other_state, *new_other_state;
9601         struct drm_crtc_state *new_crtc_state;
9602         struct amdgpu_device *adev = drm_to_adev(plane->dev);
9603         int i;
9604
9605         /*
9606          * TODO: Remove this hack for all asics once it proves that the
9607          * fast updates works fine on DCN3.2+.
9608          */
9609         if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0) && state->allow_modeset)
9610                 return true;
9611
9612         /* Exit early if we know that we're adding or removing the plane. */
9613         if (old_plane_state->crtc != new_plane_state->crtc)
9614                 return true;
9615
9616         /* old crtc == new_crtc == NULL, plane not in context. */
9617         if (!new_plane_state->crtc)
9618                 return false;
9619
9620         new_crtc_state =
9621                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9622
9623         if (!new_crtc_state)
9624                 return true;
9625
9626         /* CRTC Degamma changes currently require us to recreate planes. */
9627         if (new_crtc_state->color_mgmt_changed)
9628                 return true;
9629
9630         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9631                 return true;
9632
9633         /*
9634          * If there are any new primary or overlay planes being added or
9635          * removed then the z-order can potentially change. To ensure
9636          * correct z-order and pipe acquisition the current DC architecture
9637          * requires us to remove and recreate all existing planes.
9638          *
9639          * TODO: Come up with a more elegant solution for this.
9640          */
9641         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9642                 struct amdgpu_framebuffer *old_afb, *new_afb;
9643
9644                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9645                         continue;
9646
9647                 if (old_other_state->crtc != new_plane_state->crtc &&
9648                     new_other_state->crtc != new_plane_state->crtc)
9649                         continue;
9650
9651                 if (old_other_state->crtc != new_other_state->crtc)
9652                         return true;
9653
9654                 /* Src/dst size and scaling updates. */
9655                 if (old_other_state->src_w != new_other_state->src_w ||
9656                     old_other_state->src_h != new_other_state->src_h ||
9657                     old_other_state->crtc_w != new_other_state->crtc_w ||
9658                     old_other_state->crtc_h != new_other_state->crtc_h)
9659                         return true;
9660
9661                 /* Rotation / mirroring updates. */
9662                 if (old_other_state->rotation != new_other_state->rotation)
9663                         return true;
9664
9665                 /* Blending updates. */
9666                 if (old_other_state->pixel_blend_mode !=
9667                     new_other_state->pixel_blend_mode)
9668                         return true;
9669
9670                 /* Alpha updates. */
9671                 if (old_other_state->alpha != new_other_state->alpha)
9672                         return true;
9673
9674                 /* Colorspace changes. */
9675                 if (old_other_state->color_range != new_other_state->color_range ||
9676                     old_other_state->color_encoding != new_other_state->color_encoding)
9677                         return true;
9678
9679                 /* Framebuffer checks fall at the end. */
9680                 if (!old_other_state->fb || !new_other_state->fb)
9681                         continue;
9682
9683                 /* Pixel format changes can require bandwidth updates. */
9684                 if (old_other_state->fb->format != new_other_state->fb->format)
9685                         return true;
9686
9687                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9688                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9689
9690                 /* Tiling and DCC changes also require bandwidth updates. */
9691                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9692                     old_afb->base.modifier != new_afb->base.modifier)
9693                         return true;
9694         }
9695
9696         return false;
9697 }
9698
9699 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9700                               struct drm_plane_state *new_plane_state,
9701                               struct drm_framebuffer *fb)
9702 {
9703         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9704         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9705         unsigned int pitch;
9706         bool linear;
9707
9708         if (fb->width > new_acrtc->max_cursor_width ||
9709             fb->height > new_acrtc->max_cursor_height) {
9710                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9711                                  new_plane_state->fb->width,
9712                                  new_plane_state->fb->height);
9713                 return -EINVAL;
9714         }
9715         if (new_plane_state->src_w != fb->width << 16 ||
9716             new_plane_state->src_h != fb->height << 16) {
9717                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9718                 return -EINVAL;
9719         }
9720
9721         /* Pitch in pixels */
9722         pitch = fb->pitches[0] / fb->format->cpp[0];
9723
9724         if (fb->width != pitch) {
9725                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9726                                  fb->width, pitch);
9727                 return -EINVAL;
9728         }
9729
9730         switch (pitch) {
9731         case 64:
9732         case 128:
9733         case 256:
9734                 /* FB pitch is supported by cursor plane */
9735                 break;
9736         default:
9737                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9738                 return -EINVAL;
9739         }
9740
9741         /* Core DRM takes care of checking FB modifiers, so we only need to
9742          * check tiling flags when the FB doesn't have a modifier.
9743          */
9744         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9745                 if (adev->family < AMDGPU_FAMILY_AI) {
9746                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9747                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9748                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9749                 } else {
9750                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9751                 }
9752                 if (!linear) {
9753                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9754                         return -EINVAL;
9755                 }
9756         }
9757
9758         return 0;
9759 }
9760
9761 static int dm_update_plane_state(struct dc *dc,
9762                                  struct drm_atomic_state *state,
9763                                  struct drm_plane *plane,
9764                                  struct drm_plane_state *old_plane_state,
9765                                  struct drm_plane_state *new_plane_state,
9766                                  bool enable,
9767                                  bool *lock_and_validation_needed,
9768                                  bool *is_top_most_overlay)
9769 {
9770
9771         struct dm_atomic_state *dm_state = NULL;
9772         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9773         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9774         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9775         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9776         struct amdgpu_crtc *new_acrtc;
9777         bool needs_reset;
9778         int ret = 0;
9779
9780
9781         new_plane_crtc = new_plane_state->crtc;
9782         old_plane_crtc = old_plane_state->crtc;
9783         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9784         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9785
9786         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9787                 if (!enable || !new_plane_crtc ||
9788                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9789                         return 0;
9790
9791                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9792
9793                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9794                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9795                         return -EINVAL;
9796                 }
9797
9798                 if (new_plane_state->fb) {
9799                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9800                                                  new_plane_state->fb);
9801                         if (ret)
9802                                 return ret;
9803                 }
9804
9805                 return 0;
9806         }
9807
9808         needs_reset = should_reset_plane(state, plane, old_plane_state,
9809                                          new_plane_state);
9810
9811         /* Remove any changed/removed planes */
9812         if (!enable) {
9813                 if (!needs_reset)
9814                         return 0;
9815
9816                 if (!old_plane_crtc)
9817                         return 0;
9818
9819                 old_crtc_state = drm_atomic_get_old_crtc_state(
9820                                 state, old_plane_crtc);
9821                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9822
9823                 if (!dm_old_crtc_state->stream)
9824                         return 0;
9825
9826                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9827                                 plane->base.id, old_plane_crtc->base.id);
9828
9829                 ret = dm_atomic_get_state(state, &dm_state);
9830                 if (ret)
9831                         return ret;
9832
9833                 if (!dc_remove_plane_from_context(
9834                                 dc,
9835                                 dm_old_crtc_state->stream,
9836                                 dm_old_plane_state->dc_state,
9837                                 dm_state->context)) {
9838
9839                         return -EINVAL;
9840                 }
9841
9842                 if (dm_old_plane_state->dc_state)
9843                         dc_plane_state_release(dm_old_plane_state->dc_state);
9844
9845                 dm_new_plane_state->dc_state = NULL;
9846
9847                 *lock_and_validation_needed = true;
9848
9849         } else { /* Add new planes */
9850                 struct dc_plane_state *dc_new_plane_state;
9851
9852                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9853                         return 0;
9854
9855                 if (!new_plane_crtc)
9856                         return 0;
9857
9858                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9859                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9860
9861                 if (!dm_new_crtc_state->stream)
9862                         return 0;
9863
9864                 if (!needs_reset)
9865                         return 0;
9866
9867                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9868                 if (ret)
9869                         return ret;
9870
9871                 WARN_ON(dm_new_plane_state->dc_state);
9872
9873                 dc_new_plane_state = dc_create_plane_state(dc);
9874                 if (!dc_new_plane_state)
9875                         return -ENOMEM;
9876
9877                 /* Block top most plane from being a video plane */
9878                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9879                         if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9880                                 return -EINVAL;
9881
9882                         *is_top_most_overlay = false;
9883                 }
9884
9885                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9886                                  plane->base.id, new_plane_crtc->base.id);
9887
9888                 ret = fill_dc_plane_attributes(
9889                         drm_to_adev(new_plane_crtc->dev),
9890                         dc_new_plane_state,
9891                         new_plane_state,
9892                         new_crtc_state);
9893                 if (ret) {
9894                         dc_plane_state_release(dc_new_plane_state);
9895                         return ret;
9896                 }
9897
9898                 ret = dm_atomic_get_state(state, &dm_state);
9899                 if (ret) {
9900                         dc_plane_state_release(dc_new_plane_state);
9901                         return ret;
9902                 }
9903
9904                 /*
9905                  * Any atomic check errors that occur after this will
9906                  * not need a release. The plane state will be attached
9907                  * to the stream, and therefore part of the atomic
9908                  * state. It'll be released when the atomic state is
9909                  * cleaned.
9910                  */
9911                 if (!dc_add_plane_to_context(
9912                                 dc,
9913                                 dm_new_crtc_state->stream,
9914                                 dc_new_plane_state,
9915                                 dm_state->context)) {
9916
9917                         dc_plane_state_release(dc_new_plane_state);
9918                         return -EINVAL;
9919                 }
9920
9921                 dm_new_plane_state->dc_state = dc_new_plane_state;
9922
9923                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9924
9925                 /* Tell DC to do a full surface update every time there
9926                  * is a plane change. Inefficient, but works for now.
9927                  */
9928                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9929
9930                 *lock_and_validation_needed = true;
9931         }
9932
9933
9934         return ret;
9935 }
9936
9937 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9938                                        int *src_w, int *src_h)
9939 {
9940         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9941         case DRM_MODE_ROTATE_90:
9942         case DRM_MODE_ROTATE_270:
9943                 *src_w = plane_state->src_h >> 16;
9944                 *src_h = plane_state->src_w >> 16;
9945                 break;
9946         case DRM_MODE_ROTATE_0:
9947         case DRM_MODE_ROTATE_180:
9948         default:
9949                 *src_w = plane_state->src_w >> 16;
9950                 *src_h = plane_state->src_h >> 16;
9951                 break;
9952         }
9953 }
9954
9955 static void
9956 dm_get_plane_scale(struct drm_plane_state *plane_state,
9957                    int *out_plane_scale_w, int *out_plane_scale_h)
9958 {
9959         int plane_src_w, plane_src_h;
9960
9961         dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
9962         *out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
9963         *out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9964 }
9965
9966 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9967                                 struct drm_crtc *crtc,
9968                                 struct drm_crtc_state *new_crtc_state)
9969 {
9970         struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
9971         struct drm_plane_state *old_plane_state, *new_plane_state;
9972         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9973         int i;
9974         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9975         bool any_relevant_change = false;
9976
9977         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9978          * cursor per pipe but it's going to inherit the scaling and
9979          * positioning from the underlying pipe. Check the cursor plane's
9980          * blending properties match the underlying planes'.
9981          */
9982
9983         /* If no plane was enabled or changed scaling, no need to check again */
9984         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9985                 int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
9986
9987                 if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
9988                         continue;
9989
9990                 if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
9991                         any_relevant_change = true;
9992                         break;
9993                 }
9994
9995                 if (new_plane_state->fb == old_plane_state->fb &&
9996                     new_plane_state->crtc_w == old_plane_state->crtc_w &&
9997                     new_plane_state->crtc_h == old_plane_state->crtc_h)
9998                         continue;
9999
10000                 dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
10001                 dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
10002
10003                 if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
10004                         any_relevant_change = true;
10005                         break;
10006                 }
10007         }
10008
10009         if (!any_relevant_change)
10010                 return 0;
10011
10012         new_cursor_state = drm_atomic_get_plane_state(state, cursor);
10013         if (IS_ERR(new_cursor_state))
10014                 return PTR_ERR(new_cursor_state);
10015
10016         if (!new_cursor_state->fb)
10017                 return 0;
10018
10019         dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
10020
10021         /* Need to check all enabled planes, even if this commit doesn't change
10022          * their state
10023          */
10024         i = drm_atomic_add_affected_planes(state, crtc);
10025         if (i)
10026                 return i;
10027
10028         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
10029                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
10030                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
10031                         continue;
10032
10033                 /* Ignore disabled planes */
10034                 if (!new_underlying_state->fb)
10035                         continue;
10036
10037                 dm_get_plane_scale(new_underlying_state,
10038                                    &underlying_scale_w, &underlying_scale_h);
10039
10040                 if (cursor_scale_w != underlying_scale_w ||
10041                     cursor_scale_h != underlying_scale_h) {
10042                         drm_dbg_atomic(crtc->dev,
10043                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
10044                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
10045                         return -EINVAL;
10046                 }
10047
10048                 /* If this plane covers the whole CRTC, no need to check planes underneath */
10049                 if (new_underlying_state->crtc_x <= 0 &&
10050                     new_underlying_state->crtc_y <= 0 &&
10051                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
10052                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
10053                         break;
10054         }
10055
10056         return 0;
10057 }
10058
10059 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
10060 {
10061         struct drm_connector *connector;
10062         struct drm_connector_state *conn_state, *old_conn_state;
10063         struct amdgpu_dm_connector *aconnector = NULL;
10064         int i;
10065
10066         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
10067                 if (!conn_state->crtc)
10068                         conn_state = old_conn_state;
10069
10070                 if (conn_state->crtc != crtc)
10071                         continue;
10072
10073                 aconnector = to_amdgpu_dm_connector(connector);
10074                 if (!aconnector->mst_output_port || !aconnector->mst_root)
10075                         aconnector = NULL;
10076                 else
10077                         break;
10078         }
10079
10080         if (!aconnector)
10081                 return 0;
10082
10083         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
10084 }
10085
10086 /**
10087  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
10088  *
10089  * @dev: The DRM device
10090  * @state: The atomic state to commit
10091  *
10092  * Validate that the given atomic state is programmable by DC into hardware.
10093  * This involves constructing a &struct dc_state reflecting the new hardware
10094  * state we wish to commit, then querying DC to see if it is programmable. It's
10095  * important not to modify the existing DC state. Otherwise, atomic_check
10096  * may unexpectedly commit hardware changes.
10097  *
10098  * When validating the DC state, it's important that the right locks are
10099  * acquired. For full updates case which removes/adds/updates streams on one
10100  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
10101  * that any such full update commit will wait for completion of any outstanding
10102  * flip using DRMs synchronization events.
10103  *
10104  * Note that DM adds the affected connectors for all CRTCs in state, when that
10105  * might not seem necessary. This is because DC stream creation requires the
10106  * DC sink, which is tied to the DRM connector state. Cleaning this up should
10107  * be possible but non-trivial - a possible TODO item.
10108  *
10109  * Return: -Error code if validation failed.
10110  */
10111 static int amdgpu_dm_atomic_check(struct drm_device *dev,
10112                                   struct drm_atomic_state *state)
10113 {
10114         struct amdgpu_device *adev = drm_to_adev(dev);
10115         struct dm_atomic_state *dm_state = NULL;
10116         struct dc *dc = adev->dm.dc;
10117         struct drm_connector *connector;
10118         struct drm_connector_state *old_con_state, *new_con_state;
10119         struct drm_crtc *crtc;
10120         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
10121         struct drm_plane *plane;
10122         struct drm_plane_state *old_plane_state, *new_plane_state;
10123         enum dc_status status;
10124         int ret, i;
10125         bool lock_and_validation_needed = false;
10126         bool is_top_most_overlay = true;
10127         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
10128         struct drm_dp_mst_topology_mgr *mgr;
10129         struct drm_dp_mst_topology_state *mst_state;
10130         struct dsc_mst_fairness_vars vars[MAX_PIPES];
10131
10132         trace_amdgpu_dm_atomic_check_begin(state);
10133
10134         ret = drm_atomic_helper_check_modeset(dev, state);
10135         if (ret) {
10136                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
10137                 goto fail;
10138         }
10139
10140         /* Check connector changes */
10141         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10142                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10143                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10144
10145                 /* Skip connectors that are disabled or part of modeset already. */
10146                 if (!new_con_state->crtc)
10147                         continue;
10148
10149                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
10150                 if (IS_ERR(new_crtc_state)) {
10151                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
10152                         ret = PTR_ERR(new_crtc_state);
10153                         goto fail;
10154                 }
10155
10156                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
10157                     dm_old_con_state->scaling != dm_new_con_state->scaling)
10158                         new_crtc_state->connectors_changed = true;
10159         }
10160
10161         if (dc_resource_is_dsc_encoding_supported(dc)) {
10162                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10163                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
10164                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
10165                                 if (ret) {
10166                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
10167                                         goto fail;
10168                                 }
10169                         }
10170                 }
10171         }
10172         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10173                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
10174
10175                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
10176                     !new_crtc_state->color_mgmt_changed &&
10177                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
10178                         dm_old_crtc_state->dsc_force_changed == false)
10179                         continue;
10180
10181                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
10182                 if (ret) {
10183                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
10184                         goto fail;
10185                 }
10186
10187                 if (!new_crtc_state->enable)
10188                         continue;
10189
10190                 ret = drm_atomic_add_affected_connectors(state, crtc);
10191                 if (ret) {
10192                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
10193                         goto fail;
10194                 }
10195
10196                 ret = drm_atomic_add_affected_planes(state, crtc);
10197                 if (ret) {
10198                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
10199                         goto fail;
10200                 }
10201
10202                 if (dm_old_crtc_state->dsc_force_changed)
10203                         new_crtc_state->mode_changed = true;
10204         }
10205
10206         /*
10207          * Add all primary and overlay planes on the CRTC to the state
10208          * whenever a plane is enabled to maintain correct z-ordering
10209          * and to enable fast surface updates.
10210          */
10211         drm_for_each_crtc(crtc, dev) {
10212                 bool modified = false;
10213
10214                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
10215                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10216                                 continue;
10217
10218                         if (new_plane_state->crtc == crtc ||
10219                             old_plane_state->crtc == crtc) {
10220                                 modified = true;
10221                                 break;
10222                         }
10223                 }
10224
10225                 if (!modified)
10226                         continue;
10227
10228                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
10229                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
10230                                 continue;
10231
10232                         new_plane_state =
10233                                 drm_atomic_get_plane_state(state, plane);
10234
10235                         if (IS_ERR(new_plane_state)) {
10236                                 ret = PTR_ERR(new_plane_state);
10237                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
10238                                 goto fail;
10239                         }
10240                 }
10241         }
10242
10243         /*
10244          * DC consults the zpos (layer_index in DC terminology) to determine the
10245          * hw plane on which to enable the hw cursor (see
10246          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
10247          * atomic state, so call drm helper to normalize zpos.
10248          */
10249         ret = drm_atomic_normalize_zpos(dev, state);
10250         if (ret) {
10251                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
10252                 goto fail;
10253         }
10254
10255         /* Remove exiting planes if they are modified */
10256         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10257                 if (old_plane_state->fb && new_plane_state->fb &&
10258                     get_mem_type(old_plane_state->fb) !=
10259                     get_mem_type(new_plane_state->fb))
10260                         lock_and_validation_needed = true;
10261
10262                 ret = dm_update_plane_state(dc, state, plane,
10263                                             old_plane_state,
10264                                             new_plane_state,
10265                                             false,
10266                                             &lock_and_validation_needed,
10267                                             &is_top_most_overlay);
10268                 if (ret) {
10269                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10270                         goto fail;
10271                 }
10272         }
10273
10274         /* Disable all crtcs which require disable */
10275         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10276                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10277                                            old_crtc_state,
10278                                            new_crtc_state,
10279                                            false,
10280                                            &lock_and_validation_needed);
10281                 if (ret) {
10282                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10283                         goto fail;
10284                 }
10285         }
10286
10287         /* Enable all crtcs which require enable */
10288         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10289                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10290                                            old_crtc_state,
10291                                            new_crtc_state,
10292                                            true,
10293                                            &lock_and_validation_needed);
10294                 if (ret) {
10295                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10296                         goto fail;
10297                 }
10298         }
10299
10300         /* Add new/modified planes */
10301         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10302                 ret = dm_update_plane_state(dc, state, plane,
10303                                             old_plane_state,
10304                                             new_plane_state,
10305                                             true,
10306                                             &lock_and_validation_needed,
10307                                             &is_top_most_overlay);
10308                 if (ret) {
10309                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10310                         goto fail;
10311                 }
10312         }
10313
10314         if (dc_resource_is_dsc_encoding_supported(dc)) {
10315                 ret = pre_validate_dsc(state, &dm_state, vars);
10316                 if (ret != 0)
10317                         goto fail;
10318         }
10319
10320         /* Run this here since we want to validate the streams we created */
10321         ret = drm_atomic_helper_check_planes(dev, state);
10322         if (ret) {
10323                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10324                 goto fail;
10325         }
10326
10327         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10328                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10329                 if (dm_new_crtc_state->mpo_requested)
10330                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10331         }
10332
10333         /* Check cursor planes scaling */
10334         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10335                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10336                 if (ret) {
10337                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10338                         goto fail;
10339                 }
10340         }
10341
10342         if (state->legacy_cursor_update) {
10343                 /*
10344                  * This is a fast cursor update coming from the plane update
10345                  * helper, check if it can be done asynchronously for better
10346                  * performance.
10347                  */
10348                 state->async_update =
10349                         !drm_atomic_helper_async_check(dev, state);
10350
10351                 /*
10352                  * Skip the remaining global validation if this is an async
10353                  * update. Cursor updates can be done without affecting
10354                  * state or bandwidth calcs and this avoids the performance
10355                  * penalty of locking the private state object and
10356                  * allocating a new dc_state.
10357                  */
10358                 if (state->async_update)
10359                         return 0;
10360         }
10361
10362         /* Check scaling and underscan changes*/
10363         /* TODO Removed scaling changes validation due to inability to commit
10364          * new stream into context w\o causing full reset. Need to
10365          * decide how to handle.
10366          */
10367         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10368                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10369                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10370                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10371
10372                 /* Skip any modesets/resets */
10373                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10374                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10375                         continue;
10376
10377                 /* Skip any thing not scale or underscan changes */
10378                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10379                         continue;
10380
10381                 lock_and_validation_needed = true;
10382         }
10383
10384         /* set the slot info for each mst_state based on the link encoding format */
10385         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10386                 struct amdgpu_dm_connector *aconnector;
10387                 struct drm_connector *connector;
10388                 struct drm_connector_list_iter iter;
10389                 u8 link_coding_cap;
10390
10391                 drm_connector_list_iter_begin(dev, &iter);
10392                 drm_for_each_connector_iter(connector, &iter) {
10393                         if (connector->index == mst_state->mgr->conn_base_id) {
10394                                 aconnector = to_amdgpu_dm_connector(connector);
10395                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10396                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10397
10398                                 break;
10399                         }
10400                 }
10401                 drm_connector_list_iter_end(&iter);
10402         }
10403
10404         /**
10405          * Streams and planes are reset when there are changes that affect
10406          * bandwidth. Anything that affects bandwidth needs to go through
10407          * DC global validation to ensure that the configuration can be applied
10408          * to hardware.
10409          *
10410          * We have to currently stall out here in atomic_check for outstanding
10411          * commits to finish in this case because our IRQ handlers reference
10412          * DRM state directly - we can end up disabling interrupts too early
10413          * if we don't.
10414          *
10415          * TODO: Remove this stall and drop DM state private objects.
10416          */
10417         if (lock_and_validation_needed) {
10418                 ret = dm_atomic_get_state(state, &dm_state);
10419                 if (ret) {
10420                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10421                         goto fail;
10422                 }
10423
10424                 ret = do_aquire_global_lock(dev, state);
10425                 if (ret) {
10426                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10427                         goto fail;
10428                 }
10429
10430                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10431                 if (ret) {
10432                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10433                         ret = -EINVAL;
10434                         goto fail;
10435                 }
10436
10437                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10438                 if (ret) {
10439                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10440                         goto fail;
10441                 }
10442
10443                 /*
10444                  * Perform validation of MST topology in the state:
10445                  * We need to perform MST atomic check before calling
10446                  * dc_validate_global_state(), or there is a chance
10447                  * to get stuck in an infinite loop and hang eventually.
10448                  */
10449                 ret = drm_dp_mst_atomic_check(state);
10450                 if (ret) {
10451                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10452                         goto fail;
10453                 }
10454                 status = dc_validate_global_state(dc, dm_state->context, true);
10455                 if (status != DC_OK) {
10456                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10457                                        dc_status_to_str(status), status);
10458                         ret = -EINVAL;
10459                         goto fail;
10460                 }
10461         } else {
10462                 /*
10463                  * The commit is a fast update. Fast updates shouldn't change
10464                  * the DC context, affect global validation, and can have their
10465                  * commit work done in parallel with other commits not touching
10466                  * the same resource. If we have a new DC context as part of
10467                  * the DM atomic state from validation we need to free it and
10468                  * retain the existing one instead.
10469                  *
10470                  * Furthermore, since the DM atomic state only contains the DC
10471                  * context and can safely be annulled, we can free the state
10472                  * and clear the associated private object now to free
10473                  * some memory and avoid a possible use-after-free later.
10474                  */
10475
10476                 for (i = 0; i < state->num_private_objs; i++) {
10477                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10478
10479                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10480                                 int j = state->num_private_objs-1;
10481
10482                                 dm_atomic_destroy_state(obj,
10483                                                 state->private_objs[i].state);
10484
10485                                 /* If i is not at the end of the array then the
10486                                  * last element needs to be moved to where i was
10487                                  * before the array can safely be truncated.
10488                                  */
10489                                 if (i != j)
10490                                         state->private_objs[i] =
10491                                                 state->private_objs[j];
10492
10493                                 state->private_objs[j].ptr = NULL;
10494                                 state->private_objs[j].state = NULL;
10495                                 state->private_objs[j].old_state = NULL;
10496                                 state->private_objs[j].new_state = NULL;
10497
10498                                 state->num_private_objs = j;
10499                                 break;
10500                         }
10501                 }
10502         }
10503
10504         /* Store the overall update type for use later in atomic check. */
10505         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10506                 struct dm_crtc_state *dm_new_crtc_state =
10507                         to_dm_crtc_state(new_crtc_state);
10508
10509                 /*
10510                  * Only allow async flips for fast updates that don't change
10511                  * the FB pitch, the DCC state, rotation, etc.
10512                  */
10513                 if (new_crtc_state->async_flip && lock_and_validation_needed) {
10514                         drm_dbg_atomic(crtc->dev,
10515                                        "[CRTC:%d:%s] async flips are only supported for fast updates\n",
10516                                        crtc->base.id, crtc->name);
10517                         ret = -EINVAL;
10518                         goto fail;
10519                 }
10520
10521                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10522                         UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
10523         }
10524
10525         /* Must be success */
10526         WARN_ON(ret);
10527
10528         trace_amdgpu_dm_atomic_check_finish(state, ret);
10529
10530         return ret;
10531
10532 fail:
10533         if (ret == -EDEADLK)
10534                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10535         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10536                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10537         else
10538                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret);
10539
10540         trace_amdgpu_dm_atomic_check_finish(state, ret);
10541
10542         return ret;
10543 }
10544
10545 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10546                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10547 {
10548         u8 dpcd_data;
10549         bool capable = false;
10550
10551         if (amdgpu_dm_connector->dc_link &&
10552                 dm_helpers_dp_read_dpcd(
10553                                 NULL,
10554                                 amdgpu_dm_connector->dc_link,
10555                                 DP_DOWN_STREAM_PORT_COUNT,
10556                                 &dpcd_data,
10557                                 sizeof(dpcd_data))) {
10558                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10559         }
10560
10561         return capable;
10562 }
10563
10564 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10565                 unsigned int offset,
10566                 unsigned int total_length,
10567                 u8 *data,
10568                 unsigned int length,
10569                 struct amdgpu_hdmi_vsdb_info *vsdb)
10570 {
10571         bool res;
10572         union dmub_rb_cmd cmd;
10573         struct dmub_cmd_send_edid_cea *input;
10574         struct dmub_cmd_edid_cea_output *output;
10575
10576         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10577                 return false;
10578
10579         memset(&cmd, 0, sizeof(cmd));
10580
10581         input = &cmd.edid_cea.data.input;
10582
10583         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10584         cmd.edid_cea.header.sub_type = 0;
10585         cmd.edid_cea.header.payload_bytes =
10586                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10587         input->offset = offset;
10588         input->length = length;
10589         input->cea_total_length = total_length;
10590         memcpy(input->payload, data, length);
10591
10592         res = dm_execute_dmub_cmd(dm->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
10593         if (!res) {
10594                 DRM_ERROR("EDID CEA parser failed\n");
10595                 return false;
10596         }
10597
10598         output = &cmd.edid_cea.data.output;
10599
10600         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10601                 if (!output->ack.success) {
10602                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10603                                         output->ack.offset);
10604                 }
10605         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10606                 if (!output->amd_vsdb.vsdb_found)
10607                         return false;
10608
10609                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10610                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10611                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10612                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10613         } else {
10614                 DRM_WARN("Unknown EDID CEA parser results\n");
10615                 return false;
10616         }
10617
10618         return true;
10619 }
10620
10621 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10622                 u8 *edid_ext, int len,
10623                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10624 {
10625         int i;
10626
10627         /* send extension block to DMCU for parsing */
10628         for (i = 0; i < len; i += 8) {
10629                 bool res;
10630                 int offset;
10631
10632                 /* send 8 bytes a time */
10633                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10634                         return false;
10635
10636                 if (i+8 == len) {
10637                         /* EDID block sent completed, expect result */
10638                         int version, min_rate, max_rate;
10639
10640                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10641                         if (res) {
10642                                 /* amd vsdb found */
10643                                 vsdb_info->freesync_supported = 1;
10644                                 vsdb_info->amd_vsdb_version = version;
10645                                 vsdb_info->min_refresh_rate_hz = min_rate;
10646                                 vsdb_info->max_refresh_rate_hz = max_rate;
10647                                 return true;
10648                         }
10649                         /* not amd vsdb */
10650                         return false;
10651                 }
10652
10653                 /* check for ack*/
10654                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10655                 if (!res)
10656                         return false;
10657         }
10658
10659         return false;
10660 }
10661
10662 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10663                 u8 *edid_ext, int len,
10664                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10665 {
10666         int i;
10667
10668         /* send extension block to DMCU for parsing */
10669         for (i = 0; i < len; i += 8) {
10670                 /* send 8 bytes a time */
10671                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10672                         return false;
10673         }
10674
10675         return vsdb_info->freesync_supported;
10676 }
10677
10678 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10679                 u8 *edid_ext, int len,
10680                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10681 {
10682         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10683         bool ret;
10684
10685         mutex_lock(&adev->dm.dc_lock);
10686         if (adev->dm.dmub_srv)
10687                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10688         else
10689                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10690         mutex_unlock(&adev->dm.dc_lock);
10691         return ret;
10692 }
10693
10694 static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10695                           struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10696 {
10697         u8 *edid_ext = NULL;
10698         int i;
10699         int j = 0;
10700
10701         if (edid == NULL || edid->extensions == 0)
10702                 return -ENODEV;
10703
10704         /* Find DisplayID extension */
10705         for (i = 0; i < edid->extensions; i++) {
10706                 edid_ext = (void *)(edid + (i + 1));
10707                 if (edid_ext[0] == DISPLAYID_EXT)
10708                         break;
10709         }
10710
10711         while (j < EDID_LENGTH) {
10712                 struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
10713                 unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
10714
10715                 if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID &&
10716                                 amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) {
10717                         vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false;
10718                         vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3;
10719                         DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode);
10720
10721                         return true;
10722                 }
10723                 j++;
10724         }
10725
10726         return false;
10727 }
10728
10729 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10730                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10731 {
10732         u8 *edid_ext = NULL;
10733         int i;
10734         bool valid_vsdb_found = false;
10735
10736         /*----- drm_find_cea_extension() -----*/
10737         /* No EDID or EDID extensions */
10738         if (edid == NULL || edid->extensions == 0)
10739                 return -ENODEV;
10740
10741         /* Find CEA extension */
10742         for (i = 0; i < edid->extensions; i++) {
10743                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10744                 if (edid_ext[0] == CEA_EXT)
10745                         break;
10746         }
10747
10748         if (i == edid->extensions)
10749                 return -ENODEV;
10750
10751         /*----- cea_db_offsets() -----*/
10752         if (edid_ext[0] != CEA_EXT)
10753                 return -ENODEV;
10754
10755         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10756
10757         return valid_vsdb_found ? i : -ENODEV;
10758 }
10759
10760 /**
10761  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10762  *
10763  * @connector: Connector to query.
10764  * @edid: EDID from monitor
10765  *
10766  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10767  * track of some of the display information in the internal data struct used by
10768  * amdgpu_dm. This function checks which type of connector we need to set the
10769  * FreeSync parameters.
10770  */
10771 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10772                                     struct edid *edid)
10773 {
10774         int i = 0;
10775         struct detailed_timing *timing;
10776         struct detailed_non_pixel *data;
10777         struct detailed_data_monitor_range *range;
10778         struct amdgpu_dm_connector *amdgpu_dm_connector =
10779                         to_amdgpu_dm_connector(connector);
10780         struct dm_connector_state *dm_con_state = NULL;
10781         struct dc_sink *sink;
10782
10783         struct amdgpu_device *adev = drm_to_adev(connector->dev);
10784         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10785         bool freesync_capable = false;
10786         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10787
10788         if (!connector->state) {
10789                 DRM_ERROR("%s - Connector has no state", __func__);
10790                 goto update;
10791         }
10792
10793         sink = amdgpu_dm_connector->dc_sink ?
10794                 amdgpu_dm_connector->dc_sink :
10795                 amdgpu_dm_connector->dc_em_sink;
10796
10797         if (!edid || !sink) {
10798                 dm_con_state = to_dm_connector_state(connector->state);
10799
10800                 amdgpu_dm_connector->min_vfreq = 0;
10801                 amdgpu_dm_connector->max_vfreq = 0;
10802                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10803                 connector->display_info.monitor_range.min_vfreq = 0;
10804                 connector->display_info.monitor_range.max_vfreq = 0;
10805                 freesync_capable = false;
10806
10807                 goto update;
10808         }
10809
10810         dm_con_state = to_dm_connector_state(connector->state);
10811
10812         if (!adev->dm.freesync_module)
10813                 goto update;
10814
10815         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10816                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10817                 bool edid_check_required = false;
10818
10819                 if (edid) {
10820                         edid_check_required = is_dp_capable_without_timing_msa(
10821                                                 adev->dm.dc,
10822                                                 amdgpu_dm_connector);
10823                 }
10824
10825                 if (edid_check_required == true && (edid->version > 1 ||
10826                    (edid->version == 1 && edid->revision > 1))) {
10827                         for (i = 0; i < 4; i++) {
10828
10829                                 timing  = &edid->detailed_timings[i];
10830                                 data    = &timing->data.other_data;
10831                                 range   = &data->data.range;
10832                                 /*
10833                                  * Check if monitor has continuous frequency mode
10834                                  */
10835                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10836                                         continue;
10837                                 /*
10838                                  * Check for flag range limits only. If flag == 1 then
10839                                  * no additional timing information provided.
10840                                  * Default GTF, GTF Secondary curve and CVT are not
10841                                  * supported
10842                                  */
10843                                 if (range->flags != 1)
10844                                         continue;
10845
10846                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10847                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10848                                 amdgpu_dm_connector->pixel_clock_mhz =
10849                                         range->pixel_clock_mhz * 10;
10850
10851                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10852                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10853
10854                                 break;
10855                         }
10856
10857                         if (amdgpu_dm_connector->max_vfreq -
10858                             amdgpu_dm_connector->min_vfreq > 10) {
10859
10860                                 freesync_capable = true;
10861                         }
10862                 }
10863                 parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10864
10865                 if (vsdb_info.replay_mode) {
10866                         amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
10867                         amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
10868                         amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
10869                 }
10870
10871         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10872                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10873                 if (i >= 0 && vsdb_info.freesync_supported) {
10874                         timing  = &edid->detailed_timings[i];
10875                         data    = &timing->data.other_data;
10876
10877                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10878                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10879                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10880                                 freesync_capable = true;
10881
10882                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10883                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10884                 }
10885         }
10886
10887         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10888
10889         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10890                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10891                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10892
10893                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10894                         amdgpu_dm_connector->as_type = as_type;
10895                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10896
10897                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10898                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10899                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10900                                 freesync_capable = true;
10901
10902                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10903                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10904                 }
10905         }
10906
10907 update:
10908         if (dm_con_state)
10909                 dm_con_state->freesync_capable = freesync_capable;
10910
10911         if (connector->vrr_capable_property)
10912                 drm_connector_set_vrr_capable_property(connector,
10913                                                        freesync_capable);
10914 }
10915
10916 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10917 {
10918         struct amdgpu_device *adev = drm_to_adev(dev);
10919         struct dc *dc = adev->dm.dc;
10920         int i;
10921
10922         mutex_lock(&adev->dm.dc_lock);
10923         if (dc->current_state) {
10924                 for (i = 0; i < dc->current_state->stream_count; ++i)
10925                         dc->current_state->streams[i]
10926                                 ->triggered_crtc_reset.enabled =
10927                                 adev->dm.force_timing_sync;
10928
10929                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10930                 dc_trigger_sync(dc, dc->current_state);
10931         }
10932         mutex_unlock(&adev->dm.dc_lock);
10933 }
10934
10935 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10936                        u32 value, const char *func_name)
10937 {
10938 #ifdef DM_CHECK_ADDR_0
10939         if (address == 0) {
10940                 drm_err(adev_to_drm(ctx->driver_context),
10941                         "invalid register write. address = 0");
10942                 return;
10943         }
10944 #endif
10945         cgs_write_register(ctx->cgs_device, address, value);
10946         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10947 }
10948
10949 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10950                           const char *func_name)
10951 {
10952         u32 value;
10953 #ifdef DM_CHECK_ADDR_0
10954         if (address == 0) {
10955                 drm_err(adev_to_drm(ctx->driver_context),
10956                         "invalid register read; address = 0\n");
10957                 return 0;
10958         }
10959 #endif
10960
10961         if (ctx->dmub_srv &&
10962             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10963             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10964                 ASSERT(false);
10965                 return 0;
10966         }
10967
10968         value = cgs_read_register(ctx->cgs_device, address);
10969
10970         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10971
10972         return value;
10973 }
10974
10975 int amdgpu_dm_process_dmub_aux_transfer_sync(
10976                 struct dc_context *ctx,
10977                 unsigned int link_index,
10978                 struct aux_payload *payload,
10979                 enum aux_return_code_type *operation_result)
10980 {
10981         struct amdgpu_device *adev = ctx->driver_context;
10982         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10983         int ret = -1;
10984
10985         mutex_lock(&adev->dm.dpia_aux_lock);
10986         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10987                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10988                 goto out;
10989         }
10990
10991         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10992                 DRM_ERROR("wait_for_completion_timeout timeout!");
10993                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10994                 goto out;
10995         }
10996
10997         if (p_notify->result != AUX_RET_SUCCESS) {
10998                 /*
10999                  * Transient states before tunneling is enabled could
11000                  * lead to this error. We can ignore this for now.
11001                  */
11002                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
11003                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
11004                                         payload->address, payload->length,
11005                                         p_notify->result);
11006                 }
11007                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11008                 goto out;
11009         }
11010
11011
11012         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
11013         if (!payload->write && p_notify->aux_reply.length &&
11014                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
11015
11016                 if (payload->length != p_notify->aux_reply.length) {
11017                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
11018                                 p_notify->aux_reply.length,
11019                                         payload->address, payload->length);
11020                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
11021                         goto out;
11022                 }
11023
11024                 memcpy(payload->data, p_notify->aux_reply.data,
11025                                 p_notify->aux_reply.length);
11026         }
11027
11028         /* success */
11029         ret = p_notify->aux_reply.length;
11030         *operation_result = p_notify->result;
11031 out:
11032         reinit_completion(&adev->dm.dmub_aux_transfer_done);
11033         mutex_unlock(&adev->dm.dpia_aux_lock);
11034         return ret;
11035 }
11036
11037 int amdgpu_dm_process_dmub_set_config_sync(
11038                 struct dc_context *ctx,
11039                 unsigned int link_index,
11040                 struct set_config_cmd_payload *payload,
11041                 enum set_config_status *operation_result)
11042 {
11043         struct amdgpu_device *adev = ctx->driver_context;
11044         bool is_cmd_complete;
11045         int ret;
11046
11047         mutex_lock(&adev->dm.dpia_aux_lock);
11048         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
11049                         link_index, payload, adev->dm.dmub_notify);
11050
11051         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
11052                 ret = 0;
11053                 *operation_result = adev->dm.dmub_notify->sc_status;
11054         } else {
11055                 DRM_ERROR("wait_for_completion_timeout timeout!");
11056                 ret = -1;
11057                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
11058         }
11059
11060         if (!is_cmd_complete)
11061                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
11062         mutex_unlock(&adev->dm.dpia_aux_lock);
11063         return ret;
11064 }
11065
11066 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11067 {
11068         return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
11069 }
11070
11071 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
11072 {
11073         return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
11074 }