drivers/usb/phy/phy-tegra-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2010 Google, Inc.
   4  * Copyright (C) 2013 NVIDIA Corporation
   5  *
   6  * Author:
   7  *      Erik Gilling <[email protected]>
   8  *      Benoit Goby <[email protected]>
   9  *      Venu Byravarasu <[email protected]>
  10  */
  11
  12 #include <linux/resource.h>
  13 #include <linux/delay.h>
  14 #include <linux/slab.h>
  15 #include <linux/err.h>
  16 #include <linux/export.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/io.h>
  20 #include <linux/gpio.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_gpio.h>
  24 #include <linux/usb/otg.h>
  25 #include <linux/usb/ulpi.h>
  26 #include <linux/usb/of.h>
  27 #include <linux/usb/ehci_def.h>
  28 #include <linux/usb/tegra_usb_phy.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #define ULPI_VIEWPORT           0x170
  32
  33 /* PORTSC PTS/PHCD bits, Tegra20 only */
  34 #define TEGRA_USB_PORTSC1                               0x184
  35 #define TEGRA_USB_PORTSC1_PTS(x)                        (((x) & 0x3) << 30)
  36 #define TEGRA_USB_PORTSC1_PHCD                          (1 << 23)
  37
  38 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
  39 #define TEGRA_USB_HOSTPC1_DEVLC         0x1b4
  40 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)  (((x) & 0x7) << 29)
  41 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD    (1 << 22)
  42
  43 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  44 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  45
  46 #define USB_SUSP_CTRL           0x400
  47 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
  48 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
  49 #define   USB_SUSP_CLR          (1 << 5)
  50 #define   USB_PHY_CLK_VALID     (1 << 7)
  51 #define   UTMIP_RESET                   (1 << 11)
  52 #define   UHSIC_RESET                   (1 << 11)
  53 #define   UTMIP_PHY_ENABLE              (1 << 12)
  54 #define   ULPI_PHY_ENABLE       (1 << 13)
  55 #define   USB_SUSP_SET          (1 << 14)
  56 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
  57
  58 #define USB1_LEGACY_CTRL        0x410
  59 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
  60 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  61 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  62 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  63                                                 (1 << 1)
  64 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  65 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  66
  67 #define ULPI_TIMING_CTRL_0      0x424
  68 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
  69 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
  70
  71 #define ULPI_TIMING_CTRL_1      0x428
  72 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
  73 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
  74 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
  75 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  76 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
  77 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
  78
  79 #define UTMIP_PLL_CFG1          0x804
  80 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  81 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  82
  83 #define UTMIP_XCVR_CFG0         0x808
  84 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  85 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
  86 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  87 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  88 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
  89 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
  90 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
  91 #define   UTMIP_XCVR_LSBIAS_SEL                 (1 << 21)
  92 #define   UTMIP_XCVR_HSSLEW(x)                  (((x) & 0x3) << 4)
  93 #define   UTMIP_XCVR_HSSLEW_MSB(x)              ((((x) & 0x1fc) >> 2) << 25)
  94
  95 #define UTMIP_BIAS_CFG0         0x80c
  96 #define   UTMIP_OTGPD                   (1 << 11)
  97 #define   UTMIP_BIASPD                  (1 << 10)
  98 #define   UTMIP_HSSQUELCH_LEVEL(x)      (((x) & 0x3) << 0)
  99 #define   UTMIP_HSDISCON_LEVEL(x)       (((x) & 0x3) << 2)
 100 #define   UTMIP_HSDISCON_LEVEL_MSB(x)   ((((x) & 0x4) >> 2) << 24)
 101
 102 #define UTMIP_HSRX_CFG0         0x810
 103 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
 104 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
 105
 106 #define UTMIP_HSRX_CFG1         0x814
 107 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
 108
 109 #define UTMIP_TX_CFG0           0x820
 110 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
 111 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
 112
 113 #define UTMIP_MISC_CFG0         0x824
 114 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
 115 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
 116 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
 117 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
 118 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
 119 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
 120 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
 121
 122 #define UTMIP_MISC_CFG1         0x828
 123 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
 124 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
 125
 126 #define UTMIP_DEBOUNCE_CFG0     0x82c
 127 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
 128
 129 #define UTMIP_BAT_CHRG_CFG0     0x830
 130 #define   UTMIP_PD_CHRG                 (1 << 0)
 131
 132 #define UTMIP_SPARE_CFG0        0x834
 133 #define   FUSE_SETUP_SEL                (1 << 3)
 134
 135 #define UTMIP_XCVR_CFG1         0x838
 136 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
 137 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
 138 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
 139 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
 140
 141 #define UTMIP_BIAS_CFG1         0x83c
 142 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
 143
 144 /* For Tegra30 and above only, the address is different in Tegra20 */
 145 #define USB_USBMODE             0x1f8
 146 #define   USB_USBMODE_MASK              (3 << 0)
 147 #define   USB_USBMODE_HOST              (3 << 0)
 148 #define   USB_USBMODE_DEVICE            (2 << 0)
 149
 150 static DEFINE_SPINLOCK(utmip_pad_lock);
 151 static int utmip_pad_count;
 152
 153 struct tegra_xtal_freq {
 154         int freq;
 155         u8 enable_delay;
 156         u8 stable_count;
 157         u8 active_delay;
 158         u8 xtal_freq_count;
 159         u16 debounce;
 160 };
 161
 162 static const struct tegra_xtal_freq tegra_freq_table[] = {
 163         {
 164                 .freq = 12000000,
 165                 .enable_delay = 0x02,
 166                 .stable_count = 0x2F,
 167                 .active_delay = 0x04,
 168                 .xtal_freq_count = 0x76,
 169                 .debounce = 0x7530,
 170         },
 171         {
 172                 .freq = 13000000,
 173                 .enable_delay = 0x02,
 174                 .stable_count = 0x33,
 175                 .active_delay = 0x05,
 176                 .xtal_freq_count = 0x7F,
 177                 .debounce = 0x7EF4,
 178         },
 179         {
 180                 .freq = 19200000,
 181                 .enable_delay = 0x03,
 182                 .stable_count = 0x4B,
 183                 .active_delay = 0x06,
 184                 .xtal_freq_count = 0xBB,
 185                 .debounce = 0xBB80,
 186         },
 187         {
 188                 .freq = 26000000,
 189                 .enable_delay = 0x04,
 190                 .stable_count = 0x66,
 191                 .active_delay = 0x09,
 192                 .xtal_freq_count = 0xFE,
 193                 .debounce = 0xFDE8,
 194         },
 195 };
 196
 197 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 198 {
 199         void __iomem *base = phy->regs;
 200         unsigned long val;
 201
 202         if (phy->soc_config->has_hostpc) {
 203                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
 204                 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
 205                 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
 206                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 207         } else {
 208                 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS;
 209                 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
 210                 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
 211                 writel(val, base + TEGRA_USB_PORTSC1);
 212         }
 213 }
 214
 215 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 216 {
 217         void __iomem *base = phy->regs;
 218         unsigned long val;
 219
 220         if (phy->soc_config->has_hostpc) {
 221                 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC);
 222                 if (enable)
 223                         val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 224                 else
 225                         val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 226                 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 227         } else {
 228                 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
 229                 if (enable)
 230                         val |= TEGRA_USB_PORTSC1_PHCD;
 231                 else
 232                         val &= ~TEGRA_USB_PORTSC1_PHCD;
 233                 writel(val, base + TEGRA_USB_PORTSC1);
 234         }
 235 }
 236
 237 static int utmip_pad_open(struct tegra_usb_phy *phy)
 238 {
 239         phy->pad_clk = devm_clk_get(phy->u_phy.dev, "utmi-pads");
 240         if (IS_ERR(phy->pad_clk)) {
 241                 pr_err("%s: can't get utmip pad clock\n", __func__);
 242                 return PTR_ERR(phy->pad_clk);
 243         }
 244
 245         return 0;
 246 }
 247
 248 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 249 {
 250         unsigned long val, flags;
 251         void __iomem *base = phy->pad_regs;
 252         struct tegra_utmip_config *config = phy->config;
 253
 254         clk_prepare_enable(phy->pad_clk);
 255
 256         spin_lock_irqsave(&utmip_pad_lock, flags);
 257
 258         if (utmip_pad_count++ == 0) {
 259                 val = readl(base + UTMIP_BIAS_CFG0);
 260                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 261
 262                 if (phy->soc_config->requires_extra_tuning_parameters) {
 263                         val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
 264                                 UTMIP_HSDISCON_LEVEL(~0) |
 265                                 UTMIP_HSDISCON_LEVEL_MSB(~0));
 266
 267                         val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
 268                         val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
 269                         val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
 270                 }
 271                 writel(val, base + UTMIP_BIAS_CFG0);
 272         }
 273
 274         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 275
 276         clk_disable_unprepare(phy->pad_clk);
 277 }
 278
 279 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 280 {
 281         unsigned long val, flags;
 282         void __iomem *base = phy->pad_regs;
 283
 284         if (!utmip_pad_count) {
 285                 pr_err("%s: utmip pad already powered off\n", __func__);
 286                 return -EINVAL;
 287         }
 288
 289         clk_prepare_enable(phy->pad_clk);
 290
 291         spin_lock_irqsave(&utmip_pad_lock, flags);
 292
 293         if (--utmip_pad_count == 0) {
 294                 val = readl(base + UTMIP_BIAS_CFG0);
 295                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 296                 writel(val, base + UTMIP_BIAS_CFG0);
 297         }
 298
 299         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 300
 301         clk_disable_unprepare(phy->pad_clk);
 302
 303         return 0;
 304 }
 305
 306 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 307 {
 308         unsigned long timeout = 2000;
 309         do {
 310                 if ((readl(reg) & mask) == result)
 311                         return 0;
 312                 udelay(1);
 313                 timeout--;
 314         } while (timeout);
 315         return -1;
 316 }
 317
 318 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 319 {
 320         unsigned long val;
 321         void __iomem *base = phy->regs;
 322
 323         /*
 324          * The USB driver may have already initiated the phy clock
 325          * disable so wait to see if the clock turns off and if not
 326          * then proceed with gating the clock.
 327          */
 328         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
 329                 return;
 330
 331         if (phy->is_legacy_phy) {
 332                 val = readl(base + USB_SUSP_CTRL);
 333                 val |= USB_SUSP_SET;
 334                 writel(val, base + USB_SUSP_CTRL);
 335
 336                 udelay(10);
 337
 338                 val = readl(base + USB_SUSP_CTRL);
 339                 val &= ~USB_SUSP_SET;
 340                 writel(val, base + USB_SUSP_CTRL);
 341         } else
 342                 set_phcd(phy, true);
 343
 344         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 345                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 346 }
 347
 348 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 349 {
 350         unsigned long val;
 351         void __iomem *base = phy->regs;
 352
 353         /*
 354          * The USB driver may have already initiated the phy clock
 355          * enable so wait to see if the clock turns on and if not
 356          * then proceed with ungating the clock.
 357          */
 358         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 359                                USB_PHY_CLK_VALID) == 0)
 360                 return;
 361
 362         if (phy->is_legacy_phy) {
 363                 val = readl(base + USB_SUSP_CTRL);
 364                 val |= USB_SUSP_CLR;
 365                 writel(val, base + USB_SUSP_CTRL);
 366
 367                 udelay(10);
 368
 369                 val = readl(base + USB_SUSP_CTRL);
 370                 val &= ~USB_SUSP_CLR;
 371                 writel(val, base + USB_SUSP_CTRL);
 372         } else
 373                 set_phcd(phy, false);
 374
 375         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 376                                                      USB_PHY_CLK_VALID))
 377                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 378 }
 379
 380 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 381 {
 382         unsigned long val;
 383         void __iomem *base = phy->regs;
 384         struct tegra_utmip_config *config = phy->config;
 385
 386         val = readl(base + USB_SUSP_CTRL);
 387         val |= UTMIP_RESET;
 388         writel(val, base + USB_SUSP_CTRL);
 389
 390         if (phy->is_legacy_phy) {
 391                 val = readl(base + USB1_LEGACY_CTRL);
 392                 val |= USB1_NO_LEGACY_MODE;
 393                 writel(val, base + USB1_LEGACY_CTRL);
 394         }
 395
 396         val = readl(base + UTMIP_TX_CFG0);
 397         val |= UTMIP_FS_PREABMLE_J;
 398         writel(val, base + UTMIP_TX_CFG0);
 399
 400         val = readl(base + UTMIP_HSRX_CFG0);
 401         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 402         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 403         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 404         writel(val, base + UTMIP_HSRX_CFG0);
 405
 406         val = readl(base + UTMIP_HSRX_CFG1);
 407         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 408         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 409         writel(val, base + UTMIP_HSRX_CFG1);
 410
 411         val = readl(base + UTMIP_DEBOUNCE_CFG0);
 412         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 413         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 414         writel(val, base + UTMIP_DEBOUNCE_CFG0);
 415
 416         val = readl(base + UTMIP_MISC_CFG0);
 417         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 418         writel(val, base + UTMIP_MISC_CFG0);
 419
 420         if (!phy->soc_config->utmi_pll_config_in_car_module) {
 421                 val = readl(base + UTMIP_MISC_CFG1);
 422                 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
 423                         UTMIP_PLLU_STABLE_COUNT(~0));
 424                 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 425                         UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 426                 writel(val, base + UTMIP_MISC_CFG1);
 427
 428                 val = readl(base + UTMIP_PLL_CFG1);
 429                 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
 430                         UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 431                 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 432                         UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 433                 writel(val, base + UTMIP_PLL_CFG1);
 434         }
 435
 436         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 437                 val = readl(base + USB_SUSP_CTRL);
 438                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 439                 writel(val, base + USB_SUSP_CTRL);
 440
 441                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 442                 val &= ~UTMIP_PD_CHRG;
 443                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 444         } else {
 445                 val = readl(base + UTMIP_BAT_CHRG_CFG0);
 446                 val |= UTMIP_PD_CHRG;
 447                 writel(val, base + UTMIP_BAT_CHRG_CFG0);
 448         }
 449
 450         utmip_pad_power_on(phy);
 451
 452         val = readl(base + UTMIP_XCVR_CFG0);
 453         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 454                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
 455                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
 456                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
 457
 458         if (!config->xcvr_setup_use_fuses) {
 459                 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 460                 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
 461         }
 462         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 463         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 464
 465         if (phy->soc_config->requires_extra_tuning_parameters) {
 466                 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
 467                 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
 468                 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
 469         }
 470         writel(val, base + UTMIP_XCVR_CFG0);
 471
 472         val = readl(base + UTMIP_XCVR_CFG1);
 473         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 474                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 475         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 476         writel(val, base + UTMIP_XCVR_CFG1);
 477
 478         val = readl(base + UTMIP_BIAS_CFG1);
 479         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 480         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 481         writel(val, base + UTMIP_BIAS_CFG1);
 482
 483         val = readl(base + UTMIP_SPARE_CFG0);
 484         if (config->xcvr_setup_use_fuses)
 485                 val |= FUSE_SETUP_SEL;
 486         else
 487                 val &= ~FUSE_SETUP_SEL;
 488         writel(val, base + UTMIP_SPARE_CFG0);
 489
 490         if (!phy->is_legacy_phy) {
 491                 val = readl(base + USB_SUSP_CTRL);
 492                 val |= UTMIP_PHY_ENABLE;
 493                 writel(val, base + USB_SUSP_CTRL);
 494         }
 495
 496         val = readl(base + USB_SUSP_CTRL);
 497         val &= ~UTMIP_RESET;
 498         writel(val, base + USB_SUSP_CTRL);
 499
 500         if (phy->is_legacy_phy) {
 501                 val = readl(base + USB1_LEGACY_CTRL);
 502                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 503                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 504                 writel(val, base + USB1_LEGACY_CTRL);
 505
 506                 val = readl(base + USB_SUSP_CTRL);
 507                 val &= ~USB_SUSP_SET;
 508                 writel(val, base + USB_SUSP_CTRL);
 509         }
 510
 511         utmi_phy_clk_enable(phy);
 512
 513         if (phy->soc_config->requires_usbmode_setup) {
 514                 val = readl(base + USB_USBMODE);
 515                 val &= ~USB_USBMODE_MASK;
 516                 if (phy->mode == USB_DR_MODE_HOST)
 517                         val |= USB_USBMODE_HOST;
 518                 else
 519                         val |= USB_USBMODE_DEVICE;
 520                 writel(val, base + USB_USBMODE);
 521         }
 522
 523         if (!phy->is_legacy_phy)
 524                 set_pts(phy, 0);
 525
 526         return 0;
 527 }
 528
 529 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 530 {
 531         unsigned long val;
 532         void __iomem *base = phy->regs;
 533
 534         utmi_phy_clk_disable(phy);
 535
 536         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 537                 val = readl(base + USB_SUSP_CTRL);
 538                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 539                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 540                 writel(val, base + USB_SUSP_CTRL);
 541         }
 542
 543         val = readl(base + USB_SUSP_CTRL);
 544         val |= UTMIP_RESET;
 545         writel(val, base + USB_SUSP_CTRL);
 546
 547         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 548         val |= UTMIP_PD_CHRG;
 549         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 550
 551         val = readl(base + UTMIP_XCVR_CFG0);
 552         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 553                UTMIP_FORCE_PDZI_POWERDOWN;
 554         writel(val, base + UTMIP_XCVR_CFG0);
 555
 556         val = readl(base + UTMIP_XCVR_CFG1);
 557         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 558                UTMIP_FORCE_PDDR_POWERDOWN;
 559         writel(val, base + UTMIP_XCVR_CFG1);
 560
 561         return utmip_pad_power_off(phy);
 562 }
 563
 564 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 565 {
 566         unsigned long val;
 567         void __iomem *base = phy->regs;
 568
 569         val = readl(base + UTMIP_TX_CFG0);
 570         val |= UTMIP_HS_DISCON_DISABLE;
 571         writel(val, base + UTMIP_TX_CFG0);
 572 }
 573
 574 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 575 {
 576         unsigned long val;
 577         void __iomem *base = phy->regs;
 578
 579         val = readl(base + UTMIP_TX_CFG0);
 580         val &= ~UTMIP_HS_DISCON_DISABLE;
 581         writel(val, base + UTMIP_TX_CFG0);
 582 }
 583
 584 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 585                                    enum tegra_usb_phy_port_speed port_speed)
 586 {
 587         unsigned long val;
 588         void __iomem *base = phy->regs;
 589
 590         val = readl(base + UTMIP_MISC_CFG0);
 591         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 592         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 593                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 594         else
 595                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 596         writel(val, base + UTMIP_MISC_CFG0);
 597         udelay(1);
 598
 599         val = readl(base + UTMIP_MISC_CFG0);
 600         val |= UTMIP_DPDM_OBSERVE;
 601         writel(val, base + UTMIP_MISC_CFG0);
 602         udelay(10);
 603 }
 604
 605 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 606 {
 607         unsigned long val;
 608         void __iomem *base = phy->regs;
 609
 610         val = readl(base + UTMIP_MISC_CFG0);
 611         val &= ~UTMIP_DPDM_OBSERVE;
 612         writel(val, base + UTMIP_MISC_CFG0);
 613         udelay(10);
 614 }
 615
 616 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 617 {
 618         int ret;
 619         unsigned long val;
 620         void __iomem *base = phy->regs;
 621
 622         ret = gpio_direction_output(phy->reset_gpio, 0);
 623         if (ret < 0) {
 624                 dev_err(phy->u_phy.dev, "gpio %d not set to 0\n",
 625                         phy->reset_gpio);
 626                 return ret;
 627         }
 628         msleep(5);
 629         ret = gpio_direction_output(phy->reset_gpio, 1);
 630         if (ret < 0) {
 631                 dev_err(phy->u_phy.dev, "gpio %d not set to 1\n",
 632                         phy->reset_gpio);
 633                 return ret;
 634         }
 635
 636         clk_prepare_enable(phy->clk);
 637         msleep(1);
 638
 639         val = readl(base + USB_SUSP_CTRL);
 640         val |= UHSIC_RESET;
 641         writel(val, base + USB_SUSP_CTRL);
 642
 643         val = readl(base + ULPI_TIMING_CTRL_0);
 644         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 645         writel(val, base + ULPI_TIMING_CTRL_0);
 646
 647         val = readl(base + USB_SUSP_CTRL);
 648         val |= ULPI_PHY_ENABLE;
 649         writel(val, base + USB_SUSP_CTRL);
 650
 651         val = 0;
 652         writel(val, base + ULPI_TIMING_CTRL_1);
 653
 654         val |= ULPI_DATA_TRIMMER_SEL(4);
 655         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 656         val |= ULPI_DIR_TRIMMER_SEL(4);
 657         writel(val, base + ULPI_TIMING_CTRL_1);
 658         udelay(10);
 659
 660         val |= ULPI_DATA_TRIMMER_LOAD;
 661         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 662         val |= ULPI_DIR_TRIMMER_LOAD;
 663         writel(val, base + ULPI_TIMING_CTRL_1);
 664
 665         /* Fix VbusInvalid due to floating VBUS */
 666         ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 667         if (ret) {
 668                 pr_err("%s: ulpi write failed\n", __func__);
 669                 return ret;
 670         }
 671
 672         ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 673         if (ret) {
 674                 pr_err("%s: ulpi write failed\n", __func__);
 675                 return ret;
 676         }
 677
 678         val = readl(base + USB_SUSP_CTRL);
 679         val |= USB_SUSP_CLR;
 680         writel(val, base + USB_SUSP_CTRL);
 681         udelay(100);
 682
 683         val = readl(base + USB_SUSP_CTRL);
 684         val &= ~USB_SUSP_CLR;
 685         writel(val, base + USB_SUSP_CTRL);
 686
 687         return 0;
 688 }
 689
 690 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 691 {
 692         clk_disable(phy->clk);
 693         return gpio_direction_output(phy->reset_gpio, 0);
 694 }
 695
 696 static void tegra_usb_phy_close(struct tegra_usb_phy *phy)
 697 {
 698         if (!IS_ERR(phy->vbus))
 699                 regulator_disable(phy->vbus);
 700
 701         clk_disable_unprepare(phy->pll_u);
 702 }
 703
 704 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 705 {
 706         if (phy->is_ulpi_phy)
 707                 return ulpi_phy_power_on(phy);
 708         else
 709                 return utmi_phy_power_on(phy);
 710 }
 711
 712 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 713 {
 714         if (phy->is_ulpi_phy)
 715                 return ulpi_phy_power_off(phy);
 716         else
 717                 return utmi_phy_power_off(phy);
 718 }
 719
 720 static int      tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
 721 {
 722         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 723         if (suspend)
 724                 return tegra_usb_phy_power_off(phy);
 725         else
 726                 return tegra_usb_phy_power_on(phy);
 727 }
 728
 729 static int ulpi_open(struct tegra_usb_phy *phy)
 730 {
 731         int err;
 732
 733         phy->clk = devm_clk_get(phy->u_phy.dev, "ulpi-link");
 734         if (IS_ERR(phy->clk)) {
 735                 pr_err("%s: can't get ulpi clock\n", __func__);
 736                 return PTR_ERR(phy->clk);
 737         }
 738
 739         err = devm_gpio_request(phy->u_phy.dev, phy->reset_gpio,
 740                 "ulpi_phy_reset_b");
 741         if (err < 0) {
 742                 dev_err(phy->u_phy.dev, "request failed for gpio: %d\n",
 743                        phy->reset_gpio);
 744                 return err;
 745         }
 746
 747         err = gpio_direction_output(phy->reset_gpio, 0);
 748         if (err < 0) {
 749                 dev_err(phy->u_phy.dev, "gpio %d direction not set to output\n",
 750                        phy->reset_gpio);
 751                 return err;
 752         }
 753
 754         phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
 755         if (!phy->ulpi) {
 756                 dev_err(phy->u_phy.dev, "otg_ulpi_create returned NULL\n");
 757                 err = -ENOMEM;
 758                 return err;
 759         }
 760
 761         phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
 762         return 0;
 763 }
 764
 765 static int tegra_usb_phy_init(struct tegra_usb_phy *phy)
 766 {
 767         unsigned long parent_rate;
 768         int i;
 769         int err;
 770
 771         phy->pll_u = devm_clk_get(phy->u_phy.dev, "pll_u");
 772         if (IS_ERR(phy->pll_u)) {
 773                 pr_err("Can't get pll_u clock\n");
 774                 return PTR_ERR(phy->pll_u);
 775         }
 776
 777         err = clk_prepare_enable(phy->pll_u);
 778         if (err)
 779                 return err;
 780
 781         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 782         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 783                 if (tegra_freq_table[i].freq == parent_rate) {
 784                         phy->freq = &tegra_freq_table[i];
 785                         break;
 786                 }
 787         }
 788         if (!phy->freq) {
 789                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 790                 err = -EINVAL;
 791                 goto fail;
 792         }
 793
 794         if (!IS_ERR(phy->vbus)) {
 795                 err = regulator_enable(phy->vbus);
 796                 if (err) {
 797                         dev_err(phy->u_phy.dev,
 798                                 "failed to enable usb vbus regulator: %d\n",
 799                                 err);
 800                         goto fail;
 801                 }
 802         }
 803
 804         if (phy->is_ulpi_phy)
 805                 err = ulpi_open(phy);
 806         else
 807                 err = utmip_pad_open(phy);
 808         if (err < 0)
 809                 goto fail;
 810
 811         return 0;
 812
 813 fail:
 814         clk_disable_unprepare(phy->pll_u);
 815         return err;
 816 }
 817
 818 void tegra_usb_phy_preresume(struct usb_phy *x)
 819 {
 820         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 821
 822         if (!phy->is_ulpi_phy)
 823                 utmi_phy_preresume(phy);
 824 }
 825 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 826
 827 void tegra_usb_phy_postresume(struct usb_phy *x)
 828 {
 829         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 830
 831         if (!phy->is_ulpi_phy)
 832                 utmi_phy_postresume(phy);
 833 }
 834 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 835
 836 void tegra_ehci_phy_restore_start(struct usb_phy *x,
 837                                  enum tegra_usb_phy_port_speed port_speed)
 838 {
 839         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 840
 841         if (!phy->is_ulpi_phy)
 842                 utmi_phy_restore_start(phy, port_speed);
 843 }
 844 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 845
 846 void tegra_ehci_phy_restore_end(struct usb_phy *x)
 847 {
 848         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 849
 850         if (!phy->is_ulpi_phy)
 851                 utmi_phy_restore_end(phy);
 852 }
 853 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 854
 855 static int read_utmi_param(struct platform_device *pdev, const char *param,
 856                            u8 *dest)
 857 {
 858         u32 value;
 859         int err = of_property_read_u32(pdev->dev.of_node, param, &value);
 860         *dest = (u8)value;
 861         if (err < 0)
 862                 dev_err(&pdev->dev, "Failed to read USB UTMI parameter %s: %d\n",
 863                         param, err);
 864         return err;
 865 }
 866
 867 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
 868                           struct platform_device *pdev)
 869 {
 870         struct resource *res;
 871         int err;
 872         struct tegra_utmip_config *config;
 873
 874         tegra_phy->is_ulpi_phy = false;
 875
 876         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 877         if (!res) {
 878                 dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n");
 879                 return  -ENXIO;
 880         }
 881
 882         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
 883                 resource_size(res));
 884         if (!tegra_phy->pad_regs) {
 885                 dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n");
 886                 return -ENOMEM;
 887         }
 888
 889         tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
 890                                          GFP_KERNEL);
 891         if (!tegra_phy->config)
 892                 return -ENOMEM;
 893
 894         config = tegra_phy->config;
 895
 896         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
 897                 &config->hssync_start_delay);
 898         if (err < 0)
 899                 return err;
 900
 901         err = read_utmi_param(pdev, "nvidia,elastic-limit",
 902                 &config->elastic_limit);
 903         if (err < 0)
 904                 return err;
 905
 906         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
 907                 &config->idle_wait_delay);
 908         if (err < 0)
 909                 return err;
 910
 911         err = read_utmi_param(pdev, "nvidia,term-range-adj",
 912                 &config->term_range_adj);
 913         if (err < 0)
 914                 return err;
 915
 916         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
 917                 &config->xcvr_lsfslew);
 918         if (err < 0)
 919                 return err;
 920
 921         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
 922                 &config->xcvr_lsrslew);
 923         if (err < 0)
 924                 return err;
 925
 926         if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
 927                 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
 928                         &config->xcvr_hsslew);
 929                 if (err < 0)
 930                         return err;
 931
 932                 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
 933                         &config->hssquelch_level);
 934                 if (err < 0)
 935                         return err;
 936
 937                 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
 938                         &config->hsdiscon_level);
 939                 if (err < 0)
 940                         return err;
 941         }
 942
 943         config->xcvr_setup_use_fuses = of_property_read_bool(
 944                 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
 945
 946         if (!config->xcvr_setup_use_fuses) {
 947                 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
 948                         &config->xcvr_setup);
 949                 if (err < 0)
 950                         return err;
 951         }
 952
 953         return 0;
 954 }
 955
 956 static const struct tegra_phy_soc_config tegra20_soc_config = {
 957         .utmi_pll_config_in_car_module = false,
 958         .has_hostpc = false,
 959         .requires_usbmode_setup = false,
 960         .requires_extra_tuning_parameters = false,
 961 };
 962
 963 static const struct tegra_phy_soc_config tegra30_soc_config = {
 964         .utmi_pll_config_in_car_module = true,
 965         .has_hostpc = true,
 966         .requires_usbmode_setup = true,
 967         .requires_extra_tuning_parameters = true,
 968 };
 969
 970 static const struct of_device_id tegra_usb_phy_id_table[] = {
 971         { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
 972         { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
 973         { },
 974 };
 975 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
 976
 977 static int tegra_usb_phy_probe(struct platform_device *pdev)
 978 {
 979         const struct of_device_id *match;
 980         struct resource *res;
 981         struct tegra_usb_phy *tegra_phy = NULL;
 982         struct device_node *np = pdev->dev.of_node;
 983         enum usb_phy_interface phy_type;
 984         int err;
 985
 986         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
 987         if (!tegra_phy)
 988                 return -ENOMEM;
 989
 990         match = of_match_device(tegra_usb_phy_id_table, &pdev->dev);
 991         if (!match) {
 992                 dev_err(&pdev->dev, "Error: No device match found\n");
 993                 return -ENODEV;
 994         }
 995         tegra_phy->soc_config = match->data;
 996
 997         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 998         if (!res) {
 999                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1000                 return  -ENXIO;
1001         }
1002
1003         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1004                 resource_size(res));
1005         if (!tegra_phy->regs) {
1006                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1007                 return -ENOMEM;
1008         }
1009
1010         tegra_phy->is_legacy_phy =
1011                 of_property_read_bool(np, "nvidia,has-legacy-mode");
1012
1013         phy_type = of_usb_get_phy_mode(np);
1014         switch (phy_type) {
1015         case USBPHY_INTERFACE_MODE_UTMI:
1016                 err = utmi_phy_probe(tegra_phy, pdev);
1017                 if (err < 0)
1018                         return err;
1019                 break;
1020
1021         case USBPHY_INTERFACE_MODE_ULPI:
1022                 tegra_phy->is_ulpi_phy = true;
1023
1024                 tegra_phy->reset_gpio =
1025                         of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0);
1026                 if (!gpio_is_valid(tegra_phy->reset_gpio)) {
1027                         dev_err(&pdev->dev, "invalid gpio: %d\n",
1028                                 tegra_phy->reset_gpio);
1029                         return tegra_phy->reset_gpio;
1030                 }
1031                 tegra_phy->config = NULL;
1032                 break;
1033
1034         default:
1035                 dev_err(&pdev->dev, "phy_type is invalid or unsupported\n");
1036                 return -EINVAL;
1037         }
1038
1039         if (of_find_property(np, "dr_mode", NULL))
1040                 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1041         else
1042                 tegra_phy->mode = USB_DR_MODE_HOST;
1043
1044         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1045                 dev_err(&pdev->dev, "dr_mode is invalid\n");
1046                 return -EINVAL;
1047         }
1048
1049         /* On some boards, the VBUS regulator doesn't need to be controlled */
1050         if (of_find_property(np, "vbus-supply", NULL)) {
1051                 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1052                 if (IS_ERR(tegra_phy->vbus))
1053                         return PTR_ERR(tegra_phy->vbus);
1054         } else {
1055                 dev_notice(&pdev->dev, "no vbus regulator");
1056                 tegra_phy->vbus = ERR_PTR(-ENODEV);
1057         }
1058
1059         tegra_phy->u_phy.dev = &pdev->dev;
1060         err = tegra_usb_phy_init(tegra_phy);
1061         if (err < 0)
1062                 return err;
1063
1064         tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend;
1065
1066         platform_set_drvdata(pdev, tegra_phy);
1067
1068         err = usb_add_phy_dev(&tegra_phy->u_phy);
1069         if (err < 0) {
1070                 tegra_usb_phy_close(tegra_phy);
1071                 return err;
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int tegra_usb_phy_remove(struct platform_device *pdev)
1078 {
1079         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1080
1081         usb_remove_phy(&tegra_phy->u_phy);
1082         tegra_usb_phy_close(tegra_phy);
1083
1084         return 0;
1085 }
1086
1087 static struct platform_driver tegra_usb_phy_driver = {
1088         .probe          = tegra_usb_phy_probe,
1089         .remove         = tegra_usb_phy_remove,
1090         .driver         = {
1091                 .name   = "tegra-phy",
1092                 .of_match_table = tegra_usb_phy_id_table,
1093         },
1094 };
1095 module_platform_driver(tegra_usb_phy_driver);
1096
1097 MODULE_DESCRIPTION("Tegra USB PHY driver");
1098 MODULE_LICENSE("GPL v2");