drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <[email protected]>
   6  *           Gerald Baeza <[email protected]>
   7  *
   8  * Inspired by st-asc.c from STMicroelectronics (c)
   9  */
  10
  11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/console.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-direction.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pm_wakeirq.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/tty.h>
  36
  37 #include "stm32-usart.h"
  38
  39 static void stm32_stop_tx(struct uart_port *port);
  40 static void stm32_transmit_chars(struct uart_port *port);
  41
  42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  43 {
  44         return container_of(port, struct stm32_port, port);
  45 }
  46
  47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
  48 {
  49         u32 val;
  50
  51         val = readl_relaxed(port->membase + reg);
  52         val |= bits;
  53         writel_relaxed(val, port->membase + reg);
  54 }
  55
  56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  57 {
  58         u32 val;
  59
  60         val = readl_relaxed(port->membase + reg);
  61         val &= ~bits;
  62         writel_relaxed(val, port->membase + reg);
  63 }
  64
  65 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
  66                             bool threaded)
  67 {
  68         struct stm32_port *stm32_port = to_stm32_port(port);
  69         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
  70         enum dma_status status;
  71         struct dma_tx_state state;
  72
  73         *sr = readl_relaxed(port->membase + ofs->isr);
  74
  75         if (threaded && stm32_port->rx_ch) {
  76                 status = dmaengine_tx_status(stm32_port->rx_ch,
  77                                              stm32_port->rx_ch->cookie,
  78                                              &state);
  79                 if ((status == DMA_IN_PROGRESS) &&
  80                     (*last_res != state.residue))
  81                         return 1;
  82                 else
  83                         return 0;
  84         } else if (*sr & USART_SR_RXNE) {
  85                 return 1;
  86         }
  87         return 0;
  88 }
  89
  90 static unsigned long
  91 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
  92 {
  93         struct stm32_port *stm32_port = to_stm32_port(port);
  94         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
  95         unsigned long c;
  96
  97         if (stm32_port->rx_ch) {
  98                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
  99                 if ((*last_res) == 0)
 100                         *last_res = RX_BUF_L;
 101                 return c;
 102         } else {
 103                 return readl_relaxed(port->membase + ofs->rdr);
 104         }
 105 }
 106
 107 static void stm32_receive_chars(struct uart_port *port, bool threaded)
 108 {
 109         struct tty_port *tport = &port->state->port;
 110         struct stm32_port *stm32_port = to_stm32_port(port);
 111         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 112         unsigned long c;
 113         u32 sr;
 114         char flag;
 115
 116         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 117                 pm_wakeup_event(tport->tty->dev, 0);
 118
 119         while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
 120                 sr |= USART_SR_DUMMY_RX;
 121                 c = stm32_get_char(port, &sr, &stm32_port->last_res);
 122                 flag = TTY_NORMAL;
 123                 port->icount.rx++;
 124
 125                 if (sr & USART_SR_ERR_MASK) {
 126                         if (sr & USART_SR_LBD) {
 127                                 port->icount.brk++;
 128                                 if (uart_handle_break(port))
 129                                         continue;
 130                         } else if (sr & USART_SR_ORE) {
 131                                 if (ofs->icr != UNDEF_REG)
 132                                         writel_relaxed(USART_ICR_ORECF,
 133                                                        port->membase +
 134                                                        ofs->icr);
 135                                 port->icount.overrun++;
 136                         } else if (sr & USART_SR_PE) {
 137                                 port->icount.parity++;
 138                         } else if (sr & USART_SR_FE) {
 139                                 port->icount.frame++;
 140                         }
 141
 142                         sr &= port->read_status_mask;
 143
 144                         if (sr & USART_SR_LBD)
 145                                 flag = TTY_BREAK;
 146                         else if (sr & USART_SR_PE)
 147                                 flag = TTY_PARITY;
 148                         else if (sr & USART_SR_FE)
 149                                 flag = TTY_FRAME;
 150                 }
 151
 152                 if (uart_handle_sysrq_char(port, c))
 153                         continue;
 154                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 155         }
 156
 157         spin_unlock(&port->lock);
 158         tty_flip_buffer_push(tport);
 159         spin_lock(&port->lock);
 160 }
 161
 162 static void stm32_tx_dma_complete(void *arg)
 163 {
 164         struct uart_port *port = arg;
 165         struct stm32_port *stm32port = to_stm32_port(port);
 166         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 167         unsigned int isr;
 168         int ret;
 169
 170         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 171                                                 isr,
 172                                                 (isr & USART_SR_TC),
 173                                                 10, 100000);
 174
 175         if (ret)
 176                 dev_err(port->dev, "terminal count not set\n");
 177
 178         if (ofs->icr == UNDEF_REG)
 179                 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 180         else
 181                 stm32_set_bits(port, ofs->icr, USART_CR_TC);
 182
 183         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 184         stm32port->tx_dma_busy = false;
 185
 186         /* Let's see if we have pending data to send */
 187         stm32_transmit_chars(port);
 188 }
 189
 190 static void stm32_transmit_chars_pio(struct uart_port *port)
 191 {
 192         struct stm32_port *stm32_port = to_stm32_port(port);
 193         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 194         struct circ_buf *xmit = &port->state->xmit;
 195         unsigned int isr;
 196         int ret;
 197
 198         if (stm32_port->tx_dma_busy) {
 199                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 200                 stm32_port->tx_dma_busy = false;
 201         }
 202
 203         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 204                                                 isr,
 205                                                 (isr & USART_SR_TXE),
 206                                                 10, 100000);
 207
 208         if (ret)
 209                 dev_err(port->dev, "tx empty not set\n");
 210
 211         stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 212
 213         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 214         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 215         port->icount.tx++;
 216 }
 217
 218 static void stm32_transmit_chars_dma(struct uart_port *port)
 219 {
 220         struct stm32_port *stm32port = to_stm32_port(port);
 221         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 222         struct circ_buf *xmit = &port->state->xmit;
 223         struct dma_async_tx_descriptor *desc = NULL;
 224         dma_cookie_t cookie;
 225         unsigned int count, i;
 226
 227         if (stm32port->tx_dma_busy)
 228                 return;
 229
 230         stm32port->tx_dma_busy = true;
 231
 232         count = uart_circ_chars_pending(xmit);
 233
 234         if (count > TX_BUF_L)
 235                 count = TX_BUF_L;
 236
 237         if (xmit->tail < xmit->head) {
 238                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 239         } else {
 240                 size_t one = UART_XMIT_SIZE - xmit->tail;
 241                 size_t two;
 242
 243                 if (one > count)
 244                         one = count;
 245                 two = count - one;
 246
 247                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 248                 if (two)
 249                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 250         }
 251
 252         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 253                                            stm32port->tx_dma_buf,
 254                                            count,
 255                                            DMA_MEM_TO_DEV,
 256                                            DMA_PREP_INTERRUPT);
 257
 258         if (!desc) {
 259                 for (i = count; i > 0; i--)
 260                         stm32_transmit_chars_pio(port);
 261                 return;
 262         }
 263
 264         desc->callback = stm32_tx_dma_complete;
 265         desc->callback_param = port;
 266
 267         /* Push current DMA TX transaction in the pending queue */
 268         cookie = dmaengine_submit(desc);
 269
 270         /* Issue pending DMA TX requests */
 271         dma_async_issue_pending(stm32port->tx_ch);
 272
 273         stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 274         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 275
 276         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 277         port->icount.tx += count;
 278 }
 279
 280 static void stm32_transmit_chars(struct uart_port *port)
 281 {
 282         struct stm32_port *stm32_port = to_stm32_port(port);
 283         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 284         struct circ_buf *xmit = &port->state->xmit;
 285
 286         if (port->x_char) {
 287                 if (stm32_port->tx_dma_busy)
 288                         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 289                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 290                 port->x_char = 0;
 291                 port->icount.tx++;
 292                 if (stm32_port->tx_dma_busy)
 293                         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 294                 return;
 295         }
 296
 297         if (uart_tx_stopped(port)) {
 298                 stm32_stop_tx(port);
 299                 return;
 300         }
 301
 302         if (uart_circ_empty(xmit)) {
 303                 stm32_stop_tx(port);
 304                 return;
 305         }
 306
 307         if (stm32_port->tx_ch)
 308                 stm32_transmit_chars_dma(port);
 309         else
 310                 stm32_transmit_chars_pio(port);
 311
 312         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 313                 uart_write_wakeup(port);
 314
 315         if (uart_circ_empty(xmit))
 316                 stm32_stop_tx(port);
 317 }
 318
 319 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 320 {
 321         struct uart_port *port = ptr;
 322         struct stm32_port *stm32_port = to_stm32_port(port);
 323         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 324         u32 sr;
 325
 326         spin_lock(&port->lock);
 327
 328         sr = readl_relaxed(port->membase + ofs->isr);
 329
 330         if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
 331                 writel_relaxed(USART_ICR_WUCF,
 332                                port->membase + ofs->icr);
 333
 334         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 335                 stm32_receive_chars(port, false);
 336
 337         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 338                 stm32_transmit_chars(port);
 339
 340         spin_unlock(&port->lock);
 341
 342         if (stm32_port->rx_ch)
 343                 return IRQ_WAKE_THREAD;
 344         else
 345                 return IRQ_HANDLED;
 346 }
 347
 348 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
 349 {
 350         struct uart_port *port = ptr;
 351         struct stm32_port *stm32_port = to_stm32_port(port);
 352
 353         spin_lock(&port->lock);
 354
 355         if (stm32_port->rx_ch)
 356                 stm32_receive_chars(port, true);
 357
 358         spin_unlock(&port->lock);
 359
 360         return IRQ_HANDLED;
 361 }
 362
 363 static unsigned int stm32_tx_empty(struct uart_port *port)
 364 {
 365         struct stm32_port *stm32_port = to_stm32_port(port);
 366         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 367
 368         return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
 369 }
 370
 371 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 372 {
 373         struct stm32_port *stm32_port = to_stm32_port(port);
 374         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 375
 376         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 377                 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 378         else
 379                 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 380 }
 381
 382 static unsigned int stm32_get_mctrl(struct uart_port *port)
 383 {
 384         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 385         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 386 }
 387
 388 /* Transmit stop */
 389 static void stm32_stop_tx(struct uart_port *port)
 390 {
 391         struct stm32_port *stm32_port = to_stm32_port(port);
 392         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 393
 394         stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 395 }
 396
 397 /* There are probably characters waiting to be transmitted. */
 398 static void stm32_start_tx(struct uart_port *port)
 399 {
 400         struct circ_buf *xmit = &port->state->xmit;
 401
 402         if (uart_circ_empty(xmit))
 403                 return;
 404
 405         stm32_transmit_chars(port);
 406 }
 407
 408 /* Throttle the remote when input buffer is about to overflow. */
 409 static void stm32_throttle(struct uart_port *port)
 410 {
 411         struct stm32_port *stm32_port = to_stm32_port(port);
 412         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 413         unsigned long flags;
 414
 415         spin_lock_irqsave(&port->lock, flags);
 416         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 417         spin_unlock_irqrestore(&port->lock, flags);
 418 }
 419
 420 /* Unthrottle the remote, the input buffer can now accept data. */
 421 static void stm32_unthrottle(struct uart_port *port)
 422 {
 423         struct stm32_port *stm32_port = to_stm32_port(port);
 424         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 425         unsigned long flags;
 426
 427         spin_lock_irqsave(&port->lock, flags);
 428         stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 429         spin_unlock_irqrestore(&port->lock, flags);
 430 }
 431
 432 /* Receive stop */
 433 static void stm32_stop_rx(struct uart_port *port)
 434 {
 435         struct stm32_port *stm32_port = to_stm32_port(port);
 436         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 437
 438         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 439 }
 440
 441 /* Handle breaks - ignored by us */
 442 static void stm32_break_ctl(struct uart_port *port, int break_state)
 443 {
 444 }
 445
 446 static int stm32_startup(struct uart_port *port)
 447 {
 448         struct stm32_port *stm32_port = to_stm32_port(port);
 449         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 450         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 451         const char *name = to_platform_device(port->dev)->name;
 452         u32 val;
 453         int ret;
 454
 455         ret = request_threaded_irq(port->irq, stm32_interrupt,
 456                                    stm32_threaded_interrupt,
 457                                    IRQF_NO_SUSPEND, name, port);
 458         if (ret)
 459                 return ret;
 460
 461         if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
 462                 ret = dev_pm_set_dedicated_wake_irq(port->dev,
 463                                                     stm32_port->wakeirq);
 464                 if (ret) {
 465                         free_irq(port->irq, port);
 466                         return ret;
 467                 }
 468         }
 469
 470         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 471         if (stm32_port->fifoen)
 472                 val |= USART_CR1_FIFOEN;
 473         stm32_set_bits(port, ofs->cr1, val);
 474
 475         return 0;
 476 }
 477
 478 static void stm32_shutdown(struct uart_port *port)
 479 {
 480         struct stm32_port *stm32_port = to_stm32_port(port);
 481         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 482         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 483         u32 val;
 484
 485         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 486         val |= BIT(cfg->uart_enable_bit);
 487         if (stm32_port->fifoen)
 488                 val |= USART_CR1_FIFOEN;
 489         stm32_clr_bits(port, ofs->cr1, val);
 490
 491         dev_pm_clear_wake_irq(port->dev);
 492         free_irq(port->irq, port);
 493 }
 494
 495 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 496                             struct ktermios *old)
 497 {
 498         struct stm32_port *stm32_port = to_stm32_port(port);
 499         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 500         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 501         unsigned int baud;
 502         u32 usartdiv, mantissa, fraction, oversampling;
 503         tcflag_t cflag = termios->c_cflag;
 504         u32 cr1, cr2, cr3;
 505         unsigned long flags;
 506
 507         if (!stm32_port->hw_flow_control)
 508                 cflag &= ~CRTSCTS;
 509
 510         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 511
 512         spin_lock_irqsave(&port->lock, flags);
 513
 514         /* Stop serial port and reset value */
 515         writel_relaxed(0, port->membase + ofs->cr1);
 516
 517         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
 518         cr1 |= BIT(cfg->uart_enable_bit);
 519         if (stm32_port->fifoen)
 520                 cr1 |= USART_CR1_FIFOEN;
 521         cr2 = 0;
 522         cr3 = 0;
 523
 524         if (cflag & CSTOPB)
 525                 cr2 |= USART_CR2_STOP_2B;
 526
 527         if (cflag & PARENB) {
 528                 cr1 |= USART_CR1_PCE;
 529                 if ((cflag & CSIZE) == CS8) {
 530                         if (cfg->has_7bits_data)
 531                                 cr1 |= USART_CR1_M0;
 532                         else
 533                                 cr1 |= USART_CR1_M;
 534                 }
 535         }
 536
 537         if (cflag & PARODD)
 538                 cr1 |= USART_CR1_PS;
 539
 540         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 541         if (cflag & CRTSCTS) {
 542                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 543                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
 544         }
 545
 546         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 547
 548         /*
 549          * The USART supports 16 or 8 times oversampling.
 550          * By default we prefer 16 times oversampling, so that the receiver
 551          * has a better tolerance to clock deviations.
 552          * 8 times oversampling is only used to achieve higher speeds.
 553          */
 554         if (usartdiv < 16) {
 555                 oversampling = 8;
 556                 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 557         } else {
 558                 oversampling = 16;
 559                 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 560         }
 561
 562         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 563         fraction = usartdiv % oversampling;
 564         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 565
 566         uart_update_timeout(port, cflag, baud);
 567
 568         port->read_status_mask = USART_SR_ORE;
 569         if (termios->c_iflag & INPCK)
 570                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 571         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 572                 port->read_status_mask |= USART_SR_LBD;
 573
 574         /* Characters to ignore */
 575         port->ignore_status_mask = 0;
 576         if (termios->c_iflag & IGNPAR)
 577                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 578         if (termios->c_iflag & IGNBRK) {
 579                 port->ignore_status_mask |= USART_SR_LBD;
 580                 /*
 581                  * If we're ignoring parity and break indicators,
 582                  * ignore overruns too (for real raw support).
 583                  */
 584                 if (termios->c_iflag & IGNPAR)
 585                         port->ignore_status_mask |= USART_SR_ORE;
 586         }
 587
 588         /* Ignore all characters if CREAD is not set */
 589         if ((termios->c_cflag & CREAD) == 0)
 590                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 591
 592         if (stm32_port->rx_ch)
 593                 cr3 |= USART_CR3_DMAR;
 594
 595         writel_relaxed(cr3, port->membase + ofs->cr3);
 596         writel_relaxed(cr2, port->membase + ofs->cr2);
 597         writel_relaxed(cr1, port->membase + ofs->cr1);
 598
 599         spin_unlock_irqrestore(&port->lock, flags);
 600 }
 601
 602 static const char *stm32_type(struct uart_port *port)
 603 {
 604         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 605 }
 606
 607 static void stm32_release_port(struct uart_port *port)
 608 {
 609 }
 610
 611 static int stm32_request_port(struct uart_port *port)
 612 {
 613         return 0;
 614 }
 615
 616 static void stm32_config_port(struct uart_port *port, int flags)
 617 {
 618         if (flags & UART_CONFIG_TYPE)
 619                 port->type = PORT_STM32;
 620 }
 621
 622 static int
 623 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 624 {
 625         /* No user changeable parameters */
 626         return -EINVAL;
 627 }
 628
 629 static void stm32_pm(struct uart_port *port, unsigned int state,
 630                 unsigned int oldstate)
 631 {
 632         struct stm32_port *stm32port = container_of(port,
 633                         struct stm32_port, port);
 634         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 635         struct stm32_usart_config *cfg = &stm32port->info->cfg;
 636         unsigned long flags = 0;
 637
 638         switch (state) {
 639         case UART_PM_STATE_ON:
 640                 clk_prepare_enable(stm32port->clk);
 641                 break;
 642         case UART_PM_STATE_OFF:
 643                 spin_lock_irqsave(&port->lock, flags);
 644                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 645                 spin_unlock_irqrestore(&port->lock, flags);
 646                 clk_disable_unprepare(stm32port->clk);
 647                 break;
 648         }
 649 }
 650
 651 static const struct uart_ops stm32_uart_ops = {
 652         .tx_empty       = stm32_tx_empty,
 653         .set_mctrl      = stm32_set_mctrl,
 654         .get_mctrl      = stm32_get_mctrl,
 655         .stop_tx        = stm32_stop_tx,
 656         .start_tx       = stm32_start_tx,
 657         .throttle       = stm32_throttle,
 658         .unthrottle     = stm32_unthrottle,
 659         .stop_rx        = stm32_stop_rx,
 660         .break_ctl      = stm32_break_ctl,
 661         .startup        = stm32_startup,
 662         .shutdown       = stm32_shutdown,
 663         .set_termios    = stm32_set_termios,
 664         .pm             = stm32_pm,
 665         .type           = stm32_type,
 666         .release_port   = stm32_release_port,
 667         .request_port   = stm32_request_port,
 668         .config_port    = stm32_config_port,
 669         .verify_port    = stm32_verify_port,
 670 };
 671
 672 static int stm32_init_port(struct stm32_port *stm32port,
 673                           struct platform_device *pdev)
 674 {
 675         struct uart_port *port = &stm32port->port;
 676         struct resource *res;
 677         int ret;
 678
 679         port->iotype    = UPIO_MEM;
 680         port->flags     = UPF_BOOT_AUTOCONF;
 681         port->ops       = &stm32_uart_ops;
 682         port->dev       = &pdev->dev;
 683         port->irq       = platform_get_irq(pdev, 0);
 684         stm32port->wakeirq = platform_get_irq(pdev, 1);
 685         stm32port->fifoen = stm32port->info->cfg.has_fifo;
 686
 687         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 688         port->membase = devm_ioremap_resource(&pdev->dev, res);
 689         if (IS_ERR(port->membase))
 690                 return PTR_ERR(port->membase);
 691         port->mapbase = res->start;
 692
 693         spin_lock_init(&port->lock);
 694
 695         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 696         if (IS_ERR(stm32port->clk))
 697                 return PTR_ERR(stm32port->clk);
 698
 699         /* Ensure that clk rate is correct by enabling the clk */
 700         ret = clk_prepare_enable(stm32port->clk);
 701         if (ret)
 702                 return ret;
 703
 704         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 705         if (!stm32port->port.uartclk) {
 706                 clk_disable_unprepare(stm32port->clk);
 707                 ret = -EINVAL;
 708         }
 709
 710         return ret;
 711 }
 712
 713 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 714 {
 715         struct device_node *np = pdev->dev.of_node;
 716         int id;
 717
 718         if (!np)
 719                 return NULL;
 720
 721         id = of_alias_get_id(np, "serial");
 722         if (id < 0) {
 723                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
 724                 return NULL;
 725         }
 726
 727         if (WARN_ON(id >= STM32_MAX_PORTS))
 728                 return NULL;
 729
 730         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 731                                                         "st,hw-flow-ctrl");
 732         stm32_ports[id].port.line = id;
 733         stm32_ports[id].last_res = RX_BUF_L;
 734         return &stm32_ports[id];
 735 }
 736
 737 #ifdef CONFIG_OF
 738 static const struct of_device_id stm32_match[] = {
 739         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
 740         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
 741         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
 742         {},
 743 };
 744
 745 MODULE_DEVICE_TABLE(of, stm32_match);
 746 #endif
 747
 748 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
 749                                  struct platform_device *pdev)
 750 {
 751         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 752         struct uart_port *port = &stm32port->port;
 753         struct device *dev = &pdev->dev;
 754         struct dma_slave_config config;
 755         struct dma_async_tx_descriptor *desc = NULL;
 756         dma_cookie_t cookie;
 757         int ret;
 758
 759         /* Request DMA RX channel */
 760         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
 761         if (!stm32port->rx_ch) {
 762                 dev_info(dev, "rx dma alloc failed\n");
 763                 return -ENODEV;
 764         }
 765         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
 766                                                  &stm32port->rx_dma_buf,
 767                                                  GFP_KERNEL);
 768         if (!stm32port->rx_buf) {
 769                 ret = -ENOMEM;
 770                 goto alloc_err;
 771         }
 772
 773         /* Configure DMA channel */
 774         memset(&config, 0, sizeof(config));
 775         config.src_addr = port->mapbase + ofs->rdr;
 776         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 777
 778         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
 779         if (ret < 0) {
 780                 dev_err(dev, "rx dma channel config failed\n");
 781                 ret = -ENODEV;
 782                 goto config_err;
 783         }
 784
 785         /* Prepare a DMA cyclic transaction */
 786         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
 787                                          stm32port->rx_dma_buf,
 788                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
 789                                          DMA_PREP_INTERRUPT);
 790         if (!desc) {
 791                 dev_err(dev, "rx dma prep cyclic failed\n");
 792                 ret = -ENODEV;
 793                 goto config_err;
 794         }
 795
 796         /* No callback as dma buffer is drained on usart interrupt */
 797         desc->callback = NULL;
 798         desc->callback_param = NULL;
 799
 800         /* Push current DMA transaction in the pending queue */
 801         cookie = dmaengine_submit(desc);
 802
 803         /* Issue pending DMA requests */
 804         dma_async_issue_pending(stm32port->rx_ch);
 805
 806         return 0;
 807
 808 config_err:
 809         dma_free_coherent(&pdev->dev,
 810                           RX_BUF_L, stm32port->rx_buf,
 811                           stm32port->rx_dma_buf);
 812
 813 alloc_err:
 814         dma_release_channel(stm32port->rx_ch);
 815         stm32port->rx_ch = NULL;
 816
 817         return ret;
 818 }
 819
 820 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
 821                                  struct platform_device *pdev)
 822 {
 823         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 824         struct uart_port *port = &stm32port->port;
 825         struct device *dev = &pdev->dev;
 826         struct dma_slave_config config;
 827         int ret;
 828
 829         stm32port->tx_dma_busy = false;
 830
 831         /* Request DMA TX channel */
 832         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
 833         if (!stm32port->tx_ch) {
 834                 dev_info(dev, "tx dma alloc failed\n");
 835                 return -ENODEV;
 836         }
 837         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
 838                                                  &stm32port->tx_dma_buf,
 839                                                  GFP_KERNEL);
 840         if (!stm32port->tx_buf) {
 841                 ret = -ENOMEM;
 842                 goto alloc_err;
 843         }
 844
 845         /* Configure DMA channel */
 846         memset(&config, 0, sizeof(config));
 847         config.dst_addr = port->mapbase + ofs->tdr;
 848         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 849
 850         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
 851         if (ret < 0) {
 852                 dev_err(dev, "tx dma channel config failed\n");
 853                 ret = -ENODEV;
 854                 goto config_err;
 855         }
 856
 857         return 0;
 858
 859 config_err:
 860         dma_free_coherent(&pdev->dev,
 861                           TX_BUF_L, stm32port->tx_buf,
 862                           stm32port->tx_dma_buf);
 863
 864 alloc_err:
 865         dma_release_channel(stm32port->tx_ch);
 866         stm32port->tx_ch = NULL;
 867
 868         return ret;
 869 }
 870
 871 static int stm32_serial_probe(struct platform_device *pdev)
 872 {
 873         const struct of_device_id *match;
 874         struct stm32_port *stm32port;
 875         int ret;
 876
 877         stm32port = stm32_of_get_stm32_port(pdev);
 878         if (!stm32port)
 879                 return -ENODEV;
 880
 881         match = of_match_device(stm32_match, &pdev->dev);
 882         if (match && match->data)
 883                 stm32port->info = (struct stm32_usart_info *)match->data;
 884         else
 885                 return -EINVAL;
 886
 887         ret = stm32_init_port(stm32port, pdev);
 888         if (ret)
 889                 return ret;
 890
 891         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
 892                 ret = device_init_wakeup(&pdev->dev, true);
 893                 if (ret)
 894                         goto err_uninit;
 895         }
 896
 897         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
 898         if (ret)
 899                 goto err_nowup;
 900
 901         ret = stm32_of_dma_rx_probe(stm32port, pdev);
 902         if (ret)
 903                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
 904
 905         ret = stm32_of_dma_tx_probe(stm32port, pdev);
 906         if (ret)
 907                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
 908
 909         platform_set_drvdata(pdev, &stm32port->port);
 910
 911         return 0;
 912
 913 err_nowup:
 914         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
 915                 device_init_wakeup(&pdev->dev, false);
 916
 917 err_uninit:
 918         clk_disable_unprepare(stm32port->clk);
 919
 920         return ret;
 921 }
 922
 923 static int stm32_serial_remove(struct platform_device *pdev)
 924 {
 925         struct uart_port *port = platform_get_drvdata(pdev);
 926         struct stm32_port *stm32_port = to_stm32_port(port);
 927         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 928         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 929
 930         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 931
 932         if (stm32_port->rx_ch)
 933                 dma_release_channel(stm32_port->rx_ch);
 934
 935         if (stm32_port->rx_dma_buf)
 936                 dma_free_coherent(&pdev->dev,
 937                                   RX_BUF_L, stm32_port->rx_buf,
 938                                   stm32_port->rx_dma_buf);
 939
 940         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 941
 942         if (stm32_port->tx_ch)
 943                 dma_release_channel(stm32_port->tx_ch);
 944
 945         if (stm32_port->tx_dma_buf)
 946                 dma_free_coherent(&pdev->dev,
 947                                   TX_BUF_L, stm32_port->tx_buf,
 948                                   stm32_port->tx_dma_buf);
 949
 950         if (cfg->has_wakeup && stm32_port->wakeirq >= 0)
 951                 device_init_wakeup(&pdev->dev, false);
 952
 953         clk_disable_unprepare(stm32_port->clk);
 954
 955         return uart_remove_one_port(&stm32_usart_driver, port);
 956 }
 957
 958
 959 #ifdef CONFIG_SERIAL_STM32_CONSOLE
 960 static void stm32_console_putchar(struct uart_port *port, int ch)
 961 {
 962         struct stm32_port *stm32_port = to_stm32_port(port);
 963         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 964
 965         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
 966                 cpu_relax();
 967
 968         writel_relaxed(ch, port->membase + ofs->tdr);
 969 }
 970
 971 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
 972 {
 973         struct uart_port *port = &stm32_ports[co->index].port;
 974         struct stm32_port *stm32_port = to_stm32_port(port);
 975         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 976         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 977         unsigned long flags;
 978         u32 old_cr1, new_cr1;
 979         int locked = 1;
 980
 981         local_irq_save(flags);
 982         if (port->sysrq)
 983                 locked = 0;
 984         else if (oops_in_progress)
 985                 locked = spin_trylock(&port->lock);
 986         else
 987                 spin_lock(&port->lock);
 988
 989         /* Save and disable interrupts, enable the transmitter */
 990         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
 991         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
 992         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
 993         writel_relaxed(new_cr1, port->membase + ofs->cr1);
 994
 995         uart_console_write(port, s, cnt, stm32_console_putchar);
 996
 997         /* Restore interrupt state */
 998         writel_relaxed(old_cr1, port->membase + ofs->cr1);
 999
1000         if (locked)
1001                 spin_unlock(&port->lock);
1002         local_irq_restore(flags);
1003 }
1004
1005 static int stm32_console_setup(struct console *co, char *options)
1006 {
1007         struct stm32_port *stm32port;
1008         int baud = 9600;
1009         int bits = 8;
1010         int parity = 'n';
1011         int flow = 'n';
1012
1013         if (co->index >= STM32_MAX_PORTS)
1014                 return -ENODEV;
1015
1016         stm32port = &stm32_ports[co->index];
1017
1018         /*
1019          * This driver does not support early console initialization
1020          * (use ARM early printk support instead), so we only expect
1021          * this to be called during the uart port registration when the
1022          * driver gets probed and the port should be mapped at that point.
1023          */
1024         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1025                 return -ENXIO;
1026
1027         if (options)
1028                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1029
1030         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1031 }
1032
1033 static struct console stm32_console = {
1034         .name           = STM32_SERIAL_NAME,
1035         .device         = uart_console_device,
1036         .write          = stm32_console_write,
1037         .setup          = stm32_console_setup,
1038         .flags          = CON_PRINTBUFFER,
1039         .index          = -1,
1040         .data           = &stm32_usart_driver,
1041 };
1042
1043 #define STM32_SERIAL_CONSOLE (&stm32_console)
1044
1045 #else
1046 #define STM32_SERIAL_CONSOLE NULL
1047 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1048
1049 static struct uart_driver stm32_usart_driver = {
1050         .driver_name    = DRIVER_NAME,
1051         .dev_name       = STM32_SERIAL_NAME,
1052         .major          = 0,
1053         .minor          = 0,
1054         .nr             = STM32_MAX_PORTS,
1055         .cons           = STM32_SERIAL_CONSOLE,
1056 };
1057
1058 #ifdef CONFIG_PM_SLEEP
1059 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1060 {
1061         struct stm32_port *stm32_port = to_stm32_port(port);
1062         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1063         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1064         u32 val;
1065
1066         if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1067                 return;
1068
1069         if (enable) {
1070                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1071                 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1072                 val = readl_relaxed(port->membase + ofs->cr3);
1073                 val &= ~USART_CR3_WUS_MASK;
1074                 /* Enable Wake up interrupt from low power on start bit */
1075                 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1076                 writel_relaxed(val, port->membase + ofs->cr3);
1077                 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1078         } else {
1079                 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1080         }
1081 }
1082
1083 static int stm32_serial_suspend(struct device *dev)
1084 {
1085         struct uart_port *port = dev_get_drvdata(dev);
1086
1087         uart_suspend_port(&stm32_usart_driver, port);
1088
1089         if (device_may_wakeup(dev))
1090                 stm32_serial_enable_wakeup(port, true);
1091         else
1092                 stm32_serial_enable_wakeup(port, false);
1093
1094         return 0;
1095 }
1096
1097 static int stm32_serial_resume(struct device *dev)
1098 {
1099         struct uart_port *port = dev_get_drvdata(dev);
1100
1101         if (device_may_wakeup(dev))
1102                 stm32_serial_enable_wakeup(port, false);
1103
1104         return uart_resume_port(&stm32_usart_driver, port);
1105 }
1106 #endif /* CONFIG_PM_SLEEP */
1107
1108 static const struct dev_pm_ops stm32_serial_pm_ops = {
1109         SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1110 };
1111
1112 static struct platform_driver stm32_serial_driver = {
1113         .probe          = stm32_serial_probe,
1114         .remove         = stm32_serial_remove,
1115         .driver = {
1116                 .name   = DRIVER_NAME,
1117                 .pm     = &stm32_serial_pm_ops,
1118                 .of_match_table = of_match_ptr(stm32_match),
1119         },
1120 };
1121
1122 static int __init usart_init(void)
1123 {
1124         static char banner[] __initdata = "STM32 USART driver initialized";
1125         int ret;
1126
1127         pr_info("%s\n", banner);
1128
1129         ret = uart_register_driver(&stm32_usart_driver);
1130         if (ret)
1131                 return ret;
1132
1133         ret = platform_driver_register(&stm32_serial_driver);
1134         if (ret)
1135                 uart_unregister_driver(&stm32_usart_driver);
1136
1137         return ret;
1138 }
1139
1140 static void __exit usart_exit(void)
1141 {
1142         platform_driver_unregister(&stm32_serial_driver);
1143         uart_unregister_driver(&stm32_usart_driver);
1144 }
1145
1146 module_init(usart_init);
1147 module_exit(usart_exit);
1148
1149 MODULE_ALIAS("platform:" DRIVER_NAME);
1150 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1151 MODULE_LICENSE("GPL v2");