drivers/net/phy/dp83867.c

   1 /*
   2  * Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/ethtool.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mii.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/phy.h>
  22
  23 #include <dt-bindings/net/ti-dp83867.h>
  24
  25 #define DP83867_PHY_ID          0x2000a231
  26 #define DP83867_DEVADDR         0x1f
  27
  28 #define MII_DP83867_PHYCTRL     0x10
  29 #define MII_DP83867_MICR        0x12
  30 #define MII_DP83867_ISR         0x13
  31 #define DP83867_CTRL            0x1f
  32 #define DP83867_CFG3            0x1e
  33
  34 /* Extended Registers */
  35 #define DP83867_CFG4            0x0031
  36 #define DP83867_RGMIICTL        0x0032
  37 #define DP83867_STRAP_STS1      0x006E
  38 #define DP83867_RGMIIDCTL       0x0086
  39 #define DP83867_IO_MUX_CFG      0x0170
  40
  41 #define DP83867_SW_RESET        BIT(15)
  42 #define DP83867_SW_RESTART      BIT(14)
  43
  44 /* MICR Interrupt bits */
  45 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  46 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  47 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  48 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  49 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  50 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  51 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  52 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  53 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  54 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  55 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  56 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  57
  58 /* RGMIICTL bits */
  59 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  60 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  61
  62 /* STRAP_STS1 bits */
  63 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  64
  65 /* PHY CTRL bits */
  66 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  67 #define DP83867_PHYCR_FIFO_DEPTH_MASK           (3 << 14)
  68 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
  69
  70 /* RGMIIDCTL bits */
  71 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  72
  73 /* IO_MUX_CFG bits */
  74 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  75
  76 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  77 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  78
  79 /* CFG4 bits */
  80 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
  81
  82 enum {
  83         DP83867_PORT_MIRROING_KEEP,
  84         DP83867_PORT_MIRROING_EN,
  85         DP83867_PORT_MIRROING_DIS,
  86 };
  87
  88 struct dp83867_private {
  89         int rx_id_delay;
  90         int tx_id_delay;
  91         int fifo_depth;
  92         int io_impedance;
  93         int port_mirroring;
  94         bool rxctrl_strap_quirk;
  95 };
  96
  97 static int dp83867_ack_interrupt(struct phy_device *phydev)
  98 {
  99         int err = phy_read(phydev, MII_DP83867_ISR);
 100
 101         if (err < 0)
 102                 return err;
 103
 104         return 0;
 105 }
 106
 107 static int dp83867_config_intr(struct phy_device *phydev)
 108 {
 109         int micr_status;
 110
 111         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 112                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 113                 if (micr_status < 0)
 114                         return micr_status;
 115
 116                 micr_status |=
 117                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 118                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 119                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 120                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 121                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 122                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 123
 124                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 125         }
 126
 127         micr_status = 0x0;
 128         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 129 }
 130
 131 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 132 {
 133         struct dp83867_private *dp83867 =
 134                 (struct dp83867_private *)phydev->priv;
 135         u16 val;
 136
 137         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 138
 139         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 140                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 141         else
 142                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 143
 144         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 145
 146         return 0;
 147 }
 148
 149 #ifdef CONFIG_OF_MDIO
 150 static int dp83867_of_init(struct phy_device *phydev)
 151 {
 152         struct dp83867_private *dp83867 = phydev->priv;
 153         struct device *dev = &phydev->mdio.dev;
 154         struct device_node *of_node = dev->of_node;
 155         int ret;
 156
 157         if (!of_node)
 158                 return -ENODEV;
 159
 160         dp83867->io_impedance = -EINVAL;
 161
 162         /* Optional configuration */
 163         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 164                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 165         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 166                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 167
 168         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 169                                         "ti,dp83867-rxctrl-strap-quirk");
 170
 171         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 172                                    &dp83867->rx_id_delay);
 173         if (ret &&
 174             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 175              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 176                 return ret;
 177
 178         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 179                                    &dp83867->tx_id_delay);
 180         if (ret &&
 181             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 182              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 183                 return ret;
 184
 185         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 186                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 187
 188         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 189                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 190
 191         return of_property_read_u32(of_node, "ti,fifo-depth",
 192                                    &dp83867->fifo_depth);
 193 }
 194 #else
 195 static int dp83867_of_init(struct phy_device *phydev)
 196 {
 197         return 0;
 198 }
 199 #endif /* CONFIG_OF_MDIO */
 200
 201 static int dp83867_config_init(struct phy_device *phydev)
 202 {
 203         struct dp83867_private *dp83867;
 204         int ret, val, bs;
 205         u16 delay;
 206
 207         if (!phydev->priv) {
 208                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 209                                        GFP_KERNEL);
 210                 if (!dp83867)
 211                         return -ENOMEM;
 212
 213                 phydev->priv = dp83867;
 214                 ret = dp83867_of_init(phydev);
 215                 if (ret)
 216                         return ret;
 217         } else {
 218                 dp83867 = (struct dp83867_private *)phydev->priv;
 219         }
 220
 221         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 222         if (dp83867->rxctrl_strap_quirk) {
 223                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
 224                 val &= ~BIT(7);
 225                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
 226         }
 227
 228         if (phy_interface_is_rgmii(phydev)) {
 229                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 230                 if (val < 0)
 231                         return val;
 232                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 233                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 234
 235                 /* The code below checks if "port mirroring" N/A MODE4 has been
 236                  * enabled during power on bootstrap.
 237                  *
 238                  * Such N/A mode enabled by mistake can put PHY IC in some
 239                  * internal testing mode and disable RGMII transmission.
 240                  *
 241                  * In this particular case one needs to check STRAP_STS1
 242                  * register's bit 11 (marked as RESERVED).
 243                  */
 244
 245                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 246                 if (bs & DP83867_STRAP_STS1_RESERVED)
 247                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 248
 249                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 250                 if (ret)
 251                         return ret;
 252         }
 253
 254         if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
 255             (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 256                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 257
 258                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 259                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 260
 261                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 262                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 263
 264                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 265                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 266
 267                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 268
 269                 delay = (dp83867->rx_id_delay |
 270                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 271
 272                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 273                               delay);
 274
 275                 if (dp83867->io_impedance >= 0) {
 276                         val = phy_read_mmd(phydev, DP83867_DEVADDR,
 277                                            DP83867_IO_MUX_CFG);
 278
 279                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 280                         val |= dp83867->io_impedance &
 281                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 282
 283                         phy_write_mmd(phydev, DP83867_DEVADDR,
 284                                       DP83867_IO_MUX_CFG, val);
 285                 }
 286         }
 287
 288         /* Enable Interrupt output INT_OE in CFG3 register */
 289         if (phy_interrupt_is_valid(phydev)) {
 290                 val = phy_read(phydev, DP83867_CFG3);
 291                 val |= BIT(7);
 292                 phy_write(phydev, DP83867_CFG3, val);
 293         }
 294
 295         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 296                 dp83867_config_port_mirroring(phydev);
 297
 298         return 0;
 299 }
 300
 301 static int dp83867_phy_reset(struct phy_device *phydev)
 302 {
 303         int err;
 304
 305         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 306         if (err < 0)
 307                 return err;
 308
 309         return dp83867_config_init(phydev);
 310 }
 311
 312 static struct phy_driver dp83867_driver[] = {
 313         {
 314                 .phy_id         = DP83867_PHY_ID,
 315                 .phy_id_mask    = 0xfffffff0,
 316                 .name           = "TI DP83867",
 317                 .features       = PHY_GBIT_FEATURES,
 318                 .flags          = PHY_HAS_INTERRUPT,
 319
 320                 .config_init    = dp83867_config_init,
 321                 .soft_reset     = dp83867_phy_reset,
 322
 323                 /* IRQ related */
 324                 .ack_interrupt  = dp83867_ack_interrupt,
 325                 .config_intr    = dp83867_config_intr,
 326
 327                 .config_aneg    = genphy_config_aneg,
 328                 .read_status    = genphy_read_status,
 329                 .suspend        = genphy_suspend,
 330                 .resume         = genphy_resume,
 331         },
 332 };
 333 module_phy_driver(dp83867_driver);
 334
 335 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 336         { DP83867_PHY_ID, 0xfffffff0 },
 337         { }
 338 };
 339
 340 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 341
 342 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 343 MODULE_AUTHOR("Dan Murphy <[email protected]");
 344 MODULE_LICENSE("GPL");