drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #if defined(CONFIG_VGA_SWITCHEROO)
  38 bool radeon_has_atpx(void);
  39 #else
  40 static inline bool radeon_has_atpx(void) { return false; }
  41 #endif
  42
  43 /**
  44  * radeon_driver_unload_kms - Main unload function for KMS.
  45  *
  46  * @dev: drm dev pointer
  47  *
  48  * This is the main unload function for KMS (all asics).
  49  * It calls radeon_modeset_fini() to tear down the
  50  * displays, and radeon_device_fini() to tear down
  51  * the rest of the device (CP, writeback, etc.).
  52  * Returns 0 on success.
  53  */
  54 void radeon_driver_unload_kms(struct drm_device *dev)
  55 {
  56         struct radeon_device *rdev = dev->dev_private;
  57
  58         if (rdev == NULL)
  59                 return;
  60
  61         if (rdev->rmmio == NULL)
  62                 goto done_free;
  63
  64         if (radeon_is_px(dev)) {
  65                 pm_runtime_get_sync(dev->dev);
  66                 pm_runtime_forbid(dev->dev);
  67         }
  68
  69         radeon_acpi_fini(rdev);
  70
  71         radeon_modeset_fini(rdev);
  72         radeon_device_fini(rdev);
  73
  74 done_free:
  75         kfree(rdev);
  76         dev->dev_private = NULL;
  77 }
  78
  79 /**
  80  * radeon_driver_load_kms - Main load function for KMS.
  81  *
  82  * @dev: drm dev pointer
  83  * @flags: device flags
  84  *
  85  * This is the main load function for KMS (all asics).
  86  * It calls radeon_device_init() to set up the non-display
  87  * parts of the chip (asic init, CP, writeback, etc.), and
  88  * radeon_modeset_init() to set up the display parts
  89  * (crtcs, encoders, hotplug detect, etc.).
  90  * Returns 0 on success, error on failure.
  91  */
  92 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  93 {
  94         struct radeon_device *rdev;
  95         int r, acpi_status;
  96
  97         if (!radeon_si_support) {
  98                 switch (flags & RADEON_FAMILY_MASK) {
  99                 case CHIP_TAHITI:
 100                 case CHIP_PITCAIRN:
 101                 case CHIP_VERDE:
 102                 case CHIP_OLAND:
 103                 case CHIP_HAINAN:
 104                         dev_info(dev->dev,
 105                                  "SI support disabled by module param\n");
 106                         return -ENODEV;
 107                 }
 108         }
 109         if (!radeon_cik_support) {
 110                 switch (flags & RADEON_FAMILY_MASK) {
 111                 case CHIP_KAVERI:
 112                 case CHIP_BONAIRE:
 113                 case CHIP_HAWAII:
 114                 case CHIP_KABINI:
 115                 case CHIP_MULLINS:
 116                         dev_info(dev->dev,
 117                                  "CIK support disabled by module param\n");
 118                         return -ENODEV;
 119                 }
 120         }
 121
 122         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
 123         if (rdev == NULL) {
 124                 return -ENOMEM;
 125         }
 126         dev->dev_private = (void *)rdev;
 127
 128         /* update BUS flag */
 129         if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
 130                 flags |= RADEON_IS_AGP;
 131         } else if (pci_is_pcie(dev->pdev)) {
 132                 flags |= RADEON_IS_PCIE;
 133         } else {
 134                 flags |= RADEON_IS_PCI;
 135         }
 136
 137         if ((radeon_runtime_pm != 0) &&
 138             radeon_has_atpx() &&
 139             ((flags & RADEON_IS_IGP) == 0) &&
 140             !pci_is_thunderbolt_attached(dev->pdev))
 141                 flags |= RADEON_IS_PX;
 142
 143         /* radeon_device_init should report only fatal error
 144          * like memory allocation failure or iomapping failure,
 145          * or memory manager initialization failure, it must
 146          * properly initialize the GPU MC controller and permit
 147          * VRAM allocation
 148          */
 149         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 150         if (r) {
 151                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 152                 goto out;
 153         }
 154
 155         /* Again modeset_init should fail only on fatal error
 156          * otherwise it should provide enough functionalities
 157          * for shadowfb to run
 158          */
 159         r = radeon_modeset_init(rdev);
 160         if (r)
 161                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 162
 163         /* Call ACPI methods: require modeset init
 164          * but failure is not fatal
 165          */
 166         if (!r) {
 167                 acpi_status = radeon_acpi_init(rdev);
 168                 if (acpi_status)
 169                 dev_dbg(&dev->pdev->dev,
 170                                 "Error during ACPI methods call\n");
 171         }
 172
 173         if (radeon_is_px(dev)) {
 174                 pm_runtime_use_autosuspend(dev->dev);
 175                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 176                 pm_runtime_set_active(dev->dev);
 177                 pm_runtime_allow(dev->dev);
 178                 pm_runtime_mark_last_busy(dev->dev);
 179                 pm_runtime_put_autosuspend(dev->dev);
 180         }
 181
 182 out:
 183         if (r)
 184                 radeon_driver_unload_kms(dev);
 185
 186
 187         return r;
 188 }
 189
 190 /**
 191  * radeon_set_filp_rights - Set filp right.
 192  *
 193  * @dev: drm dev pointer
 194  * @owner: drm file
 195  * @applier: drm file
 196  * @value: value
 197  *
 198  * Sets the filp rights for the device (all asics).
 199  */
 200 static void radeon_set_filp_rights(struct drm_device *dev,
 201                                    struct drm_file **owner,
 202                                    struct drm_file *applier,
 203                                    uint32_t *value)
 204 {
 205         struct radeon_device *rdev = dev->dev_private;
 206
 207         mutex_lock(&rdev->gem.mutex);
 208         if (*value == 1) {
 209                 /* wants rights */
 210                 if (!*owner)
 211                         *owner = applier;
 212         } else if (*value == 0) {
 213                 /* revokes rights */
 214                 if (*owner == applier)
 215                         *owner = NULL;
 216         }
 217         *value = *owner == applier ? 1 : 0;
 218         mutex_unlock(&rdev->gem.mutex);
 219 }
 220
 221 /*
 222  * Userspace get information ioctl
 223  */
 224 /**
 225  * radeon_info_ioctl - answer a device specific request.
 226  *
 227  * @rdev: radeon device pointer
 228  * @data: request object
 229  * @filp: drm filp
 230  *
 231  * This function is used to pass device specific parameters to the userspace
 232  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 233  * etc. (all asics).
 234  * Returns 0 on success, -EINVAL on failure.
 235  */
 236 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 237 {
 238         struct radeon_device *rdev = dev->dev_private;
 239         struct drm_radeon_info *info = data;
 240         struct radeon_mode_info *minfo = &rdev->mode_info;
 241         uint32_t *value, value_tmp, *value_ptr, value_size;
 242         uint64_t value64;
 243         struct drm_crtc *crtc;
 244         int i, found;
 245
 246         value_ptr = (uint32_t *)((unsigned long)info->value);
 247         value = &value_tmp;
 248         value_size = sizeof(uint32_t);
 249
 250         switch (info->request) {
 251         case RADEON_INFO_DEVICE_ID:
 252                 *value = dev->pdev->device;
 253                 break;
 254         case RADEON_INFO_NUM_GB_PIPES:
 255                 *value = rdev->num_gb_pipes;
 256                 break;
 257         case RADEON_INFO_NUM_Z_PIPES:
 258                 *value = rdev->num_z_pipes;
 259                 break;
 260         case RADEON_INFO_ACCEL_WORKING:
 261                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 262                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 263                         *value = false;
 264                 else
 265                         *value = rdev->accel_working;
 266                 break;
 267         case RADEON_INFO_CRTC_FROM_ID:
 268                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 269                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 270                         return -EFAULT;
 271                 }
 272                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 273                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 274                         if (crtc && crtc->base.id == *value) {
 275                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 276                                 *value = radeon_crtc->crtc_id;
 277                                 found = 1;
 278                                 break;
 279                         }
 280                 }
 281                 if (!found) {
 282                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 283                         return -EINVAL;
 284                 }
 285                 break;
 286         case RADEON_INFO_ACCEL_WORKING2:
 287                 if (rdev->family == CHIP_HAWAII) {
 288                         if (rdev->accel_working) {
 289                                 if (rdev->new_fw)
 290                                         *value = 3;
 291                                 else
 292                                         *value = 2;
 293                         } else {
 294                                 *value = 0;
 295                         }
 296                 } else {
 297                         *value = rdev->accel_working;
 298                 }
 299                 break;
 300         case RADEON_INFO_TILING_CONFIG:
 301                 if (rdev->family >= CHIP_BONAIRE)
 302                         *value = rdev->config.cik.tile_config;
 303                 else if (rdev->family >= CHIP_TAHITI)
 304                         *value = rdev->config.si.tile_config;
 305                 else if (rdev->family >= CHIP_CAYMAN)
 306                         *value = rdev->config.cayman.tile_config;
 307                 else if (rdev->family >= CHIP_CEDAR)
 308                         *value = rdev->config.evergreen.tile_config;
 309                 else if (rdev->family >= CHIP_RV770)
 310                         *value = rdev->config.rv770.tile_config;
 311                 else if (rdev->family >= CHIP_R600)
 312                         *value = rdev->config.r600.tile_config;
 313                 else {
 314                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 315                         return -EINVAL;
 316                 }
 317                 break;
 318         case RADEON_INFO_WANT_HYPERZ:
 319                 /* The "value" here is both an input and output parameter.
 320                  * If the input value is 1, filp requests hyper-z access.
 321                  * If the input value is 0, filp revokes its hyper-z access.
 322                  *
 323                  * When returning, the value is 1 if filp owns hyper-z access,
 324                  * 0 otherwise. */
 325                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 326                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 327                         return -EFAULT;
 328                 }
 329                 if (*value >= 2) {
 330                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 331                         return -EINVAL;
 332                 }
 333                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 334                 break;
 335         case RADEON_INFO_WANT_CMASK:
 336                 /* The same logic as Hyper-Z. */
 337                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 338                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 339                         return -EFAULT;
 340                 }
 341                 if (*value >= 2) {
 342                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 343                         return -EINVAL;
 344                 }
 345                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 346                 break;
 347         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 348                 /* return clock value in KHz */
 349                 if (rdev->asic->get_xclk)
 350                         *value = radeon_get_xclk(rdev) * 10;
 351                 else
 352                         *value = rdev->clock.spll.reference_freq * 10;
 353                 break;
 354         case RADEON_INFO_NUM_BACKENDS:
 355                 if (rdev->family >= CHIP_BONAIRE)
 356                         *value = rdev->config.cik.max_backends_per_se *
 357                                 rdev->config.cik.max_shader_engines;
 358                 else if (rdev->family >= CHIP_TAHITI)
 359                         *value = rdev->config.si.max_backends_per_se *
 360                                 rdev->config.si.max_shader_engines;
 361                 else if (rdev->family >= CHIP_CAYMAN)
 362                         *value = rdev->config.cayman.max_backends_per_se *
 363                                 rdev->config.cayman.max_shader_engines;
 364                 else if (rdev->family >= CHIP_CEDAR)
 365                         *value = rdev->config.evergreen.max_backends;
 366                 else if (rdev->family >= CHIP_RV770)
 367                         *value = rdev->config.rv770.max_backends;
 368                 else if (rdev->family >= CHIP_R600)
 369                         *value = rdev->config.r600.max_backends;
 370                 else {
 371                         return -EINVAL;
 372                 }
 373                 break;
 374         case RADEON_INFO_NUM_TILE_PIPES:
 375                 if (rdev->family >= CHIP_BONAIRE)
 376                         *value = rdev->config.cik.max_tile_pipes;
 377                 else if (rdev->family >= CHIP_TAHITI)
 378                         *value = rdev->config.si.max_tile_pipes;
 379                 else if (rdev->family >= CHIP_CAYMAN)
 380                         *value = rdev->config.cayman.max_tile_pipes;
 381                 else if (rdev->family >= CHIP_CEDAR)
 382                         *value = rdev->config.evergreen.max_tile_pipes;
 383                 else if (rdev->family >= CHIP_RV770)
 384                         *value = rdev->config.rv770.max_tile_pipes;
 385                 else if (rdev->family >= CHIP_R600)
 386                         *value = rdev->config.r600.max_tile_pipes;
 387                 else {
 388                         return -EINVAL;
 389                 }
 390                 break;
 391         case RADEON_INFO_FUSION_GART_WORKING:
 392                 *value = 1;
 393                 break;
 394         case RADEON_INFO_BACKEND_MAP:
 395                 if (rdev->family >= CHIP_BONAIRE)
 396                         *value = rdev->config.cik.backend_map;
 397                 else if (rdev->family >= CHIP_TAHITI)
 398                         *value = rdev->config.si.backend_map;
 399                 else if (rdev->family >= CHIP_CAYMAN)
 400                         *value = rdev->config.cayman.backend_map;
 401                 else if (rdev->family >= CHIP_CEDAR)
 402                         *value = rdev->config.evergreen.backend_map;
 403                 else if (rdev->family >= CHIP_RV770)
 404                         *value = rdev->config.rv770.backend_map;
 405                 else if (rdev->family >= CHIP_R600)
 406                         *value = rdev->config.r600.backend_map;
 407                 else {
 408                         return -EINVAL;
 409                 }
 410                 break;
 411         case RADEON_INFO_VA_START:
 412                 /* this is where we report if vm is supported or not */
 413                 if (rdev->family < CHIP_CAYMAN)
 414                         return -EINVAL;
 415                 *value = RADEON_VA_RESERVED_SIZE;
 416                 break;
 417         case RADEON_INFO_IB_VM_MAX_SIZE:
 418                 /* this is where we report if vm is supported or not */
 419                 if (rdev->family < CHIP_CAYMAN)
 420                         return -EINVAL;
 421                 *value = RADEON_IB_VM_MAX_SIZE;
 422                 break;
 423         case RADEON_INFO_MAX_PIPES:
 424                 if (rdev->family >= CHIP_BONAIRE)
 425                         *value = rdev->config.cik.max_cu_per_sh;
 426                 else if (rdev->family >= CHIP_TAHITI)
 427                         *value = rdev->config.si.max_cu_per_sh;
 428                 else if (rdev->family >= CHIP_CAYMAN)
 429                         *value = rdev->config.cayman.max_pipes_per_simd;
 430                 else if (rdev->family >= CHIP_CEDAR)
 431                         *value = rdev->config.evergreen.max_pipes;
 432                 else if (rdev->family >= CHIP_RV770)
 433                         *value = rdev->config.rv770.max_pipes;
 434                 else if (rdev->family >= CHIP_R600)
 435                         *value = rdev->config.r600.max_pipes;
 436                 else {
 437                         return -EINVAL;
 438                 }
 439                 break;
 440         case RADEON_INFO_TIMESTAMP:
 441                 if (rdev->family < CHIP_R600) {
 442                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 443                         return -EINVAL;
 444                 }
 445                 value = (uint32_t*)&value64;
 446                 value_size = sizeof(uint64_t);
 447                 value64 = radeon_get_gpu_clock_counter(rdev);
 448                 break;
 449         case RADEON_INFO_MAX_SE:
 450                 if (rdev->family >= CHIP_BONAIRE)
 451                         *value = rdev->config.cik.max_shader_engines;
 452                 else if (rdev->family >= CHIP_TAHITI)
 453                         *value = rdev->config.si.max_shader_engines;
 454                 else if (rdev->family >= CHIP_CAYMAN)
 455                         *value = rdev->config.cayman.max_shader_engines;
 456                 else if (rdev->family >= CHIP_CEDAR)
 457                         *value = rdev->config.evergreen.num_ses;
 458                 else
 459                         *value = 1;
 460                 break;
 461         case RADEON_INFO_MAX_SH_PER_SE:
 462                 if (rdev->family >= CHIP_BONAIRE)
 463                         *value = rdev->config.cik.max_sh_per_se;
 464                 else if (rdev->family >= CHIP_TAHITI)
 465                         *value = rdev->config.si.max_sh_per_se;
 466                 else
 467                         return -EINVAL;
 468                 break;
 469         case RADEON_INFO_FASTFB_WORKING:
 470                 *value = rdev->fastfb_working;
 471                 break;
 472         case RADEON_INFO_RING_WORKING:
 473                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 474                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 475                         return -EFAULT;
 476                 }
 477                 switch (*value) {
 478                 case RADEON_CS_RING_GFX:
 479                 case RADEON_CS_RING_COMPUTE:
 480                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 481                         break;
 482                 case RADEON_CS_RING_DMA:
 483                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 484                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 485                         break;
 486                 case RADEON_CS_RING_UVD:
 487                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 488                         break;
 489                 case RADEON_CS_RING_VCE:
 490                         *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
 491                         break;
 492                 default:
 493                         return -EINVAL;
 494                 }
 495                 break;
 496         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 497                 if (rdev->family >= CHIP_BONAIRE) {
 498                         value = rdev->config.cik.tile_mode_array;
 499                         value_size = sizeof(uint32_t)*32;
 500                 } else if (rdev->family >= CHIP_TAHITI) {
 501                         value = rdev->config.si.tile_mode_array;
 502                         value_size = sizeof(uint32_t)*32;
 503                 } else {
 504                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 505                         return -EINVAL;
 506                 }
 507                 break;
 508         case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
 509                 if (rdev->family >= CHIP_BONAIRE) {
 510                         value = rdev->config.cik.macrotile_mode_array;
 511                         value_size = sizeof(uint32_t)*16;
 512                 } else {
 513                         DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
 514                         return -EINVAL;
 515                 }
 516                 break;
 517         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 518                 *value = 1;
 519                 break;
 520         case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
 521                 if (rdev->family >= CHIP_BONAIRE) {
 522                         *value = rdev->config.cik.backend_enable_mask;
 523                 } else if (rdev->family >= CHIP_TAHITI) {
 524                         *value = rdev->config.si.backend_enable_mask;
 525                 } else {
 526                         DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
 527                 }
 528                 break;
 529         case RADEON_INFO_MAX_SCLK:
 530                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
 531                     rdev->pm.dpm_enabled)
 532                         *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
 533                 else
 534                         *value = rdev->pm.default_sclk * 10;
 535                 break;
 536         case RADEON_INFO_VCE_FW_VERSION:
 537                 *value = rdev->vce.fw_version;
 538                 break;
 539         case RADEON_INFO_VCE_FB_VERSION:
 540                 *value = rdev->vce.fb_version;
 541                 break;
 542         case RADEON_INFO_NUM_BYTES_MOVED:
 543                 value = (uint32_t*)&value64;
 544                 value_size = sizeof(uint64_t);
 545                 value64 = atomic64_read(&rdev->num_bytes_moved);
 546                 break;
 547         case RADEON_INFO_VRAM_USAGE:
 548                 value = (uint32_t*)&value64;
 549                 value_size = sizeof(uint64_t);
 550                 value64 = atomic64_read(&rdev->vram_usage);
 551                 break;
 552         case RADEON_INFO_GTT_USAGE:
 553                 value = (uint32_t*)&value64;
 554                 value_size = sizeof(uint64_t);
 555                 value64 = atomic64_read(&rdev->gtt_usage);
 556                 break;
 557         case RADEON_INFO_ACTIVE_CU_COUNT:
 558                 if (rdev->family >= CHIP_BONAIRE)
 559                         *value = rdev->config.cik.active_cus;
 560                 else if (rdev->family >= CHIP_TAHITI)
 561                         *value = rdev->config.si.active_cus;
 562                 else if (rdev->family >= CHIP_CAYMAN)
 563                         *value = rdev->config.cayman.active_simds;
 564                 else if (rdev->family >= CHIP_CEDAR)
 565                         *value = rdev->config.evergreen.active_simds;
 566                 else if (rdev->family >= CHIP_RV770)
 567                         *value = rdev->config.rv770.active_simds;
 568                 else if (rdev->family >= CHIP_R600)
 569                         *value = rdev->config.r600.active_simds;
 570                 else
 571                         *value = 1;
 572                 break;
 573         case RADEON_INFO_CURRENT_GPU_TEMP:
 574                 /* get temperature in millidegrees C */
 575                 if (rdev->asic->pm.get_temperature)
 576                         *value = radeon_get_temperature(rdev);
 577                 else
 578                         *value = 0;
 579                 break;
 580         case RADEON_INFO_CURRENT_GPU_SCLK:
 581                 /* get sclk in Mhz */
 582                 if (rdev->pm.dpm_enabled)
 583                         *value = radeon_dpm_get_current_sclk(rdev) / 100;
 584                 else
 585                         *value = rdev->pm.current_sclk / 100;
 586                 break;
 587         case RADEON_INFO_CURRENT_GPU_MCLK:
 588                 /* get mclk in Mhz */
 589                 if (rdev->pm.dpm_enabled)
 590                         *value = radeon_dpm_get_current_mclk(rdev) / 100;
 591                 else
 592                         *value = rdev->pm.current_mclk / 100;
 593                 break;
 594         case RADEON_INFO_READ_REG:
 595                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 596                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 597                         return -EFAULT;
 598                 }
 599                 if (radeon_get_allowed_info_register(rdev, *value, value))
 600                         return -EINVAL;
 601                 break;
 602         case RADEON_INFO_VA_UNMAP_WORKING:
 603                 *value = true;
 604                 break;
 605         case RADEON_INFO_GPU_RESET_COUNTER:
 606                 *value = atomic_read(&rdev->gpu_reset_counter);
 607                 break;
 608         default:
 609                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 610                 return -EINVAL;
 611         }
 612         if (copy_to_user(value_ptr, (char*)value, value_size)) {
 613                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 614                 return -EFAULT;
 615         }
 616         return 0;
 617 }
 618
 619
 620 /*
 621  * Outdated mess for old drm with Xorg being in charge (void function now).
 622  */
 623 /**
 624  * radeon_driver_lastclose_kms - drm callback for last close
 625  *
 626  * @dev: drm dev pointer
 627  *
 628  * Switch vga_switcheroo state after last close (all asics).
 629  */
 630 void radeon_driver_lastclose_kms(struct drm_device *dev)
 631 {
 632         struct radeon_device *rdev = dev->dev_private;
 633
 634         radeon_fbdev_restore_mode(rdev);
 635         vga_switcheroo_process_delayed_switch();
 636 }
 637
 638 /**
 639  * radeon_driver_open_kms - drm callback for open
 640  *
 641  * @dev: drm dev pointer
 642  * @file_priv: drm file
 643  *
 644  * On device open, init vm on cayman+ (all asics).
 645  * Returns 0 on success, error on failure.
 646  */
 647 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 648 {
 649         struct radeon_device *rdev = dev->dev_private;
 650         int r;
 651
 652         file_priv->driver_priv = NULL;
 653
 654         r = pm_runtime_get_sync(dev->dev);
 655         if (r < 0)
 656                 return r;
 657
 658         /* new gpu have virtual address space support */
 659         if (rdev->family >= CHIP_CAYMAN) {
 660                 struct radeon_fpriv *fpriv;
 661                 struct radeon_vm *vm;
 662
 663                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 664                 if (unlikely(!fpriv)) {
 665                         r = -ENOMEM;
 666                         goto out_suspend;
 667                 }
 668
 669                 if (rdev->accel_working) {
 670                         vm = &fpriv->vm;
 671                         r = radeon_vm_init(rdev, vm);
 672                         if (r) {
 673                                 kfree(fpriv);
 674                                 goto out_suspend;
 675                         }
 676
 677                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 678                         if (r) {
 679                                 radeon_vm_fini(rdev, vm);
 680                                 kfree(fpriv);
 681                                 goto out_suspend;
 682                         }
 683
 684                         /* map the ib pool buffer read only into
 685                          * virtual address space */
 686                         vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
 687                                                         rdev->ring_tmp_bo.bo);
 688                         r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
 689                                                   RADEON_VA_IB_OFFSET,
 690                                                   RADEON_VM_PAGE_READABLE |
 691                                                   RADEON_VM_PAGE_SNOOPED);
 692                         if (r) {
 693                                 radeon_vm_fini(rdev, vm);
 694                                 kfree(fpriv);
 695                                 goto out_suspend;
 696                         }
 697                 }
 698                 file_priv->driver_priv = fpriv;
 699         }
 700
 701 out_suspend:
 702         pm_runtime_mark_last_busy(dev->dev);
 703         pm_runtime_put_autosuspend(dev->dev);
 704         return r;
 705 }
 706
 707 /**
 708  * radeon_driver_postclose_kms - drm callback for post close
 709  *
 710  * @dev: drm dev pointer
 711  * @file_priv: drm file
 712  *
 713  * On device close, tear down hyperz and cmask filps on r1xx-r5xx
 714  * (all asics).  And tear down vm on cayman+ (all asics).
 715  */
 716 void radeon_driver_postclose_kms(struct drm_device *dev,
 717                                  struct drm_file *file_priv)
 718 {
 719         struct radeon_device *rdev = dev->dev_private;
 720
 721         pm_runtime_get_sync(dev->dev);
 722
 723         mutex_lock(&rdev->gem.mutex);
 724         if (rdev->hyperz_filp == file_priv)
 725                 rdev->hyperz_filp = NULL;
 726         if (rdev->cmask_filp == file_priv)
 727                 rdev->cmask_filp = NULL;
 728         mutex_unlock(&rdev->gem.mutex);
 729
 730         radeon_uvd_free_handles(rdev, file_priv);
 731         radeon_vce_free_handles(rdev, file_priv);
 732
 733         /* new gpu have virtual address space support */
 734         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 735                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 736                 struct radeon_vm *vm = &fpriv->vm;
 737                 int r;
 738
 739                 if (rdev->accel_working) {
 740                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 741                         if (!r) {
 742                                 if (vm->ib_bo_va)
 743                                         radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
 744                                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 745                         }
 746                         radeon_vm_fini(rdev, vm);
 747                 }
 748
 749                 kfree(fpriv);
 750                 file_priv->driver_priv = NULL;
 751         }
 752         pm_runtime_mark_last_busy(dev->dev);
 753         pm_runtime_put_autosuspend(dev->dev);
 754 }
 755
 756 /*
 757  * VBlank related functions.
 758  */
 759 /**
 760  * radeon_get_vblank_counter_kms - get frame count
 761  *
 762  * @dev: drm dev pointer
 763  * @pipe: crtc to get the frame count from
 764  *
 765  * Gets the frame count on the requested crtc (all asics).
 766  * Returns frame count on success, -EINVAL on failure.
 767  */
 768 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 769 {
 770         int vpos, hpos, stat;
 771         u32 count;
 772         struct radeon_device *rdev = dev->dev_private;
 773
 774         if (pipe >= rdev->num_crtc) {
 775                 DRM_ERROR("Invalid crtc %u\n", pipe);
 776                 return -EINVAL;
 777         }
 778
 779         /* The hw increments its frame counter at start of vsync, not at start
 780          * of vblank, as is required by DRM core vblank counter handling.
 781          * Cook the hw count here to make it appear to the caller as if it
 782          * incremented at start of vblank. We measure distance to start of
 783          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 784          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 785          * result by 1 to give the proper appearance to caller.
 786          */
 787         if (rdev->mode_info.crtcs[pipe]) {
 788                 /* Repeat readout if needed to provide stable result if
 789                  * we cross start of vsync during the queries.
 790                  */
 791                 do {
 792                         count = radeon_get_vblank_counter(rdev, pipe);
 793                         /* Ask radeon_get_crtc_scanoutpos to return vpos as
 794                          * distance to start of vblank, instead of regular
 795                          * vertical scanout pos.
 796                          */
 797                         stat = radeon_get_crtc_scanoutpos(
 798                                 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
 799                                 &vpos, &hpos, NULL, NULL,
 800                                 &rdev->mode_info.crtcs[pipe]->base.hwmode);
 801                 } while (count != radeon_get_vblank_counter(rdev, pipe));
 802
 803                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 804                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 805                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 806                 }
 807                 else {
 808                         DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
 809                                       pipe, vpos);
 810
 811                         /* Bump counter if we are at >= leading edge of vblank,
 812                          * but before vsync where vpos would turn negative and
 813                          * the hw counter really increments.
 814                          */
 815                         if (vpos >= 0)
 816                                 count++;
 817                 }
 818         }
 819         else {
 820             /* Fallback to use value as is. */
 821             count = radeon_get_vblank_counter(rdev, pipe);
 822             DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 823         }
 824
 825         return count;
 826 }
 827
 828 /**
 829  * radeon_enable_vblank_kms - enable vblank interrupt
 830  *
 831  * @dev: drm dev pointer
 832  * @crtc: crtc to enable vblank interrupt for
 833  *
 834  * Enable the interrupt on the requested crtc (all asics).
 835  * Returns 0 on success, -EINVAL on failure.
 836  */
 837 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 838 {
 839         struct radeon_device *rdev = dev->dev_private;
 840         unsigned long irqflags;
 841         int r;
 842
 843         if (crtc < 0 || crtc >= rdev->num_crtc) {
 844                 DRM_ERROR("Invalid crtc %d\n", crtc);
 845                 return -EINVAL;
 846         }
 847
 848         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 849         rdev->irq.crtc_vblank_int[crtc] = true;
 850         r = radeon_irq_set(rdev);
 851         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 852         return r;
 853 }
 854
 855 /**
 856  * radeon_disable_vblank_kms - disable vblank interrupt
 857  *
 858  * @dev: drm dev pointer
 859  * @crtc: crtc to disable vblank interrupt for
 860  *
 861  * Disable the interrupt on the requested crtc (all asics).
 862  */
 863 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 864 {
 865         struct radeon_device *rdev = dev->dev_private;
 866         unsigned long irqflags;
 867
 868         if (crtc < 0 || crtc >= rdev->num_crtc) {
 869                 DRM_ERROR("Invalid crtc %d\n", crtc);
 870                 return;
 871         }
 872
 873         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 874         rdev->irq.crtc_vblank_int[crtc] = false;
 875         radeon_irq_set(rdev);
 876         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 877 }
 878
 879 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
 880         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 881         DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 882         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 883         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 884         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
 885         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
 886         DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
 887         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
 888         DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
 889         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
 890         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
 891         DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
 892         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
 893         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
 894         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 895         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
 896         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
 897         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
 898         DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
 899         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
 900         DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
 901         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 902         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
 903         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
 904         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
 905         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
 906         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
 907         /* KMS */
 908         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 909         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 910         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 911         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 912         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
 913         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
 914         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 915         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 916         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 917         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 918         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 919         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 920         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 921         DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 922         DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 923 };
 924 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);