drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
  29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
  30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
  31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
  32
  33 enum smu_event_type {
  34         SMU_EVENT_RESET_COMPLETE = 0,
  35 };
  36
  37 struct amd_vce_state {
  38         /* vce clocks */
  39         u32 evclk;
  40         u32 ecclk;
  41         /* gpu clocks */
  42         u32 sclk;
  43         u32 mclk;
  44         u8 clk_idx;
  45         u8 pstate;
  46 };
  47
  48
  49 enum amd_dpm_forced_level {
  50         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  51         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  52         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  53         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  54         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  55         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  56         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  57         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  58         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  59         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  60 };
  61
  62 enum amd_pm_state_type {
  63         /* not used for dpm */
  64         POWER_STATE_TYPE_DEFAULT,
  65         POWER_STATE_TYPE_POWERSAVE,
  66         /* user selectable states */
  67         POWER_STATE_TYPE_BATTERY,
  68         POWER_STATE_TYPE_BALANCED,
  69         POWER_STATE_TYPE_PERFORMANCE,
  70         /* internal states */
  71         POWER_STATE_TYPE_INTERNAL_UVD,
  72         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  73         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  74         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  75         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  76         POWER_STATE_TYPE_INTERNAL_BOOT,
  77         POWER_STATE_TYPE_INTERNAL_THERMAL,
  78         POWER_STATE_TYPE_INTERNAL_ACPI,
  79         POWER_STATE_TYPE_INTERNAL_ULV,
  80         POWER_STATE_TYPE_INTERNAL_3DPERF,
  81 };
  82
  83 #define AMD_MAX_VCE_LEVELS 6
  84
  85 enum amd_vce_level {
  86         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  87         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  88         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  89         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  90         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  91         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  92 };
  93
  94 enum amd_fan_ctrl_mode {
  95         AMD_FAN_CTRL_NONE = 0,
  96         AMD_FAN_CTRL_MANUAL = 1,
  97         AMD_FAN_CTRL_AUTO = 2,
  98 };
  99
 100 enum pp_clock_type {
 101         PP_SCLK,
 102         PP_MCLK,
 103         PP_PCIE,
 104         PP_SOCCLK,
 105         PP_FCLK,
 106         PP_DCEFCLK,
 107         PP_VCLK,
 108         PP_VCLK1,
 109         PP_DCLK,
 110         PP_DCLK1,
 111         OD_SCLK,
 112         OD_MCLK,
 113         OD_VDDC_CURVE,
 114         OD_RANGE,
 115         OD_VDDGFX_OFFSET,
 116         OD_CCLK,
 117         OD_FAN_CURVE,
 118         OD_ACOUSTIC_LIMIT,
 119         OD_ACOUSTIC_TARGET,
 120         OD_FAN_TARGET_TEMPERATURE,
 121         OD_FAN_MINIMUM_PWM,
 122 };
 123
 124 enum amd_pp_sensors {
 125         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 126         AMDGPU_PP_SENSOR_CPU_CLK,
 127         AMDGPU_PP_SENSOR_VDDNB,
 128         AMDGPU_PP_SENSOR_VDDGFX,
 129         AMDGPU_PP_SENSOR_UVD_VCLK,
 130         AMDGPU_PP_SENSOR_UVD_DCLK,
 131         AMDGPU_PP_SENSOR_VCE_ECCLK,
 132         AMDGPU_PP_SENSOR_GPU_LOAD,
 133         AMDGPU_PP_SENSOR_MEM_LOAD,
 134         AMDGPU_PP_SENSOR_GFX_MCLK,
 135         AMDGPU_PP_SENSOR_GPU_TEMP,
 136         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 137         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 138         AMDGPU_PP_SENSOR_MEM_TEMP,
 139         AMDGPU_PP_SENSOR_VCE_POWER,
 140         AMDGPU_PP_SENSOR_UVD_POWER,
 141         AMDGPU_PP_SENSOR_GPU_AVG_POWER,
 142         AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
 143         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 144         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 145         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 146         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 147         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 148         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 149         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 150         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 151         AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
 152         AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
 153 };
 154
 155 enum amd_pp_task {
 156         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 157         AMD_PP_TASK_ENABLE_USER_STATE,
 158         AMD_PP_TASK_READJUST_POWER_STATE,
 159         AMD_PP_TASK_COMPLETE_INIT,
 160         AMD_PP_TASK_MAX
 161 };
 162
 163 enum PP_SMC_POWER_PROFILE {
 164         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 165         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 166         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 167         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 168         PP_SMC_POWER_PROFILE_VR           = 0x4,
 169         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 170         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 171         PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
 172         PP_SMC_POWER_PROFILE_CAPPED       = 0x8,
 173         PP_SMC_POWER_PROFILE_UNCAPPED     = 0x9,
 174         PP_SMC_POWER_PROFILE_COUNT,
 175 };
 176
 177 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 178
 179
 180
 181 enum {
 182         PP_GROUP_UNKNOWN = 0,
 183         PP_GROUP_GFX = 1,
 184         PP_GROUP_SYS,
 185         PP_GROUP_MAX
 186 };
 187
 188 enum PP_OD_DPM_TABLE_COMMAND {
 189         PP_OD_EDIT_SCLK_VDDC_TABLE,
 190         PP_OD_EDIT_MCLK_VDDC_TABLE,
 191         PP_OD_EDIT_CCLK_VDDC_TABLE,
 192         PP_OD_EDIT_VDDC_CURVE,
 193         PP_OD_RESTORE_DEFAULT_TABLE,
 194         PP_OD_COMMIT_DPM_TABLE,
 195         PP_OD_EDIT_VDDGFX_OFFSET,
 196         PP_OD_EDIT_FAN_CURVE,
 197         PP_OD_EDIT_ACOUSTIC_LIMIT,
 198         PP_OD_EDIT_ACOUSTIC_TARGET,
 199         PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
 200         PP_OD_EDIT_FAN_MINIMUM_PWM,
 201 };
 202
 203 struct pp_states_info {
 204         uint32_t nums;
 205         uint32_t states[16];
 206 };
 207
 208 enum PP_HWMON_TEMP {
 209         PP_TEMP_EDGE = 0,
 210         PP_TEMP_JUNCTION,
 211         PP_TEMP_MEM,
 212         PP_TEMP_MAX
 213 };
 214
 215 enum pp_mp1_state {
 216         PP_MP1_STATE_NONE,
 217         PP_MP1_STATE_SHUTDOWN,
 218         PP_MP1_STATE_UNLOAD,
 219         PP_MP1_STATE_RESET,
 220 };
 221
 222 enum pp_df_cstate {
 223         DF_CSTATE_DISALLOW = 0,
 224         DF_CSTATE_ALLOW,
 225 };
 226
 227 /**
 228  * DOC: amdgpu_pp_power
 229  *
 230  * APU power is managed to system-level requirements through the PPT
 231  * (package power tracking) feature. PPT is intended to limit power to the
 232  * requirements of the power source and could be dynamically updated to
 233  * maximize APU performance within the system power budget.
 234  *
 235  * Two types of power measurement can be requested, where supported, with
 236  * :c:type:`enum pp_power_type <pp_power_type>`.
 237  */
 238
 239 /**
 240  * enum pp_power_limit_level - Used to query the power limits
 241  *
 242  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 243  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 244  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 245  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 246  */
 247 enum pp_power_limit_level {
 248         PP_PWR_LIMIT_MIN = -1,
 249         PP_PWR_LIMIT_CURRENT,
 250         PP_PWR_LIMIT_DEFAULT,
 251         PP_PWR_LIMIT_MAX,
 252 };
 253
 254 /**
 255  * enum pp_power_type - Used to specify the type of the requested power
 256  *
 257  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 258  * moving average of APU power (default ~5000 ms).
 259  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 260  * where supported.
 261  */
 262 enum pp_power_type {
 263         PP_PWR_TYPE_SUSTAINED,
 264         PP_PWR_TYPE_FAST,
 265 };
 266
 267 enum pp_xgmi_plpd_mode {
 268         XGMI_PLPD_NONE = -1,
 269         XGMI_PLPD_DISALLOW,
 270         XGMI_PLPD_DEFAULT,
 271         XGMI_PLPD_OPTIMIZED,
 272         XGMI_PLPD_COUNT,
 273 };
 274
 275 #define PP_GROUP_MASK        0xF0000000
 276 #define PP_GROUP_SHIFT       28
 277
 278 #define PP_BLOCK_MASK        0x0FFFFF00
 279 #define PP_BLOCK_SHIFT       8
 280
 281 #define PP_BLOCK_GFX_CG         0x01
 282 #define PP_BLOCK_GFX_MG         0x02
 283 #define PP_BLOCK_GFX_3D         0x04
 284 #define PP_BLOCK_GFX_RLC        0x08
 285 #define PP_BLOCK_GFX_CP         0x10
 286 #define PP_BLOCK_SYS_BIF        0x01
 287 #define PP_BLOCK_SYS_MC         0x02
 288 #define PP_BLOCK_SYS_ROM        0x04
 289 #define PP_BLOCK_SYS_DRM        0x08
 290 #define PP_BLOCK_SYS_HDP        0x10
 291 #define PP_BLOCK_SYS_SDMA       0x20
 292
 293 #define PP_STATE_MASK           0x0000000F
 294 #define PP_STATE_SHIFT          0
 295 #define PP_STATE_SUPPORT_MASK   0x000000F0
 296 #define PP_STATE_SUPPORT_SHIFT  0
 297
 298 #define PP_STATE_CG             0x01
 299 #define PP_STATE_LS             0x02
 300 #define PP_STATE_DS             0x04
 301 #define PP_STATE_SD             0x08
 302 #define PP_STATE_SUPPORT_CG     0x10
 303 #define PP_STATE_SUPPORT_LS     0x20
 304 #define PP_STATE_SUPPORT_DS     0x40
 305 #define PP_STATE_SUPPORT_SD     0x80
 306
 307 #define PP_CG_MSG_ID(group, block, support, state) \
 308                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 309                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 310
 311 #define XGMI_MODE_PSTATE_D3 0
 312 #define XGMI_MODE_PSTATE_D0 1
 313
 314 #define NUM_HBM_INSTANCES 4
 315 #define NUM_XGMI_LINKS 8
 316 #define MAX_GFX_CLKS 8
 317 #define MAX_CLKS 4
 318 #define NUM_VCN 4
 319 #define NUM_JPEG_ENG 32
 320
 321 struct seq_file;
 322 enum amd_pp_clock_type;
 323 struct amd_pp_simple_clock_info;
 324 struct amd_pp_display_configuration;
 325 struct amd_pp_clock_info;
 326 struct pp_display_clock_request;
 327 struct pp_clock_levels_with_voltage;
 328 struct pp_clock_levels_with_latency;
 329 struct amd_pp_clocks;
 330 struct pp_smu_wm_range_sets;
 331 struct pp_smu_nv_clock_table;
 332 struct dpm_clocks;
 333
 334 struct amd_pm_funcs {
 335 /* export for dpm on ci and si */
 336         int (*pre_set_power_state)(void *handle);
 337         int (*set_power_state)(void *handle);
 338         void (*post_set_power_state)(void *handle);
 339         void (*display_configuration_changed)(void *handle);
 340         void (*print_power_state)(void *handle, void *ps);
 341         bool (*vblank_too_short)(void *handle);
 342         void (*enable_bapm)(void *handle, bool enable);
 343         int (*check_state_equal)(void *handle,
 344                                 void  *cps,
 345                                 void  *rps,
 346                                 bool  *equal);
 347 /* export for sysfs */
 348         int (*set_fan_control_mode)(void *handle, u32 mode);
 349         int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
 350         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 351         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 352         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 353         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 354         int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
 355         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 356         int (*get_sclk_od)(void *handle);
 357         int (*set_sclk_od)(void *handle, uint32_t value);
 358         int (*get_mclk_od)(void *handle);
 359         int (*set_mclk_od)(void *handle, uint32_t value);
 360         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 361         int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
 362         int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
 363         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 364         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 365         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 366         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 367         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 368         int (*get_pp_table)(void *handle, char **table);
 369         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 370         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 371         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 372 /* export to amdgpu */
 373         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 374         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 375                         enum amd_pm_state_type *user_state);
 376         int (*load_firmware)(void *handle);
 377         int (*wait_for_fw_loading_complete)(void *handle);
 378         int (*set_powergating_by_smu)(void *handle,
 379                                 uint32_t block_type, bool gate);
 380         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 381         int (*set_power_limit)(void *handle, uint32_t n);
 382         int (*get_power_limit)(void *handle, uint32_t *limit,
 383                         enum pp_power_limit_level pp_limit_level,
 384                         enum pp_power_type power_type);
 385         int (*get_power_profile_mode)(void *handle, char *buf);
 386         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 387         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 388         int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 389                                   long *input, uint32_t size);
 390         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 391         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 392         int (*gfx_state_change_set)(void *handle, uint32_t state);
 393 /* export to DC */
 394         u32 (*get_sclk)(void *handle, bool low);
 395         u32 (*get_mclk)(void *handle, bool low);
 396         int (*display_configuration_change)(void *handle,
 397                 const struct amd_pp_display_configuration *input);
 398         int (*get_display_power_level)(void *handle,
 399                 struct amd_pp_simple_clock_info *output);
 400         int (*get_current_clocks)(void *handle,
 401                 struct amd_pp_clock_info *clocks);
 402         int (*get_clock_by_type)(void *handle,
 403                 enum amd_pp_clock_type type,
 404                 struct amd_pp_clocks *clocks);
 405         int (*get_clock_by_type_with_latency)(void *handle,
 406                 enum amd_pp_clock_type type,
 407                 struct pp_clock_levels_with_latency *clocks);
 408         int (*get_clock_by_type_with_voltage)(void *handle,
 409                 enum amd_pp_clock_type type,
 410                 struct pp_clock_levels_with_voltage *clocks);
 411         int (*set_watermarks_for_clocks_ranges)(void *handle,
 412                                                 void *clock_ranges);
 413         int (*display_clock_voltage_request)(void *handle,
 414                                 struct pp_display_clock_request *clock);
 415         int (*get_display_mode_validation_clocks)(void *handle,
 416                 struct amd_pp_simple_clock_info *clocks);
 417         int (*notify_smu_enable_pwe)(void *handle);
 418         int (*enable_mgpu_fan_boost)(void *handle);
 419         int (*set_active_display_count)(void *handle, uint32_t count);
 420         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 421         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 422         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 423         bool (*get_asic_baco_capability)(void *handle);
 424         int (*get_asic_baco_state)(void *handle, int *state);
 425         int (*set_asic_baco_state)(void *handle, int state);
 426         int (*get_ppfeature_status)(void *handle, char *buf);
 427         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 428         int (*asic_reset_mode_2)(void *handle);
 429         int (*asic_reset_enable_gfx_features)(void *handle);
 430         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 431         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 432         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 433         ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
 434         int (*set_watermarks_for_clock_ranges)(void *handle,
 435                                                struct pp_smu_wm_range_sets *ranges);
 436         int (*display_disable_memory_clock_switch)(void *handle,
 437                                                    bool disable_memory_clock_switch);
 438         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 439                                                 struct pp_smu_nv_clock_table *max_clocks);
 440         int (*get_uclk_dpm_states)(void *handle,
 441                                    unsigned int *clock_values_in_khz,
 442                                    unsigned int *num_states);
 443         int (*get_dpm_clock_table)(void *handle,
 444                                    struct dpm_clocks *clock_table);
 445         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 446         void (*pm_compute_clocks)(void *handle);
 447         int (*notify_rlc_state)(void *handle, bool en);
 448 };
 449
 450 struct metrics_table_header {
 451         uint16_t                        structure_size;
 452         uint8_t                         format_revision;
 453         uint8_t                         content_revision;
 454 };
 455
 456 /*
 457  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 458  * Use gpu_metrics_v1_1 or later instead.
 459  */
 460 struct gpu_metrics_v1_0 {
 461         struct metrics_table_header     common_header;
 462
 463         /* Driver attached timestamp (in ns) */
 464         uint64_t                        system_clock_counter;
 465
 466         /* Temperature */
 467         uint16_t                        temperature_edge;
 468         uint16_t                        temperature_hotspot;
 469         uint16_t                        temperature_mem;
 470         uint16_t                        temperature_vrgfx;
 471         uint16_t                        temperature_vrsoc;
 472         uint16_t                        temperature_vrmem;
 473
 474         /* Utilization */
 475         uint16_t                        average_gfx_activity;
 476         uint16_t                        average_umc_activity; // memory controller
 477         uint16_t                        average_mm_activity; // UVD or VCN
 478
 479         /* Power/Energy */
 480         uint16_t                        average_socket_power;
 481         uint32_t                        energy_accumulator;
 482
 483         /* Average clocks */
 484         uint16_t                        average_gfxclk_frequency;
 485         uint16_t                        average_socclk_frequency;
 486         uint16_t                        average_uclk_frequency;
 487         uint16_t                        average_vclk0_frequency;
 488         uint16_t                        average_dclk0_frequency;
 489         uint16_t                        average_vclk1_frequency;
 490         uint16_t                        average_dclk1_frequency;
 491
 492         /* Current clocks */
 493         uint16_t                        current_gfxclk;
 494         uint16_t                        current_socclk;
 495         uint16_t                        current_uclk;
 496         uint16_t                        current_vclk0;
 497         uint16_t                        current_dclk0;
 498         uint16_t                        current_vclk1;
 499         uint16_t                        current_dclk1;
 500
 501         /* Throttle status */
 502         uint32_t                        throttle_status;
 503
 504         /* Fans */
 505         uint16_t                        current_fan_speed;
 506
 507         /* Link width/speed */
 508         uint8_t                         pcie_link_width;
 509         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 510 };
 511
 512 struct gpu_metrics_v1_1 {
 513         struct metrics_table_header     common_header;
 514
 515         /* Temperature */
 516         uint16_t                        temperature_edge;
 517         uint16_t                        temperature_hotspot;
 518         uint16_t                        temperature_mem;
 519         uint16_t                        temperature_vrgfx;
 520         uint16_t                        temperature_vrsoc;
 521         uint16_t                        temperature_vrmem;
 522
 523         /* Utilization */
 524         uint16_t                        average_gfx_activity;
 525         uint16_t                        average_umc_activity; // memory controller
 526         uint16_t                        average_mm_activity; // UVD or VCN
 527
 528         /* Power/Energy */
 529         uint16_t                        average_socket_power;
 530         uint64_t                        energy_accumulator;
 531
 532         /* Driver attached timestamp (in ns) */
 533         uint64_t                        system_clock_counter;
 534
 535         /* Average clocks */
 536         uint16_t                        average_gfxclk_frequency;
 537         uint16_t                        average_socclk_frequency;
 538         uint16_t                        average_uclk_frequency;
 539         uint16_t                        average_vclk0_frequency;
 540         uint16_t                        average_dclk0_frequency;
 541         uint16_t                        average_vclk1_frequency;
 542         uint16_t                        average_dclk1_frequency;
 543
 544         /* Current clocks */
 545         uint16_t                        current_gfxclk;
 546         uint16_t                        current_socclk;
 547         uint16_t                        current_uclk;
 548         uint16_t                        current_vclk0;
 549         uint16_t                        current_dclk0;
 550         uint16_t                        current_vclk1;
 551         uint16_t                        current_dclk1;
 552
 553         /* Throttle status */
 554         uint32_t                        throttle_status;
 555
 556         /* Fans */
 557         uint16_t                        current_fan_speed;
 558
 559         /* Link width/speed */
 560         uint16_t                        pcie_link_width;
 561         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 562
 563         uint16_t                        padding;
 564
 565         uint32_t                        gfx_activity_acc;
 566         uint32_t                        mem_activity_acc;
 567
 568         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 569 };
 570
 571 struct gpu_metrics_v1_2 {
 572         struct metrics_table_header     common_header;
 573
 574         /* Temperature */
 575         uint16_t                        temperature_edge;
 576         uint16_t                        temperature_hotspot;
 577         uint16_t                        temperature_mem;
 578         uint16_t                        temperature_vrgfx;
 579         uint16_t                        temperature_vrsoc;
 580         uint16_t                        temperature_vrmem;
 581
 582         /* Utilization */
 583         uint16_t                        average_gfx_activity;
 584         uint16_t                        average_umc_activity; // memory controller
 585         uint16_t                        average_mm_activity; // UVD or VCN
 586
 587         /* Power/Energy */
 588         uint16_t                        average_socket_power;
 589         uint64_t                        energy_accumulator;
 590
 591         /* Driver attached timestamp (in ns) */
 592         uint64_t                        system_clock_counter;
 593
 594         /* Average clocks */
 595         uint16_t                        average_gfxclk_frequency;
 596         uint16_t                        average_socclk_frequency;
 597         uint16_t                        average_uclk_frequency;
 598         uint16_t                        average_vclk0_frequency;
 599         uint16_t                        average_dclk0_frequency;
 600         uint16_t                        average_vclk1_frequency;
 601         uint16_t                        average_dclk1_frequency;
 602
 603         /* Current clocks */
 604         uint16_t                        current_gfxclk;
 605         uint16_t                        current_socclk;
 606         uint16_t                        current_uclk;
 607         uint16_t                        current_vclk0;
 608         uint16_t                        current_dclk0;
 609         uint16_t                        current_vclk1;
 610         uint16_t                        current_dclk1;
 611
 612         /* Throttle status (ASIC dependent) */
 613         uint32_t                        throttle_status;
 614
 615         /* Fans */
 616         uint16_t                        current_fan_speed;
 617
 618         /* Link width/speed */
 619         uint16_t                        pcie_link_width;
 620         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 621
 622         uint16_t                        padding;
 623
 624         uint32_t                        gfx_activity_acc;
 625         uint32_t                        mem_activity_acc;
 626
 627         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 628
 629         /* PMFW attached timestamp (10ns resolution) */
 630         uint64_t                        firmware_timestamp;
 631 };
 632
 633 struct gpu_metrics_v1_3 {
 634         struct metrics_table_header     common_header;
 635
 636         /* Temperature */
 637         uint16_t                        temperature_edge;
 638         uint16_t                        temperature_hotspot;
 639         uint16_t                        temperature_mem;
 640         uint16_t                        temperature_vrgfx;
 641         uint16_t                        temperature_vrsoc;
 642         uint16_t                        temperature_vrmem;
 643
 644         /* Utilization */
 645         uint16_t                        average_gfx_activity;
 646         uint16_t                        average_umc_activity; // memory controller
 647         uint16_t                        average_mm_activity; // UVD or VCN
 648
 649         /* Power/Energy */
 650         uint16_t                        average_socket_power;
 651         uint64_t                        energy_accumulator;
 652
 653         /* Driver attached timestamp (in ns) */
 654         uint64_t                        system_clock_counter;
 655
 656         /* Average clocks */
 657         uint16_t                        average_gfxclk_frequency;
 658         uint16_t                        average_socclk_frequency;
 659         uint16_t                        average_uclk_frequency;
 660         uint16_t                        average_vclk0_frequency;
 661         uint16_t                        average_dclk0_frequency;
 662         uint16_t                        average_vclk1_frequency;
 663         uint16_t                        average_dclk1_frequency;
 664
 665         /* Current clocks */
 666         uint16_t                        current_gfxclk;
 667         uint16_t                        current_socclk;
 668         uint16_t                        current_uclk;
 669         uint16_t                        current_vclk0;
 670         uint16_t                        current_dclk0;
 671         uint16_t                        current_vclk1;
 672         uint16_t                        current_dclk1;
 673
 674         /* Throttle status */
 675         uint32_t                        throttle_status;
 676
 677         /* Fans */
 678         uint16_t                        current_fan_speed;
 679
 680         /* Link width/speed */
 681         uint16_t                        pcie_link_width;
 682         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 683
 684         uint16_t                        padding;
 685
 686         uint32_t                        gfx_activity_acc;
 687         uint32_t                        mem_activity_acc;
 688
 689         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 690
 691         /* PMFW attached timestamp (10ns resolution) */
 692         uint64_t                        firmware_timestamp;
 693
 694         /* Voltage (mV) */
 695         uint16_t                        voltage_soc;
 696         uint16_t                        voltage_gfx;
 697         uint16_t                        voltage_mem;
 698
 699         uint16_t                        padding1;
 700
 701         /* Throttle status (ASIC independent) */
 702         uint64_t                        indep_throttle_status;
 703 };
 704
 705 struct gpu_metrics_v1_4 {
 706         struct metrics_table_header     common_header;
 707
 708         /* Temperature (Celsius) */
 709         uint16_t                        temperature_hotspot;
 710         uint16_t                        temperature_mem;
 711         uint16_t                        temperature_vrsoc;
 712
 713         /* Power (Watts) */
 714         uint16_t                        curr_socket_power;
 715
 716         /* Utilization (%) */
 717         uint16_t                        average_gfx_activity;
 718         uint16_t                        average_umc_activity; // memory controller
 719         uint16_t                        vcn_activity[NUM_VCN];
 720
 721         /* Energy (15.259uJ (2^-16) units) */
 722         uint64_t                        energy_accumulator;
 723
 724         /* Driver attached timestamp (in ns) */
 725         uint64_t                        system_clock_counter;
 726
 727         /* Throttle status */
 728         uint32_t                        throttle_status;
 729
 730         /* Clock Lock Status. Each bit corresponds to clock instance */
 731         uint32_t                        gfxclk_lock_status;
 732
 733         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 734         uint16_t                        pcie_link_width;
 735         uint16_t                        pcie_link_speed;
 736
 737         /* XGMI bus width and bitrate (in Gbps) */
 738         uint16_t                        xgmi_link_width;
 739         uint16_t                        xgmi_link_speed;
 740
 741         /* Utilization Accumulated (%) */
 742         uint32_t                        gfx_activity_acc;
 743         uint32_t                        mem_activity_acc;
 744
 745         /*PCIE accumulated bandwidth (GB/sec) */
 746         uint64_t                        pcie_bandwidth_acc;
 747
 748         /*PCIE instantaneous bandwidth (GB/sec) */
 749         uint64_t                        pcie_bandwidth_inst;
 750
 751         /* PCIE L0 to recovery state transition accumulated count */
 752         uint64_t                        pcie_l0_to_recov_count_acc;
 753
 754         /* PCIE replay accumulated count */
 755         uint64_t                        pcie_replay_count_acc;
 756
 757         /* PCIE replay rollover accumulated count */
 758         uint64_t                        pcie_replay_rover_count_acc;
 759
 760         /* XGMI accumulated data transfer size(KiloBytes) */
 761         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 762         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 763
 764         /* PMFW attached timestamp (10ns resolution) */
 765         uint64_t                        firmware_timestamp;
 766
 767         /* Current clocks (Mhz) */
 768         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 769         uint16_t                        current_socclk[MAX_CLKS];
 770         uint16_t                        current_vclk0[MAX_CLKS];
 771         uint16_t                        current_dclk0[MAX_CLKS];
 772         uint16_t                        current_uclk;
 773
 774         uint16_t                        padding;
 775 };
 776
 777 struct gpu_metrics_v1_5 {
 778         struct metrics_table_header     common_header;
 779
 780         /* Temperature (Celsius) */
 781         uint16_t                        temperature_hotspot;
 782         uint16_t                        temperature_mem;
 783         uint16_t                        temperature_vrsoc;
 784
 785         /* Power (Watts) */
 786         uint16_t                        curr_socket_power;
 787
 788         /* Utilization (%) */
 789         uint16_t                        average_gfx_activity;
 790         uint16_t                        average_umc_activity; // memory controller
 791         uint16_t                        vcn_activity[NUM_VCN];
 792         uint16_t                        jpeg_activity[NUM_JPEG_ENG];
 793
 794         /* Energy (15.259uJ (2^-16) units) */
 795         uint64_t                        energy_accumulator;
 796
 797         /* Driver attached timestamp (in ns) */
 798         uint64_t                        system_clock_counter;
 799
 800         /* Throttle status */
 801         uint32_t                        throttle_status;
 802
 803         /* Clock Lock Status. Each bit corresponds to clock instance */
 804         uint32_t                        gfxclk_lock_status;
 805
 806         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 807         uint16_t                        pcie_link_width;
 808         uint16_t                        pcie_link_speed;
 809
 810         /* XGMI bus width and bitrate (in Gbps) */
 811         uint16_t                        xgmi_link_width;
 812         uint16_t                        xgmi_link_speed;
 813
 814         /* Utilization Accumulated (%) */
 815         uint32_t                        gfx_activity_acc;
 816         uint32_t                        mem_activity_acc;
 817
 818         /*PCIE accumulated bandwidth (GB/sec) */
 819         uint64_t                        pcie_bandwidth_acc;
 820
 821         /*PCIE instantaneous bandwidth (GB/sec) */
 822         uint64_t                        pcie_bandwidth_inst;
 823
 824         /* PCIE L0 to recovery state transition accumulated count */
 825         uint64_t                        pcie_l0_to_recov_count_acc;
 826
 827         /* PCIE replay accumulated count */
 828         uint64_t                        pcie_replay_count_acc;
 829
 830         /* PCIE replay rollover accumulated count */
 831         uint64_t                        pcie_replay_rover_count_acc;
 832
 833         /* PCIE NAK sent  accumulated count */
 834         uint32_t                        pcie_nak_sent_count_acc;
 835
 836         /* PCIE NAK received accumulated count */
 837         uint32_t                        pcie_nak_rcvd_count_acc;
 838
 839         /* XGMI accumulated data transfer size(KiloBytes) */
 840         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 841         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 842
 843         /* PMFW attached timestamp (10ns resolution) */
 844         uint64_t                        firmware_timestamp;
 845
 846         /* Current clocks (Mhz) */
 847         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 848         uint16_t                        current_socclk[MAX_CLKS];
 849         uint16_t                        current_vclk0[MAX_CLKS];
 850         uint16_t                        current_dclk0[MAX_CLKS];
 851         uint16_t                        current_uclk;
 852
 853         uint16_t                        padding;
 854 };
 855
 856 /*
 857  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 858  * Use gpu_metrics_v2_1 or later instead.
 859  */
 860 struct gpu_metrics_v2_0 {
 861         struct metrics_table_header     common_header;
 862
 863         /* Driver attached timestamp (in ns) */
 864         uint64_t                        system_clock_counter;
 865
 866         /* Temperature */
 867         uint16_t                        temperature_gfx; // gfx temperature on APUs
 868         uint16_t                        temperature_soc; // soc temperature on APUs
 869         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 870         uint16_t                        temperature_l3[2];
 871
 872         /* Utilization */
 873         uint16_t                        average_gfx_activity;
 874         uint16_t                        average_mm_activity; // UVD or VCN
 875
 876         /* Power/Energy */
 877         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 878         uint16_t                        average_cpu_power;
 879         uint16_t                        average_soc_power;
 880         uint16_t                        average_gfx_power;
 881         uint16_t                        average_core_power[8]; // CPU core power on APUs
 882
 883         /* Average clocks */
 884         uint16_t                        average_gfxclk_frequency;
 885         uint16_t                        average_socclk_frequency;
 886         uint16_t                        average_uclk_frequency;
 887         uint16_t                        average_fclk_frequency;
 888         uint16_t                        average_vclk_frequency;
 889         uint16_t                        average_dclk_frequency;
 890
 891         /* Current clocks */
 892         uint16_t                        current_gfxclk;
 893         uint16_t                        current_socclk;
 894         uint16_t                        current_uclk;
 895         uint16_t                        current_fclk;
 896         uint16_t                        current_vclk;
 897         uint16_t                        current_dclk;
 898         uint16_t                        current_coreclk[8]; // CPU core clocks
 899         uint16_t                        current_l3clk[2];
 900
 901         /* Throttle status */
 902         uint32_t                        throttle_status;
 903
 904         /* Fans */
 905         uint16_t                        fan_pwm;
 906
 907         uint16_t                        padding;
 908 };
 909
 910 struct gpu_metrics_v2_1 {
 911         struct metrics_table_header     common_header;
 912
 913         /* Temperature */
 914         uint16_t                        temperature_gfx; // gfx temperature on APUs
 915         uint16_t                        temperature_soc; // soc temperature on APUs
 916         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 917         uint16_t                        temperature_l3[2];
 918
 919         /* Utilization */
 920         uint16_t                        average_gfx_activity;
 921         uint16_t                        average_mm_activity; // UVD or VCN
 922
 923         /* Driver attached timestamp (in ns) */
 924         uint64_t                        system_clock_counter;
 925
 926         /* Power/Energy */
 927         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 928         uint16_t                        average_cpu_power;
 929         uint16_t                        average_soc_power;
 930         uint16_t                        average_gfx_power;
 931         uint16_t                        average_core_power[8]; // CPU core power on APUs
 932
 933         /* Average clocks */
 934         uint16_t                        average_gfxclk_frequency;
 935         uint16_t                        average_socclk_frequency;
 936         uint16_t                        average_uclk_frequency;
 937         uint16_t                        average_fclk_frequency;
 938         uint16_t                        average_vclk_frequency;
 939         uint16_t                        average_dclk_frequency;
 940
 941         /* Current clocks */
 942         uint16_t                        current_gfxclk;
 943         uint16_t                        current_socclk;
 944         uint16_t                        current_uclk;
 945         uint16_t                        current_fclk;
 946         uint16_t                        current_vclk;
 947         uint16_t                        current_dclk;
 948         uint16_t                        current_coreclk[8]; // CPU core clocks
 949         uint16_t                        current_l3clk[2];
 950
 951         /* Throttle status */
 952         uint32_t                        throttle_status;
 953
 954         /* Fans */
 955         uint16_t                        fan_pwm;
 956
 957         uint16_t                        padding[3];
 958 };
 959
 960 struct gpu_metrics_v2_2 {
 961         struct metrics_table_header     common_header;
 962
 963         /* Temperature */
 964         uint16_t                        temperature_gfx; // gfx temperature on APUs
 965         uint16_t                        temperature_soc; // soc temperature on APUs
 966         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 967         uint16_t                        temperature_l3[2];
 968
 969         /* Utilization */
 970         uint16_t                        average_gfx_activity;
 971         uint16_t                        average_mm_activity; // UVD or VCN
 972
 973         /* Driver attached timestamp (in ns) */
 974         uint64_t                        system_clock_counter;
 975
 976         /* Power/Energy */
 977         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 978         uint16_t                        average_cpu_power;
 979         uint16_t                        average_soc_power;
 980         uint16_t                        average_gfx_power;
 981         uint16_t                        average_core_power[8]; // CPU core power on APUs
 982
 983         /* Average clocks */
 984         uint16_t                        average_gfxclk_frequency;
 985         uint16_t                        average_socclk_frequency;
 986         uint16_t                        average_uclk_frequency;
 987         uint16_t                        average_fclk_frequency;
 988         uint16_t                        average_vclk_frequency;
 989         uint16_t                        average_dclk_frequency;
 990
 991         /* Current clocks */
 992         uint16_t                        current_gfxclk;
 993         uint16_t                        current_socclk;
 994         uint16_t                        current_uclk;
 995         uint16_t                        current_fclk;
 996         uint16_t                        current_vclk;
 997         uint16_t                        current_dclk;
 998         uint16_t                        current_coreclk[8]; // CPU core clocks
 999         uint16_t                        current_l3clk[2];
1000
1001         /* Throttle status (ASIC dependent) */
1002         uint32_t                        throttle_status;
1003
1004         /* Fans */
1005         uint16_t                        fan_pwm;
1006
1007         uint16_t                        padding[3];
1008
1009         /* Throttle status (ASIC independent) */
1010         uint64_t                        indep_throttle_status;
1011 };
1012
1013 struct gpu_metrics_v2_3 {
1014         struct metrics_table_header     common_header;
1015
1016         /* Temperature */
1017         uint16_t                        temperature_gfx; // gfx temperature on APUs
1018         uint16_t                        temperature_soc; // soc temperature on APUs
1019         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1020         uint16_t                        temperature_l3[2];
1021
1022         /* Utilization */
1023         uint16_t                        average_gfx_activity;
1024         uint16_t                        average_mm_activity; // UVD or VCN
1025
1026         /* Driver attached timestamp (in ns) */
1027         uint64_t                        system_clock_counter;
1028
1029         /* Power/Energy */
1030         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1031         uint16_t                        average_cpu_power;
1032         uint16_t                        average_soc_power;
1033         uint16_t                        average_gfx_power;
1034         uint16_t                        average_core_power[8]; // CPU core power on APUs
1035
1036         /* Average clocks */
1037         uint16_t                        average_gfxclk_frequency;
1038         uint16_t                        average_socclk_frequency;
1039         uint16_t                        average_uclk_frequency;
1040         uint16_t                        average_fclk_frequency;
1041         uint16_t                        average_vclk_frequency;
1042         uint16_t                        average_dclk_frequency;
1043
1044         /* Current clocks */
1045         uint16_t                        current_gfxclk;
1046         uint16_t                        current_socclk;
1047         uint16_t                        current_uclk;
1048         uint16_t                        current_fclk;
1049         uint16_t                        current_vclk;
1050         uint16_t                        current_dclk;
1051         uint16_t                        current_coreclk[8]; // CPU core clocks
1052         uint16_t                        current_l3clk[2];
1053
1054         /* Throttle status (ASIC dependent) */
1055         uint32_t                        throttle_status;
1056
1057         /* Fans */
1058         uint16_t                        fan_pwm;
1059
1060         uint16_t                        padding[3];
1061
1062         /* Throttle status (ASIC independent) */
1063         uint64_t                        indep_throttle_status;
1064
1065         /* Average Temperature */
1066         uint16_t                        average_temperature_gfx; // average gfx temperature on APUs
1067         uint16_t                        average_temperature_soc; // average soc temperature on APUs
1068         uint16_t                        average_temperature_core[8]; // average CPU core temperature on APUs
1069         uint16_t                        average_temperature_l3[2];
1070 };
1071
1072 struct gpu_metrics_v2_4 {
1073         struct metrics_table_header     common_header;
1074
1075         /* Temperature (unit: centi-Celsius) */
1076         uint16_t                        temperature_gfx;
1077         uint16_t                        temperature_soc;
1078         uint16_t                        temperature_core[8];
1079         uint16_t                        temperature_l3[2];
1080
1081         /* Utilization (unit: centi) */
1082         uint16_t                        average_gfx_activity;
1083         uint16_t                        average_mm_activity;
1084
1085         /* Driver attached timestamp (in ns) */
1086         uint64_t                        system_clock_counter;
1087
1088         /* Power/Energy (unit: mW) */
1089         uint16_t                        average_socket_power;
1090         uint16_t                        average_cpu_power;
1091         uint16_t                        average_soc_power;
1092         uint16_t                        average_gfx_power;
1093         uint16_t                        average_core_power[8];
1094
1095         /* Average clocks (unit: MHz) */
1096         uint16_t                        average_gfxclk_frequency;
1097         uint16_t                        average_socclk_frequency;
1098         uint16_t                        average_uclk_frequency;
1099         uint16_t                        average_fclk_frequency;
1100         uint16_t                        average_vclk_frequency;
1101         uint16_t                        average_dclk_frequency;
1102
1103         /* Current clocks (unit: MHz) */
1104         uint16_t                        current_gfxclk;
1105         uint16_t                        current_socclk;
1106         uint16_t                        current_uclk;
1107         uint16_t                        current_fclk;
1108         uint16_t                        current_vclk;
1109         uint16_t                        current_dclk;
1110         uint16_t                        current_coreclk[8];
1111         uint16_t                        current_l3clk[2];
1112
1113         /* Throttle status (ASIC dependent) */
1114         uint32_t                        throttle_status;
1115
1116         /* Fans */
1117         uint16_t                        fan_pwm;
1118
1119         uint16_t                        padding[3];
1120
1121         /* Throttle status (ASIC independent) */
1122         uint64_t                        indep_throttle_status;
1123
1124         /* Average Temperature (unit: centi-Celsius) */
1125         uint16_t                        average_temperature_gfx;
1126         uint16_t                        average_temperature_soc;
1127         uint16_t                        average_temperature_core[8];
1128         uint16_t                        average_temperature_l3[2];
1129
1130         /* Power/Voltage (unit: mV) */
1131         uint16_t                        average_cpu_voltage;
1132         uint16_t                        average_soc_voltage;
1133         uint16_t                        average_gfx_voltage;
1134
1135         /* Power/Current (unit: mA) */
1136         uint16_t                        average_cpu_current;
1137         uint16_t                        average_soc_current;
1138         uint16_t                        average_gfx_current;
1139 };
1140
1141 struct gpu_metrics_v3_0 {
1142         struct metrics_table_header     common_header;
1143
1144         /* Temperature */
1145         /* gfx temperature on APUs */
1146         uint16_t                        temperature_gfx;
1147         /* soc temperature on APUs */
1148         uint16_t                        temperature_soc;
1149         /* CPU core temperature on APUs */
1150         uint16_t                        temperature_core[16];
1151         /* skin temperature on APUs */
1152         uint16_t                        temperature_skin;
1153
1154         /* Utilization */
1155         /* time filtered GFX busy % [0-100] */
1156         uint16_t                        average_gfx_activity;
1157         /* time filtered VCN busy % [0-100] */
1158         uint16_t                        average_vcn_activity;
1159         /* time filtered IPU per-column busy % [0-100] */
1160         uint16_t                        average_ipu_activity[8];
1161         /* time filtered per-core C0 residency % [0-100]*/
1162         uint16_t                        average_core_c0_activity[16];
1163         /* time filtered DRAM read bandwidth [MB/sec] */
1164         uint16_t                        average_dram_reads;
1165         /* time filtered DRAM write bandwidth [MB/sec] */
1166         uint16_t                        average_dram_writes;
1167         /* time filtered IPU read bandwidth [MB/sec] */
1168         uint16_t                        average_ipu_reads;
1169         /* time filtered IPU write bandwidth [MB/sec] */
1170         uint16_t                        average_ipu_writes;
1171
1172         /* Driver attached timestamp (in ns) */
1173         uint64_t                        system_clock_counter;
1174
1175         /* Power/Energy */
1176         /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1177         uint32_t                        average_socket_power;
1178         /* time filtered IPU power [mW] */
1179         uint16_t                        average_ipu_power;
1180         /* time filtered APU power [mW] */
1181         uint32_t                        average_apu_power;
1182         /* time filtered GFX power [mW] */
1183         uint32_t                        average_gfx_power;
1184         /* time filtered dGPU power [mW] */
1185         uint32_t                        average_dgpu_power;
1186         /* time filtered sum of core power across all cores in the socket [mW] */
1187         uint32_t                        average_all_core_power;
1188         /* calculated core power [mW] */
1189         uint16_t                        average_core_power[16];
1190         /* time filtered total system power [mW] */
1191         uint16_t                        average_sys_power;
1192         /* maximum IRM defined STAPM power limit [mW] */
1193         uint16_t                        stapm_power_limit;
1194         /* time filtered STAPM power limit [mW] */
1195         uint16_t                        current_stapm_power_limit;
1196
1197         /* time filtered clocks [MHz] */
1198         uint16_t                        average_gfxclk_frequency;
1199         uint16_t                        average_socclk_frequency;
1200         uint16_t                        average_vpeclk_frequency;
1201         uint16_t                        average_ipuclk_frequency;
1202         uint16_t                        average_fclk_frequency;
1203         uint16_t                        average_vclk_frequency;
1204         uint16_t                        average_uclk_frequency;
1205         uint16_t                        average_mpipu_frequency;
1206
1207         /* Current clocks */
1208         /* target core frequency [MHz] */
1209         uint16_t                        current_coreclk[16];
1210         /* CCLK frequency limit enforced on classic cores [MHz] */
1211         uint16_t                        current_core_maxfreq;
1212         /* GFXCLK frequency limit enforced on GFX [MHz] */
1213         uint16_t                        current_gfx_maxfreq;
1214
1215         /* Throttle Residency (ASIC dependent) */
1216         uint32_t                        throttle_residency_prochot;
1217         uint32_t                        throttle_residency_spl;
1218         uint32_t                        throttle_residency_fppt;
1219         uint32_t                        throttle_residency_sppt;
1220         uint32_t                        throttle_residency_thm_core;
1221         uint32_t                        throttle_residency_thm_gfx;
1222         uint32_t                        throttle_residency_thm_soc;
1223
1224         /* Metrics table alpha filter time constant [us] */
1225         uint32_t                        time_filter_alphavalue;
1226 };
1227
1228 struct amdgpu_pmmetrics_header {
1229         uint16_t structure_size;
1230         uint16_t pad;
1231         uint32_t mp1_ip_discovery_version;
1232         uint32_t pmfw_version;
1233         uint32_t pmmetrics_version;
1234 };
1235
1236 struct amdgpu_pm_metrics {
1237         struct amdgpu_pmmetrics_header common_header;
1238
1239         uint8_t data[];
1240 };
1241
1242 #endif