drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 116 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 117 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 118 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 119 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 120 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 121
 122 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 123 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 124 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 125 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 126 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 127 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 128 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 129 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 130 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 131 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 132 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 133
 134 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 135 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 137 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 138 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 139 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 140
 141 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 142 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 143 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 144 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 145 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 146 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 147
 148 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 149 {
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 190 };
 191
 192 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 193 {
 194         /* Pending on emulation bring up */
 195 };
 196
 197 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 198 {
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1251 };
1252
1253 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1254 {
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1293 };
1294
1295 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1296 {
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1337 };
1338
1339 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1340 {
1341         static void *scratch_reg0;
1342         static void *scratch_reg1;
1343         static void *scratch_reg2;
1344         static void *scratch_reg3;
1345         static void *spare_int;
1346         static uint32_t grbm_cntl;
1347         static uint32_t grbm_idx;
1348         uint32_t i = 0;
1349         uint32_t retries = 50000;
1350
1351         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1352         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1353         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1354         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1355         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1356
1357         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1358         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1359
1360         if (amdgpu_sriov_runtime(adev)) {
1361                 pr_err("shouldn't call rlcg write register during runtime\n");
1362                 return;
1363         }
1364
1365         writel(v, scratch_reg0);
1366         writel(offset | 0x80000000, scratch_reg1);
1367         writel(1, spare_int);
1368         for (i = 0; i < retries; i++) {
1369                 u32 tmp;
1370
1371                 tmp = readl(scratch_reg1);
1372                 if (!(tmp & 0x80000000))
1373                         break;
1374
1375                 udelay(10);
1376         }
1377
1378         if (i >= retries)
1379                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1380 }
1381
1382 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1383 {
1384         /* Pending on emulation bring up */
1385 };
1386
1387 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1388 {
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2009 };
2010
2011 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2012 {
2013         /* Pending on emulation bring up */
2014 };
2015
2016 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2017 {
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3070 };
3071
3072 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3073 {
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3110 };
3111
3112 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3113 {
3114         /* Pending on emulation bring up */
3115 };
3116
3117 #define DEFAULT_SH_MEM_CONFIG \
3118         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3119          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3120          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3121          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3122
3123
3124 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3125 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3126 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3127 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3128 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3129                                  struct amdgpu_cu_info *cu_info);
3130 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3131 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3132                                    u32 sh_num, u32 instance);
3133 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3134
3135 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3136 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3137 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3138 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3139 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3140 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3141 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3142
3143 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3144 {
3145         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3146         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3147                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3148         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3149         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3150         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3151         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3152         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3153         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3154 }
3155
3156 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3157                                  struct amdgpu_ring *ring)
3158 {
3159         struct amdgpu_device *adev = kiq_ring->adev;
3160         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3161         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3162         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3163
3164         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3165         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3166         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3167                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3168                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3169                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3170                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3171                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3172                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3173                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3174                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3175                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3176         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3177         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3178         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3179         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3180         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3181 }
3182
3183 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3184                                    struct amdgpu_ring *ring,
3185                                    enum amdgpu_unmap_queues_action action,
3186                                    u64 gpu_addr, u64 seq)
3187 {
3188         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3189
3190         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3191         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3192                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3193                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3194                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3195                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3196         amdgpu_ring_write(kiq_ring,
3197                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3198
3199         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3200                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3201                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3202                 amdgpu_ring_write(kiq_ring, seq);
3203         } else {
3204                 amdgpu_ring_write(kiq_ring, 0);
3205                 amdgpu_ring_write(kiq_ring, 0);
3206                 amdgpu_ring_write(kiq_ring, 0);
3207         }
3208 }
3209
3210 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3211                                    struct amdgpu_ring *ring,
3212                                    u64 addr,
3213                                    u64 seq)
3214 {
3215         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3216
3217         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3218         amdgpu_ring_write(kiq_ring,
3219                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3220                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3221                           PACKET3_QUERY_STATUS_COMMAND(2));
3222         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3223                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3224                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3225         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3226         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3227         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3228         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3229 }
3230
3231 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3232                                 uint16_t pasid, uint32_t flush_type,
3233                                 bool all_hub)
3234 {
3235         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3236         amdgpu_ring_write(kiq_ring,
3237                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3238                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3239                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3240                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3241 }
3242
3243 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3244         .kiq_set_resources = gfx10_kiq_set_resources,
3245         .kiq_map_queues = gfx10_kiq_map_queues,
3246         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3247         .kiq_query_status = gfx10_kiq_query_status,
3248         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3249         .set_resources_size = 8,
3250         .map_queues_size = 7,
3251         .unmap_queues_size = 6,
3252         .query_status_size = 7,
3253         .invalidate_tlbs_size = 2,
3254 };
3255
3256 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3257 {
3258         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3259 }
3260
3261 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3262 {
3263         switch (adev->asic_type) {
3264         case CHIP_NAVI10:
3265                 soc15_program_register_sequence(adev,
3266                                                 golden_settings_gc_10_1,
3267                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3268                 soc15_program_register_sequence(adev,
3269                                                 golden_settings_gc_10_0_nv10,
3270                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3271                 soc15_program_register_sequence(adev,
3272                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3273                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3274                 break;
3275         case CHIP_NAVI14:
3276                 soc15_program_register_sequence(adev,
3277                                                 golden_settings_gc_10_1_1,
3278                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3279                 soc15_program_register_sequence(adev,
3280                                                 golden_settings_gc_10_1_nv14,
3281                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3282                 soc15_program_register_sequence(adev,
3283                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3284                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3285                 break;
3286         case CHIP_NAVI12:
3287                 soc15_program_register_sequence(adev,
3288                                                 golden_settings_gc_10_1_2,
3289                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3290                 soc15_program_register_sequence(adev,
3291                                                 golden_settings_gc_10_1_2_nv12,
3292                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3293                 soc15_program_register_sequence(adev,
3294                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3295                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3296                 break;
3297         case CHIP_SIENNA_CICHLID:
3298                 soc15_program_register_sequence(adev,
3299                                                 golden_settings_gc_10_3,
3300                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3301                 soc15_program_register_sequence(adev,
3302                                                 golden_settings_gc_10_3_sienna_cichlid,
3303                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3304                 break;
3305         default:
3306                 break;
3307         }
3308 }
3309
3310 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3311 {
3312         adev->gfx.scratch.num_reg = 8;
3313         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3314         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3315 }
3316
3317 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3318                                        bool wc, uint32_t reg, uint32_t val)
3319 {
3320         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3321         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3322                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3323         amdgpu_ring_write(ring, reg);
3324         amdgpu_ring_write(ring, 0);
3325         amdgpu_ring_write(ring, val);
3326 }
3327
3328 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3329                                   int mem_space, int opt, uint32_t addr0,
3330                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3331                                   uint32_t inv)
3332 {
3333         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3334         amdgpu_ring_write(ring,
3335                           /* memory (1) or register (0) */
3336                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3337                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3338                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3339                            WAIT_REG_MEM_ENGINE(eng_sel)));
3340
3341         if (mem_space)
3342                 BUG_ON(addr0 & 0x3); /* Dword align */
3343         amdgpu_ring_write(ring, addr0);
3344         amdgpu_ring_write(ring, addr1);
3345         amdgpu_ring_write(ring, ref);
3346         amdgpu_ring_write(ring, mask);
3347         amdgpu_ring_write(ring, inv); /* poll interval */
3348 }
3349
3350 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3351 {
3352         struct amdgpu_device *adev = ring->adev;
3353         uint32_t scratch;
3354         uint32_t tmp = 0;
3355         unsigned i;
3356         int r;
3357
3358         r = amdgpu_gfx_scratch_get(adev, &scratch);
3359         if (r) {
3360                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3361                 return r;
3362         }
3363
3364         WREG32(scratch, 0xCAFEDEAD);
3365
3366         r = amdgpu_ring_alloc(ring, 3);
3367         if (r) {
3368                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3369                           ring->idx, r);
3370                 amdgpu_gfx_scratch_free(adev, scratch);
3371                 return r;
3372         }
3373
3374         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3375         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3376         amdgpu_ring_write(ring, 0xDEADBEEF);
3377         amdgpu_ring_commit(ring);
3378
3379         for (i = 0; i < adev->usec_timeout; i++) {
3380                 tmp = RREG32(scratch);
3381                 if (tmp == 0xDEADBEEF)
3382                         break;
3383                 if (amdgpu_emu_mode == 1)
3384                         msleep(1);
3385                 else
3386                         udelay(1);
3387         }
3388
3389         if (i >= adev->usec_timeout)
3390                 r = -ETIMEDOUT;
3391
3392         amdgpu_gfx_scratch_free(adev, scratch);
3393
3394         return r;
3395 }
3396
3397 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3398 {
3399         struct amdgpu_device *adev = ring->adev;
3400         struct amdgpu_ib ib;
3401         struct dma_fence *f = NULL;
3402         unsigned index;
3403         uint64_t gpu_addr;
3404         uint32_t tmp;
3405         long r;
3406
3407         r = amdgpu_device_wb_get(adev, &index);
3408         if (r)
3409                 return r;
3410
3411         gpu_addr = adev->wb.gpu_addr + (index * 4);
3412         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3413         memset(&ib, 0, sizeof(ib));
3414         r = amdgpu_ib_get(adev, NULL, 16,
3415                                         AMDGPU_IB_POOL_DIRECT, &ib);
3416         if (r)
3417                 goto err1;
3418
3419         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3420         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3421         ib.ptr[2] = lower_32_bits(gpu_addr);
3422         ib.ptr[3] = upper_32_bits(gpu_addr);
3423         ib.ptr[4] = 0xDEADBEEF;
3424         ib.length_dw = 5;
3425
3426         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3427         if (r)
3428                 goto err2;
3429
3430         r = dma_fence_wait_timeout(f, false, timeout);
3431         if (r == 0) {
3432                 r = -ETIMEDOUT;
3433                 goto err2;
3434         } else if (r < 0) {
3435                 goto err2;
3436         }
3437
3438         tmp = adev->wb.wb[index];
3439         if (tmp == 0xDEADBEEF)
3440                 r = 0;
3441         else
3442                 r = -EINVAL;
3443 err2:
3444         amdgpu_ib_free(adev, &ib, NULL);
3445         dma_fence_put(f);
3446 err1:
3447         amdgpu_device_wb_free(adev, index);
3448         return r;
3449 }
3450
3451 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3452 {
3453         release_firmware(adev->gfx.pfp_fw);
3454         adev->gfx.pfp_fw = NULL;
3455         release_firmware(adev->gfx.me_fw);
3456         adev->gfx.me_fw = NULL;
3457         release_firmware(adev->gfx.ce_fw);
3458         adev->gfx.ce_fw = NULL;
3459         release_firmware(adev->gfx.rlc_fw);
3460         adev->gfx.rlc_fw = NULL;
3461         release_firmware(adev->gfx.mec_fw);
3462         adev->gfx.mec_fw = NULL;
3463         release_firmware(adev->gfx.mec2_fw);
3464         adev->gfx.mec2_fw = NULL;
3465
3466         kfree(adev->gfx.rlc.register_list_format);
3467 }
3468
3469 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3470 {
3471         adev->gfx.cp_fw_write_wait = false;
3472
3473         switch (adev->asic_type) {
3474         case CHIP_NAVI10:
3475         case CHIP_NAVI12:
3476         case CHIP_NAVI14:
3477                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3478                     (adev->gfx.me_feature_version >= 27) &&
3479                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3480                     (adev->gfx.pfp_feature_version >= 27) &&
3481                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3482                     (adev->gfx.mec_feature_version >= 27))
3483                         adev->gfx.cp_fw_write_wait = true;
3484                 break;
3485         case CHIP_SIENNA_CICHLID:
3486                 adev->gfx.cp_fw_write_wait = true;
3487                 break;
3488         default:
3489                 break;
3490         }
3491
3492         if (adev->gfx.cp_fw_write_wait == false)
3493                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3494 }
3495
3496
3497 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3498 {
3499         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3500
3501         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3502         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3503         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3504         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3505         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3506         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3507         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3508         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3509         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3510         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3511         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3512         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3513         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3514         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3515                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3516 }
3517
3518 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3519 {
3520         bool ret = false;
3521
3522         switch (adev->pdev->revision) {
3523         case 0xc2:
3524         case 0xc3:
3525                 ret = true;
3526                 break;
3527         default:
3528                 ret = false;
3529                 break;
3530         }
3531
3532         return ret ;
3533 }
3534
3535 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3536 {
3537         switch (adev->asic_type) {
3538         case CHIP_NAVI10:
3539                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3540                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3541                 break;
3542         default:
3543                 break;
3544         }
3545 }
3546
3547 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3548 {
3549         const char *chip_name;
3550         char fw_name[40];
3551         char wks[10];
3552         int err;
3553         struct amdgpu_firmware_info *info = NULL;
3554         const struct common_firmware_header *header = NULL;
3555         const struct gfx_firmware_header_v1_0 *cp_hdr;
3556         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3557         unsigned int *tmp = NULL;
3558         unsigned int i = 0;
3559         uint16_t version_major;
3560         uint16_t version_minor;
3561
3562         DRM_DEBUG("\n");
3563
3564         memset(wks, 0, sizeof(wks));
3565         switch (adev->asic_type) {
3566         case CHIP_NAVI10:
3567                 chip_name = "navi10";
3568                 break;
3569         case CHIP_NAVI14:
3570                 chip_name = "navi14";
3571                 if (!(adev->pdev->device == 0x7340 &&
3572                       adev->pdev->revision != 0x00))
3573                         snprintf(wks, sizeof(wks), "_wks");
3574                 break;
3575         case CHIP_NAVI12:
3576                 chip_name = "navi12";
3577                 break;
3578         case CHIP_SIENNA_CICHLID:
3579                 chip_name = "sienna_cichlid";
3580                 break;
3581         default:
3582                 BUG();
3583         }
3584
3585         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3586         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3587         if (err)
3588                 goto out;
3589         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3590         if (err)
3591                 goto out;
3592         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3593         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3594         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3595
3596         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3597         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3598         if (err)
3599                 goto out;
3600         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3601         if (err)
3602                 goto out;
3603         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3604         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3605         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3606
3607         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3608         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3609         if (err)
3610                 goto out;
3611         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3612         if (err)
3613                 goto out;
3614         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3615         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3616         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3617
3618         if (!amdgpu_sriov_vf(adev)) {
3619                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3620                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3621                 if (err)
3622                         goto out;
3623                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3624                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3625                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3626                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3627                 if (version_major == 2 && version_minor == 1)
3628                         adev->gfx.rlc.is_rlc_v2_1 = true;
3629
3630                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3631                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3632                 adev->gfx.rlc.save_and_restore_offset =
3633                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3634                 adev->gfx.rlc.clear_state_descriptor_offset =
3635                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3636                 adev->gfx.rlc.avail_scratch_ram_locations =
3637                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3638                 adev->gfx.rlc.reg_restore_list_size =
3639                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3640                 adev->gfx.rlc.reg_list_format_start =
3641                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3642                 adev->gfx.rlc.reg_list_format_separate_start =
3643                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3644                 adev->gfx.rlc.starting_offsets_start =
3645                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3646                 adev->gfx.rlc.reg_list_format_size_bytes =
3647                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3648                 adev->gfx.rlc.reg_list_size_bytes =
3649                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3650                 adev->gfx.rlc.register_list_format =
3651                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3652                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3653                 if (!adev->gfx.rlc.register_list_format) {
3654                         err = -ENOMEM;
3655                         goto out;
3656                 }
3657
3658                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3659                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3660                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3661                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3662
3663                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3664
3665                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3666                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3667                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3668                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3669
3670                 if (adev->gfx.rlc.is_rlc_v2_1)
3671                         gfx_v10_0_init_rlc_ext_microcode(adev);
3672         }
3673
3674         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3675         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3676         if (err)
3677                 goto out;
3678         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3679         if (err)
3680                 goto out;
3681         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3682         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3683         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3684
3685         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3686         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3687         if (!err) {
3688                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3689                 if (err)
3690                         goto out;
3691                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3692                 adev->gfx.mec2_fw->data;
3693                 adev->gfx.mec2_fw_version =
3694                 le32_to_cpu(cp_hdr->header.ucode_version);
3695                 adev->gfx.mec2_feature_version =
3696                 le32_to_cpu(cp_hdr->ucode_feature_version);
3697         } else {
3698                 err = 0;
3699                 adev->gfx.mec2_fw = NULL;
3700         }
3701
3702         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3703                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3704                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3705                 info->fw = adev->gfx.pfp_fw;
3706                 header = (const struct common_firmware_header *)info->fw->data;
3707                 adev->firmware.fw_size +=
3708                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3709
3710                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3711                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3712                 info->fw = adev->gfx.me_fw;
3713                 header = (const struct common_firmware_header *)info->fw->data;
3714                 adev->firmware.fw_size +=
3715                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3716
3717                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3718                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3719                 info->fw = adev->gfx.ce_fw;
3720                 header = (const struct common_firmware_header *)info->fw->data;
3721                 adev->firmware.fw_size +=
3722                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3723
3724                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3725                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3726                 info->fw = adev->gfx.rlc_fw;
3727                 if (info->fw) {
3728                         header = (const struct common_firmware_header *)info->fw->data;
3729                         adev->firmware.fw_size +=
3730                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3731                 }
3732                 if (adev->gfx.rlc.is_rlc_v2_1 &&
3733                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3734                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3735                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3736                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3737                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3738                         info->fw = adev->gfx.rlc_fw;
3739                         adev->firmware.fw_size +=
3740                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3741
3742                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3743                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3744                         info->fw = adev->gfx.rlc_fw;
3745                         adev->firmware.fw_size +=
3746                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3747
3748                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3749                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3750                         info->fw = adev->gfx.rlc_fw;
3751                         adev->firmware.fw_size +=
3752                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3753                 }
3754
3755                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3756                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3757                 info->fw = adev->gfx.mec_fw;
3758                 header = (const struct common_firmware_header *)info->fw->data;
3759                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3760                 adev->firmware.fw_size +=
3761                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3762                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3763
3764                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3765                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3766                 info->fw = adev->gfx.mec_fw;
3767                 adev->firmware.fw_size +=
3768                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3769
3770                 if (adev->gfx.mec2_fw) {
3771                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3772                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3773                         info->fw = adev->gfx.mec2_fw;
3774                         header = (const struct common_firmware_header *)info->fw->data;
3775                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3776                         adev->firmware.fw_size +=
3777                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3778                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3779                                       PAGE_SIZE);
3780                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3781                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3782                         info->fw = adev->gfx.mec2_fw;
3783                         adev->firmware.fw_size +=
3784                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3785                                       PAGE_SIZE);
3786                 }
3787         }
3788
3789         gfx_v10_0_check_fw_write_wait(adev);
3790 out:
3791         if (err) {
3792                 dev_err(adev->dev,
3793                         "gfx10: Failed to load firmware \"%s\"\n",
3794                         fw_name);
3795                 release_firmware(adev->gfx.pfp_fw);
3796                 adev->gfx.pfp_fw = NULL;
3797                 release_firmware(adev->gfx.me_fw);
3798                 adev->gfx.me_fw = NULL;
3799                 release_firmware(adev->gfx.ce_fw);
3800                 adev->gfx.ce_fw = NULL;
3801                 release_firmware(adev->gfx.rlc_fw);
3802                 adev->gfx.rlc_fw = NULL;
3803                 release_firmware(adev->gfx.mec_fw);
3804                 adev->gfx.mec_fw = NULL;
3805                 release_firmware(adev->gfx.mec2_fw);
3806                 adev->gfx.mec2_fw = NULL;
3807         }
3808
3809         gfx_v10_0_check_gfxoff_flag(adev);
3810
3811         return err;
3812 }
3813
3814 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3815 {
3816         u32 count = 0;
3817         const struct cs_section_def *sect = NULL;
3818         const struct cs_extent_def *ext = NULL;
3819
3820         /* begin clear state */
3821         count += 2;
3822         /* context control state */
3823         count += 3;
3824
3825         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3826                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3827                         if (sect->id == SECT_CONTEXT)
3828                                 count += 2 + ext->reg_count;
3829                         else
3830                                 return 0;
3831                 }
3832         }
3833
3834         /* set PA_SC_TILE_STEERING_OVERRIDE */
3835         count += 3;
3836         /* end clear state */
3837         count += 2;
3838         /* clear state */
3839         count += 2;
3840
3841         return count;
3842 }
3843
3844 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3845                                     volatile u32 *buffer)
3846 {
3847         u32 count = 0, i;
3848         const struct cs_section_def *sect = NULL;
3849         const struct cs_extent_def *ext = NULL;
3850         int ctx_reg_offset;
3851
3852         if (adev->gfx.rlc.cs_data == NULL)
3853                 return;
3854         if (buffer == NULL)
3855                 return;
3856
3857         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3858         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3859
3860         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3861         buffer[count++] = cpu_to_le32(0x80000000);
3862         buffer[count++] = cpu_to_le32(0x80000000);
3863
3864         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3865                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3866                         if (sect->id == SECT_CONTEXT) {
3867                                 buffer[count++] =
3868                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3869                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3870                                                 PACKET3_SET_CONTEXT_REG_START);
3871                                 for (i = 0; i < ext->reg_count; i++)
3872                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3873                         } else {
3874                                 return;
3875                         }
3876                 }
3877         }
3878
3879         ctx_reg_offset =
3880                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3881         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3882         buffer[count++] = cpu_to_le32(ctx_reg_offset);
3883         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
3884
3885         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3886         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3887
3888         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3889         buffer[count++] = cpu_to_le32(0);
3890 }
3891
3892 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
3893 {
3894         /* clear state block */
3895         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
3896                         &adev->gfx.rlc.clear_state_gpu_addr,
3897                         (void **)&adev->gfx.rlc.cs_ptr);
3898
3899         /* jump table block */
3900         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
3901                         &adev->gfx.rlc.cp_table_gpu_addr,
3902                         (void **)&adev->gfx.rlc.cp_table_ptr);
3903 }
3904
3905 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
3906 {
3907         const struct cs_section_def *cs_data;
3908         int r;
3909
3910         adev->gfx.rlc.cs_data = gfx10_cs_data;
3911
3912         cs_data = adev->gfx.rlc.cs_data;
3913
3914         if (cs_data) {
3915                 /* init clear state block */
3916                 r = amdgpu_gfx_rlc_init_csb(adev);
3917                 if (r)
3918                         return r;
3919         }
3920
3921         /* init spm vmid with 0xf */
3922         if (adev->gfx.rlc.funcs->update_spm_vmid)
3923                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
3924
3925         return 0;
3926 }
3927
3928 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
3929 {
3930         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
3931         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
3932 }
3933
3934 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
3935 {
3936         int r;
3937
3938         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
3939
3940         amdgpu_gfx_graphics_queue_acquire(adev);
3941
3942         r = gfx_v10_0_init_microcode(adev);
3943         if (r)
3944                 DRM_ERROR("Failed to load gfx firmware!\n");
3945
3946         return r;
3947 }
3948
3949 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
3950 {
3951         int r;
3952         u32 *hpd;
3953         const __le32 *fw_data = NULL;
3954         unsigned fw_size;
3955         u32 *fw = NULL;
3956         size_t mec_hpd_size;
3957
3958         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
3959
3960         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3961
3962         /* take ownership of the relevant compute queues */
3963         amdgpu_gfx_compute_queue_acquire(adev);
3964         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
3965
3966         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
3967                                       AMDGPU_GEM_DOMAIN_GTT,
3968                                       &adev->gfx.mec.hpd_eop_obj,
3969                                       &adev->gfx.mec.hpd_eop_gpu_addr,
3970                                       (void **)&hpd);
3971         if (r) {
3972                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
3973                 gfx_v10_0_mec_fini(adev);
3974                 return r;
3975         }
3976
3977         memset(hpd, 0, mec_hpd_size);
3978
3979         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
3980         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3981
3982         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3983                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3984
3985                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3986                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3987                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3988
3989                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3990                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3991                                               &adev->gfx.mec.mec_fw_obj,
3992                                               &adev->gfx.mec.mec_fw_gpu_addr,
3993                                               (void **)&fw);
3994                 if (r) {
3995                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3996                         gfx_v10_0_mec_fini(adev);
3997                         return r;
3998                 }
3999
4000                 memcpy(fw, fw_data, fw_size);
4001
4002                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4003                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4004         }
4005
4006         return 0;
4007 }
4008
4009 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4010 {
4011         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4012                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4013                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4014         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4015 }
4016
4017 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4018                            uint32_t thread, uint32_t regno,
4019                            uint32_t num, uint32_t *out)
4020 {
4021         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4022                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4023                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4024                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4025                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4026         while (num--)
4027                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4028 }
4029
4030 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4031 {
4032         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4033          * field when performing a select_se_sh so it should be
4034          * zero here */
4035         WARN_ON(simd != 0);
4036
4037         /* type 2 wave data */
4038         dst[(*no_fields)++] = 2;
4039         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4040         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4041         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4042         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4043         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4044         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4045         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4046         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4047         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4048         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4049         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4050         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4051         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4052         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4053         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4054 }
4055
4056 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4057                                      uint32_t wave, uint32_t start,
4058                                      uint32_t size, uint32_t *dst)
4059 {
4060         WARN_ON(simd != 0);
4061
4062         wave_read_regs(
4063                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4064                 dst);
4065 }
4066
4067 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4068                                       uint32_t wave, uint32_t thread,
4069                                       uint32_t start, uint32_t size,
4070                                       uint32_t *dst)
4071 {
4072         wave_read_regs(
4073                 adev, wave, thread,
4074                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4075 }
4076
4077 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4078                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4079  {
4080        nv_grbm_select(adev, me, pipe, q, vm);
4081  }
4082
4083
4084 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4085         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4086         .select_se_sh = &gfx_v10_0_select_se_sh,
4087         .read_wave_data = &gfx_v10_0_read_wave_data,
4088         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4089         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4090         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4091 };
4092
4093 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4094 {
4095         u32 gb_addr_config;
4096
4097         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4098
4099         switch (adev->asic_type) {
4100         case CHIP_NAVI10:
4101         case CHIP_NAVI14:
4102         case CHIP_NAVI12:
4103                 adev->gfx.config.max_hw_contexts = 8;
4104                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4105                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4106                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4107                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4108                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4109                 break;
4110         case CHIP_SIENNA_CICHLID:
4111                 adev->gfx.config.max_hw_contexts = 8;
4112                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4113                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4114                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4115                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4116                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4117                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4118                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4119                 break;
4120         default:
4121                 BUG();
4122                 break;
4123         }
4124
4125         adev->gfx.config.gb_addr_config = gb_addr_config;
4126
4127         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4128                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4129                                       GB_ADDR_CONFIG, NUM_PIPES);
4130
4131         adev->gfx.config.max_tile_pipes =
4132                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4133
4134         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4135                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4136                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4137         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4138                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4139                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4140         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4141                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4142                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4143         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4144                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4145                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4146 }
4147
4148 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4149                                    int me, int pipe, int queue)
4150 {
4151         int r;
4152         struct amdgpu_ring *ring;
4153         unsigned int irq_type;
4154
4155         ring = &adev->gfx.gfx_ring[ring_id];
4156
4157         ring->me = me;
4158         ring->pipe = pipe;
4159         ring->queue = queue;
4160
4161         ring->ring_obj = NULL;
4162         ring->use_doorbell = true;
4163
4164         if (!ring_id)
4165                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4166         else
4167                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4168         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4169
4170         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4171         r = amdgpu_ring_init(adev, ring, 1024,
4172                              &adev->gfx.eop_irq, irq_type,
4173                              AMDGPU_RING_PRIO_DEFAULT);
4174         if (r)
4175                 return r;
4176         return 0;
4177 }
4178
4179 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4180                                        int mec, int pipe, int queue)
4181 {
4182         int r;
4183         unsigned irq_type;
4184         struct amdgpu_ring *ring;
4185         unsigned int hw_prio;
4186
4187         ring = &adev->gfx.compute_ring[ring_id];
4188
4189         /* mec0 is me1 */
4190         ring->me = mec + 1;
4191         ring->pipe = pipe;
4192         ring->queue = queue;
4193
4194         ring->ring_obj = NULL;
4195         ring->use_doorbell = true;
4196         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4197         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4198                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4199         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4200
4201         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4202                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4203                 + ring->pipe;
4204         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4205                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4206         /* type-2 packets are deprecated on MEC, use type-3 instead */
4207         r = amdgpu_ring_init(adev, ring, 1024,
4208                              &adev->gfx.eop_irq, irq_type, hw_prio);
4209         if (r)
4210                 return r;
4211
4212         return 0;
4213 }
4214
4215 static int gfx_v10_0_sw_init(void *handle)
4216 {
4217         int i, j, k, r, ring_id = 0;
4218         struct amdgpu_kiq *kiq;
4219         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4220
4221         switch (adev->asic_type) {
4222         case CHIP_NAVI10:
4223         case CHIP_NAVI14:
4224         case CHIP_NAVI12:
4225                 adev->gfx.me.num_me = 1;
4226                 adev->gfx.me.num_pipe_per_me = 1;
4227                 adev->gfx.me.num_queue_per_pipe = 1;
4228                 adev->gfx.mec.num_mec = 2;
4229                 adev->gfx.mec.num_pipe_per_mec = 4;
4230                 adev->gfx.mec.num_queue_per_pipe = 8;
4231                 break;
4232         case CHIP_SIENNA_CICHLID:
4233                 adev->gfx.me.num_me = 1;
4234                 adev->gfx.me.num_pipe_per_me = 1;
4235                 adev->gfx.me.num_queue_per_pipe = 1;
4236                 adev->gfx.mec.num_mec = 2;
4237                 adev->gfx.mec.num_pipe_per_mec = 4;
4238                 adev->gfx.mec.num_queue_per_pipe = 4;
4239                 break;
4240         default:
4241                 adev->gfx.me.num_me = 1;
4242                 adev->gfx.me.num_pipe_per_me = 1;
4243                 adev->gfx.me.num_queue_per_pipe = 1;
4244                 adev->gfx.mec.num_mec = 1;
4245                 adev->gfx.mec.num_pipe_per_mec = 4;
4246                 adev->gfx.mec.num_queue_per_pipe = 8;
4247                 break;
4248         }
4249
4250         /* KIQ event */
4251         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4252                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4253                               &adev->gfx.kiq.irq);
4254         if (r)
4255                 return r;
4256
4257         /* EOP Event */
4258         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4259                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4260                               &adev->gfx.eop_irq);
4261         if (r)
4262                 return r;
4263
4264         /* Privileged reg */
4265         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4266                               &adev->gfx.priv_reg_irq);
4267         if (r)
4268                 return r;
4269
4270         /* Privileged inst */
4271         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4272                               &adev->gfx.priv_inst_irq);
4273         if (r)
4274                 return r;
4275
4276         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4277
4278         gfx_v10_0_scratch_init(adev);
4279
4280         r = gfx_v10_0_me_init(adev);
4281         if (r)
4282                 return r;
4283
4284         r = gfx_v10_0_rlc_init(adev);
4285         if (r) {
4286                 DRM_ERROR("Failed to init rlc BOs!\n");
4287                 return r;
4288         }
4289
4290         r = gfx_v10_0_mec_init(adev);
4291         if (r) {
4292                 DRM_ERROR("Failed to init MEC BOs!\n");
4293                 return r;
4294         }
4295
4296         /* set up the gfx ring */
4297         for (i = 0; i < adev->gfx.me.num_me; i++) {
4298                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4299                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4300                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4301                                         continue;
4302
4303                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4304                                                             i, k, j);
4305                                 if (r)
4306                                         return r;
4307                                 ring_id++;
4308                         }
4309                 }
4310         }
4311
4312         ring_id = 0;
4313         /* set up the compute queues - allocate horizontally across pipes */
4314         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4315                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4316                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4317                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4318                                                                      j))
4319                                         continue;
4320
4321                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4322                                                                 i, k, j);
4323                                 if (r)
4324                                         return r;
4325
4326                                 ring_id++;
4327                         }
4328                 }
4329         }
4330
4331         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4332         if (r) {
4333                 DRM_ERROR("Failed to init KIQ BOs!\n");
4334                 return r;
4335         }
4336
4337         kiq = &adev->gfx.kiq;
4338         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4339         if (r)
4340                 return r;
4341
4342         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4343         if (r)
4344                 return r;
4345
4346         /* allocate visible FB for rlc auto-loading fw */
4347         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4348                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4349                 if (r)
4350                         return r;
4351         }
4352
4353         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4354
4355         gfx_v10_0_gpu_early_init(adev);
4356
4357         return 0;
4358 }
4359
4360 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4361 {
4362         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4363                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4364                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4365 }
4366
4367 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4368 {
4369         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4370                               &adev->gfx.ce.ce_fw_gpu_addr,
4371                               (void **)&adev->gfx.ce.ce_fw_ptr);
4372 }
4373
4374 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4375 {
4376         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4377                               &adev->gfx.me.me_fw_gpu_addr,
4378                               (void **)&adev->gfx.me.me_fw_ptr);
4379 }
4380
4381 static int gfx_v10_0_sw_fini(void *handle)
4382 {
4383         int i;
4384         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4385
4386         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4387                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4388         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4389                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4390
4391         amdgpu_gfx_mqd_sw_fini(adev);
4392         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4393         amdgpu_gfx_kiq_fini(adev);
4394
4395         gfx_v10_0_pfp_fini(adev);
4396         gfx_v10_0_ce_fini(adev);
4397         gfx_v10_0_me_fini(adev);
4398         gfx_v10_0_rlc_fini(adev);
4399         gfx_v10_0_mec_fini(adev);
4400
4401         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4402                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4403
4404         gfx_v10_0_free_microcode(adev);
4405
4406         return 0;
4407 }
4408
4409 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4410                                    u32 sh_num, u32 instance)
4411 {
4412         u32 data;
4413
4414         if (instance == 0xffffffff)
4415                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4416                                      INSTANCE_BROADCAST_WRITES, 1);
4417         else
4418                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4419                                      instance);
4420
4421         if (se_num == 0xffffffff)
4422                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4423                                      1);
4424         else
4425                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4426
4427         if (sh_num == 0xffffffff)
4428                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4429                                      1);
4430         else
4431                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4432
4433         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4434 }
4435
4436 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4437 {
4438         u32 data, mask;
4439
4440         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4441         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4442
4443         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4444         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4445
4446         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4447                                          adev->gfx.config.max_sh_per_se);
4448
4449         return (~data) & mask;
4450 }
4451
4452 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4453 {
4454         int i, j;
4455         u32 data;
4456         u32 active_rbs = 0;
4457         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4458                                         adev->gfx.config.max_sh_per_se;
4459
4460         mutex_lock(&adev->grbm_idx_mutex);
4461         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4462                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4463                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4464                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4465                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4466                                                rb_bitmap_width_per_sh);
4467                 }
4468         }
4469         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4470         mutex_unlock(&adev->grbm_idx_mutex);
4471
4472         adev->gfx.config.backend_enable_mask = active_rbs;
4473         adev->gfx.config.num_rbs = hweight32(active_rbs);
4474 }
4475
4476 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4477 {
4478         uint32_t num_sc;
4479         uint32_t enabled_rb_per_sh;
4480         uint32_t active_rb_bitmap;
4481         uint32_t num_rb_per_sc;
4482         uint32_t num_packer_per_sc;
4483         uint32_t pa_sc_tile_steering_override;
4484
4485         /* for ASICs that integrates GFX v10.3
4486          * pa_sc_tile_steering_override should be set to 0 */
4487         if (adev->asic_type == CHIP_SIENNA_CICHLID)
4488                 return 0;
4489
4490         /* init num_sc */
4491         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4492                         adev->gfx.config.num_sc_per_sh;
4493         /* init num_rb_per_sc */
4494         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4495         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4496         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4497         /* init num_packer_per_sc */
4498         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4499
4500         pa_sc_tile_steering_override = 0;
4501         pa_sc_tile_steering_override |=
4502                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4503                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4504         pa_sc_tile_steering_override |=
4505                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4506                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4507         pa_sc_tile_steering_override |=
4508                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4509                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4510
4511         return pa_sc_tile_steering_override;
4512 }
4513
4514 #define DEFAULT_SH_MEM_BASES    (0x6000)
4515 #define FIRST_COMPUTE_VMID      (8)
4516 #define LAST_COMPUTE_VMID       (16)
4517
4518 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4519 {
4520         int i;
4521         uint32_t sh_mem_bases;
4522
4523         /*
4524          * Configure apertures:
4525          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4526          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4527          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4528          */
4529         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4530
4531         mutex_lock(&adev->srbm_mutex);
4532         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
4533                 nv_grbm_select(adev, 0, 0, 0, i);
4534                 /* CP and shaders */
4535                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4536                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4537         }
4538         nv_grbm_select(adev, 0, 0, 0, 0);
4539         mutex_unlock(&adev->srbm_mutex);
4540
4541         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4542            acccess. These should be enabled by FW for target VMIDs. */
4543         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
4544                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4545                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4546                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4547                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4548         }
4549 }
4550
4551 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4552 {
4553         int vmid;
4554
4555         /*
4556          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4557          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4558          * the driver can enable them for graphics. VMID0 should maintain
4559          * access so that HWS firmware can save/restore entries.
4560          */
4561         for (vmid = 1; vmid < 16; vmid++) {
4562                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4563                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4564                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4565                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4566         }
4567 }
4568
4569
4570 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4571 {
4572         int i, j, k;
4573         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4574         u32 tmp, wgp_active_bitmap = 0;
4575         u32 gcrd_targets_disable_tcp = 0;
4576         u32 utcl_invreq_disable = 0;
4577         /*
4578          * GCRD_TARGETS_DISABLE field contains
4579          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4580          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4581          */
4582         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4583                 2 * max_wgp_per_sh + /* TCP */
4584                 max_wgp_per_sh + /* SQC */
4585                 4); /* GL1C */
4586         /*
4587          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4588          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4589          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4590          */
4591         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4592                 2 * max_wgp_per_sh + /* TCP */
4593                 2 * max_wgp_per_sh + /* SQC */
4594                 4 + /* RMI */
4595                 1); /* SQG */
4596
4597         if (adev->asic_type == CHIP_NAVI10 ||
4598             adev->asic_type == CHIP_NAVI14 ||
4599             adev->asic_type == CHIP_NAVI12) {
4600                 mutex_lock(&adev->grbm_idx_mutex);
4601                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4602                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4603                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4604                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4605                                 /*
4606                                  * Set corresponding TCP bits for the inactive WGPs in
4607                                  * GCRD_SA_TARGETS_DISABLE
4608                                  */
4609                                 gcrd_targets_disable_tcp = 0;
4610                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4611                                 utcl_invreq_disable = 0;
4612
4613                                 for (k = 0; k < max_wgp_per_sh; k++) {
4614                                         if (!(wgp_active_bitmap & (1 << k))) {
4615                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4616                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4617                                                         (3 << (2 * (max_wgp_per_sh + k)));
4618                                         }
4619                                 }
4620
4621                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4622                                 /* only override TCP & SQC bits */
4623                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4624                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4625                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4626
4627                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4628                                 /* only override TCP bits */
4629                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4630                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4631                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4632                         }
4633                 }
4634
4635                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4636                 mutex_unlock(&adev->grbm_idx_mutex);
4637         }
4638 }
4639
4640 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4641 {
4642         /* TCCs are global (not instanced). */
4643         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4644                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4645
4646         adev->gfx.config.tcc_disabled_mask =
4647                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4648                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4649 }
4650
4651 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4652 {
4653         u32 tmp;
4654         int i;
4655
4656         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4657
4658         gfx_v10_0_setup_rb(adev);
4659         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4660         gfx_v10_0_get_tcc_info(adev);
4661         adev->gfx.config.pa_sc_tile_steering_override =
4662                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4663
4664         /* XXX SH_MEM regs */
4665         /* where to put LDS, scratch, GPUVM in FSA64 space */
4666         mutex_lock(&adev->srbm_mutex);
4667         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4668                 nv_grbm_select(adev, 0, 0, 0, i);
4669                 /* CP and shaders */
4670                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4671                 if (i != 0) {
4672                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4673                                 (adev->gmc.private_aperture_start >> 48));
4674                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4675                                 (adev->gmc.shared_aperture_start >> 48));
4676                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4677                 }
4678         }
4679         nv_grbm_select(adev, 0, 0, 0, 0);
4680
4681         mutex_unlock(&adev->srbm_mutex);
4682
4683         gfx_v10_0_init_compute_vmid(adev);
4684         gfx_v10_0_init_gds_vmid(adev);
4685
4686 }
4687
4688 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4689                                                bool enable)
4690 {
4691         u32 tmp;
4692
4693         if (amdgpu_sriov_vf(adev))
4694                 return;
4695
4696         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4697
4698         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4699                             enable ? 1 : 0);
4700         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4701                             enable ? 1 : 0);
4702         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4703                             enable ? 1 : 0);
4704         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4705                             enable ? 1 : 0);
4706
4707         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4708 }
4709
4710 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4711 {
4712         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4713
4714         /* csib */
4715         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4716                          adev->gfx.rlc.clear_state_gpu_addr >> 32);
4717         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4718                          adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4719         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4720
4721         return 0;
4722 }
4723
4724 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4725 {
4726         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4727
4728         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4729         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4730 }
4731
4732 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4733 {
4734         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4735         udelay(50);
4736         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4737         udelay(50);
4738 }
4739
4740 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4741                                              bool enable)
4742 {
4743         uint32_t rlc_pg_cntl;
4744
4745         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4746
4747         if (!enable) {
4748                 /* RLC_PG_CNTL[23] = 0 (default)
4749                  * RLC will wait for handshake acks with SMU
4750                  * GFXOFF will be enabled
4751                  * RLC_PG_CNTL[23] = 1
4752                  * RLC will not issue any message to SMU
4753                  * hence no handshake between SMU & RLC
4754                  * GFXOFF will be disabled
4755                  */
4756                 rlc_pg_cntl |= 0x800000;
4757         } else
4758                 rlc_pg_cntl &= ~0x800000;
4759         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4760 }
4761
4762 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4763 {
4764         /* TODO: enable rlc & smu handshake until smu
4765          * and gfxoff feature works as expected */
4766         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4767                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4768
4769         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4770         udelay(50);
4771 }
4772
4773 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4774 {
4775         uint32_t tmp;
4776
4777         /* enable Save Restore Machine */
4778         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4779         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4780         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4781         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4782 }
4783
4784 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4785 {
4786         const struct rlc_firmware_header_v2_0 *hdr;
4787         const __le32 *fw_data;
4788         unsigned i, fw_size;
4789
4790         if (!adev->gfx.rlc_fw)
4791                 return -EINVAL;
4792
4793         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4794         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4795
4796         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4797                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4798         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4799
4800         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4801                      RLCG_UCODE_LOADING_START_ADDRESS);
4802
4803         for (i = 0; i < fw_size; i++)
4804                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4805                              le32_to_cpup(fw_data++));
4806
4807         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4808
4809         return 0;
4810 }
4811
4812 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4813 {
4814         int r;
4815
4816         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4817
4818                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4819                 if (r)
4820                         return r;
4821
4822                 gfx_v10_0_init_csb(adev);
4823
4824                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4825                         gfx_v10_0_rlc_enable_srm(adev);
4826         } else {
4827                 if (amdgpu_sriov_vf(adev)) {
4828                         gfx_v10_0_init_csb(adev);
4829                         return 0;
4830                 }
4831
4832                 adev->gfx.rlc.funcs->stop(adev);
4833
4834                 /* disable CG */
4835                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4836
4837                 /* disable PG */
4838                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4839
4840                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4841                         /* legacy rlc firmware loading */
4842                         r = gfx_v10_0_rlc_load_microcode(adev);
4843                         if (r)
4844                                 return r;
4845                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4846                         /* rlc backdoor autoload firmware */
4847                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4848                         if (r)
4849                                 return r;
4850                 }
4851
4852                 gfx_v10_0_init_csb(adev);
4853
4854                 adev->gfx.rlc.funcs->start(adev);
4855
4856                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4857                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4858                         if (r)
4859                                 return r;
4860                 }
4861         }
4862         return 0;
4863 }
4864
4865 static struct {
4866         FIRMWARE_ID     id;
4867         unsigned int    offset;
4868         unsigned int    size;
4869 } rlc_autoload_info[FIRMWARE_ID_MAX];
4870
4871 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
4872 {
4873         int ret;
4874         RLC_TABLE_OF_CONTENT *rlc_toc;
4875
4876         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
4877                                         AMDGPU_GEM_DOMAIN_GTT,
4878                                         &adev->gfx.rlc.rlc_toc_bo,
4879                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
4880                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
4881         if (ret) {
4882                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
4883                 return ret;
4884         }
4885
4886         /* Copy toc from psp sos fw to rlc toc buffer */
4887         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
4888
4889         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
4890         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
4891                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
4892                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
4893                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
4894                         /* Offset needs 4KB alignment */
4895                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
4896                 }
4897
4898                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
4899                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
4900                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
4901
4902                 rlc_toc++;
4903         }
4904
4905         return 0;
4906 }
4907
4908 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
4909 {
4910         uint32_t total_size = 0;
4911         FIRMWARE_ID id;
4912         int ret;
4913
4914         ret = gfx_v10_0_parse_rlc_toc(adev);
4915         if (ret) {
4916                 dev_err(adev->dev, "failed to parse rlc toc\n");
4917                 return 0;
4918         }
4919
4920         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
4921                 total_size += rlc_autoload_info[id].size;
4922
4923         /* In case the offset in rlc toc ucode is aligned */
4924         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
4925                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
4926                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
4927
4928         return total_size;
4929 }
4930
4931 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
4932 {
4933         int r;
4934         uint32_t total_size;
4935
4936         total_size = gfx_v10_0_calc_toc_total_size(adev);
4937
4938         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
4939                                       AMDGPU_GEM_DOMAIN_GTT,
4940                                       &adev->gfx.rlc.rlc_autoload_bo,
4941                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
4942                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
4943         if (r) {
4944                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
4945                 return r;
4946         }
4947
4948         return 0;
4949 }
4950
4951 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
4952 {
4953         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
4954                               &adev->gfx.rlc.rlc_toc_gpu_addr,
4955                               (void **)&adev->gfx.rlc.rlc_toc_buf);
4956         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
4957                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
4958                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
4959 }
4960
4961 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
4962                                                        FIRMWARE_ID id,
4963                                                        const void *fw_data,
4964                                                        uint32_t fw_size)
4965 {
4966         uint32_t toc_offset;
4967         uint32_t toc_fw_size;
4968         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
4969
4970         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
4971                 return;
4972
4973         toc_offset = rlc_autoload_info[id].offset;
4974         toc_fw_size = rlc_autoload_info[id].size;
4975
4976         if (fw_size == 0)
4977                 fw_size = toc_fw_size;
4978
4979         if (fw_size > toc_fw_size)
4980                 fw_size = toc_fw_size;
4981
4982         memcpy(ptr + toc_offset, fw_data, fw_size);
4983
4984         if (fw_size < toc_fw_size)
4985                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
4986 }
4987
4988 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
4989 {
4990         void *data;
4991         uint32_t size;
4992
4993         data = adev->gfx.rlc.rlc_toc_buf;
4994         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
4995
4996         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4997                                                    FIRMWARE_ID_RLC_TOC,
4998                                                    data, size);
4999 }
5000
5001 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5002 {
5003         const __le32 *fw_data;
5004         uint32_t fw_size;
5005         const struct gfx_firmware_header_v1_0 *cp_hdr;
5006         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5007
5008         /* pfp ucode */
5009         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5010                 adev->gfx.pfp_fw->data;
5011         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5012                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5013         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5014         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5015                                                    FIRMWARE_ID_CP_PFP,
5016                                                    fw_data, fw_size);
5017
5018         /* ce ucode */
5019         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5020                 adev->gfx.ce_fw->data;
5021         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5022                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5023         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5024         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5025                                                    FIRMWARE_ID_CP_CE,
5026                                                    fw_data, fw_size);
5027
5028         /* me ucode */
5029         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5030                 adev->gfx.me_fw->data;
5031         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5032                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5033         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5034         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5035                                                    FIRMWARE_ID_CP_ME,
5036                                                    fw_data, fw_size);
5037
5038         /* rlc ucode */
5039         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5040                 adev->gfx.rlc_fw->data;
5041         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5042                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5043         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5044         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5045                                                    FIRMWARE_ID_RLC_G_UCODE,
5046                                                    fw_data, fw_size);
5047
5048         /* mec1 ucode */
5049         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5050                 adev->gfx.mec_fw->data;
5051         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5052                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5053         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5054                 cp_hdr->jt_size * 4;
5055         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5056                                                    FIRMWARE_ID_CP_MEC,
5057                                                    fw_data, fw_size);
5058         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5059 }
5060
5061 /* Temporarily put sdma part here */
5062 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5063 {
5064         const __le32 *fw_data;
5065         uint32_t fw_size;
5066         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5067         int i;
5068
5069         for (i = 0; i < adev->sdma.num_instances; i++) {
5070                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5071                         adev->sdma.instance[i].fw->data;
5072                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5073                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5074                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5075
5076                 if (i == 0) {
5077                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5078                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5079                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5080                                 FIRMWARE_ID_SDMA0_JT,
5081                                 (uint32_t *)fw_data +
5082                                 sdma_hdr->jt_offset,
5083                                 sdma_hdr->jt_size * 4);
5084                 } else if (i == 1) {
5085                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5086                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5087                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5088                                 FIRMWARE_ID_SDMA1_JT,
5089                                 (uint32_t *)fw_data +
5090                                 sdma_hdr->jt_offset,
5091                                 sdma_hdr->jt_size * 4);
5092                 }
5093         }
5094 }
5095
5096 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5097 {
5098         uint32_t rlc_g_offset, rlc_g_size, tmp;
5099         uint64_t gpu_addr;
5100
5101         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5102         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5103         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5104
5105         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5106         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5107         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5108
5109         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5110         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5111         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5112
5113         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5114         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5115                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5116                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5117                 return -EINVAL;
5118         }
5119
5120         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5121         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5122                 DRM_ERROR("RLC ROM should halt itself\n");
5123                 return -EINVAL;
5124         }
5125
5126         return 0;
5127 }
5128
5129 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5130 {
5131         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5132         uint32_t tmp;
5133         int i;
5134         uint64_t addr;
5135
5136         /* Trigger an invalidation of the L1 instruction caches */
5137         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5138         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5139         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5140
5141         /* Wait for invalidation complete */
5142         for (i = 0; i < usec_timeout; i++) {
5143                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5144                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5145                         INVALIDATE_CACHE_COMPLETE))
5146                         break;
5147                 udelay(1);
5148         }
5149
5150         if (i >= usec_timeout) {
5151                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5152                 return -EINVAL;
5153         }
5154
5155         /* Program me ucode address into intruction cache address register */
5156         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5157                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5158         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5159                         lower_32_bits(addr) & 0xFFFFF000);
5160         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5161                         upper_32_bits(addr));
5162
5163         return 0;
5164 }
5165
5166 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5167 {
5168         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5169         uint32_t tmp;
5170         int i;
5171         uint64_t addr;
5172
5173         /* Trigger an invalidation of the L1 instruction caches */
5174         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5175         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5176         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5177
5178         /* Wait for invalidation complete */
5179         for (i = 0; i < usec_timeout; i++) {
5180                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5181                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5182                         INVALIDATE_CACHE_COMPLETE))
5183                         break;
5184                 udelay(1);
5185         }
5186
5187         if (i >= usec_timeout) {
5188                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5189                 return -EINVAL;
5190         }
5191
5192         /* Program ce ucode address into intruction cache address register */
5193         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5194                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5195         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5196                         lower_32_bits(addr) & 0xFFFFF000);
5197         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5198                         upper_32_bits(addr));
5199
5200         return 0;
5201 }
5202
5203 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5204 {
5205         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5206         uint32_t tmp;
5207         int i;
5208         uint64_t addr;
5209
5210         /* Trigger an invalidation of the L1 instruction caches */
5211         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5212         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5213         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5214
5215         /* Wait for invalidation complete */
5216         for (i = 0; i < usec_timeout; i++) {
5217                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5218                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5219                         INVALIDATE_CACHE_COMPLETE))
5220                         break;
5221                 udelay(1);
5222         }
5223
5224         if (i >= usec_timeout) {
5225                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5226                 return -EINVAL;
5227         }
5228
5229         /* Program pfp ucode address into intruction cache address register */
5230         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5231                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5232         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5233                         lower_32_bits(addr) & 0xFFFFF000);
5234         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5235                         upper_32_bits(addr));
5236
5237         return 0;
5238 }
5239
5240 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5241 {
5242         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5243         uint32_t tmp;
5244         int i;
5245         uint64_t addr;
5246
5247         /* Trigger an invalidation of the L1 instruction caches */
5248         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5249         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5250         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5251
5252         /* Wait for invalidation complete */
5253         for (i = 0; i < usec_timeout; i++) {
5254                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5255                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5256                         INVALIDATE_CACHE_COMPLETE))
5257                         break;
5258                 udelay(1);
5259         }
5260
5261         if (i >= usec_timeout) {
5262                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5263                 return -EINVAL;
5264         }
5265
5266         /* Program mec1 ucode address into intruction cache address register */
5267         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5268                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5269         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5270                         lower_32_bits(addr) & 0xFFFFF000);
5271         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5272                         upper_32_bits(addr));
5273
5274         return 0;
5275 }
5276
5277 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5278 {
5279         uint32_t cp_status;
5280         uint32_t bootload_status;
5281         int i, r;
5282
5283         for (i = 0; i < adev->usec_timeout; i++) {
5284                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5285                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5286                 if ((cp_status == 0) &&
5287                     (REG_GET_FIELD(bootload_status,
5288                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5289                         break;
5290                 }
5291                 udelay(1);
5292         }
5293
5294         if (i >= adev->usec_timeout) {
5295                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5296                 return -ETIMEDOUT;
5297         }
5298
5299         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5300                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5301                 if (r)
5302                         return r;
5303
5304                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5305                 if (r)
5306                         return r;
5307
5308                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5309                 if (r)
5310                         return r;
5311
5312                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5313                 if (r)
5314                         return r;
5315         }
5316
5317         return 0;
5318 }
5319
5320 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5321 {
5322         int i;
5323         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5324
5325         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5326         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5327         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5328         WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5329
5330         for (i = 0; i < adev->usec_timeout; i++) {
5331                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5332                         break;
5333                 udelay(1);
5334         }
5335
5336         if (i >= adev->usec_timeout)
5337                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5338
5339         return 0;
5340 }
5341
5342 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5343 {
5344         int r;
5345         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5346         const __le32 *fw_data;
5347         unsigned i, fw_size;
5348         uint32_t tmp;
5349         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5350
5351         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5352                 adev->gfx.pfp_fw->data;
5353
5354         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5355
5356         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5357                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5358         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5359
5360         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5361                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5362                                       &adev->gfx.pfp.pfp_fw_obj,
5363                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5364                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5365         if (r) {
5366                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5367                 gfx_v10_0_pfp_fini(adev);
5368                 return r;
5369         }
5370
5371         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5372
5373         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5374         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5375
5376         /* Trigger an invalidation of the L1 instruction caches */
5377         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5378         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5379         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5380
5381         /* Wait for invalidation complete */
5382         for (i = 0; i < usec_timeout; i++) {
5383                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5384                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5385                         INVALIDATE_CACHE_COMPLETE))
5386                         break;
5387                 udelay(1);
5388         }
5389
5390         if (i >= usec_timeout) {
5391                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5392                 return -EINVAL;
5393         }
5394
5395         if (amdgpu_emu_mode == 1)
5396                 adev->nbio.funcs->hdp_flush(adev, NULL);
5397
5398         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5399         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5400         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5401         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5402         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5403         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5404         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5405                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5406         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5407                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5408
5409         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5410
5411         for (i = 0; i < pfp_hdr->jt_size; i++)
5412                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5413                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5414
5415         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5416
5417         return 0;
5418 }
5419
5420 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5421 {
5422         int r;
5423         const struct gfx_firmware_header_v1_0 *ce_hdr;
5424         const __le32 *fw_data;
5425         unsigned i, fw_size;
5426         uint32_t tmp;
5427         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5428
5429         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5430                 adev->gfx.ce_fw->data;
5431
5432         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5433
5434         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5435                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5436         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5437
5438         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5439                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5440                                       &adev->gfx.ce.ce_fw_obj,
5441                                       &adev->gfx.ce.ce_fw_gpu_addr,
5442                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5443         if (r) {
5444                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5445                 gfx_v10_0_ce_fini(adev);
5446                 return r;
5447         }
5448
5449         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5450
5451         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5452         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5453
5454         /* Trigger an invalidation of the L1 instruction caches */
5455         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5456         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5457         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5458
5459         /* Wait for invalidation complete */
5460         for (i = 0; i < usec_timeout; i++) {
5461                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5462                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5463                         INVALIDATE_CACHE_COMPLETE))
5464                         break;
5465                 udelay(1);
5466         }
5467
5468         if (i >= usec_timeout) {
5469                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5470                 return -EINVAL;
5471         }
5472
5473         if (amdgpu_emu_mode == 1)
5474                 adev->nbio.funcs->hdp_flush(adev, NULL);
5475
5476         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5477         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5478         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5479         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5480         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5481         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5482                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5483         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5484                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5485
5486         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5487
5488         for (i = 0; i < ce_hdr->jt_size; i++)
5489                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5490                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5491
5492         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5493
5494         return 0;
5495 }
5496
5497 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5498 {
5499         int r;
5500         const struct gfx_firmware_header_v1_0 *me_hdr;
5501         const __le32 *fw_data;
5502         unsigned i, fw_size;
5503         uint32_t tmp;
5504         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5505
5506         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5507                 adev->gfx.me_fw->data;
5508
5509         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5510
5511         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5512                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5513         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5514
5515         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5516                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5517                                       &adev->gfx.me.me_fw_obj,
5518                                       &adev->gfx.me.me_fw_gpu_addr,
5519                                       (void **)&adev->gfx.me.me_fw_ptr);
5520         if (r) {
5521                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5522                 gfx_v10_0_me_fini(adev);
5523                 return r;
5524         }
5525
5526         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5527
5528         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5529         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5530
5531         /* Trigger an invalidation of the L1 instruction caches */
5532         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5533         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5534         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5535
5536         /* Wait for invalidation complete */
5537         for (i = 0; i < usec_timeout; i++) {
5538                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5539                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5540                         INVALIDATE_CACHE_COMPLETE))
5541                         break;
5542                 udelay(1);
5543         }
5544
5545         if (i >= usec_timeout) {
5546                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5547                 return -EINVAL;
5548         }
5549
5550         if (amdgpu_emu_mode == 1)
5551                 adev->nbio.funcs->hdp_flush(adev, NULL);
5552
5553         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5554         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5555         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5556         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5557         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5558         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5559                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5560         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5561                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5562
5563         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5564
5565         for (i = 0; i < me_hdr->jt_size; i++)
5566                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5567                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5568
5569         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5570
5571         return 0;
5572 }
5573
5574 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5575 {
5576         int r;
5577
5578         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5579                 return -EINVAL;
5580
5581         gfx_v10_0_cp_gfx_enable(adev, false);
5582
5583         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5584         if (r) {
5585                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5586                 return r;
5587         }
5588
5589         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5590         if (r) {
5591                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5592                 return r;
5593         }
5594
5595         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5596         if (r) {
5597                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5598                 return r;
5599         }
5600
5601         return 0;
5602 }
5603
5604 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5605 {
5606         struct amdgpu_ring *ring;
5607         const struct cs_section_def *sect = NULL;
5608         const struct cs_extent_def *ext = NULL;
5609         int r, i;
5610         int ctx_reg_offset;
5611
5612         /* init the CP */
5613         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5614                      adev->gfx.config.max_hw_contexts - 1);
5615         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5616
5617         gfx_v10_0_cp_gfx_enable(adev, true);
5618
5619         ring = &adev->gfx.gfx_ring[0];
5620         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5621         if (r) {
5622                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5623                 return r;
5624         }
5625
5626         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5627         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5628
5629         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5630         amdgpu_ring_write(ring, 0x80000000);
5631         amdgpu_ring_write(ring, 0x80000000);
5632
5633         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5634                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5635                         if (sect->id == SECT_CONTEXT) {
5636                                 amdgpu_ring_write(ring,
5637                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5638                                                           ext->reg_count));
5639                                 amdgpu_ring_write(ring, ext->reg_index -
5640                                                   PACKET3_SET_CONTEXT_REG_START);
5641                                 for (i = 0; i < ext->reg_count; i++)
5642                                         amdgpu_ring_write(ring, ext->extent[i]);
5643                         }
5644                 }
5645         }
5646
5647         ctx_reg_offset =
5648                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5649         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5650         amdgpu_ring_write(ring, ctx_reg_offset);
5651         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5652
5653         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5654         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5655
5656         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5657         amdgpu_ring_write(ring, 0);
5658
5659         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5660         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5661         amdgpu_ring_write(ring, 0x8000);
5662         amdgpu_ring_write(ring, 0x8000);
5663
5664         amdgpu_ring_commit(ring);
5665
5666         /* submit cs packet to copy state 0 to next available state */
5667         if (adev->gfx.num_gfx_rings > 1) {
5668                 /* maximum supported gfx ring is 2 */
5669                 ring = &adev->gfx.gfx_ring[1];
5670                 r = amdgpu_ring_alloc(ring, 2);
5671                 if (r) {
5672                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5673                         return r;
5674                 }
5675
5676                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5677                 amdgpu_ring_write(ring, 0);
5678
5679                 amdgpu_ring_commit(ring);
5680         }
5681         return 0;
5682 }
5683
5684 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5685                                          CP_PIPE_ID pipe)
5686 {
5687         u32 tmp;
5688
5689         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5690         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5691
5692         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5693 }
5694
5695 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5696                                           struct amdgpu_ring *ring)
5697 {
5698         u32 tmp;
5699
5700         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5701         if (ring->use_doorbell) {
5702                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5703                                     DOORBELL_OFFSET, ring->doorbell_index);
5704                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5705                                     DOORBELL_EN, 1);
5706         } else {
5707                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5708                                     DOORBELL_EN, 0);
5709         }
5710         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5711         switch (adev->asic_type) {
5712         case CHIP_SIENNA_CICHLID:
5713                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5714                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5715                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5716
5717                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5718                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5719                 break;
5720         default:
5721                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5722                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5723                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5724
5725                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5726                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5727                 break;
5728         }
5729 }
5730
5731 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5732 {
5733         struct amdgpu_ring *ring;
5734         u32 tmp;
5735         u32 rb_bufsz;
5736         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5737         u32 i;
5738
5739         /* Set the write pointer delay */
5740         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5741
5742         /* set the RB to use vmid 0 */
5743         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5744
5745         /* Init gfx ring 0 for pipe 0 */
5746         mutex_lock(&adev->srbm_mutex);
5747         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5748
5749         /* Set ring buffer size */
5750         ring = &adev->gfx.gfx_ring[0];
5751         rb_bufsz = order_base_2(ring->ring_size / 8);
5752         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5753         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5754 #ifdef __BIG_ENDIAN
5755         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5756 #endif
5757         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5758
5759         /* Initialize the ring buffer's write pointers */
5760         ring->wptr = 0;
5761         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5762         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5763
5764         /* set the wb address wether it's enabled or not */
5765         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5766         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5767         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5768                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5769
5770         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5771         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5772                      lower_32_bits(wptr_gpu_addr));
5773         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5774                      upper_32_bits(wptr_gpu_addr));
5775
5776         mdelay(1);
5777         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5778
5779         rb_addr = ring->gpu_addr >> 8;
5780         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5781         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5782
5783         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5784
5785         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5786         mutex_unlock(&adev->srbm_mutex);
5787
5788         /* Init gfx ring 1 for pipe 1 */
5789         if (adev->gfx.num_gfx_rings > 1) {
5790                 mutex_lock(&adev->srbm_mutex);
5791                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5792                 /* maximum supported gfx ring is 2 */
5793                 ring = &adev->gfx.gfx_ring[1];
5794                 rb_bufsz = order_base_2(ring->ring_size / 8);
5795                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5796                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5797                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5798                 /* Initialize the ring buffer's write pointers */
5799                 ring->wptr = 0;
5800                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5801                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5802                 /* Set the wb address wether it's enabled or not */
5803                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5804                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5805                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5806                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5807                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5808                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5809                              lower_32_bits(wptr_gpu_addr));
5810                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5811                              upper_32_bits(wptr_gpu_addr));
5812
5813                 mdelay(1);
5814                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5815
5816                 rb_addr = ring->gpu_addr >> 8;
5817                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5818                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5819                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5820
5821                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5822                 mutex_unlock(&adev->srbm_mutex);
5823         }
5824         /* Switch to pipe 0 */
5825         mutex_lock(&adev->srbm_mutex);
5826         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5827         mutex_unlock(&adev->srbm_mutex);
5828
5829         /* start the ring */
5830         gfx_v10_0_cp_gfx_start(adev);
5831
5832         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5833                 ring = &adev->gfx.gfx_ring[i];
5834                 ring->sched.ready = true;
5835         }
5836
5837         return 0;
5838 }
5839
5840 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5841 {
5842         if (enable) {
5843                 switch (adev->asic_type) {
5844                 case CHIP_SIENNA_CICHLID:
5845                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5846                         break;
5847                 default:
5848                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5849                         break;
5850                 }
5851         } else {
5852                 switch (adev->asic_type) {
5853                 case CHIP_SIENNA_CICHLID:
5854                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
5855                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5856                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5857                         break;
5858                 default:
5859                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
5860                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5861                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5862                         break;
5863                 }
5864                 adev->gfx.kiq.ring.sched.ready = false;
5865         }
5866         udelay(50);
5867 }
5868
5869 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
5870 {
5871         const struct gfx_firmware_header_v1_0 *mec_hdr;
5872         const __le32 *fw_data;
5873         unsigned i;
5874         u32 tmp;
5875         u32 usec_timeout = 50000; /* Wait for 50 ms */
5876
5877         if (!adev->gfx.mec_fw)
5878                 return -EINVAL;
5879
5880         gfx_v10_0_cp_compute_enable(adev, false);
5881
5882         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
5883         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
5884
5885         fw_data = (const __le32 *)
5886                 (adev->gfx.mec_fw->data +
5887                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
5888
5889         /* Trigger an invalidation of the L1 instruction caches */
5890         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5891         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5892         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5893
5894         /* Wait for invalidation complete */
5895         for (i = 0; i < usec_timeout; i++) {
5896                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5897                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5898                                        INVALIDATE_CACHE_COMPLETE))
5899                         break;
5900                 udelay(1);
5901         }
5902
5903         if (i >= usec_timeout) {
5904                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5905                 return -EINVAL;
5906         }
5907
5908         if (amdgpu_emu_mode == 1)
5909                 adev->nbio.funcs->hdp_flush(adev, NULL);
5910
5911         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
5912         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5913         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
5914         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5915         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
5916
5917         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
5918                      0xFFFFF000);
5919         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5920                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
5921
5922         /* MEC1 */
5923         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
5924
5925         for (i = 0; i < mec_hdr->jt_size; i++)
5926                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
5927                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
5928
5929         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
5930
5931         /*
5932          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
5933          * different microcode than MEC1.
5934          */
5935
5936         return 0;
5937 }
5938
5939 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
5940 {
5941         uint32_t tmp;
5942         struct amdgpu_device *adev = ring->adev;
5943
5944         /* tell RLC which is KIQ queue */
5945         switch (adev->asic_type) {
5946         case CHIP_SIENNA_CICHLID:
5947                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
5948                 tmp &= 0xffffff00;
5949                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5950                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
5951                 tmp |= 0x80;
5952                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
5953                 break;
5954         default:
5955                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
5956                 tmp &= 0xffffff00;
5957                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5958                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
5959                 tmp |= 0x80;
5960                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
5961                 break;
5962         }
5963 }
5964
5965 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
5966 {
5967         struct amdgpu_device *adev = ring->adev;
5968         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
5969         uint64_t hqd_gpu_addr, wb_gpu_addr;
5970         uint32_t tmp;
5971         uint32_t rb_bufsz;
5972
5973         /* set up gfx hqd wptr */
5974         mqd->cp_gfx_hqd_wptr = 0;
5975         mqd->cp_gfx_hqd_wptr_hi = 0;
5976
5977         /* set the pointer to the MQD */
5978         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
5979         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
5980
5981         /* set up mqd control */
5982         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
5983         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
5984         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
5985         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
5986         mqd->cp_gfx_mqd_control = tmp;
5987
5988         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
5989         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
5990         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
5991         mqd->cp_gfx_hqd_vmid = 0;
5992
5993         /* set up default queue priority level
5994          * 0x0 = low priority, 0x1 = high priority */
5995         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
5996         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
5997         mqd->cp_gfx_hqd_queue_priority = tmp;
5998
5999         /* set up time quantum */
6000         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6001         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6002         mqd->cp_gfx_hqd_quantum = tmp;
6003
6004         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6005         hqd_gpu_addr = ring->gpu_addr >> 8;
6006         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6007         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6008
6009         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6010         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6011         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6012         mqd->cp_gfx_hqd_rptr_addr_hi =
6013                 upper_32_bits(wb_gpu_addr) & 0xffff;
6014
6015         /* set up rb_wptr_poll addr */
6016         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6017         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6018         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6019
6020         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6021         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6022         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6023         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6024         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6025 #ifdef __BIG_ENDIAN
6026         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6027 #endif
6028         mqd->cp_gfx_hqd_cntl = tmp;
6029
6030         /* set up cp_doorbell_control */
6031         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6032         if (ring->use_doorbell) {
6033                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6034                                     DOORBELL_OFFSET, ring->doorbell_index);
6035                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6036                                     DOORBELL_EN, 1);
6037         } else
6038                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6039                                     DOORBELL_EN, 0);
6040         mqd->cp_rb_doorbell_control = tmp;
6041
6042         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6043         ring->wptr = 0;
6044         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6045
6046         /* active the queue */
6047         mqd->cp_gfx_hqd_active = 1;
6048
6049         return 0;
6050 }
6051
6052 #ifdef BRING_UP_DEBUG
6053 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6054 {
6055         struct amdgpu_device *adev = ring->adev;
6056         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6057
6058         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6059         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6060         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6061
6062         /* set GFX_MQD_BASE */
6063         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6064         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6065
6066         /* set GFX_MQD_CONTROL */
6067         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6068
6069         /* set GFX_HQD_VMID to 0 */
6070         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6071
6072         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6073                         mqd->cp_gfx_hqd_queue_priority);
6074         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6075
6076         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6077         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6078         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6079
6080         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6081         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6082         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6083
6084         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6085         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6086
6087         /* set RB_WPTR_POLL_ADDR */
6088         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6089         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6090
6091         /* set RB_DOORBELL_CONTROL */
6092         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6093
6094         /* active the queue */
6095         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6096
6097         return 0;
6098 }
6099 #endif
6100
6101 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6102 {
6103         struct amdgpu_device *adev = ring->adev;
6104         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6105         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6106
6107         if (!adev->in_gpu_reset && !adev->in_suspend) {
6108                 memset((void *)mqd, 0, sizeof(*mqd));
6109                 mutex_lock(&adev->srbm_mutex);
6110                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6111                 gfx_v10_0_gfx_mqd_init(ring);
6112 #ifdef BRING_UP_DEBUG
6113                 gfx_v10_0_gfx_queue_init_register(ring);
6114 #endif
6115                 nv_grbm_select(adev, 0, 0, 0, 0);
6116                 mutex_unlock(&adev->srbm_mutex);
6117                 if (adev->gfx.me.mqd_backup[mqd_idx])
6118                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6119         } else if (adev->in_gpu_reset) {
6120                 /* reset mqd with the backup copy */
6121                 if (adev->gfx.me.mqd_backup[mqd_idx])
6122                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6123                 /* reset the ring */
6124                 ring->wptr = 0;
6125                 adev->wb.wb[ring->wptr_offs] = 0;
6126                 amdgpu_ring_clear_ring(ring);
6127 #ifdef BRING_UP_DEBUG
6128                 mutex_lock(&adev->srbm_mutex);
6129                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6130                 gfx_v10_0_gfx_queue_init_register(ring);
6131                 nv_grbm_select(adev, 0, 0, 0, 0);
6132                 mutex_unlock(&adev->srbm_mutex);
6133 #endif
6134         } else {
6135                 amdgpu_ring_clear_ring(ring);
6136         }
6137
6138         return 0;
6139 }
6140
6141 #ifndef BRING_UP_DEBUG
6142 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6143 {
6144         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6145         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6146         int r, i;
6147
6148         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6149                 return -EINVAL;
6150
6151         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6152                                         adev->gfx.num_gfx_rings);
6153         if (r) {
6154                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6155                 return r;
6156         }
6157
6158         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6159                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6160
6161         return amdgpu_ring_test_helper(kiq_ring);
6162 }
6163 #endif
6164
6165 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6166 {
6167         int r, i;
6168         struct amdgpu_ring *ring;
6169
6170         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6171                 ring = &adev->gfx.gfx_ring[i];
6172
6173                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6174                 if (unlikely(r != 0))
6175                         goto done;
6176
6177                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6178                 if (!r) {
6179                         r = gfx_v10_0_gfx_init_queue(ring);
6180                         amdgpu_bo_kunmap(ring->mqd_obj);
6181                         ring->mqd_ptr = NULL;
6182                 }
6183                 amdgpu_bo_unreserve(ring->mqd_obj);
6184                 if (r)
6185                         goto done;
6186         }
6187 #ifndef BRING_UP_DEBUG
6188         r = gfx_v10_0_kiq_enable_kgq(adev);
6189         if (r)
6190                 goto done;
6191 #endif
6192         r = gfx_v10_0_cp_gfx_start(adev);
6193         if (r)
6194                 goto done;
6195
6196         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6197                 ring = &adev->gfx.gfx_ring[i];
6198                 ring->sched.ready = true;
6199         }
6200 done:
6201         return r;
6202 }
6203
6204 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6205 {
6206         struct amdgpu_device *adev = ring->adev;
6207
6208         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6209                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6210                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6211                         mqd->cp_hqd_queue_priority =
6212                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6213                 }
6214         }
6215 }
6216
6217 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6218 {
6219         struct amdgpu_device *adev = ring->adev;
6220         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6221         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6222         uint32_t tmp;
6223
6224         mqd->header = 0xC0310800;
6225         mqd->compute_pipelinestat_enable = 0x00000001;
6226         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6227         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6228         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6229         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6230         mqd->compute_misc_reserved = 0x00000003;
6231
6232         eop_base_addr = ring->eop_gpu_addr >> 8;
6233         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6234         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6235
6236         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6237         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6238         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6239                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6240
6241         mqd->cp_hqd_eop_control = tmp;
6242
6243         /* enable doorbell? */
6244         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6245
6246         if (ring->use_doorbell) {
6247                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6248                                     DOORBELL_OFFSET, ring->doorbell_index);
6249                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6250                                     DOORBELL_EN, 1);
6251                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6252                                     DOORBELL_SOURCE, 0);
6253                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6254                                     DOORBELL_HIT, 0);
6255         } else {
6256                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6257                                     DOORBELL_EN, 0);
6258         }
6259
6260         mqd->cp_hqd_pq_doorbell_control = tmp;
6261
6262         /* disable the queue if it's active */
6263         ring->wptr = 0;
6264         mqd->cp_hqd_dequeue_request = 0;
6265         mqd->cp_hqd_pq_rptr = 0;
6266         mqd->cp_hqd_pq_wptr_lo = 0;
6267         mqd->cp_hqd_pq_wptr_hi = 0;
6268
6269         /* set the pointer to the MQD */
6270         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6271         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6272
6273         /* set MQD vmid to 0 */
6274         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6275         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6276         mqd->cp_mqd_control = tmp;
6277
6278         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6279         hqd_gpu_addr = ring->gpu_addr >> 8;
6280         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6281         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6282
6283         /* set up the HQD, this is similar to CP_RB0_CNTL */
6284         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6285         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6286                             (order_base_2(ring->ring_size / 4) - 1));
6287         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6288                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6289 #ifdef __BIG_ENDIAN
6290         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6291 #endif
6292         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6293         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6294         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6295         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6296         mqd->cp_hqd_pq_control = tmp;
6297
6298         /* set the wb address whether it's enabled or not */
6299         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6300         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6301         mqd->cp_hqd_pq_rptr_report_addr_hi =
6302                 upper_32_bits(wb_gpu_addr) & 0xffff;
6303
6304         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6305         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6306         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6307         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6308
6309         tmp = 0;
6310         /* enable the doorbell if requested */
6311         if (ring->use_doorbell) {
6312                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6313                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6314                                 DOORBELL_OFFSET, ring->doorbell_index);
6315
6316                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6317                                     DOORBELL_EN, 1);
6318                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6319                                     DOORBELL_SOURCE, 0);
6320                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6321                                     DOORBELL_HIT, 0);
6322         }
6323
6324         mqd->cp_hqd_pq_doorbell_control = tmp;
6325
6326         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6327         ring->wptr = 0;
6328         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6329
6330         /* set the vmid for the queue */
6331         mqd->cp_hqd_vmid = 0;
6332
6333         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6334         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6335         mqd->cp_hqd_persistent_state = tmp;
6336
6337         /* set MIN_IB_AVAIL_SIZE */
6338         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6339         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6340         mqd->cp_hqd_ib_control = tmp;
6341
6342         /* set static priority for a compute queue/ring */
6343         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6344
6345         /* map_queues packet doesn't need activate the queue,
6346          * so only kiq need set this field.
6347          */
6348         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6349                 mqd->cp_hqd_active = 1;
6350
6351         return 0;
6352 }
6353
6354 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6355 {
6356         struct amdgpu_device *adev = ring->adev;
6357         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6358         int j;
6359
6360         /* disable wptr polling */
6361         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6362
6363         /* write the EOP addr */
6364         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6365                mqd->cp_hqd_eop_base_addr_lo);
6366         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6367                mqd->cp_hqd_eop_base_addr_hi);
6368
6369         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6370         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6371                mqd->cp_hqd_eop_control);
6372
6373         /* enable doorbell? */
6374         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6375                mqd->cp_hqd_pq_doorbell_control);
6376
6377         /* disable the queue if it's active */
6378         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6379                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6380                 for (j = 0; j < adev->usec_timeout; j++) {
6381                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6382                                 break;
6383                         udelay(1);
6384                 }
6385                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6386                        mqd->cp_hqd_dequeue_request);
6387                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6388                        mqd->cp_hqd_pq_rptr);
6389                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6390                        mqd->cp_hqd_pq_wptr_lo);
6391                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6392                        mqd->cp_hqd_pq_wptr_hi);
6393         }
6394
6395         /* set the pointer to the MQD */
6396         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6397                mqd->cp_mqd_base_addr_lo);
6398         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6399                mqd->cp_mqd_base_addr_hi);
6400
6401         /* set MQD vmid to 0 */
6402         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6403                mqd->cp_mqd_control);
6404
6405         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6406         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6407                mqd->cp_hqd_pq_base_lo);
6408         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6409                mqd->cp_hqd_pq_base_hi);
6410
6411         /* set up the HQD, this is similar to CP_RB0_CNTL */
6412         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6413                mqd->cp_hqd_pq_control);
6414
6415         /* set the wb address whether it's enabled or not */
6416         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6417                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6418         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6419                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6420
6421         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6422         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6423                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6424         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6425                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6426
6427         /* enable the doorbell if requested */
6428         if (ring->use_doorbell) {
6429                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6430                         (adev->doorbell_index.kiq * 2) << 2);
6431                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6432                         (adev->doorbell_index.userqueue_end * 2) << 2);
6433         }
6434
6435         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6436                mqd->cp_hqd_pq_doorbell_control);
6437
6438         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6439         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6440                mqd->cp_hqd_pq_wptr_lo);
6441         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6442                mqd->cp_hqd_pq_wptr_hi);
6443
6444         /* set the vmid for the queue */
6445         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6446
6447         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6448                mqd->cp_hqd_persistent_state);
6449
6450         /* activate the queue */
6451         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6452                mqd->cp_hqd_active);
6453
6454         if (ring->use_doorbell)
6455                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6456
6457         return 0;
6458 }
6459
6460 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6461 {
6462         struct amdgpu_device *adev = ring->adev;
6463         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6464         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6465
6466         gfx_v10_0_kiq_setting(ring);
6467
6468         if (adev->in_gpu_reset) { /* for GPU_RESET case */
6469                 /* reset MQD to a clean status */
6470                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6471                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6472
6473                 /* reset ring buffer */
6474                 ring->wptr = 0;
6475                 amdgpu_ring_clear_ring(ring);
6476
6477                 mutex_lock(&adev->srbm_mutex);
6478                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6479                 gfx_v10_0_kiq_init_register(ring);
6480                 nv_grbm_select(adev, 0, 0, 0, 0);
6481                 mutex_unlock(&adev->srbm_mutex);
6482         } else {
6483                 memset((void *)mqd, 0, sizeof(*mqd));
6484                 mutex_lock(&adev->srbm_mutex);
6485                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6486                 gfx_v10_0_compute_mqd_init(ring);
6487                 gfx_v10_0_kiq_init_register(ring);
6488                 nv_grbm_select(adev, 0, 0, 0, 0);
6489                 mutex_unlock(&adev->srbm_mutex);
6490
6491                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6492                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6493         }
6494
6495         return 0;
6496 }
6497
6498 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6499 {
6500         struct amdgpu_device *adev = ring->adev;
6501         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6502         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6503
6504         if (!adev->in_gpu_reset && !adev->in_suspend) {
6505                 memset((void *)mqd, 0, sizeof(*mqd));
6506                 mutex_lock(&adev->srbm_mutex);
6507                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6508                 gfx_v10_0_compute_mqd_init(ring);
6509                 nv_grbm_select(adev, 0, 0, 0, 0);
6510                 mutex_unlock(&adev->srbm_mutex);
6511
6512                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6513                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6514         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
6515                 /* reset MQD to a clean status */
6516                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6517                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6518
6519                 /* reset ring buffer */
6520                 ring->wptr = 0;
6521                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6522                 amdgpu_ring_clear_ring(ring);
6523         } else {
6524                 amdgpu_ring_clear_ring(ring);
6525         }
6526
6527         return 0;
6528 }
6529
6530 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6531 {
6532         struct amdgpu_ring *ring;
6533         int r;
6534
6535         ring = &adev->gfx.kiq.ring;
6536
6537         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6538         if (unlikely(r != 0))
6539                 return r;
6540
6541         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6542         if (unlikely(r != 0))
6543                 return r;
6544
6545         gfx_v10_0_kiq_init_queue(ring);
6546         amdgpu_bo_kunmap(ring->mqd_obj);
6547         ring->mqd_ptr = NULL;
6548         amdgpu_bo_unreserve(ring->mqd_obj);
6549         ring->sched.ready = true;
6550         return 0;
6551 }
6552
6553 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6554 {
6555         struct amdgpu_ring *ring = NULL;
6556         int r = 0, i;
6557
6558         gfx_v10_0_cp_compute_enable(adev, true);
6559
6560         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6561                 ring = &adev->gfx.compute_ring[i];
6562
6563                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6564                 if (unlikely(r != 0))
6565                         goto done;
6566                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6567                 if (!r) {
6568                         r = gfx_v10_0_kcq_init_queue(ring);
6569                         amdgpu_bo_kunmap(ring->mqd_obj);
6570                         ring->mqd_ptr = NULL;
6571                 }
6572                 amdgpu_bo_unreserve(ring->mqd_obj);
6573                 if (r)
6574                         goto done;
6575         }
6576
6577         r = amdgpu_gfx_enable_kcq(adev);
6578 done:
6579         return r;
6580 }
6581
6582 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6583 {
6584         int r, i;
6585         struct amdgpu_ring *ring;
6586
6587         if (!(adev->flags & AMD_IS_APU))
6588                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6589
6590         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6591                 /* legacy firmware loading */
6592                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6593                 if (r)
6594                         return r;
6595
6596                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6597                 if (r)
6598                         return r;
6599         }
6600
6601         r = gfx_v10_0_kiq_resume(adev);
6602         if (r)
6603                 return r;
6604
6605         r = gfx_v10_0_kcq_resume(adev);
6606         if (r)
6607                 return r;
6608
6609         if (!amdgpu_async_gfx_ring) {
6610                 r = gfx_v10_0_cp_gfx_resume(adev);
6611                 if (r)
6612                         return r;
6613         } else {
6614                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6615                 if (r)
6616                         return r;
6617         }
6618
6619         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6620                 ring = &adev->gfx.gfx_ring[i];
6621                 r = amdgpu_ring_test_helper(ring);
6622                 if (r)
6623                         return r;
6624         }
6625
6626         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6627                 ring = &adev->gfx.compute_ring[i];
6628                 r = amdgpu_ring_test_helper(ring);
6629                 if (r)
6630                         return r;
6631         }
6632
6633         return 0;
6634 }
6635
6636 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6637 {
6638         gfx_v10_0_cp_gfx_enable(adev, enable);
6639         gfx_v10_0_cp_compute_enable(adev, enable);
6640 }
6641
6642 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6643 {
6644         uint32_t data, pattern = 0xDEADBEEF;
6645
6646         /* check if mmVGT_ESGS_RING_SIZE_UMD
6647          * has been remapped to mmVGT_ESGS_RING_SIZE */
6648         switch (adev->asic_type) {
6649         case CHIP_SIENNA_CICHLID:
6650                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6651                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6652                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6653
6654                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6655                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6656                         return true;
6657                 } else {
6658                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6659                         return false;
6660                 }
6661                 break;
6662         default:
6663                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6664                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6665                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6666
6667                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6668                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6669                         return true;
6670                 } else {
6671                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6672                         return false;
6673                 }
6674                 break;
6675         }
6676 }
6677
6678 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6679 {
6680         uint32_t data;
6681
6682         /* initialize cam_index to 0
6683          * index will auto-inc after each data writting */
6684         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6685
6686         switch (adev->asic_type) {
6687         case CHIP_SIENNA_CICHLID:
6688                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6689                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6690                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6691                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6692                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6693                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6694                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6695
6696                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6697                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6698                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6699                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6700                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6701                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6702                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6703
6704                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6705                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6706                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6707                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6708                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6709                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6710                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6711
6712                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6713                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6714                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6715                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6716                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6717                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6718                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6719
6720                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6721                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6722                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6723                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6724                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6725                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6726                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6727
6728                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6729                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6730                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6731                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6732                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6733                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6734                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6735
6736                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6737                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6738                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6739                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6740                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6741                 break;
6742         default:
6743                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6744                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6745                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6746                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6747                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6748                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6749                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6750
6751                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6752                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6753                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6754                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6755                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6756                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6757                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6758
6759                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6760                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6761                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6762                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6763                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6764                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6765                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6766
6767                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6768                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6769                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6770                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6771                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6772                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6773                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6774
6775                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6776                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6777                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6778                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6779                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6780                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6781                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6782
6783                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6784                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6785                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6786                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6787                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6788                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6789                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6790
6791                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6792                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6793                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6794                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6795                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6796                 break;
6797         }
6798
6799         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6800         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6801 }
6802
6803 static int gfx_v10_0_hw_init(void *handle)
6804 {
6805         int r;
6806         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6807
6808         if (!amdgpu_emu_mode)
6809                 gfx_v10_0_init_golden_registers(adev);
6810
6811         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6812                 /**
6813                  * For gfx 10, rlc firmware loading relies on smu firmware is
6814                  * loaded firstly, so in direct type, it has to load smc ucode
6815                  * here before rlc.
6816                  */
6817                 if (adev->smu.ppt_funcs != NULL) {
6818                         r = smu_load_microcode(&adev->smu);
6819                         if (r)
6820                                 return r;
6821
6822                         r = smu_check_fw_status(&adev->smu);
6823                         if (r) {
6824                                 pr_err("SMC firmware status is not correct\n");
6825                                 return r;
6826                         }
6827                 }
6828         }
6829
6830         /* if GRBM CAM not remapped, set up the remapping */
6831         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6832                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6833
6834         gfx_v10_0_constants_init(adev);
6835
6836         r = gfx_v10_0_rlc_resume(adev);
6837         if (r)
6838                 return r;
6839
6840         /*
6841          * init golden registers and rlc resume may override some registers,
6842          * reconfig them here
6843          */
6844         gfx_v10_0_tcp_harvest(adev);
6845
6846         r = gfx_v10_0_cp_resume(adev);
6847         if (r)
6848                 return r;
6849
6850         return r;
6851 }
6852
6853 #ifndef BRING_UP_DEBUG
6854 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
6855 {
6856         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6857         struct amdgpu_ring *kiq_ring = &kiq->ring;
6858         int i;
6859
6860         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
6861                 return -EINVAL;
6862
6863         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
6864                                         adev->gfx.num_gfx_rings))
6865                 return -ENOMEM;
6866
6867         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6868                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
6869                                            PREEMPT_QUEUES, 0, 0);
6870
6871         return amdgpu_ring_test_helper(kiq_ring);
6872 }
6873 #endif
6874
6875 static int gfx_v10_0_hw_fini(void *handle)
6876 {
6877         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6878         int r;
6879         uint32_t tmp;
6880
6881         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
6882         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
6883 #ifndef BRING_UP_DEBUG
6884         if (amdgpu_async_gfx_ring) {
6885                 r = gfx_v10_0_kiq_disable_kgq(adev);
6886                 if (r)
6887                         DRM_ERROR("KGQ disable failed\n");
6888         }
6889 #endif
6890         if (amdgpu_gfx_disable_kcq(adev))
6891                 DRM_ERROR("KCQ disable failed\n");
6892         if (amdgpu_sriov_vf(adev)) {
6893                 gfx_v10_0_cp_gfx_enable(adev, false);
6894                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
6895                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6896                 tmp &= 0xffffff00;
6897                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6898
6899                 return 0;
6900         }
6901         gfx_v10_0_cp_enable(adev, false);
6902         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6903
6904         return 0;
6905 }
6906
6907 static int gfx_v10_0_suspend(void *handle)
6908 {
6909         return gfx_v10_0_hw_fini(handle);
6910 }
6911
6912 static int gfx_v10_0_resume(void *handle)
6913 {
6914         return gfx_v10_0_hw_init(handle);
6915 }
6916
6917 static bool gfx_v10_0_is_idle(void *handle)
6918 {
6919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6920
6921         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
6922                                 GRBM_STATUS, GUI_ACTIVE))
6923                 return false;
6924         else
6925                 return true;
6926 }
6927
6928 static int gfx_v10_0_wait_for_idle(void *handle)
6929 {
6930         unsigned i;
6931         u32 tmp;
6932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6933
6934         for (i = 0; i < adev->usec_timeout; i++) {
6935                 /* read MC_STATUS */
6936                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
6937                         GRBM_STATUS__GUI_ACTIVE_MASK;
6938
6939                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
6940                         return 0;
6941                 udelay(1);
6942         }
6943         return -ETIMEDOUT;
6944 }
6945
6946 static int gfx_v10_0_soft_reset(void *handle)
6947 {
6948         u32 grbm_soft_reset = 0;
6949         u32 tmp;
6950         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6951
6952         /* GRBM_STATUS */
6953         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
6954         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
6955                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
6956                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
6957                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
6958                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
6959                    | GRBM_STATUS__BCI_BUSY_MASK)) {
6960                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6961                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
6962                                                 1);
6963                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6964                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
6965                                                 1);
6966         }
6967
6968         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
6969                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6970                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
6971                                                 1);
6972         }
6973
6974         /* GRBM_STATUS2 */
6975         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
6976         switch (adev->asic_type) {
6977         case CHIP_SIENNA_CICHLID:
6978                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
6979                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6980                                                         GRBM_SOFT_RESET,
6981                                                         SOFT_RESET_RLC,
6982                                                         1);
6983                 break;
6984         default:
6985                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
6986                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6987                                                         GRBM_SOFT_RESET,
6988                                                         SOFT_RESET_RLC,
6989                                                         1);
6990                 break;
6991         }
6992
6993         if (grbm_soft_reset) {
6994                 /* stop the rlc */
6995                 gfx_v10_0_rlc_stop(adev);
6996
6997                 /* Disable GFX parsing/prefetching */
6998                 gfx_v10_0_cp_gfx_enable(adev, false);
6999
7000                 /* Disable MEC parsing/prefetching */
7001                 gfx_v10_0_cp_compute_enable(adev, false);
7002
7003                 if (grbm_soft_reset) {
7004                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7005                         tmp |= grbm_soft_reset;
7006                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7007                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7008                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7009
7010                         udelay(50);
7011
7012                         tmp &= ~grbm_soft_reset;
7013                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7014                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7015                 }
7016
7017                 /* Wait a little for things to settle down */
7018                 udelay(50);
7019         }
7020         return 0;
7021 }
7022
7023 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7024 {
7025         uint64_t clock;
7026
7027         amdgpu_gfx_off_ctrl(adev, false);
7028         mutex_lock(&adev->gfx.gpu_clock_mutex);
7029         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7030                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7031         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7032         amdgpu_gfx_off_ctrl(adev, true);
7033         return clock;
7034 }
7035
7036 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7037                                            uint32_t vmid,
7038                                            uint32_t gds_base, uint32_t gds_size,
7039                                            uint32_t gws_base, uint32_t gws_size,
7040                                            uint32_t oa_base, uint32_t oa_size)
7041 {
7042         struct amdgpu_device *adev = ring->adev;
7043
7044         /* GDS Base */
7045         gfx_v10_0_write_data_to_reg(ring, 0, false,
7046                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7047                                     gds_base);
7048
7049         /* GDS Size */
7050         gfx_v10_0_write_data_to_reg(ring, 0, false,
7051                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7052                                     gds_size);
7053
7054         /* GWS */
7055         gfx_v10_0_write_data_to_reg(ring, 0, false,
7056                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7057                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7058
7059         /* OA */
7060         gfx_v10_0_write_data_to_reg(ring, 0, false,
7061                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7062                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7063 }
7064
7065 static int gfx_v10_0_early_init(void *handle)
7066 {
7067         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7068
7069         switch (adev->asic_type) {
7070         case CHIP_NAVI10:
7071         case CHIP_NAVI14:
7072         case CHIP_NAVI12:
7073                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7074                 break;
7075         case CHIP_SIENNA_CICHLID:
7076                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7077                 break;
7078         default:
7079                 break;
7080         }
7081
7082         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
7083
7084         gfx_v10_0_set_kiq_pm4_funcs(adev);
7085         gfx_v10_0_set_ring_funcs(adev);
7086         gfx_v10_0_set_irq_funcs(adev);
7087         gfx_v10_0_set_gds_init(adev);
7088         gfx_v10_0_set_rlc_funcs(adev);
7089
7090         return 0;
7091 }
7092
7093 static int gfx_v10_0_late_init(void *handle)
7094 {
7095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7096         int r;
7097
7098         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7099         if (r)
7100                 return r;
7101
7102         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7103         if (r)
7104                 return r;
7105
7106         return 0;
7107 }
7108
7109 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7110 {
7111         uint32_t rlc_cntl;
7112
7113         /* if RLC is not enabled, do nothing */
7114         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7115         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7116 }
7117
7118 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7119 {
7120         uint32_t data;
7121         unsigned i;
7122
7123         data = RLC_SAFE_MODE__CMD_MASK;
7124         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7125
7126         switch (adev->asic_type) {
7127         case CHIP_SIENNA_CICHLID:
7128                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7129
7130                 /* wait for RLC_SAFE_MODE */
7131                 for (i = 0; i < adev->usec_timeout; i++) {
7132                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7133                                            RLC_SAFE_MODE, CMD))
7134                                 break;
7135                         udelay(1);
7136                 }
7137                 break;
7138         default:
7139                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7140
7141                 /* wait for RLC_SAFE_MODE */
7142                 for (i = 0; i < adev->usec_timeout; i++) {
7143                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7144                                            RLC_SAFE_MODE, CMD))
7145                                 break;
7146                         udelay(1);
7147                 }
7148                 break;
7149         }
7150 }
7151
7152 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7153 {
7154         uint32_t data;
7155
7156         data = RLC_SAFE_MODE__CMD_MASK;
7157         switch (adev->asic_type) {
7158         case CHIP_SIENNA_CICHLID:
7159                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7160                 break;
7161         default:
7162                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7163                 break;
7164         }
7165 }
7166
7167 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7168                                                       bool enable)
7169 {
7170         uint32_t data, def;
7171
7172         /* It is disabled by HW by default */
7173         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7174                 /* 0 - Disable some blocks' MGCG */
7175                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7176                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7177                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7178                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7179
7180                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7181                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7182                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7183                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7184                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7185
7186                 /* only for Vega10 & Raven1 */
7187                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
7188
7189                 if (def != data)
7190                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7191
7192                 /* MGLS is a global flag to control all MGLS in GFX */
7193                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7194                         /* 2 - RLC memory Light sleep */
7195                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7196                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7197                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7198                                 if (def != data)
7199                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7200                         }
7201                         /* 3 - CP memory Light sleep */
7202                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7203                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7204                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7205                                 if (def != data)
7206                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7207                         }
7208                 }
7209         } else {
7210                 /* 1 - MGCG_OVERRIDE */
7211                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7212                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7213                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7214                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7215                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7216                 if (def != data)
7217                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7218
7219                 /* 2 - disable MGLS in CP */
7220                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7221                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7222                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7223                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7224                 }
7225
7226                 /* 3 - disable MGLS in RLC */
7227                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7228                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7229                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7230                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7231                 }
7232
7233         }
7234 }
7235
7236 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7237                                            bool enable)
7238 {
7239         uint32_t data, def;
7240
7241         /* Enable 3D CGCG/CGLS */
7242         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7243                 /* write cmd to clear cgcg/cgls ov */
7244                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7245                 /* unset CGCG override */
7246                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7247                 /* update CGCG and CGLS override bits */
7248                 if (def != data)
7249                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7250                 /* enable 3Dcgcg FSM(0x0000363f) */
7251                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7252                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7253                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7254                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7255                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7256                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7257                 if (def != data)
7258                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7259
7260                 /* set IDLE_POLL_COUNT(0x00900100) */
7261                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7262                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7263                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7264                 if (def != data)
7265                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7266         } else {
7267                 /* Disable CGCG/CGLS */
7268                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7269                 /* disable cgcg, cgls should be disabled */
7270                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7271                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7272                 /* disable cgcg and cgls in FSM */
7273                 if (def != data)
7274                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7275         }
7276 }
7277
7278 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7279                                                       bool enable)
7280 {
7281         uint32_t def, data;
7282
7283         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7284                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7285                 /* unset CGCG override */
7286                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7287                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7288                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7289                 else
7290                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7291                 /* update CGCG and CGLS override bits */
7292                 if (def != data)
7293                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7294
7295                 /* enable cgcg FSM(0x0000363F) */
7296                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7297                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7298                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7299                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7300                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7301                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7302                 if (def != data)
7303                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7304
7305                 /* set IDLE_POLL_COUNT(0x00900100) */
7306                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7307                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7308                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7309                 if (def != data)
7310                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7311         } else {
7312                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7313                 /* reset CGCG/CGLS bits */
7314                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7315                 /* disable cgcg and cgls in FSM */
7316                 if (def != data)
7317                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7318         }
7319 }
7320
7321 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7322                                             bool enable)
7323 {
7324         amdgpu_gfx_rlc_enter_safe_mode(adev);
7325
7326         if (enable) {
7327                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7328                  * ===  MGCG + MGLS ===
7329                  */
7330                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7331                 /* ===  CGCG /CGLS for GFX 3D Only === */
7332                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7333                 /* ===  CGCG + CGLS === */
7334                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7335         } else {
7336                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7337                  * ===  CGCG + CGLS ===
7338                  */
7339                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7340                 /* ===  CGCG /CGLS for GFX 3D Only === */
7341                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7342                 /* ===  MGCG + MGLS === */
7343                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7344         }
7345
7346         if (adev->cg_flags &
7347             (AMD_CG_SUPPORT_GFX_MGCG |
7348              AMD_CG_SUPPORT_GFX_CGLS |
7349              AMD_CG_SUPPORT_GFX_CGCG |
7350              AMD_CG_SUPPORT_GFX_CGLS |
7351              AMD_CG_SUPPORT_GFX_3D_CGCG |
7352              AMD_CG_SUPPORT_GFX_3D_CGLS))
7353                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7354
7355         amdgpu_gfx_rlc_exit_safe_mode(adev);
7356
7357         return 0;
7358 }
7359
7360 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7361 {
7362         u32 reg, data;
7363
7364         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7365         if (amdgpu_sriov_is_pp_one_vf(adev))
7366                 data = RREG32_NO_KIQ(reg);
7367         else
7368                 data = RREG32(reg);
7369
7370         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7371         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7372
7373         if (amdgpu_sriov_is_pp_one_vf(adev))
7374                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7375         else
7376                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7377 }
7378
7379 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7380                                         uint32_t offset,
7381                                         struct soc15_reg_rlcg *entries, int arr_size)
7382 {
7383         int i;
7384         uint32_t reg;
7385
7386         if (!entries)
7387                 return false;
7388
7389         for (i = 0; i < arr_size; i++) {
7390                 const struct soc15_reg_rlcg *entry;
7391
7392                 entry = &entries[i];
7393                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7394                 if (offset == reg)
7395                         return true;
7396         }
7397
7398         return false;
7399 }
7400
7401 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7402 {
7403         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7404 }
7405
7406 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7407         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7408         .set_safe_mode = gfx_v10_0_set_safe_mode,
7409         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7410         .init = gfx_v10_0_rlc_init,
7411         .get_csb_size = gfx_v10_0_get_csb_size,
7412         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7413         .resume = gfx_v10_0_rlc_resume,
7414         .stop = gfx_v10_0_rlc_stop,
7415         .reset = gfx_v10_0_rlc_reset,
7416         .start = gfx_v10_0_rlc_start,
7417         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7418 };
7419
7420 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7421         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7422         .set_safe_mode = gfx_v10_0_set_safe_mode,
7423         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7424         .init = gfx_v10_0_rlc_init,
7425         .get_csb_size = gfx_v10_0_get_csb_size,
7426         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7427         .resume = gfx_v10_0_rlc_resume,
7428         .stop = gfx_v10_0_rlc_stop,
7429         .reset = gfx_v10_0_rlc_reset,
7430         .start = gfx_v10_0_rlc_start,
7431         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7432         .rlcg_wreg = gfx_v10_rlcg_wreg,
7433         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7434 };
7435
7436 static int gfx_v10_0_set_powergating_state(void *handle,
7437                                           enum amd_powergating_state state)
7438 {
7439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7440         bool enable = (state == AMD_PG_STATE_GATE);
7441
7442         if (amdgpu_sriov_vf(adev))
7443                 return 0;
7444
7445         switch (adev->asic_type) {
7446         case CHIP_NAVI10:
7447         case CHIP_NAVI14:
7448         case CHIP_NAVI12:
7449         case CHIP_SIENNA_CICHLID:
7450                 amdgpu_gfx_off_ctrl(adev, enable);
7451                 break;
7452         default:
7453                 break;
7454         }
7455         return 0;
7456 }
7457
7458 static int gfx_v10_0_set_clockgating_state(void *handle,
7459                                           enum amd_clockgating_state state)
7460 {
7461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7462
7463         if (amdgpu_sriov_vf(adev))
7464                 return 0;
7465
7466         switch (adev->asic_type) {
7467         case CHIP_NAVI10:
7468         case CHIP_NAVI14:
7469         case CHIP_NAVI12:
7470         case CHIP_SIENNA_CICHLID:
7471                 gfx_v10_0_update_gfx_clock_gating(adev,
7472                                                  state == AMD_CG_STATE_GATE);
7473                 break;
7474         default:
7475                 break;
7476         }
7477         return 0;
7478 }
7479
7480 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7481 {
7482         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7483         int data;
7484
7485         /* AMD_CG_SUPPORT_GFX_MGCG */
7486         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7487         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7488                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7489
7490         /* AMD_CG_SUPPORT_GFX_CGCG */
7491         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7492         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7493                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7494
7495         /* AMD_CG_SUPPORT_GFX_CGLS */
7496         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7497                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7498
7499         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7500         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7501         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7502                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7503
7504         /* AMD_CG_SUPPORT_GFX_CP_LS */
7505         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7506         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7507                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7508
7509         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7510         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7511         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7512                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7513
7514         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7515         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7516                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7517 }
7518
7519 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7520 {
7521         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7522 }
7523
7524 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7525 {
7526         struct amdgpu_device *adev = ring->adev;
7527         u64 wptr;
7528
7529         /* XXX check if swapping is necessary on BE */
7530         if (ring->use_doorbell) {
7531                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7532         } else {
7533                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7534                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7535         }
7536
7537         return wptr;
7538 }
7539
7540 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7541 {
7542         struct amdgpu_device *adev = ring->adev;
7543
7544         if (ring->use_doorbell) {
7545                 /* XXX check if swapping is necessary on BE */
7546                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7547                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7548         } else {
7549                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7550                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7551         }
7552 }
7553
7554 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7555 {
7556         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7557 }
7558
7559 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7560 {
7561         u64 wptr;
7562
7563         /* XXX check if swapping is necessary on BE */
7564         if (ring->use_doorbell)
7565                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7566         else
7567                 BUG();
7568         return wptr;
7569 }
7570
7571 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7572 {
7573         struct amdgpu_device *adev = ring->adev;
7574
7575         /* XXX check if swapping is necessary on BE */
7576         if (ring->use_doorbell) {
7577                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7578                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7579         } else {
7580                 BUG(); /* only DOORBELL method supported on gfx10 now */
7581         }
7582 }
7583
7584 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7585 {
7586         struct amdgpu_device *adev = ring->adev;
7587         u32 ref_and_mask, reg_mem_engine;
7588         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7589
7590         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7591                 switch (ring->me) {
7592                 case 1:
7593                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7594                         break;
7595                 case 2:
7596                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7597                         break;
7598                 default:
7599                         return;
7600                 }
7601                 reg_mem_engine = 0;
7602         } else {
7603                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7604                 reg_mem_engine = 1; /* pfp */
7605         }
7606
7607         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7608                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7609                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7610                                ref_and_mask, ref_and_mask, 0x20);
7611 }
7612
7613 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7614                                        struct amdgpu_job *job,
7615                                        struct amdgpu_ib *ib,
7616                                        uint32_t flags)
7617 {
7618         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7619         u32 header, control = 0;
7620
7621         if (ib->flags & AMDGPU_IB_FLAG_CE)
7622                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7623         else
7624                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7625
7626         control |= ib->length_dw | (vmid << 24);
7627
7628         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7629                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7630
7631                 if (flags & AMDGPU_IB_PREEMPTED)
7632                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7633
7634                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7635                         gfx_v10_0_ring_emit_de_meta(ring,
7636                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7637         }
7638
7639         amdgpu_ring_write(ring, header);
7640         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7641         amdgpu_ring_write(ring,
7642 #ifdef __BIG_ENDIAN
7643                 (2 << 0) |
7644 #endif
7645                 lower_32_bits(ib->gpu_addr));
7646         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7647         amdgpu_ring_write(ring, control);
7648 }
7649
7650 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7651                                            struct amdgpu_job *job,
7652                                            struct amdgpu_ib *ib,
7653                                            uint32_t flags)
7654 {
7655         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7656         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7657
7658         /* Currently, there is a high possibility to get wave ID mismatch
7659          * between ME and GDS, leading to a hw deadlock, because ME generates
7660          * different wave IDs than the GDS expects. This situation happens
7661          * randomly when at least 5 compute pipes use GDS ordered append.
7662          * The wave IDs generated by ME are also wrong after suspend/resume.
7663          * Those are probably bugs somewhere else in the kernel driver.
7664          *
7665          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7666          * GDS to 0 for this ring (me/pipe).
7667          */
7668         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7669                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7670                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7671                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7672         }
7673
7674         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7675         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7676         amdgpu_ring_write(ring,
7677 #ifdef __BIG_ENDIAN
7678                                 (2 << 0) |
7679 #endif
7680                                 lower_32_bits(ib->gpu_addr));
7681         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7682         amdgpu_ring_write(ring, control);
7683 }
7684
7685 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7686                                      u64 seq, unsigned flags)
7687 {
7688         struct amdgpu_device *adev = ring->adev;
7689         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7690         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7691
7692         /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
7693         if (adev->pdev->device == 0x50)
7694                 int_sel = false;
7695
7696         /* RELEASE_MEM - flush caches, send int */
7697         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7698         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7699                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7700                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7701                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7702                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7703                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7704                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7705         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7706                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7707
7708         /*
7709          * the address should be Qword aligned if 64bit write, Dword
7710          * aligned if only send 32bit data low (discard data high)
7711          */
7712         if (write64bit)
7713                 BUG_ON(addr & 0x7);
7714         else
7715                 BUG_ON(addr & 0x3);
7716         amdgpu_ring_write(ring, lower_32_bits(addr));
7717         amdgpu_ring_write(ring, upper_32_bits(addr));
7718         amdgpu_ring_write(ring, lower_32_bits(seq));
7719         amdgpu_ring_write(ring, upper_32_bits(seq));
7720         amdgpu_ring_write(ring, 0);
7721 }
7722
7723 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7724 {
7725         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7726         uint32_t seq = ring->fence_drv.sync_seq;
7727         uint64_t addr = ring->fence_drv.gpu_addr;
7728
7729         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7730                                upper_32_bits(addr), seq, 0xffffffff, 4);
7731 }
7732
7733 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7734                                          unsigned vmid, uint64_t pd_addr)
7735 {
7736         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7737
7738         /* compute doesn't have PFP */
7739         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7740                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7741                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7742                 amdgpu_ring_write(ring, 0x0);
7743         }
7744 }
7745
7746 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7747                                           u64 seq, unsigned int flags)
7748 {
7749         struct amdgpu_device *adev = ring->adev;
7750
7751         /* we only allocate 32bit for each seq wb address */
7752         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7753
7754         /* write fence seq to the "addr" */
7755         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7756         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7757                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7758         amdgpu_ring_write(ring, lower_32_bits(addr));
7759         amdgpu_ring_write(ring, upper_32_bits(addr));
7760         amdgpu_ring_write(ring, lower_32_bits(seq));
7761
7762         if (flags & AMDGPU_FENCE_FLAG_INT) {
7763                 /* set register to trigger INT */
7764                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7765                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7766                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7767                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7768                 amdgpu_ring_write(ring, 0);
7769                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7770         }
7771 }
7772
7773 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7774 {
7775         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7776         amdgpu_ring_write(ring, 0);
7777 }
7778
7779 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7780                                          uint32_t flags)
7781 {
7782         uint32_t dw2 = 0;
7783
7784         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7785                 gfx_v10_0_ring_emit_ce_meta(ring,
7786                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7787
7788         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7789         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7790                 /* set load_global_config & load_global_uconfig */
7791                 dw2 |= 0x8001;
7792                 /* set load_cs_sh_regs */
7793                 dw2 |= 0x01000000;
7794                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7795                 dw2 |= 0x10002;
7796
7797                 /* set load_ce_ram if preamble presented */
7798                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7799                         dw2 |= 0x10000000;
7800         } else {
7801                 /* still load_ce_ram if this is the first time preamble presented
7802                  * although there is no context switch happens.
7803                  */
7804                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7805                         dw2 |= 0x10000000;
7806         }
7807
7808         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7809         amdgpu_ring_write(ring, dw2);
7810         amdgpu_ring_write(ring, 0);
7811 }
7812
7813 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7814 {
7815         unsigned ret;
7816
7817         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7818         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7819         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7820         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7821         ret = ring->wptr & ring->buf_mask;
7822         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7823
7824         return ret;
7825 }
7826
7827 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7828 {
7829         unsigned cur;
7830         BUG_ON(offset > ring->buf_mask);
7831         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7832
7833         cur = (ring->wptr - 1) & ring->buf_mask;
7834         if (likely(cur > offset))
7835                 ring->ring[offset] = cur - offset;
7836         else
7837                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7838 }
7839
7840 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7841 {
7842         int i, r = 0;
7843         struct amdgpu_device *adev = ring->adev;
7844         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7845         struct amdgpu_ring *kiq_ring = &kiq->ring;
7846
7847         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7848                 return -EINVAL;
7849
7850         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
7851                 return -ENOMEM;
7852
7853         /* assert preemption condition */
7854         amdgpu_ring_set_preempt_cond_exec(ring, false);
7855
7856         /* assert IB preemption, emit the trailing fence */
7857         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
7858                                    ring->trail_fence_gpu_addr,
7859                                    ++ring->trail_seq);
7860         amdgpu_ring_commit(kiq_ring);
7861
7862         /* poll the trailing fence */
7863         for (i = 0; i < adev->usec_timeout; i++) {
7864                 if (ring->trail_seq ==
7865                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
7866                         break;
7867                 udelay(1);
7868         }
7869
7870         if (i >= adev->usec_timeout) {
7871                 r = -EINVAL;
7872                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
7873         }
7874
7875         /* deassert preemption condition */
7876         amdgpu_ring_set_preempt_cond_exec(ring, true);
7877         return r;
7878 }
7879
7880 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
7881 {
7882         struct amdgpu_device *adev = ring->adev;
7883         struct v10_ce_ib_state ce_payload = {0};
7884         uint64_t csa_addr;
7885         int cnt;
7886
7887         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
7888         csa_addr = amdgpu_csa_vaddr(ring->adev);
7889
7890         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7891         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7892                                  WRITE_DATA_DST_SEL(8) |
7893                                  WR_CONFIRM) |
7894                                  WRITE_DATA_CACHE_POLICY(0));
7895         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7896                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7897         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7898                               offsetof(struct v10_gfx_meta_data, ce_payload)));
7899
7900         if (resume)
7901                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7902                                            offsetof(struct v10_gfx_meta_data,
7903                                                     ce_payload),
7904                                            sizeof(ce_payload) >> 2);
7905         else
7906                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
7907                                            sizeof(ce_payload) >> 2);
7908 }
7909
7910 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
7911 {
7912         struct amdgpu_device *adev = ring->adev;
7913         struct v10_de_ib_state de_payload = {0};
7914         uint64_t csa_addr, gds_addr;
7915         int cnt;
7916
7917         csa_addr = amdgpu_csa_vaddr(ring->adev);
7918         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
7919                          PAGE_SIZE);
7920         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
7921         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
7922
7923         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
7924         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7925         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7926                                  WRITE_DATA_DST_SEL(8) |
7927                                  WR_CONFIRM) |
7928                                  WRITE_DATA_CACHE_POLICY(0));
7929         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7930                               offsetof(struct v10_gfx_meta_data, de_payload)));
7931         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7932                               offsetof(struct v10_gfx_meta_data, de_payload)));
7933
7934         if (resume)
7935                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7936                                            offsetof(struct v10_gfx_meta_data,
7937                                                     de_payload),
7938                                            sizeof(de_payload) >> 2);
7939         else
7940                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
7941                                            sizeof(de_payload) >> 2);
7942 }
7943
7944 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
7945                                     bool secure)
7946 {
7947         uint32_t v = secure ? FRAME_TMZ : 0;
7948
7949         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
7950         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
7951 }
7952
7953 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
7954                                      uint32_t reg_val_offs)
7955 {
7956         struct amdgpu_device *adev = ring->adev;
7957
7958         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
7959         amdgpu_ring_write(ring, 0 |     /* src: register*/
7960                                 (5 << 8) |      /* dst: memory */
7961                                 (1 << 20));     /* write confirm */
7962         amdgpu_ring_write(ring, reg);
7963         amdgpu_ring_write(ring, 0);
7964         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
7965                                 reg_val_offs * 4));
7966         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
7967                                 reg_val_offs * 4));
7968 }
7969
7970 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
7971                                    uint32_t val)
7972 {
7973         uint32_t cmd = 0;
7974
7975         switch (ring->funcs->type) {
7976         case AMDGPU_RING_TYPE_GFX:
7977                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
7978                 break;
7979         case AMDGPU_RING_TYPE_KIQ:
7980                 cmd = (1 << 16); /* no inc addr */
7981                 break;
7982         default:
7983                 cmd = WR_CONFIRM;
7984                 break;
7985         }
7986         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7987         amdgpu_ring_write(ring, cmd);
7988         amdgpu_ring_write(ring, reg);
7989         amdgpu_ring_write(ring, 0);
7990         amdgpu_ring_write(ring, val);
7991 }
7992
7993 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
7994                                         uint32_t val, uint32_t mask)
7995 {
7996         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
7997 }
7998
7999 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8000                                                    uint32_t reg0, uint32_t reg1,
8001                                                    uint32_t ref, uint32_t mask)
8002 {
8003         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8004         struct amdgpu_device *adev = ring->adev;
8005         bool fw_version_ok = false;
8006
8007         fw_version_ok = adev->gfx.cp_fw_write_wait;
8008
8009         if (fw_version_ok)
8010                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8011                                        ref, mask, 0x20);
8012         else
8013                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8014                                                            ref, mask);
8015 }
8016
8017 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8018                                          unsigned vmid)
8019 {
8020         struct amdgpu_device *adev = ring->adev;
8021         uint32_t value = 0;
8022
8023         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8024         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8025         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8026         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8027         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8028 }
8029
8030 static void
8031 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8032                                       uint32_t me, uint32_t pipe,
8033                                       enum amdgpu_interrupt_state state)
8034 {
8035         uint32_t cp_int_cntl, cp_int_cntl_reg;
8036
8037         if (!me) {
8038                 switch (pipe) {
8039                 case 0:
8040                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8041                         break;
8042                 case 1:
8043                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8044                         break;
8045                 default:
8046                         DRM_DEBUG("invalid pipe %d\n", pipe);
8047                         return;
8048                 }
8049         } else {
8050                 DRM_DEBUG("invalid me %d\n", me);
8051                 return;
8052         }
8053
8054         switch (state) {
8055         case AMDGPU_IRQ_STATE_DISABLE:
8056                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8057                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8058                                             TIME_STAMP_INT_ENABLE, 0);
8059                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8060                 break;
8061         case AMDGPU_IRQ_STATE_ENABLE:
8062                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8063                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8064                                             TIME_STAMP_INT_ENABLE, 1);
8065                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8066                 break;
8067         default:
8068                 break;
8069         }
8070 }
8071
8072 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8073                                                      int me, int pipe,
8074                                                      enum amdgpu_interrupt_state state)
8075 {
8076         u32 mec_int_cntl, mec_int_cntl_reg;
8077
8078         /*
8079          * amdgpu controls only the first MEC. That's why this function only
8080          * handles the setting of interrupts for this specific MEC. All other
8081          * pipes' interrupts are set by amdkfd.
8082          */
8083
8084         if (me == 1) {
8085                 switch (pipe) {
8086                 case 0:
8087                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8088                         break;
8089                 case 1:
8090                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8091                         break;
8092                 case 2:
8093                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8094                         break;
8095                 case 3:
8096                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8097                         break;
8098                 default:
8099                         DRM_DEBUG("invalid pipe %d\n", pipe);
8100                         return;
8101                 }
8102         } else {
8103                 DRM_DEBUG("invalid me %d\n", me);
8104                 return;
8105         }
8106
8107         switch (state) {
8108         case AMDGPU_IRQ_STATE_DISABLE:
8109                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8110                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8111                                              TIME_STAMP_INT_ENABLE, 0);
8112                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8113                 break;
8114         case AMDGPU_IRQ_STATE_ENABLE:
8115                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8116                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8117                                              TIME_STAMP_INT_ENABLE, 1);
8118                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8119                 break;
8120         default:
8121                 break;
8122         }
8123 }
8124
8125 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8126                                             struct amdgpu_irq_src *src,
8127                                             unsigned type,
8128                                             enum amdgpu_interrupt_state state)
8129 {
8130         switch (type) {
8131         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8132                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8133                 break;
8134         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8135                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8136                 break;
8137         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8138                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8139                 break;
8140         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8141                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8142                 break;
8143         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8144                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8145                 break;
8146         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8147                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8148                 break;
8149         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8150                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8151                 break;
8152         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8153                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8154                 break;
8155         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8156                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8157                 break;
8158         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8159                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8160                 break;
8161         default:
8162                 break;
8163         }
8164         return 0;
8165 }
8166
8167 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8168                              struct amdgpu_irq_src *source,
8169                              struct amdgpu_iv_entry *entry)
8170 {
8171         int i;
8172         u8 me_id, pipe_id, queue_id;
8173         struct amdgpu_ring *ring;
8174
8175         DRM_DEBUG("IH: CP EOP\n");
8176         me_id = (entry->ring_id & 0x0c) >> 2;
8177         pipe_id = (entry->ring_id & 0x03) >> 0;
8178         queue_id = (entry->ring_id & 0x70) >> 4;
8179
8180         switch (me_id) {
8181         case 0:
8182                 if (pipe_id == 0)
8183                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8184                 else
8185                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8186                 break;
8187         case 1:
8188         case 2:
8189                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8190                         ring = &adev->gfx.compute_ring[i];
8191                         /* Per-queue interrupt is supported for MEC starting from VI.
8192                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8193                           */
8194                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8195                                 amdgpu_fence_process(ring);
8196                 }
8197                 break;
8198         }
8199         return 0;
8200 }
8201
8202 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8203                                               struct amdgpu_irq_src *source,
8204                                               unsigned type,
8205                                               enum amdgpu_interrupt_state state)
8206 {
8207         switch (state) {
8208         case AMDGPU_IRQ_STATE_DISABLE:
8209         case AMDGPU_IRQ_STATE_ENABLE:
8210                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8211                                PRIV_REG_INT_ENABLE,
8212                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8213                 break;
8214         default:
8215                 break;
8216         }
8217
8218         return 0;
8219 }
8220
8221 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8222                                                struct amdgpu_irq_src *source,
8223                                                unsigned type,
8224                                                enum amdgpu_interrupt_state state)
8225 {
8226         switch (state) {
8227         case AMDGPU_IRQ_STATE_DISABLE:
8228         case AMDGPU_IRQ_STATE_ENABLE:
8229                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8230                                PRIV_INSTR_INT_ENABLE,
8231                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8232         default:
8233                 break;
8234         }
8235
8236         return 0;
8237 }
8238
8239 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8240                                         struct amdgpu_iv_entry *entry)
8241 {
8242         u8 me_id, pipe_id, queue_id;
8243         struct amdgpu_ring *ring;
8244         int i;
8245
8246         me_id = (entry->ring_id & 0x0c) >> 2;
8247         pipe_id = (entry->ring_id & 0x03) >> 0;
8248         queue_id = (entry->ring_id & 0x70) >> 4;
8249
8250         switch (me_id) {
8251         case 0:
8252                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8253                         ring = &adev->gfx.gfx_ring[i];
8254                         /* we only enabled 1 gfx queue per pipe for now */
8255                         if (ring->me == me_id && ring->pipe == pipe_id)
8256                                 drm_sched_fault(&ring->sched);
8257                 }
8258                 break;
8259         case 1:
8260         case 2:
8261                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8262                         ring = &adev->gfx.compute_ring[i];
8263                         if (ring->me == me_id && ring->pipe == pipe_id &&
8264                             ring->queue == queue_id)
8265                                 drm_sched_fault(&ring->sched);
8266                 }
8267                 break;
8268         default:
8269                 BUG();
8270         }
8271 }
8272
8273 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8274                                   struct amdgpu_irq_src *source,
8275                                   struct amdgpu_iv_entry *entry)
8276 {
8277         DRM_ERROR("Illegal register access in command stream\n");
8278         gfx_v10_0_handle_priv_fault(adev, entry);
8279         return 0;
8280 }
8281
8282 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8283                                    struct amdgpu_irq_src *source,
8284                                    struct amdgpu_iv_entry *entry)
8285 {
8286         DRM_ERROR("Illegal instruction in command stream\n");
8287         gfx_v10_0_handle_priv_fault(adev, entry);
8288         return 0;
8289 }
8290
8291 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8292                                              struct amdgpu_irq_src *src,
8293                                              unsigned int type,
8294                                              enum amdgpu_interrupt_state state)
8295 {
8296         uint32_t tmp, target;
8297         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8298
8299         if (ring->me == 1)
8300                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8301         else
8302                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8303         target += ring->pipe;
8304
8305         switch (type) {
8306         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8307                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8308                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8309                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8310                                             GENERIC2_INT_ENABLE, 0);
8311                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8312
8313                         tmp = RREG32(target);
8314                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8315                                             GENERIC2_INT_ENABLE, 0);
8316                         WREG32(target, tmp);
8317                 } else {
8318                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8319                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8320                                             GENERIC2_INT_ENABLE, 1);
8321                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8322
8323                         tmp = RREG32(target);
8324                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8325                                             GENERIC2_INT_ENABLE, 1);
8326                         WREG32(target, tmp);
8327                 }
8328                 break;
8329         default:
8330                 BUG(); /* kiq only support GENERIC2_INT now */
8331                 break;
8332         }
8333         return 0;
8334 }
8335
8336 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8337                              struct amdgpu_irq_src *source,
8338                              struct amdgpu_iv_entry *entry)
8339 {
8340         u8 me_id, pipe_id, queue_id;
8341         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8342
8343         me_id = (entry->ring_id & 0x0c) >> 2;
8344         pipe_id = (entry->ring_id & 0x03) >> 0;
8345         queue_id = (entry->ring_id & 0x70) >> 4;
8346         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8347                    me_id, pipe_id, queue_id);
8348
8349         amdgpu_fence_process(ring);
8350         return 0;
8351 }
8352
8353 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8354 {
8355         const unsigned int gcr_cntl =
8356                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8357                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8358                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8359                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8360                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8361                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8362                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8363                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8364
8365         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8366         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8367         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8368         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8369         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8370         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8371         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8372         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8373         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8374 }
8375
8376 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8377         .name = "gfx_v10_0",
8378         .early_init = gfx_v10_0_early_init,
8379         .late_init = gfx_v10_0_late_init,
8380         .sw_init = gfx_v10_0_sw_init,
8381         .sw_fini = gfx_v10_0_sw_fini,
8382         .hw_init = gfx_v10_0_hw_init,
8383         .hw_fini = gfx_v10_0_hw_fini,
8384         .suspend = gfx_v10_0_suspend,
8385         .resume = gfx_v10_0_resume,
8386         .is_idle = gfx_v10_0_is_idle,
8387         .wait_for_idle = gfx_v10_0_wait_for_idle,
8388         .soft_reset = gfx_v10_0_soft_reset,
8389         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8390         .set_powergating_state = gfx_v10_0_set_powergating_state,
8391         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8392 };
8393
8394 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8395         .type = AMDGPU_RING_TYPE_GFX,
8396         .align_mask = 0xff,
8397         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8398         .support_64bit_ptrs = true,
8399         .vmhub = AMDGPU_GFXHUB_0,
8400         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8401         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8402         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8403         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8404                 5 + /* COND_EXEC */
8405                 7 + /* PIPELINE_SYNC */
8406                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8407                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8408                 2 + /* VM_FLUSH */
8409                 8 + /* FENCE for VM_FLUSH */
8410                 20 + /* GDS switch */
8411                 4 + /* double SWITCH_BUFFER,
8412                      * the first COND_EXEC jump to the place
8413                      * just prior to this double SWITCH_BUFFER
8414                      */
8415                 5 + /* COND_EXEC */
8416                 7 + /* HDP_flush */
8417                 4 + /* VGT_flush */
8418                 14 + /* CE_META */
8419                 31 + /* DE_META */
8420                 3 + /* CNTX_CTRL */
8421                 5 + /* HDP_INVL */
8422                 8 + 8 + /* FENCE x2 */
8423                 2 + /* SWITCH_BUFFER */
8424                 8, /* gfx_v10_0_emit_mem_sync */
8425         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8426         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8427         .emit_fence = gfx_v10_0_ring_emit_fence,
8428         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8429         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8430         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8431         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8432         .test_ring = gfx_v10_0_ring_test_ring,
8433         .test_ib = gfx_v10_0_ring_test_ib,
8434         .insert_nop = amdgpu_ring_insert_nop,
8435         .pad_ib = amdgpu_ring_generic_pad_ib,
8436         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8437         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8438         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8439         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8440         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8441         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8442         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8443         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8444         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8445         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8446         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8447 };
8448
8449 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8450         .type = AMDGPU_RING_TYPE_COMPUTE,
8451         .align_mask = 0xff,
8452         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8453         .support_64bit_ptrs = true,
8454         .vmhub = AMDGPU_GFXHUB_0,
8455         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8456         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8457         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8458         .emit_frame_size =
8459                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8460                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8461                 5 + /* hdp invalidate */
8462                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8463                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8464                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8465                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8466                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8467                 8, /* gfx_v10_0_emit_mem_sync */
8468         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8469         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8470         .emit_fence = gfx_v10_0_ring_emit_fence,
8471         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8472         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8473         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8474         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8475         .test_ring = gfx_v10_0_ring_test_ring,
8476         .test_ib = gfx_v10_0_ring_test_ib,
8477         .insert_nop = amdgpu_ring_insert_nop,
8478         .pad_ib = amdgpu_ring_generic_pad_ib,
8479         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8480         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8481         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8482         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8483 };
8484
8485 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8486         .type = AMDGPU_RING_TYPE_KIQ,
8487         .align_mask = 0xff,
8488         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8489         .support_64bit_ptrs = true,
8490         .vmhub = AMDGPU_GFXHUB_0,
8491         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8492         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8493         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8494         .emit_frame_size =
8495                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8496                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8497                 5 + /*hdp invalidate */
8498                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8499                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8500                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8501                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8502                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8503         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8504         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8505         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8506         .test_ring = gfx_v10_0_ring_test_ring,
8507         .test_ib = gfx_v10_0_ring_test_ib,
8508         .insert_nop = amdgpu_ring_insert_nop,
8509         .pad_ib = amdgpu_ring_generic_pad_ib,
8510         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8511         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8512         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8513         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8514 };
8515
8516 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8517 {
8518         int i;
8519
8520         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8521
8522         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8523                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8524
8525         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8526                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8527 }
8528
8529 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8530         .set = gfx_v10_0_set_eop_interrupt_state,
8531         .process = gfx_v10_0_eop_irq,
8532 };
8533
8534 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8535         .set = gfx_v10_0_set_priv_reg_fault_state,
8536         .process = gfx_v10_0_priv_reg_irq,
8537 };
8538
8539 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8540         .set = gfx_v10_0_set_priv_inst_fault_state,
8541         .process = gfx_v10_0_priv_inst_irq,
8542 };
8543
8544 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8545         .set = gfx_v10_0_kiq_set_interrupt_state,
8546         .process = gfx_v10_0_kiq_irq,
8547 };
8548
8549 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8550 {
8551         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8552         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8553
8554         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8555         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8556
8557         adev->gfx.priv_reg_irq.num_types = 1;
8558         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8559
8560         adev->gfx.priv_inst_irq.num_types = 1;
8561         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8562 }
8563
8564 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8565 {
8566         switch (adev->asic_type) {
8567         case CHIP_NAVI10:
8568         case CHIP_NAVI14:
8569         case CHIP_SIENNA_CICHLID:
8570                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8571                 break;
8572         case CHIP_NAVI12:
8573                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8574                 break;
8575         default:
8576                 break;
8577         }
8578 }
8579
8580 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8581 {
8582         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8583                             adev->gfx.config.max_sh_per_se *
8584                             adev->gfx.config.max_shader_engines;
8585
8586         adev->gds.gds_size = 0x10000;
8587         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8588         adev->gds.gws_size = 64;
8589         adev->gds.oa_size = 16;
8590 }
8591
8592 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8593                                                           u32 bitmap)
8594 {
8595         u32 data;
8596
8597         if (!bitmap)
8598                 return;
8599
8600         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8601         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8602
8603         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8604 }
8605
8606 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8607 {
8608         u32 data, wgp_bitmask;
8609         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8610         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8611
8612         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8613         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8614
8615         wgp_bitmask =
8616                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8617
8618         return (~data) & wgp_bitmask;
8619 }
8620
8621 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8622 {
8623         u32 wgp_idx, wgp_active_bitmap;
8624         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8625
8626         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8627         cu_active_bitmap = 0;
8628
8629         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8630                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8631                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8632                 if (wgp_active_bitmap & (1 << wgp_idx))
8633                         cu_active_bitmap |= cu_bitmap_per_wgp;
8634         }
8635
8636         return cu_active_bitmap;
8637 }
8638
8639 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8640                                  struct amdgpu_cu_info *cu_info)
8641 {
8642         int i, j, k, counter, active_cu_number = 0;
8643         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8644         unsigned disable_masks[4 * 2];
8645
8646         if (!adev || !cu_info)
8647                 return -EINVAL;
8648
8649         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8650
8651         mutex_lock(&adev->grbm_idx_mutex);
8652         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8653                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8654                         mask = 1;
8655                         ao_bitmap = 0;
8656                         counter = 0;
8657                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8658                         if (i < 4 && j < 2)
8659                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8660                                         adev, disable_masks[i * 2 + j]);
8661                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8662                         cu_info->bitmap[i][j] = bitmap;
8663
8664                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8665                                 if (bitmap & mask) {
8666                                         if (counter < adev->gfx.config.max_cu_per_sh)
8667                                                 ao_bitmap |= mask;
8668                                         counter++;
8669                                 }
8670                                 mask <<= 1;
8671                         }
8672                         active_cu_number += counter;
8673                         if (i < 2 && j < 2)
8674                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8675                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8676                 }
8677         }
8678         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8679         mutex_unlock(&adev->grbm_idx_mutex);
8680
8681         cu_info->number = active_cu_number;
8682         cu_info->ao_cu_mask = ao_cu_mask;
8683         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8684
8685         return 0;
8686 }
8687
8688 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8689 {
8690         .type = AMD_IP_BLOCK_TYPE_GFX,
8691         .major = 10,
8692         .minor = 0,
8693         .rev = 0,
8694         .funcs = &gfx_v10_0_ip_funcs,
8695 };