drivers/gpu/drm/i915/vlv_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <[email protected]>
  24  */
  25
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <drm/drm_mipi_dsi.h>
  31 #include <linux/slab.h>
  32 #include <linux/gpio/consumer.h>
  33 #include "i915_drv.h"
  34 #include "intel_drv.h"
  35 #include "intel_dsi.h"
  36
  37 /* return pixels in terms of txbyteclkhs */
  38 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
  39                        u16 burst_mode_ratio)
  40 {
  41         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
  42                                          8 * 100), lane_count);
  43 }
  44
  45 /* return pixels equvalent to txbyteclkhs */
  46 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
  47                         u16 burst_mode_ratio)
  48 {
  49         return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
  50                                                 (bpp * burst_mode_ratio));
  51 }
  52
  53 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
  54 {
  55         /* It just so happens the VBT matches register contents. */
  56         switch (fmt) {
  57         case VID_MODE_FORMAT_RGB888:
  58                 return MIPI_DSI_FMT_RGB888;
  59         case VID_MODE_FORMAT_RGB666:
  60                 return MIPI_DSI_FMT_RGB666;
  61         case VID_MODE_FORMAT_RGB666_PACKED:
  62                 return MIPI_DSI_FMT_RGB666_PACKED;
  63         case VID_MODE_FORMAT_RGB565:
  64                 return MIPI_DSI_FMT_RGB565;
  65         default:
  66                 MISSING_CASE(fmt);
  67                 return MIPI_DSI_FMT_RGB666;
  68         }
  69 }
  70
  71 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
  72 {
  73         struct drm_encoder *encoder = &intel_dsi->base.base;
  74         struct drm_device *dev = encoder->dev;
  75         struct drm_i915_private *dev_priv = to_i915(dev);
  76         u32 mask;
  77
  78         mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
  79                 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
  80
  81         if (intel_wait_for_register(dev_priv,
  82                                     MIPI_GEN_FIFO_STAT(port), mask, mask,
  83                                     100))
  84                 DRM_ERROR("DPI FIFOs are not empty\n");
  85 }
  86
  87 static void write_data(struct drm_i915_private *dev_priv,
  88                        i915_reg_t reg,
  89                        const u8 *data, u32 len)
  90 {
  91         u32 i, j;
  92
  93         for (i = 0; i < len; i += 4) {
  94                 u32 val = 0;
  95
  96                 for (j = 0; j < min_t(u32, len - i, 4); j++)
  97                         val |= *data++ << 8 * j;
  98
  99                 I915_WRITE(reg, val);
 100         }
 101 }
 102
 103 static void read_data(struct drm_i915_private *dev_priv,
 104                       i915_reg_t reg,
 105                       u8 *data, u32 len)
 106 {
 107         u32 i, j;
 108
 109         for (i = 0; i < len; i += 4) {
 110                 u32 val = I915_READ(reg);
 111
 112                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 113                         *data++ = val >> 8 * j;
 114         }
 115 }
 116
 117 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
 118                                        const struct mipi_dsi_msg *msg)
 119 {
 120         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
 121         struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
 122         struct drm_i915_private *dev_priv = to_i915(dev);
 123         enum port port = intel_dsi_host->port;
 124         struct mipi_dsi_packet packet;
 125         ssize_t ret;
 126         const u8 *header, *data;
 127         i915_reg_t data_reg, ctrl_reg;
 128         u32 data_mask, ctrl_mask;
 129
 130         ret = mipi_dsi_create_packet(&packet, msg);
 131         if (ret < 0)
 132                 return ret;
 133
 134         header = packet.header;
 135         data = packet.payload;
 136
 137         if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
 138                 data_reg = MIPI_LP_GEN_DATA(port);
 139                 data_mask = LP_DATA_FIFO_FULL;
 140                 ctrl_reg = MIPI_LP_GEN_CTRL(port);
 141                 ctrl_mask = LP_CTRL_FIFO_FULL;
 142         } else {
 143                 data_reg = MIPI_HS_GEN_DATA(port);
 144                 data_mask = HS_DATA_FIFO_FULL;
 145                 ctrl_reg = MIPI_HS_GEN_CTRL(port);
 146                 ctrl_mask = HS_CTRL_FIFO_FULL;
 147         }
 148
 149         /* note: this is never true for reads */
 150         if (packet.payload_length) {
 151                 if (intel_wait_for_register(dev_priv,
 152                                             MIPI_GEN_FIFO_STAT(port),
 153                                             data_mask, 0,
 154                                             50))
 155                         DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
 156
 157                 write_data(dev_priv, data_reg, packet.payload,
 158                            packet.payload_length);
 159         }
 160
 161         if (msg->rx_len) {
 162                 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
 163         }
 164
 165         if (intel_wait_for_register(dev_priv,
 166                                     MIPI_GEN_FIFO_STAT(port),
 167                                     ctrl_mask, 0,
 168                                     50)) {
 169                 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
 170         }
 171
 172         I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
 173
 174         /* ->rx_len is set only for reads */
 175         if (msg->rx_len) {
 176                 data_mask = GEN_READ_DATA_AVAIL;
 177                 if (intel_wait_for_register(dev_priv,
 178                                             MIPI_INTR_STAT(port),
 179                                             data_mask, data_mask,
 180                                             50))
 181                         DRM_ERROR("Timeout waiting for read data.\n");
 182
 183                 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
 184         }
 185
 186         /* XXX: fix for reads and writes */
 187         return 4 + packet.payload_length;
 188 }
 189
 190 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
 191                                  struct mipi_dsi_device *dsi)
 192 {
 193         return 0;
 194 }
 195
 196 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
 197                                  struct mipi_dsi_device *dsi)
 198 {
 199         return 0;
 200 }
 201
 202 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
 203         .attach = intel_dsi_host_attach,
 204         .detach = intel_dsi_host_detach,
 205         .transfer = intel_dsi_host_transfer,
 206 };
 207
 208 /*
 209  * send a video mode command
 210  *
 211  * XXX: commands with data in MIPI_DPI_DATA?
 212  */
 213 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
 214                         enum port port)
 215 {
 216         struct drm_encoder *encoder = &intel_dsi->base.base;
 217         struct drm_device *dev = encoder->dev;
 218         struct drm_i915_private *dev_priv = to_i915(dev);
 219         u32 mask;
 220
 221         /* XXX: pipe, hs */
 222         if (hs)
 223                 cmd &= ~DPI_LP_MODE;
 224         else
 225                 cmd |= DPI_LP_MODE;
 226
 227         /* clear bit */
 228         I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
 229
 230         /* XXX: old code skips write if control unchanged */
 231         if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
 232                 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
 233
 234         I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
 235
 236         mask = SPL_PKT_SENT_INTERRUPT;
 237         if (intel_wait_for_register(dev_priv,
 238                                     MIPI_INTR_STAT(port), mask, mask,
 239                                     100))
 240                 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
 241
 242         return 0;
 243 }
 244
 245 static void band_gap_reset(struct drm_i915_private *dev_priv)
 246 {
 247         mutex_lock(&dev_priv->sb_lock);
 248
 249         vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
 250         vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
 251         vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
 252         udelay(150);
 253         vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
 254         vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
 255
 256         mutex_unlock(&dev_priv->sb_lock);
 257 }
 258
 259 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 260                                     struct intel_crtc_state *pipe_config,
 261                                     struct drm_connector_state *conn_state)
 262 {
 263         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 264         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
 265                                                    base);
 266         struct intel_connector *intel_connector = intel_dsi->attached_connector;
 267         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 268         const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 269         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 270         int ret;
 271
 272         DRM_DEBUG_KMS("\n");
 273         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 274
 275         if (fixed_mode) {
 276                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 277
 278                 if (HAS_GMCH(dev_priv))
 279                         intel_gmch_panel_fitting(crtc, pipe_config,
 280                                                  conn_state->scaling_mode);
 281                 else
 282                         intel_pch_panel_fitting(crtc, pipe_config,
 283                                                 conn_state->scaling_mode);
 284         }
 285
 286         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 287                 return -EINVAL;
 288
 289         /* DSI uses short packets for sync events, so clear mode flags for DSI */
 290         adjusted_mode->flags = 0;
 291
 292         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
 293                 pipe_config->pipe_bpp = 24;
 294         else
 295                 pipe_config->pipe_bpp = 18;
 296
 297         if (IS_GEN9_LP(dev_priv)) {
 298                 /* Enable Frame time stamp based scanline reporting */
 299                 adjusted_mode->private_flags |=
 300                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
 301
 302                 /* Dual link goes to DSI transcoder A. */
 303                 if (intel_dsi->ports == BIT(PORT_C))
 304                         pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
 305                 else
 306                         pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
 307
 308                 ret = bxt_dsi_pll_compute(encoder, pipe_config);
 309                 if (ret)
 310                         return -EINVAL;
 311         } else {
 312                 ret = vlv_dsi_pll_compute(encoder, pipe_config);
 313                 if (ret)
 314                         return -EINVAL;
 315         }
 316
 317         pipe_config->clock_set = true;
 318
 319         return 0;
 320 }
 321
 322 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
 323 {
 324         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 325         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 326         enum port port;
 327         u32 tmp;
 328         bool cold_boot = false;
 329
 330         /* Set the MIPI mode
 331          * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
 332          * Power ON MIPI IO first and then write into IO reset and LP wake bits
 333          */
 334         for_each_dsi_port(port, intel_dsi->ports) {
 335                 tmp = I915_READ(MIPI_CTRL(port));
 336                 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
 337         }
 338
 339         /* Put the IO into reset */
 340         tmp = I915_READ(MIPI_CTRL(PORT_A));
 341         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 342         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 343
 344         /* Program LP Wake */
 345         for_each_dsi_port(port, intel_dsi->ports) {
 346                 tmp = I915_READ(MIPI_CTRL(port));
 347                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
 348                         tmp &= ~GLK_LP_WAKE;
 349                 else
 350                         tmp |= GLK_LP_WAKE;
 351                 I915_WRITE(MIPI_CTRL(port), tmp);
 352         }
 353
 354         /* Wait for Pwr ACK */
 355         for_each_dsi_port(port, intel_dsi->ports) {
 356                 if (intel_wait_for_register(dev_priv,
 357                                 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
 358                                 GLK_MIPIIO_PORT_POWERED, 20))
 359                         DRM_ERROR("MIPIO port is powergated\n");
 360         }
 361
 362         /* Check for cold boot scenario */
 363         for_each_dsi_port(port, intel_dsi->ports) {
 364                 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
 365                                                         DEVICE_READY);
 366         }
 367
 368         return cold_boot;
 369 }
 370
 371 static void glk_dsi_device_ready(struct intel_encoder *encoder)
 372 {
 373         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 374         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 375         enum port port;
 376         u32 val;
 377
 378         /* Wait for MIPI PHY status bit to set */
 379         for_each_dsi_port(port, intel_dsi->ports) {
 380                 if (intel_wait_for_register(dev_priv,
 381                                 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
 382                                 GLK_PHY_STATUS_PORT_READY, 20))
 383                         DRM_ERROR("PHY is not ON\n");
 384         }
 385
 386         /* Get IO out of reset */
 387         val = I915_READ(MIPI_CTRL(PORT_A));
 388         I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
 389
 390         /* Get IO out of Low power state*/
 391         for_each_dsi_port(port, intel_dsi->ports) {
 392                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
 393                         val = I915_READ(MIPI_DEVICE_READY(port));
 394                         val &= ~ULPS_STATE_MASK;
 395                         val |= DEVICE_READY;
 396                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 397                         usleep_range(10, 15);
 398                 } else {
 399                         /* Enter ULPS */
 400                         val = I915_READ(MIPI_DEVICE_READY(port));
 401                         val &= ~ULPS_STATE_MASK;
 402                         val |= (ULPS_STATE_ENTER | DEVICE_READY);
 403                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 404
 405                         /* Wait for ULPS active */
 406                         if (intel_wait_for_register(dev_priv,
 407                                 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
 408                                 DRM_ERROR("ULPS not active\n");
 409
 410                         /* Exit ULPS */
 411                         val = I915_READ(MIPI_DEVICE_READY(port));
 412                         val &= ~ULPS_STATE_MASK;
 413                         val |= (ULPS_STATE_EXIT | DEVICE_READY);
 414                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 415
 416                         /* Enter Normal Mode */
 417                         val = I915_READ(MIPI_DEVICE_READY(port));
 418                         val &= ~ULPS_STATE_MASK;
 419                         val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
 420                         I915_WRITE(MIPI_DEVICE_READY(port), val);
 421
 422                         val = I915_READ(MIPI_CTRL(port));
 423                         val &= ~GLK_LP_WAKE;
 424                         I915_WRITE(MIPI_CTRL(port), val);
 425                 }
 426         }
 427
 428         /* Wait for Stop state */
 429         for_each_dsi_port(port, intel_dsi->ports) {
 430                 if (intel_wait_for_register(dev_priv,
 431                                 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
 432                                 GLK_DATA_LANE_STOP_STATE, 20))
 433                         DRM_ERROR("Date lane not in STOP state\n");
 434         }
 435
 436         /* Wait for AFE LATCH */
 437         for_each_dsi_port(port, intel_dsi->ports) {
 438                 if (intel_wait_for_register(dev_priv,
 439                                 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
 440                                 AFE_LATCHOUT, 20))
 441                         DRM_ERROR("D-PHY not entering LP-11 state\n");
 442         }
 443 }
 444
 445 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
 446 {
 447         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 448         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 449         enum port port;
 450         u32 val;
 451
 452         DRM_DEBUG_KMS("\n");
 453
 454         /* Enable MIPI PHY transparent latch */
 455         for_each_dsi_port(port, intel_dsi->ports) {
 456                 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
 457                 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
 458                 usleep_range(2000, 2500);
 459         }
 460
 461         /* Clear ULPS and set device ready */
 462         for_each_dsi_port(port, intel_dsi->ports) {
 463                 val = I915_READ(MIPI_DEVICE_READY(port));
 464                 val &= ~ULPS_STATE_MASK;
 465                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 466                 usleep_range(2000, 2500);
 467                 val |= DEVICE_READY;
 468                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 469         }
 470 }
 471
 472 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
 473 {
 474         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 475         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 476         enum port port;
 477         u32 val;
 478
 479         DRM_DEBUG_KMS("\n");
 480
 481         mutex_lock(&dev_priv->sb_lock);
 482         /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
 483          * needed everytime after power gate */
 484         vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
 485         mutex_unlock(&dev_priv->sb_lock);
 486
 487         /* bandgap reset is needed after everytime we do power gate */
 488         band_gap_reset(dev_priv);
 489
 490         for_each_dsi_port(port, intel_dsi->ports) {
 491
 492                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
 493                 usleep_range(2500, 3000);
 494
 495                 /* Enable MIPI PHY transparent latch
 496                  * Common bit for both MIPI Port A & MIPI Port C
 497                  * No similar bit in MIPI Port C reg
 498                  */
 499                 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
 500                 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 501                 usleep_range(1000, 1500);
 502
 503                 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
 504                 usleep_range(2500, 3000);
 505
 506                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
 507                 usleep_range(2500, 3000);
 508         }
 509 }
 510
 511 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 512 {
 513         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 514
 515         if (IS_GEMINILAKE(dev_priv))
 516                 glk_dsi_device_ready(encoder);
 517         else if (IS_GEN9_LP(dev_priv))
 518                 bxt_dsi_device_ready(encoder);
 519         else
 520                 vlv_dsi_device_ready(encoder);
 521 }
 522
 523 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
 524 {
 525         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 526         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 527         enum port port;
 528         u32 val;
 529
 530         /* Enter ULPS */
 531         for_each_dsi_port(port, intel_dsi->ports) {
 532                 val = I915_READ(MIPI_DEVICE_READY(port));
 533                 val &= ~ULPS_STATE_MASK;
 534                 val |= (ULPS_STATE_ENTER | DEVICE_READY);
 535                 I915_WRITE(MIPI_DEVICE_READY(port), val);
 536         }
 537
 538         /* Wait for MIPI PHY status bit to unset */
 539         for_each_dsi_port(port, intel_dsi->ports) {
 540                 if (intel_wait_for_register(dev_priv,
 541                                             MIPI_CTRL(port),
 542                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 543                         DRM_ERROR("PHY is not turning OFF\n");
 544         }
 545
 546         /* Wait for Pwr ACK bit to unset */
 547         for_each_dsi_port(port, intel_dsi->ports) {
 548                 if (intel_wait_for_register(dev_priv,
 549                                             MIPI_CTRL(port),
 550                                             GLK_MIPIIO_PORT_POWERED, 0, 20))
 551                         DRM_ERROR("MIPI IO Port is not powergated\n");
 552         }
 553 }
 554
 555 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
 556 {
 557         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 558         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 559         enum port port;
 560         u32 tmp;
 561
 562         /* Put the IO into reset */
 563         tmp = I915_READ(MIPI_CTRL(PORT_A));
 564         tmp &= ~GLK_MIPIIO_RESET_RELEASED;
 565         I915_WRITE(MIPI_CTRL(PORT_A), tmp);
 566
 567         /* Wait for MIPI PHY status bit to unset */
 568         for_each_dsi_port(port, intel_dsi->ports) {
 569                 if (intel_wait_for_register(dev_priv,
 570                                             MIPI_CTRL(port),
 571                                             GLK_PHY_STATUS_PORT_READY, 0, 20))
 572                         DRM_ERROR("PHY is not turning OFF\n");
 573         }
 574
 575         /* Clear MIPI mode */
 576         for_each_dsi_port(port, intel_dsi->ports) {
 577                 tmp = I915_READ(MIPI_CTRL(port));
 578                 tmp &= ~GLK_MIPIIO_ENABLE;
 579                 I915_WRITE(MIPI_CTRL(port), tmp);
 580         }
 581 }
 582
 583 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
 584 {
 585         glk_dsi_enter_low_power_mode(encoder);
 586         glk_dsi_disable_mipi_io(encoder);
 587 }
 588
 589 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
 590 {
 591         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 592         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 593         enum port port;
 594
 595         DRM_DEBUG_KMS("\n");
 596         for_each_dsi_port(port, intel_dsi->ports) {
 597                 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
 598                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 599                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
 600                 u32 val;
 601
 602                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 603                                                         ULPS_STATE_ENTER);
 604                 usleep_range(2000, 2500);
 605
 606                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 607                                                         ULPS_STATE_EXIT);
 608                 usleep_range(2000, 2500);
 609
 610                 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
 611                                                         ULPS_STATE_ENTER);
 612                 usleep_range(2000, 2500);
 613
 614                 /*
 615                  * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
 616                  * Port A only. MIPI Port C has no similar bit for checking.
 617                  */
 618                 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
 619                     intel_wait_for_register(dev_priv,
 620                                             port_ctrl, AFE_LATCHOUT, 0,
 621                                             30))
 622                         DRM_ERROR("DSI LP not going Low\n");
 623
 624                 /* Disable MIPI PHY transparent latch */
 625                 val = I915_READ(port_ctrl);
 626                 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 627                 usleep_range(1000, 1500);
 628
 629                 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
 630                 usleep_range(2000, 2500);
 631         }
 632 }
 633
 634 static void intel_dsi_port_enable(struct intel_encoder *encoder,
 635                                   const struct intel_crtc_state *crtc_state)
 636 {
 637         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 638         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 639         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 640         enum port port;
 641
 642         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 643                 u32 temp;
 644                 if (IS_GEN9_LP(dev_priv)) {
 645                         for_each_dsi_port(port, intel_dsi->ports) {
 646                                 temp = I915_READ(MIPI_CTRL(port));
 647                                 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
 648                                         intel_dsi->pixel_overlap <<
 649                                         BXT_PIXEL_OVERLAP_CNT_SHIFT;
 650                                 I915_WRITE(MIPI_CTRL(port), temp);
 651                         }
 652                 } else {
 653                         temp = I915_READ(VLV_CHICKEN_3);
 654                         temp &= ~PIXEL_OVERLAP_CNT_MASK |
 655                                         intel_dsi->pixel_overlap <<
 656                                         PIXEL_OVERLAP_CNT_SHIFT;
 657                         I915_WRITE(VLV_CHICKEN_3, temp);
 658                 }
 659         }
 660
 661         for_each_dsi_port(port, intel_dsi->ports) {
 662                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 663                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 664                 u32 temp;
 665
 666                 temp = I915_READ(port_ctrl);
 667
 668                 temp &= ~LANE_CONFIGURATION_MASK;
 669                 temp &= ~DUAL_LINK_MODE_MASK;
 670
 671                 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
 672                         temp |= (intel_dsi->dual_link - 1)
 673                                                 << DUAL_LINK_MODE_SHIFT;
 674                         if (IS_BROXTON(dev_priv))
 675                                 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
 676                         else
 677                                 temp |= crtc->pipe ?
 678                                         LANE_CONFIGURATION_DUAL_LINK_B :
 679                                         LANE_CONFIGURATION_DUAL_LINK_A;
 680                 }
 681
 682                 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
 683                         temp |= DITHERING_ENABLE;
 684
 685                 /* assert ip_tg_enable signal */
 686                 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
 687                 POSTING_READ(port_ctrl);
 688         }
 689 }
 690
 691 static void intel_dsi_port_disable(struct intel_encoder *encoder)
 692 {
 693         struct drm_device *dev = encoder->base.dev;
 694         struct drm_i915_private *dev_priv = to_i915(dev);
 695         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 696         enum port port;
 697
 698         for_each_dsi_port(port, intel_dsi->ports) {
 699                 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
 700                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 701                 u32 temp;
 702
 703                 /* de-assert ip_tg_enable signal */
 704                 temp = I915_READ(port_ctrl);
 705                 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
 706                 POSTING_READ(port_ctrl);
 707         }
 708 }
 709
 710 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
 711                               const struct intel_crtc_state *pipe_config);
 712 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 713
 714 /*
 715  * Panel enable/disable sequences from the VBT spec.
 716  *
 717  * Note the spec has AssertReset / DeassertReset swapped from their
 718  * usual naming. We use the normal names to avoid confusion (so below
 719  * they are swapped compared to the spec).
 720  *
 721  * Steps starting with MIPI refer to VBT sequences, note that for v2
 722  * VBTs several steps which have a VBT in v2 are expected to be handled
 723  * directly by the driver, by directly driving gpios for example.
 724  *
 725  * v2 video mode seq         v3 video mode seq         command mode seq
 726  * - power on                - MIPIPanelPowerOn        - power on
 727  * - wait t1+t2                                        - wait t1+t2
 728  * - MIPIDeassertResetPin    - MIPIDeassertResetPin    - MIPIDeassertResetPin
 729  * - io lines to lp-11       - io lines to lp-11       - io lines to lp-11
 730  * - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds  - MIPISendInitialDcsCmds
 731  *                                                     - MIPITearOn
 732  *                                                     - MIPIDisplayOn
 733  * - turn on DPI             - turn on DPI             - set pipe to dsr mode
 734  * - MIPIDisplayOn           - MIPIDisplayOn
 735  * - wait t5                                           - wait t5
 736  * - backlight on            - MIPIBacklightOn         - backlight on
 737  * ...                       ...                       ... issue mem cmds ...
 738  * - backlight off           - MIPIBacklightOff        - backlight off
 739  * - wait t6                                           - wait t6
 740  * - MIPIDisplayOff
 741  * - turn off DPI            - turn off DPI            - disable pipe dsr mode
 742  *                                                     - MIPITearOff
 743  *                           - MIPIDisplayOff          - MIPIDisplayOff
 744  * - io lines to lp-00       - io lines to lp-00       - io lines to lp-00
 745  * - MIPIAssertResetPin      - MIPIAssertResetPin      - MIPIAssertResetPin
 746  * - wait t3                                           - wait t3
 747  * - power off               - MIPIPanelPowerOff       - power off
 748  * - wait t4                                           - wait t4
 749  */
 750
 751 /*
 752  * DSI port enable has to be done before pipe and plane enable, so we do it in
 753  * the pre_enable hook instead of the enable hook.
 754  */
 755 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 756                                  const struct intel_crtc_state *pipe_config,
 757                                  const struct drm_connector_state *conn_state)
 758 {
 759         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 760         struct drm_crtc *crtc = pipe_config->base.crtc;
 761         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 762         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 763         int pipe = intel_crtc->pipe;
 764         enum port port;
 765         u32 val;
 766         bool glk_cold_boot = false;
 767
 768         DRM_DEBUG_KMS("\n");
 769
 770         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 771
 772         /*
 773          * The BIOS may leave the PLL in a wonky state where it doesn't
 774          * lock. It needs to be fully powered down to fix it.
 775          */
 776         if (IS_GEN9_LP(dev_priv)) {
 777                 bxt_dsi_pll_disable(encoder);
 778                 bxt_dsi_pll_enable(encoder, pipe_config);
 779         } else {
 780                 vlv_dsi_pll_disable(encoder);
 781                 vlv_dsi_pll_enable(encoder, pipe_config);
 782         }
 783
 784         if (IS_BROXTON(dev_priv)) {
 785                 /* Add MIPI IO reset programming for modeset */
 786                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 787                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 788                                         val | MIPIO_RST_CTRL);
 789
 790                 /* Power up DSI regulator */
 791                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 792                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
 793         }
 794
 795         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 796                 u32 val;
 797
 798                 /* Disable DPOunit clock gating, can stall pipe */
 799                 val = I915_READ(DSPCLK_GATE_D);
 800                 val |= DPOUNIT_CLOCK_GATE_DISABLE;
 801                 I915_WRITE(DSPCLK_GATE_D, val);
 802         }
 803
 804         if (!IS_GEMINILAKE(dev_priv))
 805                 intel_dsi_prepare(encoder, pipe_config);
 806
 807         /* Power on, try both CRC pmic gpio and VBT */
 808         if (intel_dsi->gpio_panel)
 809                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
 810         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
 811         intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 812
 813         /* Deassert reset */
 814         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
 815
 816         if (IS_GEMINILAKE(dev_priv)) {
 817                 glk_cold_boot = glk_dsi_enable_io(encoder);
 818
 819                 /* Prepare port in cold boot(s3/s4) scenario */
 820                 if (glk_cold_boot)
 821                         intel_dsi_prepare(encoder, pipe_config);
 822         }
 823
 824         /* Put device in ready state (LP-11) */
 825         intel_dsi_device_ready(encoder);
 826
 827         /* Prepare port in normal boot scenario */
 828         if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
 829                 intel_dsi_prepare(encoder, pipe_config);
 830
 831         /* Send initialization commands in LP mode */
 832         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 833
 834         /* Enable port in pre-enable phase itself because as per hw team
 835          * recommendation, port should be enabled befor plane & pipe */
 836         if (is_cmd_mode(intel_dsi)) {
 837                 for_each_dsi_port(port, intel_dsi->ports)
 838                         I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
 839                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
 840                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 841         } else {
 842                 msleep(20); /* XXX */
 843                 for_each_dsi_port(port, intel_dsi->ports)
 844                         dpi_send_cmd(intel_dsi, TURN_ON, false, port);
 845                 intel_dsi_msleep(intel_dsi, 100);
 846
 847                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 848
 849                 intel_dsi_port_enable(encoder, pipe_config);
 850         }
 851
 852         intel_panel_enable_backlight(pipe_config, conn_state);
 853         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 854 }
 855
 856 /*
 857  * DSI port disable has to be done after pipe and plane disable, so we do it in
 858  * the post_disable hook.
 859  */
 860 static void intel_dsi_disable(struct intel_encoder *encoder,
 861                               const struct intel_crtc_state *old_crtc_state,
 862                               const struct drm_connector_state *old_conn_state)
 863 {
 864         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 865         enum port port;
 866
 867         DRM_DEBUG_KMS("\n");
 868
 869         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
 870         intel_panel_disable_backlight(old_conn_state);
 871
 872         /*
 873          * According to the spec we should send SHUTDOWN before
 874          * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
 875          * has shown that the v3 sequence works for v2 VBTs too
 876          */
 877         if (is_vid_mode(intel_dsi)) {
 878                 /* Send Shutdown command to the panel in LP mode */
 879                 for_each_dsi_port(port, intel_dsi->ports)
 880                         dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
 881                 msleep(10);
 882         }
 883 }
 884
 885 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 886 {
 887         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 888
 889         if (IS_GEMINILAKE(dev_priv))
 890                 glk_dsi_clear_device_ready(encoder);
 891         else
 892                 vlv_dsi_clear_device_ready(encoder);
 893 }
 894
 895 static void intel_dsi_post_disable(struct intel_encoder *encoder,
 896                                    const struct intel_crtc_state *pipe_config,
 897                                    const struct drm_connector_state *conn_state)
 898 {
 899         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 900         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 901         enum port port;
 902         u32 val;
 903
 904         DRM_DEBUG_KMS("\n");
 905
 906         if (is_vid_mode(intel_dsi)) {
 907                 for_each_dsi_port(port, intel_dsi->ports)
 908                         vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
 909
 910                 intel_dsi_port_disable(encoder);
 911                 usleep_range(2000, 5000);
 912         }
 913
 914         intel_dsi_unprepare(encoder);
 915
 916         /*
 917          * if disable packets are sent before sending shutdown packet then in
 918          * some next enable sequence send turn on packet error is observed
 919          */
 920         if (is_cmd_mode(intel_dsi))
 921                 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
 922         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 923
 924         /* Transition to LP-00 */
 925         intel_dsi_clear_device_ready(encoder);
 926
 927         if (IS_BROXTON(dev_priv)) {
 928                 /* Power down DSI regulator to save power */
 929                 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
 930                 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
 931
 932                 /* Add MIPI IO reset programming for modeset */
 933                 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
 934                 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
 935                                 val & ~MIPIO_RST_CTRL);
 936         }
 937
 938         if (IS_GEN9_LP(dev_priv)) {
 939                 bxt_dsi_pll_disable(encoder);
 940         } else {
 941                 u32 val;
 942
 943                 vlv_dsi_pll_disable(encoder);
 944
 945                 val = I915_READ(DSPCLK_GATE_D);
 946                 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
 947                 I915_WRITE(DSPCLK_GATE_D, val);
 948         }
 949
 950         /* Assert reset */
 951         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 952
 953         /* Power off, try both CRC pmic gpio and VBT */
 954         intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
 955         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 956         if (intel_dsi->gpio_panel)
 957                 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 958
 959         /*
 960          * FIXME As we do with eDP, just make a note of the time here
 961          * and perform the wait before the next panel power on.
 962          */
 963         intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 964 }
 965
 966 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 967                                    enum pipe *pipe)
 968 {
 969         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 970         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 971         intel_wakeref_t wakeref;
 972         enum port port;
 973         bool active = false;
 974
 975         DRM_DEBUG_KMS("\n");
 976
 977         wakeref = intel_display_power_get_if_enabled(dev_priv,
 978                                                      encoder->power_domain);
 979         if (!wakeref)
 980                 return false;
 981
 982         /*
 983          * On Broxton the PLL needs to be enabled with a valid divider
 984          * configuration, otherwise accessing DSI registers will hang the
 985          * machine. See BSpec North Display Engine registers/MIPI[BXT].
 986          */
 987         if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv))
 988                 goto out_put_power;
 989
 990         /* XXX: this only works for one DSI output */
 991         for_each_dsi_port(port, intel_dsi->ports) {
 992                 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
 993                         BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
 994                 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 995
 996                 /*
 997                  * Due to some hardware limitations on VLV/CHV, the DPI enable
 998                  * bit in port C control register does not get set. As a
 999                  * workaround, check pipe B conf instead.
1000                  */
1001                 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1002                     port == PORT_C)
1003                         enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1004
1005                 /* Try command mode if video mode not enabled */
1006                 if (!enabled) {
1007                         u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1008                         enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1009                 }
1010
1011                 if (!enabled)
1012                         continue;
1013
1014                 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1015                         continue;
1016
1017                 if (IS_GEN9_LP(dev_priv)) {
1018                         u32 tmp = I915_READ(MIPI_CTRL(port));
1019                         tmp &= BXT_PIPE_SELECT_MASK;
1020                         tmp >>= BXT_PIPE_SELECT_SHIFT;
1021
1022                         if (WARN_ON(tmp > PIPE_C))
1023                                 continue;
1024
1025                         *pipe = tmp;
1026                 } else {
1027                         *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1028                 }
1029
1030                 active = true;
1031                 break;
1032         }
1033
1034 out_put_power:
1035         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1036
1037         return active;
1038 }
1039
1040 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1041                                     struct intel_crtc_state *pipe_config)
1042 {
1043         struct drm_device *dev = encoder->base.dev;
1044         struct drm_i915_private *dev_priv = to_i915(dev);
1045         struct drm_display_mode *adjusted_mode =
1046                                         &pipe_config->base.adjusted_mode;
1047         struct drm_display_mode *adjusted_mode_sw;
1048         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1049         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1050         unsigned int lane_count = intel_dsi->lane_count;
1051         unsigned int bpp, fmt;
1052         enum port port;
1053         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1054         u16 hfp_sw, hsync_sw, hbp_sw;
1055         u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1056                                 crtc_hblank_start_sw, crtc_hblank_end_sw;
1057
1058         /* FIXME: hw readout should not depend on SW state */
1059         adjusted_mode_sw = &crtc->config->base.adjusted_mode;
1060
1061         /*
1062          * Atleast one port is active as encoder->get_config called only if
1063          * encoder->get_hw_state() returns true.
1064          */
1065         for_each_dsi_port(port, intel_dsi->ports) {
1066                 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1067                         break;
1068         }
1069
1070         fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1071         bpp = mipi_dsi_pixel_format_to_bpp(
1072                         pixel_format_from_register_bits(fmt));
1073
1074         /* Enable Frame time stamo based scanline reporting */
1075         adjusted_mode->private_flags |=
1076                         I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1077
1078         /* In terms of pixels */
1079         adjusted_mode->crtc_hdisplay =
1080                                 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1081         adjusted_mode->crtc_vdisplay =
1082                                 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1083         adjusted_mode->crtc_vtotal =
1084                                 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1085
1086         hactive = adjusted_mode->crtc_hdisplay;
1087         hfp = I915_READ(MIPI_HFP_COUNT(port));
1088
1089         /*
1090          * Meaningful for video mode non-burst sync pulse mode only,
1091          * can be zero for non-burst sync events and burst modes
1092          */
1093         hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1094         hbp = I915_READ(MIPI_HBP_COUNT(port));
1095
1096         /* harizontal values are in terms of high speed byte clock */
1097         hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1098                                                 intel_dsi->burst_mode_ratio);
1099         hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1100                                                 intel_dsi->burst_mode_ratio);
1101         hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1102                                                 intel_dsi->burst_mode_ratio);
1103
1104         if (intel_dsi->dual_link) {
1105                 hfp *= 2;
1106                 hsync *= 2;
1107                 hbp *= 2;
1108         }
1109
1110         /* vertical values are in terms of lines */
1111         vfp = I915_READ(MIPI_VFP_COUNT(port));
1112         vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1113         vbp = I915_READ(MIPI_VBP_COUNT(port));
1114
1115         adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1116         adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1117         adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1118         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1119         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1120
1121         adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1122         adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1123         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1124         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1125
1126         /*
1127          * In BXT DSI there is no regs programmed with few horizontal timings
1128          * in Pixels but txbyteclkhs.. So retrieval process adds some
1129          * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1130          * Actually here for the given adjusted_mode, we are calculating the
1131          * value programmed to the port and then back to the horizontal timing
1132          * param in pixels. This is the expected value, including roundup errors
1133          * And if that is same as retrieved value from port, then
1134          * (HW state) adjusted_mode's horizontal timings are corrected to
1135          * match with SW state to nullify the errors.
1136          */
1137         /* Calculating the value programmed to the Port register */
1138         hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1139                                         adjusted_mode_sw->crtc_hdisplay;
1140         hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1141                                         adjusted_mode_sw->crtc_hsync_start;
1142         hbp_sw = adjusted_mode_sw->crtc_htotal -
1143                                         adjusted_mode_sw->crtc_hsync_end;
1144
1145         if (intel_dsi->dual_link) {
1146                 hfp_sw /= 2;
1147                 hsync_sw /= 2;
1148                 hbp_sw /= 2;
1149         }
1150
1151         hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1152                                                 intel_dsi->burst_mode_ratio);
1153         hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1154                             intel_dsi->burst_mode_ratio);
1155         hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1156                                                 intel_dsi->burst_mode_ratio);
1157
1158         /* Reverse calculating the adjusted mode parameters from port reg vals*/
1159         hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1160                                                 intel_dsi->burst_mode_ratio);
1161         hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1162                                                 intel_dsi->burst_mode_ratio);
1163         hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1164                                                 intel_dsi->burst_mode_ratio);
1165
1166         if (intel_dsi->dual_link) {
1167                 hfp_sw *= 2;
1168                 hsync_sw *= 2;
1169                 hbp_sw *= 2;
1170         }
1171
1172         crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1173                                                         hsync_sw + hbp_sw;
1174         crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1175         crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1176         crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1177         crtc_hblank_end_sw = crtc_htotal_sw;
1178
1179         if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1180                 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1181
1182         if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1183                 adjusted_mode->crtc_hsync_start =
1184                                         adjusted_mode_sw->crtc_hsync_start;
1185
1186         if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1187                 adjusted_mode->crtc_hsync_end =
1188                                         adjusted_mode_sw->crtc_hsync_end;
1189
1190         if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1191                 adjusted_mode->crtc_hblank_start =
1192                                         adjusted_mode_sw->crtc_hblank_start;
1193
1194         if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1195                 adjusted_mode->crtc_hblank_end =
1196                                         adjusted_mode_sw->crtc_hblank_end;
1197 }
1198
1199 static void intel_dsi_get_config(struct intel_encoder *encoder,
1200                                  struct intel_crtc_state *pipe_config)
1201 {
1202         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1203         u32 pclk;
1204         DRM_DEBUG_KMS("\n");
1205
1206         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1207
1208         if (IS_GEN9_LP(dev_priv)) {
1209                 bxt_dsi_get_pipe_config(encoder, pipe_config);
1210                 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1211         } else {
1212                 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1213         }
1214
1215         if (pclk) {
1216                 pipe_config->base.adjusted_mode.crtc_clock = pclk;
1217                 pipe_config->port_clock = pclk;
1218         }
1219 }
1220
1221 /* return txclkesc cycles in terms of divider and duration in us */
1222 static u16 txclkesc(u32 divider, unsigned int us)
1223 {
1224         switch (divider) {
1225         case ESCAPE_CLOCK_DIVIDER_1:
1226         default:
1227                 return 20 * us;
1228         case ESCAPE_CLOCK_DIVIDER_2:
1229                 return 10 * us;
1230         case ESCAPE_CLOCK_DIVIDER_4:
1231                 return 5 * us;
1232         }
1233 }
1234
1235 static void set_dsi_timings(struct drm_encoder *encoder,
1236                             const struct drm_display_mode *adjusted_mode)
1237 {
1238         struct drm_device *dev = encoder->dev;
1239         struct drm_i915_private *dev_priv = to_i915(dev);
1240         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1241         enum port port;
1242         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1243         unsigned int lane_count = intel_dsi->lane_count;
1244
1245         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1246
1247         hactive = adjusted_mode->crtc_hdisplay;
1248         hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1249         hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1250         hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1251
1252         if (intel_dsi->dual_link) {
1253                 hactive /= 2;
1254                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1255                         hactive += intel_dsi->pixel_overlap;
1256                 hfp /= 2;
1257                 hsync /= 2;
1258                 hbp /= 2;
1259         }
1260
1261         vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1262         vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1263         vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1264
1265         /* horizontal values are in terms of high speed byte clock */
1266         hactive = txbyteclkhs(hactive, bpp, lane_count,
1267                               intel_dsi->burst_mode_ratio);
1268         hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1269         hsync = txbyteclkhs(hsync, bpp, lane_count,
1270                             intel_dsi->burst_mode_ratio);
1271         hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1272
1273         for_each_dsi_port(port, intel_dsi->ports) {
1274                 if (IS_GEN9_LP(dev_priv)) {
1275                         /*
1276                          * Program hdisplay and vdisplay on MIPI transcoder.
1277                          * This is different from calculated hactive and
1278                          * vactive, as they are calculated per channel basis,
1279                          * whereas these values should be based on resolution.
1280                          */
1281                         I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1282                                    adjusted_mode->crtc_hdisplay);
1283                         I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1284                                    adjusted_mode->crtc_vdisplay);
1285                         I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1286                                    adjusted_mode->crtc_vtotal);
1287                 }
1288
1289                 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1290                 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1291
1292                 /* meaningful for video mode non-burst sync pulse mode only,
1293                  * can be zero for non-burst sync events and burst modes */
1294                 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1295                 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1296
1297                 /* vertical values are in terms of lines */
1298                 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1299                 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1300                 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1301         }
1302 }
1303
1304 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1305 {
1306         switch (fmt) {
1307         case MIPI_DSI_FMT_RGB888:
1308                 return VID_MODE_FORMAT_RGB888;
1309         case MIPI_DSI_FMT_RGB666:
1310                 return VID_MODE_FORMAT_RGB666;
1311         case MIPI_DSI_FMT_RGB666_PACKED:
1312                 return VID_MODE_FORMAT_RGB666_PACKED;
1313         case MIPI_DSI_FMT_RGB565:
1314                 return VID_MODE_FORMAT_RGB565;
1315         default:
1316                 MISSING_CASE(fmt);
1317                 return VID_MODE_FORMAT_RGB666;
1318         }
1319 }
1320
1321 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1322                               const struct intel_crtc_state *pipe_config)
1323 {
1324         struct drm_encoder *encoder = &intel_encoder->base;
1325         struct drm_device *dev = encoder->dev;
1326         struct drm_i915_private *dev_priv = to_i915(dev);
1327         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1328         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1329         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1330         enum port port;
1331         unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1332         u32 val, tmp;
1333         u16 mode_hdisplay;
1334
1335         DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1336
1337         mode_hdisplay = adjusted_mode->crtc_hdisplay;
1338
1339         if (intel_dsi->dual_link) {
1340                 mode_hdisplay /= 2;
1341                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1342                         mode_hdisplay += intel_dsi->pixel_overlap;
1343         }
1344
1345         for_each_dsi_port(port, intel_dsi->ports) {
1346                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1347                         /*
1348                          * escape clock divider, 20MHz, shared for A and C.
1349                          * device ready must be off when doing this! txclkesc?
1350                          */
1351                         tmp = I915_READ(MIPI_CTRL(PORT_A));
1352                         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1353                         I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1354                                         ESCAPE_CLOCK_DIVIDER_1);
1355
1356                         /* read request priority is per pipe */
1357                         tmp = I915_READ(MIPI_CTRL(port));
1358                         tmp &= ~READ_REQUEST_PRIORITY_MASK;
1359                         I915_WRITE(MIPI_CTRL(port), tmp |
1360                                         READ_REQUEST_PRIORITY_HIGH);
1361                 } else if (IS_GEN9_LP(dev_priv)) {
1362                         enum pipe pipe = intel_crtc->pipe;
1363
1364                         tmp = I915_READ(MIPI_CTRL(port));
1365                         tmp &= ~BXT_PIPE_SELECT_MASK;
1366
1367                         tmp |= BXT_PIPE_SELECT(pipe);
1368                         I915_WRITE(MIPI_CTRL(port), tmp);
1369                 }
1370
1371                 /* XXX: why here, why like this? handling in irq handler?! */
1372                 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1373                 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1374
1375                 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1376
1377                 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1378                         adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1379                         mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1380         }
1381
1382         set_dsi_timings(encoder, adjusted_mode);
1383
1384         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1385         if (is_cmd_mode(intel_dsi)) {
1386                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1387                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1388         } else {
1389                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1390                 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1391         }
1392
1393         tmp = 0;
1394         if (intel_dsi->eotp_pkt == 0)
1395                 tmp |= EOT_DISABLE;
1396         if (intel_dsi->clock_stop)
1397                 tmp |= CLOCKSTOP;
1398
1399         if (IS_GEN9_LP(dev_priv)) {
1400                 tmp |= BXT_DPHY_DEFEATURE_EN;
1401                 if (!is_cmd_mode(intel_dsi))
1402                         tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1403         }
1404
1405         for_each_dsi_port(port, intel_dsi->ports) {
1406                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1407
1408                 /* timeouts for recovery. one frame IIUC. if counter expires,
1409                  * EOT and stop state. */
1410
1411                 /*
1412                  * In burst mode, value greater than one DPI line Time in byte
1413                  * clock (txbyteclkhs) To timeout this timer 1+ of the above
1414                  * said value is recommended.
1415                  *
1416                  * In non-burst mode, Value greater than one DPI frame time in
1417                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1418                  * said value is recommended.
1419                  *
1420                  * In DBI only mode, value greater than one DBI frame time in
1421                  * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1422                  * said value is recommended.
1423                  */
1424
1425                 if (is_vid_mode(intel_dsi) &&
1426                         intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1427                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1428                                 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1429                                             intel_dsi->lane_count,
1430                                             intel_dsi->burst_mode_ratio) + 1);
1431                 } else {
1432                         I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1433                                 txbyteclkhs(adjusted_mode->crtc_vtotal *
1434                                             adjusted_mode->crtc_htotal,
1435                                             bpp, intel_dsi->lane_count,
1436                                             intel_dsi->burst_mode_ratio) + 1);
1437                 }
1438                 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1439                 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1440                                                 intel_dsi->turn_arnd_val);
1441                 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1442                                                 intel_dsi->rst_timer_val);
1443
1444                 /* dphy stuff */
1445
1446                 /* in terms of low power clock */
1447                 I915_WRITE(MIPI_INIT_COUNT(port),
1448                                 txclkesc(intel_dsi->escape_clk_div, 100));
1449
1450                 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1451                         /*
1452                          * BXT spec says write MIPI_INIT_COUNT for
1453                          * both the ports, even if only one is
1454                          * getting used. So write the other port
1455                          * if not in dual link mode.
1456                          */
1457                         I915_WRITE(MIPI_INIT_COUNT(port ==
1458                                                 PORT_A ? PORT_C : PORT_A),
1459                                         intel_dsi->init_count);
1460                 }
1461
1462                 /* recovery disables */
1463                 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1464
1465                 /* in terms of low power clock */
1466                 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1467
1468                 /* in terms of txbyteclkhs. actual high to low switch +
1469                  * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1470                  *
1471                  * XXX: write MIPI_STOP_STATE_STALL?
1472                  */
1473                 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1474                                                 intel_dsi->hs_to_lp_count);
1475
1476                 /* XXX: low power clock equivalence in terms of byte clock.
1477                  * the number of byte clocks occupied in one low power clock.
1478                  * based on txbyteclkhs and txclkesc.
1479                  * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1480                  * ) / 105.???
1481                  */
1482                 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1483
1484                 if (IS_GEMINILAKE(dev_priv)) {
1485                         I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1486                                         intel_dsi->lp_byte_clk);
1487                         /* Shadow of DPHY reg */
1488                         I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1489                                         intel_dsi->dphy_reg);
1490                 }
1491
1492                 /* the bw essential for transmitting 16 long packets containing
1493                  * 252 bytes meant for dcs write memory command is programmed in
1494                  * this register in terms of byte clocks. based on dsi transfer
1495                  * rate and the number of lanes configured the time taken to
1496                  * transmit 16 long packets in a dsi stream varies. */
1497                 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1498
1499                 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1500                 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1501                 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1502
1503                 if (is_vid_mode(intel_dsi))
1504                         /* Some panels might have resolution which is not a
1505                          * multiple of 64 like 1366 x 768. Enable RANDOM
1506                          * resolution support for such panels by default */
1507                         I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1508                                 intel_dsi->video_frmt_cfg_bits |
1509                                 intel_dsi->video_mode_format |
1510                                 IP_TG_CONFIG |
1511                                 RANDOM_DPI_DISPLAY_RESOLUTION);
1512         }
1513 }
1514
1515 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1516 {
1517         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1518         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1519         enum port port;
1520         u32 val;
1521
1522         if (IS_GEMINILAKE(dev_priv))
1523                 return;
1524
1525         for_each_dsi_port(port, intel_dsi->ports) {
1526                 /* Panel commands can be sent when clock is in LP11 */
1527                 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1528
1529                 if (IS_GEN9_LP(dev_priv))
1530                         bxt_dsi_reset_clocks(encoder, port);
1531                 else
1532                         vlv_dsi_reset_clocks(encoder, port);
1533                 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1534
1535                 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1536                 val &= ~VID_MODE_FORMAT_MASK;
1537                 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1538
1539                 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1540         }
1541 }
1542
1543 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1544 {
1545         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1546
1547         /* dispose of the gpios */
1548         if (intel_dsi->gpio_panel)
1549                 gpiod_put(intel_dsi->gpio_panel);
1550
1551         intel_encoder_destroy(encoder);
1552 }
1553
1554 static const struct drm_encoder_funcs intel_dsi_funcs = {
1555         .destroy = intel_dsi_encoder_destroy,
1556 };
1557
1558 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1559         .get_modes = intel_dsi_get_modes,
1560         .mode_valid = intel_dsi_mode_valid,
1561         .atomic_check = intel_digital_connector_atomic_check,
1562 };
1563
1564 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1565         .late_register = intel_connector_register,
1566         .early_unregister = intel_connector_unregister,
1567         .destroy = intel_connector_destroy,
1568         .fill_modes = drm_helper_probe_single_connector_modes,
1569         .atomic_get_property = intel_digital_connector_atomic_get_property,
1570         .atomic_set_property = intel_digital_connector_atomic_set_property,
1571         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1572         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1573 };
1574
1575 static enum drm_panel_orientation
1576 vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector)
1577 {
1578         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1579         struct intel_encoder *encoder = connector->encoder;
1580         enum intel_display_power_domain power_domain;
1581         enum drm_panel_orientation orientation;
1582         struct intel_plane *plane;
1583         struct intel_crtc *crtc;
1584         intel_wakeref_t wakeref;
1585         enum pipe pipe;
1586         u32 val;
1587
1588         if (!encoder->get_hw_state(encoder, &pipe))
1589                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1590
1591         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1592         plane = to_intel_plane(crtc->base.primary);
1593
1594         power_domain = POWER_DOMAIN_PIPE(pipe);
1595         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1596         if (!wakeref)
1597                 return DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1598
1599         val = I915_READ(DSPCNTR(plane->i9xx_plane));
1600
1601         if (!(val & DISPLAY_PLANE_ENABLE))
1602                 orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
1603         else if (val & DISPPLANE_ROTATE_180)
1604                 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1605         else
1606                 orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1607
1608         intel_display_power_put(dev_priv, power_domain, wakeref);
1609
1610         return orientation;
1611 }
1612
1613 static enum drm_panel_orientation
1614 vlv_dsi_get_panel_orientation(struct intel_connector *connector)
1615 {
1616         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1617         enum drm_panel_orientation orientation;
1618
1619         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1620                 orientation = vlv_dsi_get_hw_panel_orientation(connector);
1621                 if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
1622                         return orientation;
1623         }
1624
1625         return intel_dsi_get_panel_orientation(connector);
1626 }
1627
1628 static void intel_dsi_add_properties(struct intel_connector *connector)
1629 {
1630         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1631
1632         if (connector->panel.fixed_mode) {
1633                 u32 allowed_scalers;
1634
1635                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1636                 if (!HAS_GMCH(dev_priv))
1637                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1638
1639                 drm_connector_attach_scaling_mode_property(&connector->base,
1640                                                                 allowed_scalers);
1641
1642                 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1643
1644                 connector->base.display_info.panel_orientation =
1645                         vlv_dsi_get_panel_orientation(connector);
1646                 drm_connector_init_panel_orientation_property(
1647                                 &connector->base,
1648                                 connector->panel.fixed_mode->hdisplay,
1649                                 connector->panel.fixed_mode->vdisplay);
1650         }
1651 }
1652
1653 void vlv_dsi_init(struct drm_i915_private *dev_priv)
1654 {
1655         struct drm_device *dev = &dev_priv->drm;
1656         struct intel_dsi *intel_dsi;
1657         struct intel_encoder *intel_encoder;
1658         struct drm_encoder *encoder;
1659         struct intel_connector *intel_connector;
1660         struct drm_connector *connector;
1661         struct drm_display_mode *scan, *fixed_mode = NULL;
1662         enum port port;
1663
1664         DRM_DEBUG_KMS("\n");
1665
1666         /* There is no detection method for MIPI so rely on VBT */
1667         if (!intel_bios_is_dsi_present(dev_priv, &port))
1668                 return;
1669
1670         if (IS_GEN9_LP(dev_priv))
1671                 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1672         else
1673                 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1674
1675         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1676         if (!intel_dsi)
1677                 return;
1678
1679         intel_connector = intel_connector_alloc();
1680         if (!intel_connector) {
1681                 kfree(intel_dsi);
1682                 return;
1683         }
1684
1685         intel_encoder = &intel_dsi->base;
1686         encoder = &intel_encoder->base;
1687         intel_dsi->attached_connector = intel_connector;
1688
1689         connector = &intel_connector->base;
1690
1691         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1692                          "DSI %c", port_name(port));
1693
1694         intel_encoder->compute_config = intel_dsi_compute_config;
1695         intel_encoder->pre_enable = intel_dsi_pre_enable;
1696         intel_encoder->disable = intel_dsi_disable;
1697         intel_encoder->post_disable = intel_dsi_post_disable;
1698         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1699         intel_encoder->get_config = intel_dsi_get_config;
1700         intel_encoder->update_pipe = intel_panel_update_backlight;
1701
1702         intel_connector->get_hw_state = intel_connector_get_hw_state;
1703
1704         intel_encoder->port = port;
1705
1706         /*
1707          * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1708          * port C. BXT isn't limited like this.
1709          */
1710         if (IS_GEN9_LP(dev_priv))
1711                 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1712         else if (port == PORT_A)
1713                 intel_encoder->crtc_mask = BIT(PIPE_A);
1714         else
1715                 intel_encoder->crtc_mask = BIT(PIPE_B);
1716
1717         if (dev_priv->vbt.dsi.config->dual_link)
1718                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1719         else
1720                 intel_dsi->ports = BIT(port);
1721
1722         intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1723         intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1724
1725         /* Create a DSI host (and a device) for each port. */
1726         for_each_dsi_port(port, intel_dsi->ports) {
1727                 struct intel_dsi_host *host;
1728
1729                 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1730                                            port);
1731                 if (!host)
1732                         goto err;
1733
1734                 intel_dsi->dsi_hosts[port] = host;
1735         }
1736
1737         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1738                 DRM_DEBUG_KMS("no device found\n");
1739                 goto err;
1740         }
1741
1742         /*
1743          * In case of BYT with CRC PMIC, we need to use GPIO for
1744          * Panel control.
1745          */
1746         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1747             (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1748                 intel_dsi->gpio_panel =
1749                         gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1750
1751                 if (IS_ERR(intel_dsi->gpio_panel)) {
1752                         DRM_ERROR("Failed to own gpio for panel control\n");
1753                         intel_dsi->gpio_panel = NULL;
1754                 }
1755         }
1756
1757         intel_encoder->type = INTEL_OUTPUT_DSI;
1758         intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1759         intel_encoder->cloneable = 0;
1760         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1761                            DRM_MODE_CONNECTOR_DSI);
1762
1763         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1764
1765         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1766         connector->interlace_allowed = false;
1767         connector->doublescan_allowed = false;
1768
1769         intel_connector_attach_encoder(intel_connector, intel_encoder);
1770
1771         mutex_lock(&dev->mode_config.mutex);
1772         intel_dsi_vbt_get_modes(intel_dsi);
1773         list_for_each_entry(scan, &connector->probed_modes, head) {
1774                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1775                         fixed_mode = drm_mode_duplicate(dev, scan);
1776                         break;
1777                 }
1778         }
1779         mutex_unlock(&dev->mode_config.mutex);
1780
1781         if (!fixed_mode) {
1782                 DRM_DEBUG_KMS("no fixed mode\n");
1783                 goto err;
1784         }
1785
1786         connector->display_info.width_mm = fixed_mode->width_mm;
1787         connector->display_info.height_mm = fixed_mode->height_mm;
1788
1789         intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
1790         intel_panel_setup_backlight(connector, INVALID_PIPE);
1791
1792         intel_dsi_add_properties(intel_connector);
1793
1794         return;
1795
1796 err:
1797         drm_encoder_cleanup(&intel_encoder->base);
1798         kfree(intel_dsi);
1799         kfree(intel_connector);
1800 }