drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /**************************************************************************
   3  *
   4  * Copyright 2009-2020 VMware, Inc., Palo Alto, CA., USA
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include <linux/sched/signal.h>
  29
  30 #include <drm/ttm/ttm_placement.h>
  31
  32 #include "vmwgfx_drv.h"
  33
  34 struct vmw_temp_set_context {
  35         SVGA3dCmdHeader header;
  36         SVGA3dCmdDXTempSetContext body;
  37 };
  38
  39 bool vmw_supports_3d(struct vmw_private *dev_priv)
  40 {
  41         uint32_t fifo_min, hwversion;
  42         const struct vmw_fifo_state *fifo = &dev_priv->fifo;
  43
  44         if (!(dev_priv->capabilities & SVGA_CAP_3D))
  45                 return false;
  46
  47         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
  48                 uint32_t result;
  49
  50                 if (!dev_priv->has_mob)
  51                         return false;
  52
  53                 spin_lock(&dev_priv->cap_lock);
  54                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
  55                 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
  56                 spin_unlock(&dev_priv->cap_lock);
  57
  58                 return (result != 0);
  59         }
  60
  61         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  62                 return false;
  63
  64         fifo_min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
  65         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  66                 return false;
  67
  68         hwversion = vmw_fifo_mem_read(dev_priv,
  69                                       ((fifo->capabilities &
  70                                         SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
  71                                                SVGA_FIFO_3D_HWVERSION_REVISED :
  72                                                SVGA_FIFO_3D_HWVERSION));
  73
  74         if (hwversion == 0)
  75                 return false;
  76
  77         if (hwversion < SVGA3D_HWVERSION_WS8_B1)
  78                 return false;
  79
  80         /* Legacy Display Unit does not support surfaces */
  81         if (dev_priv->active_display_unit == vmw_du_legacy)
  82                 return false;
  83
  84         return true;
  85 }
  86
  87 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  88 {
  89         uint32_t caps;
  90
  91         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  92                 return false;
  93
  94         caps = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);
  95         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  96                 return true;
  97
  98         return false;
  99 }
 100
 101 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 102 {
 103         uint32_t max;
 104         uint32_t min;
 105
 106         fifo->dx = false;
 107         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
 108         fifo->static_buffer = vmalloc(fifo->static_buffer_size);
 109         if (unlikely(fifo->static_buffer == NULL))
 110                 return -ENOMEM;
 111
 112         fifo->dynamic_buffer = NULL;
 113         fifo->reserved_size = 0;
 114         fifo->using_bounce_buffer = false;
 115
 116         mutex_init(&fifo->fifo_mutex);
 117         init_rwsem(&fifo->rwsem);
 118
 119         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
 120         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
 121         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
 122
 123         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
 124         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
 125         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 126
 127         vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
 128                   SVGA_REG_ENABLE_HIDE);
 129
 130         vmw_write(dev_priv, SVGA_REG_TRACES, 0);
 131
 132         min = 4;
 133         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
 134                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
 135         min <<= 2;
 136
 137         if (min < PAGE_SIZE)
 138                 min = PAGE_SIZE;
 139
 140         vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MIN, min);
 141         vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size);
 142         wmb();
 143         vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, min);
 144         vmw_fifo_mem_write(dev_priv, SVGA_FIFO_STOP, min);
 145         vmw_fifo_mem_write(dev_priv, SVGA_FIFO_BUSY, 0);
 146         mb();
 147
 148         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
 149
 150         max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
 151         min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
 152         fifo->capabilities = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);
 153
 154         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
 155                  (unsigned int) max,
 156                  (unsigned int) min,
 157                  (unsigned int) fifo->capabilities);
 158
 159         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
 160         vmw_fifo_mem_write(dev_priv, SVGA_FIFO_FENCE, dev_priv->last_read_seqno);
 161
 162         return 0;
 163 }
 164
 165 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 166 {
 167         u32 *fifo_mem = dev_priv->fifo_mem;
 168
 169         if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0)
 170                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 171 }
 172
 173 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 174 {
 175         vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 176         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 177                 ;
 178
 179         dev_priv->last_read_seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
 180
 181         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
 182                   dev_priv->config_done_state);
 183         vmw_write(dev_priv, SVGA_REG_ENABLE,
 184                   dev_priv->enable_state);
 185         vmw_write(dev_priv, SVGA_REG_TRACES,
 186                   dev_priv->traces_state);
 187
 188         if (likely(fifo->static_buffer != NULL)) {
 189                 vfree(fifo->static_buffer);
 190                 fifo->static_buffer = NULL;
 191         }
 192
 193         if (likely(fifo->dynamic_buffer != NULL)) {
 194                 vfree(fifo->dynamic_buffer);
 195                 fifo->dynamic_buffer = NULL;
 196         }
 197 }
 198
 199 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
 200 {
 201         uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
 202         uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
 203         uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
 204         uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);
 205
 206         return ((max - next_cmd) + (stop - min) <= bytes);
 207 }
 208
 209 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
 210                                uint32_t bytes, bool interruptible,
 211                                unsigned long timeout)
 212 {
 213         int ret = 0;
 214         unsigned long end_jiffies = jiffies + timeout;
 215         DEFINE_WAIT(__wait);
 216
 217         DRM_INFO("Fifo wait noirq.\n");
 218
 219         for (;;) {
 220                 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
 221                                 (interruptible) ?
 222                                 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
 223                 if (!vmw_fifo_is_full(dev_priv, bytes))
 224                         break;
 225                 if (time_after_eq(jiffies, end_jiffies)) {
 226                         ret = -EBUSY;
 227                         DRM_ERROR("SVGA device lockup.\n");
 228                         break;
 229                 }
 230                 schedule_timeout(1);
 231                 if (interruptible && signal_pending(current)) {
 232                         ret = -ERESTARTSYS;
 233                         break;
 234                 }
 235         }
 236         finish_wait(&dev_priv->fifo_queue, &__wait);
 237         wake_up_all(&dev_priv->fifo_queue);
 238         DRM_INFO("Fifo noirq exit.\n");
 239         return ret;
 240 }
 241
 242 static int vmw_fifo_wait(struct vmw_private *dev_priv,
 243                          uint32_t bytes, bool interruptible,
 244                          unsigned long timeout)
 245 {
 246         long ret = 1L;
 247
 248         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
 249                 return 0;
 250
 251         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
 252         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
 253                 return vmw_fifo_wait_noirq(dev_priv, bytes,
 254                                            interruptible, timeout);
 255
 256         vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
 257                                &dev_priv->fifo_queue_waiters);
 258
 259         if (interruptible)
 260                 ret = wait_event_interruptible_timeout
 261                     (dev_priv->fifo_queue,
 262                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 263         else
 264                 ret = wait_event_timeout
 265                     (dev_priv->fifo_queue,
 266                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 267
 268         if (unlikely(ret == 0))
 269                 ret = -EBUSY;
 270         else if (likely(ret > 0))
 271                 ret = 0;
 272
 273         vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS,
 274                                   &dev_priv->fifo_queue_waiters);
 275
 276         return ret;
 277 }
 278
 279 /*
 280  * Reserve @bytes number of bytes in the fifo.
 281  *
 282  * This function will return NULL (error) on two conditions:
 283  *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 284  *   available fifo space.
 285  *
 286  * Returns:
 287  *   Pointer to the fifo, or null on error (possible hardware hang).
 288  */
 289 static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,
 290                                     uint32_t bytes)
 291 {
 292         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 293         u32  *fifo_mem = dev_priv->fifo_mem;
 294         uint32_t max;
 295         uint32_t min;
 296         uint32_t next_cmd;
 297         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 298         int ret;
 299
 300         mutex_lock(&fifo_state->fifo_mutex);
 301         max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
 302         min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
 303         next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
 304
 305         if (unlikely(bytes >= (max - min)))
 306                 goto out_err;
 307
 308         BUG_ON(fifo_state->reserved_size != 0);
 309         BUG_ON(fifo_state->dynamic_buffer != NULL);
 310
 311         fifo_state->reserved_size = bytes;
 312
 313         while (1) {
 314                 uint32_t stop = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_STOP);
 315                 bool need_bounce = false;
 316                 bool reserve_in_place = false;
 317
 318                 if (next_cmd >= stop) {
 319                         if (likely((next_cmd + bytes < max ||
 320                                     (next_cmd + bytes == max && stop > min))))
 321                                 reserve_in_place = true;
 322
 323                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
 324                                 ret = vmw_fifo_wait(dev_priv, bytes,
 325                                                     false, 3 * HZ);
 326                                 if (unlikely(ret != 0))
 327                                         goto out_err;
 328                         } else
 329                                 need_bounce = true;
 330
 331                 } else {
 332
 333                         if (likely((next_cmd + bytes < stop)))
 334                                 reserve_in_place = true;
 335                         else {
 336                                 ret = vmw_fifo_wait(dev_priv, bytes,
 337                                                     false, 3 * HZ);
 338                                 if (unlikely(ret != 0))
 339                                         goto out_err;
 340                         }
 341                 }
 342
 343                 if (reserve_in_place) {
 344                         if (reserveable || bytes <= sizeof(uint32_t)) {
 345                                 fifo_state->using_bounce_buffer = false;
 346
 347                                 if (reserveable)
 348                                         vmw_fifo_mem_write(dev_priv,
 349                                                            SVGA_FIFO_RESERVED,
 350                                                            bytes);
 351                                 return (void __force *) (fifo_mem +
 352                                                          (next_cmd >> 2));
 353                         } else {
 354                                 need_bounce = true;
 355                         }
 356                 }
 357
 358                 if (need_bounce) {
 359                         fifo_state->using_bounce_buffer = true;
 360                         if (bytes < fifo_state->static_buffer_size)
 361                                 return fifo_state->static_buffer;
 362                         else {
 363                                 fifo_state->dynamic_buffer = vmalloc(bytes);
 364                                 if (!fifo_state->dynamic_buffer)
 365                                         goto out_err;
 366                                 return fifo_state->dynamic_buffer;
 367                         }
 368                 }
 369         }
 370 out_err:
 371         fifo_state->reserved_size = 0;
 372         mutex_unlock(&fifo_state->fifo_mutex);
 373
 374         return NULL;
 375 }
 376
 377 void *vmw_cmd_ctx_reserve(struct vmw_private *dev_priv, uint32_t bytes,
 378                           int ctx_id)
 379 {
 380         void *ret;
 381
 382         if (dev_priv->cman)
 383                 ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,
 384                                          ctx_id, false, NULL);
 385         else if (ctx_id == SVGA3D_INVALID_ID)
 386                 ret = vmw_local_fifo_reserve(dev_priv, bytes);
 387         else {
 388                 WARN(1, "Command buffer has not been allocated.\n");
 389                 ret = NULL;
 390         }
 391         if (IS_ERR_OR_NULL(ret))
 392                 return NULL;
 393
 394         return ret;
 395 }
 396
 397 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
 398                               struct vmw_private *vmw,
 399                               uint32_t next_cmd,
 400                               uint32_t max, uint32_t min, uint32_t bytes)
 401 {
 402         u32 *fifo_mem = vmw->fifo_mem;
 403         uint32_t chunk_size = max - next_cmd;
 404         uint32_t rest;
 405         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 406             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 407
 408         if (bytes < chunk_size)
 409                 chunk_size = bytes;
 410
 411         vmw_fifo_mem_write(vmw, SVGA_FIFO_RESERVED, bytes);
 412         mb();
 413         memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
 414         rest = bytes - chunk_size;
 415         if (rest)
 416                 memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest);
 417 }
 418
 419 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
 420                                struct vmw_private *vmw,
 421                                uint32_t next_cmd,
 422                                uint32_t max, uint32_t min, uint32_t bytes)
 423 {
 424         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 425             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 426
 427         while (bytes > 0) {
 428                 vmw_fifo_mem_write(vmw, (next_cmd >> 2), *buffer++);
 429                 next_cmd += sizeof(uint32_t);
 430                 if (unlikely(next_cmd == max))
 431                         next_cmd = min;
 432                 mb();
 433                 vmw_fifo_mem_write(vmw, SVGA_FIFO_NEXT_CMD, next_cmd);
 434                 mb();
 435                 bytes -= sizeof(uint32_t);
 436         }
 437 }
 438
 439 static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 440 {
 441         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 442         uint32_t next_cmd = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_NEXT_CMD);
 443         uint32_t max = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MAX);
 444         uint32_t min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
 445         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 446
 447         if (fifo_state->dx)
 448                 bytes += sizeof(struct vmw_temp_set_context);
 449
 450         fifo_state->dx = false;
 451         BUG_ON((bytes & 3) != 0);
 452         BUG_ON(bytes > fifo_state->reserved_size);
 453
 454         fifo_state->reserved_size = 0;
 455
 456         if (fifo_state->using_bounce_buffer) {
 457                 if (reserveable)
 458                         vmw_fifo_res_copy(fifo_state, dev_priv,
 459                                           next_cmd, max, min, bytes);
 460                 else
 461                         vmw_fifo_slow_copy(fifo_state, dev_priv,
 462                                            next_cmd, max, min, bytes);
 463
 464                 if (fifo_state->dynamic_buffer) {
 465                         vfree(fifo_state->dynamic_buffer);
 466                         fifo_state->dynamic_buffer = NULL;
 467                 }
 468
 469         }
 470
 471         down_write(&fifo_state->rwsem);
 472         if (fifo_state->using_bounce_buffer || reserveable) {
 473                 next_cmd += bytes;
 474                 if (next_cmd >= max)
 475                         next_cmd -= max - min;
 476                 mb();
 477                 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_NEXT_CMD, next_cmd);
 478         }
 479
 480         if (reserveable)
 481                 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_RESERVED, 0);
 482         mb();
 483         up_write(&fifo_state->rwsem);
 484         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
 485         mutex_unlock(&fifo_state->fifo_mutex);
 486 }
 487
 488 void vmw_cmd_commit(struct vmw_private *dev_priv, uint32_t bytes)
 489 {
 490         if (dev_priv->cman)
 491                 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
 492         else
 493                 vmw_local_fifo_commit(dev_priv, bytes);
 494 }
 495
 496
 497 /**
 498  * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands.
 499  *
 500  * @dev_priv: Pointer to device private structure.
 501  * @bytes: Number of bytes to commit.
 502  */
 503 void vmw_cmd_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
 504 {
 505         if (dev_priv->cman)
 506                 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
 507         else
 508                 vmw_local_fifo_commit(dev_priv, bytes);
 509 }
 510
 511 /**
 512  * vmw_fifo_flush - Flush any buffered commands and make sure command processing
 513  * starts.
 514  *
 515  * @dev_priv: Pointer to device private structure.
 516  * @interruptible: Whether to wait interruptible if function needs to sleep.
 517  */
 518 int vmw_cmd_flush(struct vmw_private *dev_priv, bool interruptible)
 519 {
 520         might_sleep();
 521
 522         if (dev_priv->cman)
 523                 return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);
 524         else
 525                 return 0;
 526 }
 527
 528 int vmw_cmd_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
 529 {
 530         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 531         struct svga_fifo_cmd_fence *cmd_fence;
 532         u32 *fm;
 533         int ret = 0;
 534         uint32_t bytes = sizeof(u32) + sizeof(*cmd_fence);
 535
 536         fm = VMW_CMD_RESERVE(dev_priv, bytes);
 537         if (unlikely(fm == NULL)) {
 538                 *seqno = atomic_read(&dev_priv->marker_seq);
 539                 ret = -ENOMEM;
 540                 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
 541                                         false, 3*HZ);
 542                 goto out_err;
 543         }
 544
 545         do {
 546                 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
 547         } while (*seqno == 0);
 548
 549         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
 550
 551                 /*
 552                  * Don't request hardware to send a fence. The
 553                  * waiting code in vmwgfx_irq.c will emulate this.
 554                  */
 555
 556                 vmw_cmd_commit(dev_priv, 0);
 557                 return 0;
 558         }
 559
 560         *fm++ = SVGA_CMD_FENCE;
 561         cmd_fence = (struct svga_fifo_cmd_fence *) fm;
 562         cmd_fence->fence = *seqno;
 563         vmw_cmd_commit_flush(dev_priv, bytes);
 564         vmw_update_seqno(dev_priv, fifo_state);
 565
 566 out_err:
 567         return ret;
 568 }
 569
 570 /**
 571  * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
 572  * legacy query commands.
 573  *
 574  * @dev_priv: The device private structure.
 575  * @cid: The hardware context id used for the query.
 576  *
 577  * See the vmw_fifo_emit_dummy_query documentation.
 578  */
 579 static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
 580                                             uint32_t cid)
 581 {
 582         /*
 583          * A query wait without a preceding query end will
 584          * actually finish all queries for this cid
 585          * without writing to the query result structure.
 586          */
 587
 588         struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
 589         struct {
 590                 SVGA3dCmdHeader header;
 591                 SVGA3dCmdWaitForQuery body;
 592         } *cmd;
 593
 594         cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
 595         if (unlikely(cmd == NULL))
 596                 return -ENOMEM;
 597
 598         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
 599         cmd->header.size = sizeof(cmd->body);
 600         cmd->body.cid = cid;
 601         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 602
 603         if (bo->mem.mem_type == TTM_PL_VRAM) {
 604                 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
 605                 cmd->body.guestResult.offset = bo->mem.start << PAGE_SHIFT;
 606         } else {
 607                 cmd->body.guestResult.gmrId = bo->mem.start;
 608                 cmd->body.guestResult.offset = 0;
 609         }
 610
 611         vmw_cmd_commit(dev_priv, sizeof(*cmd));
 612
 613         return 0;
 614 }
 615
 616 /**
 617  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 618  * guest-backed resource query commands.
 619  *
 620  * @dev_priv: The device private structure.
 621  * @cid: The hardware context id used for the query.
 622  *
 623  * See the vmw_fifo_emit_dummy_query documentation.
 624  */
 625 static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
 626                                         uint32_t cid)
 627 {
 628         /*
 629          * A query wait without a preceding query end will
 630          * actually finish all queries for this cid
 631          * without writing to the query result structure.
 632          */
 633
 634         struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
 635         struct {
 636                 SVGA3dCmdHeader header;
 637                 SVGA3dCmdWaitForGBQuery body;
 638         } *cmd;
 639
 640         cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
 641         if (unlikely(cmd == NULL))
 642                 return -ENOMEM;
 643
 644         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
 645         cmd->header.size = sizeof(cmd->body);
 646         cmd->body.cid = cid;
 647         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 648         BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
 649         cmd->body.mobid = bo->mem.start;
 650         cmd->body.offset = 0;
 651
 652         vmw_cmd_commit(dev_priv, sizeof(*cmd));
 653
 654         return 0;
 655 }
 656
 657
 658 /**
 659  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 660  * appropriate resource query commands.
 661  *
 662  * @dev_priv: The device private structure.
 663  * @cid: The hardware context id used for the query.
 664  *
 665  * This function is used to emit a dummy occlusion query with
 666  * no primitives rendered between query begin and query end.
 667  * It's used to provide a query barrier, in order to know that when
 668  * this query is finished, all preceding queries are also finished.
 669  *
 670  * A Query results structure should have been initialized at the start
 671  * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 672  * must also be either reserved or pinned when this function is called.
 673  *
 674  * Returns -ENOMEM on failure to reserve fifo space.
 675  */
 676 int vmw_cmd_emit_dummy_query(struct vmw_private *dev_priv,
 677                               uint32_t cid)
 678 {
 679         if (dev_priv->has_mob)
 680                 return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
 681
 682         return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
 683 }