drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/kthread.h>
  27 #include <linux/pci.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_pm.h"
  33 #include "amdgpu_dm_debugfs.h"
  34 #include "amdgpu_ras.h"
  35 #include "amdgpu_rap.h"
  36 #include "amdgpu_securedisplay.h"
  37 #include "amdgpu_fw_attestation.h"
  38 #include "amdgpu_umr.h"
  39
  40 #include "amdgpu_reset.h"
  41 #include "amdgpu_psp_ta.h"
  42
  43 #if defined(CONFIG_DEBUG_FS)
  44
  45 /**
  46  * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes
  47  *
  48  * @read: True if reading
  49  * @f: open file handle
  50  * @buf: User buffer to write/read to
  51  * @size: Number of bytes to write/read
  52  * @pos:  Offset to seek to
  53  *
  54  * This debugfs entry has special meaning on the offset being sought.
  55  * Various bits have different meanings:
  56  *
  57  * Bit 62:  Indicates a GRBM bank switch is needed
  58  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
  59  *          zero)
  60  * Bits 24..33: The SE or ME selector if needed
  61  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  62  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  63  *
  64  * Bit 23:  Indicates that the PM power gating lock should be held
  65  *          This is necessary to read registers that might be
  66  *          unreliable during a power gating transistion.
  67  *
  68  * The lower bits are the BYTE offset of the register to read.  This
  69  * allows reading multiple registers in a single call and having
  70  * the returned size reflect that.
  71  */
  72 static int  amdgpu_debugfs_process_reg_op(bool read, struct file *f,
  73                 char __user *buf, size_t size, loff_t *pos)
  74 {
  75         struct amdgpu_device *adev = file_inode(f)->i_private;
  76         ssize_t result = 0;
  77         int r;
  78         bool pm_pg_lock, use_bank, use_ring;
  79         unsigned int instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
  80
  81         pm_pg_lock = use_bank = use_ring = false;
  82         instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
  83
  84         if (size & 0x3 || *pos & 0x3 ||
  85                         ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
  86                 return -EINVAL;
  87
  88         /* are we reading registers for which a PG lock is necessary? */
  89         pm_pg_lock = (*pos >> 23) & 1;
  90
  91         if (*pos & (1ULL << 62)) {
  92                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
  93                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
  94                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
  95
  96                 if (se_bank == 0x3FF)
  97                         se_bank = 0xFFFFFFFF;
  98                 if (sh_bank == 0x3FF)
  99                         sh_bank = 0xFFFFFFFF;
 100                 if (instance_bank == 0x3FF)
 101                         instance_bank = 0xFFFFFFFF;
 102                 use_bank = true;
 103         } else if (*pos & (1ULL << 61)) {
 104
 105                 me = (*pos & GENMASK_ULL(33, 24)) >> 24;
 106                 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
 107                 queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
 108                 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54;
 109
 110                 use_ring = true;
 111         } else {
 112                 use_bank = use_ring = false;
 113         }
 114
 115         *pos &= (1UL << 22) - 1;
 116
 117         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 118         if (r < 0) {
 119                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 120                 return r;
 121         }
 122
 123         r = amdgpu_virt_enable_access_debugfs(adev);
 124         if (r < 0) {
 125                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 126                 return r;
 127         }
 128
 129         if (use_bank) {
 130                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
 131                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
 132                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 133                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 134                         amdgpu_virt_disable_access_debugfs(adev);
 135                         return -EINVAL;
 136                 }
 137                 mutex_lock(&adev->grbm_idx_mutex);
 138                 amdgpu_gfx_select_se_sh(adev, se_bank,
 139                                         sh_bank, instance_bank, 0);
 140         } else if (use_ring) {
 141                 mutex_lock(&adev->srbm_mutex);
 142                 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid, 0);
 143         }
 144
 145         if (pm_pg_lock)
 146                 mutex_lock(&adev->pm.mutex);
 147
 148         while (size) {
 149                 uint32_t value;
 150
 151                 if (read) {
 152                         value = RREG32(*pos >> 2);
 153                         r = put_user(value, (uint32_t *)buf);
 154                 } else {
 155                         r = get_user(value, (uint32_t *)buf);
 156                         if (!r)
 157                                 amdgpu_mm_wreg_mmio_rlc(adev, *pos >> 2, value, 0);
 158                 }
 159                 if (r) {
 160                         result = r;
 161                         goto end;
 162                 }
 163
 164                 result += 4;
 165                 buf += 4;
 166                 *pos += 4;
 167                 size -= 4;
 168         }
 169
 170 end:
 171         if (use_bank) {
 172                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
 173                 mutex_unlock(&adev->grbm_idx_mutex);
 174         } else if (use_ring) {
 175                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, 0);
 176                 mutex_unlock(&adev->srbm_mutex);
 177         }
 178
 179         if (pm_pg_lock)
 180                 mutex_unlock(&adev->pm.mutex);
 181
 182         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 183         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 184
 185         amdgpu_virt_disable_access_debugfs(adev);
 186         return result;
 187 }
 188
 189 /*
 190  * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
 191  */
 192 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
 193                                         size_t size, loff_t *pos)
 194 {
 195         return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
 196 }
 197
 198 /*
 199  * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
 200  */
 201 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
 202                                          size_t size, loff_t *pos)
 203 {
 204         return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
 205 }
 206
 207 static int amdgpu_debugfs_regs2_open(struct inode *inode, struct file *file)
 208 {
 209         struct amdgpu_debugfs_regs2_data *rd;
 210
 211         rd = kzalloc(sizeof(*rd), GFP_KERNEL);
 212         if (!rd)
 213                 return -ENOMEM;
 214         rd->adev = file_inode(file)->i_private;
 215         file->private_data = rd;
 216         mutex_init(&rd->lock);
 217
 218         return 0;
 219 }
 220
 221 static int amdgpu_debugfs_regs2_release(struct inode *inode, struct file *file)
 222 {
 223         struct amdgpu_debugfs_regs2_data *rd = file->private_data;
 224
 225         mutex_destroy(&rd->lock);
 226         kfree(file->private_data);
 227         return 0;
 228 }
 229
 230 static ssize_t amdgpu_debugfs_regs2_op(struct file *f, char __user *buf, u32 offset, size_t size, int write_en)
 231 {
 232         struct amdgpu_debugfs_regs2_data *rd = f->private_data;
 233         struct amdgpu_device *adev = rd->adev;
 234         ssize_t result = 0;
 235         int r;
 236         uint32_t value;
 237
 238         if (size & 0x3 || offset & 0x3)
 239                 return -EINVAL;
 240
 241         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 242         if (r < 0) {
 243                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 244                 return r;
 245         }
 246
 247         r = amdgpu_virt_enable_access_debugfs(adev);
 248         if (r < 0) {
 249                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 250                 return r;
 251         }
 252
 253         mutex_lock(&rd->lock);
 254
 255         if (rd->id.use_grbm) {
 256                 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||
 257                     (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {
 258                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 259                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 260                         amdgpu_virt_disable_access_debugfs(adev);
 261                         mutex_unlock(&rd->lock);
 262                         return -EINVAL;
 263                 }
 264                 mutex_lock(&adev->grbm_idx_mutex);
 265                 amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se,
 266                                                   rd->id.grbm.sh,
 267                                                   rd->id.grbm.instance, rd->id.xcc_id);
 268         }
 269
 270         if (rd->id.use_srbm) {
 271                 mutex_lock(&adev->srbm_mutex);
 272                 amdgpu_gfx_select_me_pipe_q(adev, rd->id.srbm.me, rd->id.srbm.pipe,
 273                                             rd->id.srbm.queue, rd->id.srbm.vmid, rd->id.xcc_id);
 274         }
 275
 276         if (rd->id.pg_lock)
 277                 mutex_lock(&adev->pm.mutex);
 278
 279         while (size) {
 280                 if (!write_en) {
 281                         value = RREG32(offset >> 2);
 282                         r = put_user(value, (uint32_t *)buf);
 283                 } else {
 284                         r = get_user(value, (uint32_t *)buf);
 285                         if (!r)
 286                                 amdgpu_mm_wreg_mmio_rlc(adev, offset >> 2, value, rd->id.xcc_id);
 287                 }
 288                 if (r) {
 289                         result = r;
 290                         goto end;
 291                 }
 292                 offset += 4;
 293                 size -= 4;
 294                 result += 4;
 295                 buf += 4;
 296         }
 297 end:
 298         if (rd->id.use_grbm) {
 299                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, rd->id.xcc_id);
 300                 mutex_unlock(&adev->grbm_idx_mutex);
 301         }
 302
 303         if (rd->id.use_srbm) {
 304                 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, rd->id.xcc_id);
 305                 mutex_unlock(&adev->srbm_mutex);
 306         }
 307
 308         if (rd->id.pg_lock)
 309                 mutex_unlock(&adev->pm.mutex);
 310
 311         mutex_unlock(&rd->lock);
 312
 313         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 314         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 315
 316         amdgpu_virt_disable_access_debugfs(adev);
 317         return result;
 318 }
 319
 320 static long amdgpu_debugfs_regs2_ioctl(struct file *f, unsigned int cmd, unsigned long data)
 321 {
 322         struct amdgpu_debugfs_regs2_data *rd = f->private_data;
 323         struct amdgpu_debugfs_regs2_iocdata v1_data;
 324         int r;
 325
 326         mutex_lock(&rd->lock);
 327
 328         switch (cmd) {
 329         case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2:
 330                 r = copy_from_user(&rd->id, (struct amdgpu_debugfs_regs2_iocdata_v2 *)data,
 331                                    sizeof(rd->id));
 332                 if (r)
 333                         r = -EINVAL;
 334                 goto done;
 335         case AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE:
 336                 r = copy_from_user(&v1_data, (struct amdgpu_debugfs_regs2_iocdata *)data,
 337                                    sizeof(v1_data));
 338                 if (r) {
 339                         r = -EINVAL;
 340                         goto done;
 341                 }
 342                 goto v1_copy;
 343         default:
 344                 r = -EINVAL;
 345                 goto done;
 346         }
 347
 348 v1_copy:
 349         rd->id.use_srbm = v1_data.use_srbm;
 350         rd->id.use_grbm = v1_data.use_grbm;
 351         rd->id.pg_lock = v1_data.pg_lock;
 352         rd->id.grbm.se = v1_data.grbm.se;
 353         rd->id.grbm.sh = v1_data.grbm.sh;
 354         rd->id.grbm.instance = v1_data.grbm.instance;
 355         rd->id.srbm.me = v1_data.srbm.me;
 356         rd->id.srbm.pipe = v1_data.srbm.pipe;
 357         rd->id.srbm.queue = v1_data.srbm.queue;
 358         rd->id.xcc_id = 0;
 359 done:
 360         mutex_unlock(&rd->lock);
 361         return r;
 362 }
 363
 364 static ssize_t amdgpu_debugfs_regs2_read(struct file *f, char __user *buf, size_t size, loff_t *pos)
 365 {
 366         return amdgpu_debugfs_regs2_op(f, buf, *pos, size, 0);
 367 }
 368
 369 static ssize_t amdgpu_debugfs_regs2_write(struct file *f, const char __user *buf, size_t size, loff_t *pos)
 370 {
 371         return amdgpu_debugfs_regs2_op(f, (char __user *)buf, *pos, size, 1);
 372 }
 373
 374 static int amdgpu_debugfs_gprwave_open(struct inode *inode, struct file *file)
 375 {
 376         struct amdgpu_debugfs_gprwave_data *rd;
 377
 378         rd = kzalloc(sizeof(*rd), GFP_KERNEL);
 379         if (!rd)
 380                 return -ENOMEM;
 381         rd->adev = file_inode(file)->i_private;
 382         file->private_data = rd;
 383         mutex_init(&rd->lock);
 384
 385         return 0;
 386 }
 387
 388 static int amdgpu_debugfs_gprwave_release(struct inode *inode, struct file *file)
 389 {
 390         struct amdgpu_debugfs_gprwave_data *rd = file->private_data;
 391
 392         mutex_destroy(&rd->lock);
 393         kfree(file->private_data);
 394         return 0;
 395 }
 396
 397 static ssize_t amdgpu_debugfs_gprwave_read(struct file *f, char __user *buf, size_t size, loff_t *pos)
 398 {
 399         struct amdgpu_debugfs_gprwave_data *rd = f->private_data;
 400         struct amdgpu_device *adev = rd->adev;
 401         ssize_t result = 0;
 402         int r;
 403         uint32_t *data, x;
 404
 405         if (size & 0x3 || *pos & 0x3)
 406                 return -EINVAL;
 407
 408         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 409         if (r < 0) {
 410                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 411                 return r;
 412         }
 413
 414         r = amdgpu_virt_enable_access_debugfs(adev);
 415         if (r < 0) {
 416                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 417                 return r;
 418         }
 419
 420         data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
 421         if (!data) {
 422                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 423                 amdgpu_virt_disable_access_debugfs(adev);
 424                 return -ENOMEM;
 425         }
 426
 427         /* switch to the specific se/sh/cu */
 428         mutex_lock(&adev->grbm_idx_mutex);
 429         amdgpu_gfx_select_se_sh(adev, rd->id.se, rd->id.sh, rd->id.cu, rd->id.xcc_id);
 430
 431         if (!rd->id.gpr_or_wave) {
 432                 x = 0;
 433                 if (adev->gfx.funcs->read_wave_data)
 434                         adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x);
 435         } else {
 436                 x = size >> 2;
 437                 if (rd->id.gpr.vpgr_or_sgpr) {
 438                         if (adev->gfx.funcs->read_wave_vgprs)
 439                                 adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data);
 440                 } else {
 441                         if (adev->gfx.funcs->read_wave_sgprs)
 442                                 adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, data);
 443                 }
 444         }
 445
 446         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, rd->id.xcc_id);
 447         mutex_unlock(&adev->grbm_idx_mutex);
 448
 449         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 450         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 451
 452         if (!x) {
 453                 result = -EINVAL;
 454                 goto done;
 455         }
 456
 457         while (size && (*pos < x * 4)) {
 458                 uint32_t value;
 459
 460                 value = data[*pos >> 2];
 461                 r = put_user(value, (uint32_t *)buf);
 462                 if (r) {
 463                         result = r;
 464                         goto done;
 465                 }
 466
 467                 result += 4;
 468                 buf += 4;
 469                 *pos += 4;
 470                 size -= 4;
 471         }
 472
 473 done:
 474         amdgpu_virt_disable_access_debugfs(adev);
 475         kfree(data);
 476         return result;
 477 }
 478
 479 static long amdgpu_debugfs_gprwave_ioctl(struct file *f, unsigned int cmd, unsigned long data)
 480 {
 481         struct amdgpu_debugfs_gprwave_data *rd = f->private_data;
 482         int r = 0;
 483
 484         mutex_lock(&rd->lock);
 485
 486         switch (cmd) {
 487         case AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE:
 488                 if (copy_from_user(&rd->id,
 489                                    (struct amdgpu_debugfs_gprwave_iocdata *)data,
 490                                    sizeof(rd->id)))
 491                         r = -EFAULT;
 492                 goto done;
 493         default:
 494                 r = -EINVAL;
 495                 goto done;
 496         }
 497
 498 done:
 499         mutex_unlock(&rd->lock);
 500         return r;
 501 }
 502
 503
 504
 505
 506 /**
 507  * amdgpu_debugfs_regs_pcie_read - Read from a PCIE register
 508  *
 509  * @f: open file handle
 510  * @buf: User buffer to store read data in
 511  * @size: Number of bytes to read
 512  * @pos:  Offset to seek to
 513  *
 514  * The lower bits are the BYTE offset of the register to read.  This
 515  * allows reading multiple registers in a single call and having
 516  * the returned size reflect that.
 517  */
 518 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
 519                                         size_t size, loff_t *pos)
 520 {
 521         struct amdgpu_device *adev = file_inode(f)->i_private;
 522         ssize_t result = 0;
 523         int r;
 524
 525         if (size & 0x3 || *pos & 0x3)
 526                 return -EINVAL;
 527
 528         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 529         if (r < 0) {
 530                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 531                 return r;
 532         }
 533
 534         r = amdgpu_virt_enable_access_debugfs(adev);
 535         if (r < 0) {
 536                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 537                 return r;
 538         }
 539
 540         while (size) {
 541                 uint32_t value;
 542
 543                 value = RREG32_PCIE(*pos);
 544                 r = put_user(value, (uint32_t *)buf);
 545                 if (r)
 546                         goto out;
 547
 548                 result += 4;
 549                 buf += 4;
 550                 *pos += 4;
 551                 size -= 4;
 552         }
 553
 554         r = result;
 555 out:
 556         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 557         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 558         amdgpu_virt_disable_access_debugfs(adev);
 559         return r;
 560 }
 561
 562 /**
 563  * amdgpu_debugfs_regs_pcie_write - Write to a PCIE register
 564  *
 565  * @f: open file handle
 566  * @buf: User buffer to write data from
 567  * @size: Number of bytes to write
 568  * @pos:  Offset to seek to
 569  *
 570  * The lower bits are the BYTE offset of the register to write.  This
 571  * allows writing multiple registers in a single call and having
 572  * the returned size reflect that.
 573  */
 574 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
 575                                          size_t size, loff_t *pos)
 576 {
 577         struct amdgpu_device *adev = file_inode(f)->i_private;
 578         ssize_t result = 0;
 579         int r;
 580
 581         if (size & 0x3 || *pos & 0x3)
 582                 return -EINVAL;
 583
 584         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 585         if (r < 0) {
 586                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 587                 return r;
 588         }
 589
 590         r = amdgpu_virt_enable_access_debugfs(adev);
 591         if (r < 0) {
 592                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 593                 return r;
 594         }
 595
 596         while (size) {
 597                 uint32_t value;
 598
 599                 r = get_user(value, (uint32_t *)buf);
 600                 if (r)
 601                         goto out;
 602
 603                 WREG32_PCIE(*pos, value);
 604
 605                 result += 4;
 606                 buf += 4;
 607                 *pos += 4;
 608                 size -= 4;
 609         }
 610
 611         r = result;
 612 out:
 613         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 614         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 615         amdgpu_virt_disable_access_debugfs(adev);
 616         return r;
 617 }
 618
 619 /**
 620  * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
 621  *
 622  * @f: open file handle
 623  * @buf: User buffer to store read data in
 624  * @size: Number of bytes to read
 625  * @pos:  Offset to seek to
 626  *
 627  * The lower bits are the BYTE offset of the register to read.  This
 628  * allows reading multiple registers in a single call and having
 629  * the returned size reflect that.
 630  */
 631 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
 632                                         size_t size, loff_t *pos)
 633 {
 634         struct amdgpu_device *adev = file_inode(f)->i_private;
 635         ssize_t result = 0;
 636         int r;
 637
 638         if (size & 0x3 || *pos & 0x3)
 639                 return -EINVAL;
 640
 641         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 642         if (r < 0) {
 643                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 644                 return r;
 645         }
 646
 647         r = amdgpu_virt_enable_access_debugfs(adev);
 648         if (r < 0) {
 649                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 650                 return r;
 651         }
 652
 653         while (size) {
 654                 uint32_t value;
 655
 656                 value = RREG32_DIDT(*pos >> 2);
 657                 r = put_user(value, (uint32_t *)buf);
 658                 if (r)
 659                         goto out;
 660
 661                 result += 4;
 662                 buf += 4;
 663                 *pos += 4;
 664                 size -= 4;
 665         }
 666
 667         r = result;
 668 out:
 669         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 670         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 671         amdgpu_virt_disable_access_debugfs(adev);
 672         return r;
 673 }
 674
 675 /**
 676  * amdgpu_debugfs_regs_didt_write - Write to a DIDT register
 677  *
 678  * @f: open file handle
 679  * @buf: User buffer to write data from
 680  * @size: Number of bytes to write
 681  * @pos:  Offset to seek to
 682  *
 683  * The lower bits are the BYTE offset of the register to write.  This
 684  * allows writing multiple registers in a single call and having
 685  * the returned size reflect that.
 686  */
 687 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
 688                                          size_t size, loff_t *pos)
 689 {
 690         struct amdgpu_device *adev = file_inode(f)->i_private;
 691         ssize_t result = 0;
 692         int r;
 693
 694         if (size & 0x3 || *pos & 0x3)
 695                 return -EINVAL;
 696
 697         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 698         if (r < 0) {
 699                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 700                 return r;
 701         }
 702
 703         r = amdgpu_virt_enable_access_debugfs(adev);
 704         if (r < 0) {
 705                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 706                 return r;
 707         }
 708
 709         while (size) {
 710                 uint32_t value;
 711
 712                 r = get_user(value, (uint32_t *)buf);
 713                 if (r)
 714                         goto out;
 715
 716                 WREG32_DIDT(*pos >> 2, value);
 717
 718                 result += 4;
 719                 buf += 4;
 720                 *pos += 4;
 721                 size -= 4;
 722         }
 723
 724         r = result;
 725 out:
 726         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 727         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 728         amdgpu_virt_disable_access_debugfs(adev);
 729         return r;
 730 }
 731
 732 /**
 733  * amdgpu_debugfs_regs_smc_read - Read from a SMC register
 734  *
 735  * @f: open file handle
 736  * @buf: User buffer to store read data in
 737  * @size: Number of bytes to read
 738  * @pos:  Offset to seek to
 739  *
 740  * The lower bits are the BYTE offset of the register to read.  This
 741  * allows reading multiple registers in a single call and having
 742  * the returned size reflect that.
 743  */
 744 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
 745                                         size_t size, loff_t *pos)
 746 {
 747         struct amdgpu_device *adev = file_inode(f)->i_private;
 748         ssize_t result = 0;
 749         int r;
 750
 751         if (size & 0x3 || *pos & 0x3)
 752                 return -EINVAL;
 753
 754         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 755         if (r < 0) {
 756                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 757                 return r;
 758         }
 759
 760         r = amdgpu_virt_enable_access_debugfs(adev);
 761         if (r < 0) {
 762                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 763                 return r;
 764         }
 765
 766         while (size) {
 767                 uint32_t value;
 768
 769                 value = RREG32_SMC(*pos);
 770                 r = put_user(value, (uint32_t *)buf);
 771                 if (r)
 772                         goto out;
 773
 774                 result += 4;
 775                 buf += 4;
 776                 *pos += 4;
 777                 size -= 4;
 778         }
 779
 780         r = result;
 781 out:
 782         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 783         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 784         amdgpu_virt_disable_access_debugfs(adev);
 785         return r;
 786 }
 787
 788 /**
 789  * amdgpu_debugfs_regs_smc_write - Write to a SMC register
 790  *
 791  * @f: open file handle
 792  * @buf: User buffer to write data from
 793  * @size: Number of bytes to write
 794  * @pos:  Offset to seek to
 795  *
 796  * The lower bits are the BYTE offset of the register to write.  This
 797  * allows writing multiple registers in a single call and having
 798  * the returned size reflect that.
 799  */
 800 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
 801                                          size_t size, loff_t *pos)
 802 {
 803         struct amdgpu_device *adev = file_inode(f)->i_private;
 804         ssize_t result = 0;
 805         int r;
 806
 807         if (size & 0x3 || *pos & 0x3)
 808                 return -EINVAL;
 809
 810         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 811         if (r < 0) {
 812                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 813                 return r;
 814         }
 815
 816         r = amdgpu_virt_enable_access_debugfs(adev);
 817         if (r < 0) {
 818                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 819                 return r;
 820         }
 821
 822         while (size) {
 823                 uint32_t value;
 824
 825                 r = get_user(value, (uint32_t *)buf);
 826                 if (r)
 827                         goto out;
 828
 829                 WREG32_SMC(*pos, value);
 830
 831                 result += 4;
 832                 buf += 4;
 833                 *pos += 4;
 834                 size -= 4;
 835         }
 836
 837         r = result;
 838 out:
 839         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 840         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 841         amdgpu_virt_disable_access_debugfs(adev);
 842         return r;
 843 }
 844
 845 /**
 846  * amdgpu_debugfs_gca_config_read - Read from gfx config data
 847  *
 848  * @f: open file handle
 849  * @buf: User buffer to store read data in
 850  * @size: Number of bytes to read
 851  * @pos:  Offset to seek to
 852  *
 853  * This file is used to access configuration data in a somewhat
 854  * stable fashion.  The format is a series of DWORDs with the first
 855  * indicating which revision it is.  New content is appended to the
 856  * end so that older software can still read the data.
 857  */
 858
 859 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
 860                                         size_t size, loff_t *pos)
 861 {
 862         struct amdgpu_device *adev = file_inode(f)->i_private;
 863         ssize_t result = 0;
 864         int r;
 865         uint32_t *config, no_regs = 0;
 866
 867         if (size & 0x3 || *pos & 0x3)
 868                 return -EINVAL;
 869
 870         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
 871         if (!config)
 872                 return -ENOMEM;
 873
 874         /* version, increment each time something is added */
 875         config[no_regs++] = 5;
 876         config[no_regs++] = adev->gfx.config.max_shader_engines;
 877         config[no_regs++] = adev->gfx.config.max_tile_pipes;
 878         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
 879         config[no_regs++] = adev->gfx.config.max_sh_per_se;
 880         config[no_regs++] = adev->gfx.config.max_backends_per_se;
 881         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
 882         config[no_regs++] = adev->gfx.config.max_gprs;
 883         config[no_regs++] = adev->gfx.config.max_gs_threads;
 884         config[no_regs++] = adev->gfx.config.max_hw_contexts;
 885         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
 886         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
 887         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
 888         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
 889         config[no_regs++] = adev->gfx.config.num_tile_pipes;
 890         config[no_regs++] = adev->gfx.config.backend_enable_mask;
 891         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
 892         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
 893         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
 894         config[no_regs++] = adev->gfx.config.num_gpus;
 895         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
 896         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
 897         config[no_regs++] = adev->gfx.config.gb_addr_config;
 898         config[no_regs++] = adev->gfx.config.num_rbs;
 899
 900         /* rev==1 */
 901         config[no_regs++] = adev->rev_id;
 902         config[no_regs++] = lower_32_bits(adev->pg_flags);
 903         config[no_regs++] = lower_32_bits(adev->cg_flags);
 904
 905         /* rev==2 */
 906         config[no_regs++] = adev->family;
 907         config[no_regs++] = adev->external_rev_id;
 908
 909         /* rev==3 */
 910         config[no_regs++] = adev->pdev->device;
 911         config[no_regs++] = adev->pdev->revision;
 912         config[no_regs++] = adev->pdev->subsystem_device;
 913         config[no_regs++] = adev->pdev->subsystem_vendor;
 914
 915         /* rev==4 APU flag */
 916         config[no_regs++] = adev->flags & AMD_IS_APU ? 1 : 0;
 917
 918         /* rev==5 PG/CG flag upper 32bit */
 919         config[no_regs++] = upper_32_bits(adev->pg_flags);
 920         config[no_regs++] = upper_32_bits(adev->cg_flags);
 921
 922         while (size && (*pos < no_regs * 4)) {
 923                 uint32_t value;
 924
 925                 value = config[*pos >> 2];
 926                 r = put_user(value, (uint32_t *)buf);
 927                 if (r) {
 928                         kfree(config);
 929                         return r;
 930                 }
 931
 932                 result += 4;
 933                 buf += 4;
 934                 *pos += 4;
 935                 size -= 4;
 936         }
 937
 938         kfree(config);
 939         return result;
 940 }
 941
 942 /**
 943  * amdgpu_debugfs_sensor_read - Read from the powerplay sensors
 944  *
 945  * @f: open file handle
 946  * @buf: User buffer to store read data in
 947  * @size: Number of bytes to read
 948  * @pos:  Offset to seek to
 949  *
 950  * The offset is treated as the BYTE address of one of the sensors
 951  * enumerated in amd/include/kgd_pp_interface.h under the
 952  * 'amd_pp_sensors' enumeration.  For instance to read the UVD VCLK
 953  * you would use the offset 3 * 4 = 12.
 954  */
 955 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
 956                                         size_t size, loff_t *pos)
 957 {
 958         struct amdgpu_device *adev = file_inode(f)->i_private;
 959         int idx, x, outsize, r, valuesize;
 960         uint32_t values[16];
 961
 962         if (size & 3 || *pos & 0x3)
 963                 return -EINVAL;
 964
 965         if (!adev->pm.dpm_enabled)
 966                 return -EINVAL;
 967
 968         /* convert offset to sensor number */
 969         idx = *pos >> 2;
 970
 971         valuesize = sizeof(values);
 972
 973         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
 974         if (r < 0) {
 975                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 976                 return r;
 977         }
 978
 979         r = amdgpu_virt_enable_access_debugfs(adev);
 980         if (r < 0) {
 981                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 982                 return r;
 983         }
 984
 985         r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
 986
 987         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 988         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
 989
 990         if (r) {
 991                 amdgpu_virt_disable_access_debugfs(adev);
 992                 return r;
 993         }
 994
 995         if (size > valuesize) {
 996                 amdgpu_virt_disable_access_debugfs(adev);
 997                 return -EINVAL;
 998         }
 999
1000         outsize = 0;
1001         x = 0;
1002         if (!r) {
1003                 while (size) {
1004                         r = put_user(values[x++], (int32_t *)buf);
1005                         buf += 4;
1006                         size -= 4;
1007                         outsize += 4;
1008                 }
1009         }
1010
1011         amdgpu_virt_disable_access_debugfs(adev);
1012         return !r ? outsize : r;
1013 }
1014
1015 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
1016  *
1017  * @f: open file handle
1018  * @buf: User buffer to store read data in
1019  * @size: Number of bytes to read
1020  * @pos:  Offset to seek to
1021  *
1022  * The offset being sought changes which wave that the status data
1023  * will be returned for.  The bits are used as follows:
1024  *
1025  * Bits 0..6:   Byte offset into data
1026  * Bits 7..14:  SE selector
1027  * Bits 15..22: SH/SA selector
1028  * Bits 23..30: CU/{WGP+SIMD} selector
1029  * Bits 31..36: WAVE ID selector
1030  * Bits 37..44: SIMD ID selector
1031  *
1032  * The returned data begins with one DWORD of version information
1033  * Followed by WAVE STATUS registers relevant to the GFX IP version
1034  * being used.  See gfx_v8_0_read_wave_data() for an example output.
1035  */
1036 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
1037                                         size_t size, loff_t *pos)
1038 {
1039         struct amdgpu_device *adev = f->f_inode->i_private;
1040         int r, x;
1041         ssize_t result = 0;
1042         uint32_t offset, se, sh, cu, wave, simd, data[32];
1043
1044         if (size & 3 || *pos & 3)
1045                 return -EINVAL;
1046
1047         /* decode offset */
1048         offset = (*pos & GENMASK_ULL(6, 0));
1049         se = (*pos & GENMASK_ULL(14, 7)) >> 7;
1050         sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
1051         cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
1052         wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
1053         simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
1054
1055         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1056         if (r < 0) {
1057                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1058                 return r;
1059         }
1060
1061         r = amdgpu_virt_enable_access_debugfs(adev);
1062         if (r < 0) {
1063                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1064                 return r;
1065         }
1066
1067         /* switch to the specific se/sh/cu */
1068         mutex_lock(&adev->grbm_idx_mutex);
1069         amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0);
1070
1071         x = 0;
1072         if (adev->gfx.funcs->read_wave_data)
1073                 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x);
1074
1075         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);
1076         mutex_unlock(&adev->grbm_idx_mutex);
1077
1078         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1079         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1080
1081         if (!x) {
1082                 amdgpu_virt_disable_access_debugfs(adev);
1083                 return -EINVAL;
1084         }
1085
1086         while (size && (offset < x * 4)) {
1087                 uint32_t value;
1088
1089                 value = data[offset >> 2];
1090                 r = put_user(value, (uint32_t *)buf);
1091                 if (r) {
1092                         amdgpu_virt_disable_access_debugfs(adev);
1093                         return r;
1094                 }
1095
1096                 result += 4;
1097                 buf += 4;
1098                 offset += 4;
1099                 size -= 4;
1100         }
1101
1102         amdgpu_virt_disable_access_debugfs(adev);
1103         return result;
1104 }
1105
1106 /** amdgpu_debugfs_gpr_read - Read wave gprs
1107  *
1108  * @f: open file handle
1109  * @buf: User buffer to store read data in
1110  * @size: Number of bytes to read
1111  * @pos:  Offset to seek to
1112  *
1113  * The offset being sought changes which wave that the status data
1114  * will be returned for.  The bits are used as follows:
1115  *
1116  * Bits 0..11:  Byte offset into data
1117  * Bits 12..19: SE selector
1118  * Bits 20..27: SH/SA selector
1119  * Bits 28..35: CU/{WGP+SIMD} selector
1120  * Bits 36..43: WAVE ID selector
1121  * Bits 37..44: SIMD ID selector
1122  * Bits 52..59: Thread selector
1123  * Bits 60..61: Bank selector (VGPR=0,SGPR=1)
1124  *
1125  * The return data comes from the SGPR or VGPR register bank for
1126  * the selected operational unit.
1127  */
1128 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
1129                                         size_t size, loff_t *pos)
1130 {
1131         struct amdgpu_device *adev = f->f_inode->i_private;
1132         int r;
1133         ssize_t result = 0;
1134         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
1135
1136         if (size > 4096 || size & 3 || *pos & 3)
1137                 return -EINVAL;
1138
1139         /* decode offset */
1140         offset = (*pos & GENMASK_ULL(11, 0)) >> 2;
1141         se = (*pos & GENMASK_ULL(19, 12)) >> 12;
1142         sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
1143         cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
1144         wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
1145         simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
1146         thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
1147         bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
1148
1149         data = kcalloc(1024, sizeof(*data), GFP_KERNEL);
1150         if (!data)
1151                 return -ENOMEM;
1152
1153         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1154         if (r < 0)
1155                 goto err;
1156
1157         r = amdgpu_virt_enable_access_debugfs(adev);
1158         if (r < 0)
1159                 goto err;
1160
1161         /* switch to the specific se/sh/cu */
1162         mutex_lock(&adev->grbm_idx_mutex);
1163         amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0);
1164
1165         if (bank == 0) {
1166                 if (adev->gfx.funcs->read_wave_vgprs)
1167                         adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data);
1168         } else {
1169                 if (adev->gfx.funcs->read_wave_sgprs)
1170                         adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data);
1171         }
1172
1173         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0);
1174         mutex_unlock(&adev->grbm_idx_mutex);
1175
1176         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1177         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1178
1179         while (size) {
1180                 uint32_t value;
1181
1182                 value = data[result >> 2];
1183                 r = put_user(value, (uint32_t *)buf);
1184                 if (r) {
1185                         amdgpu_virt_disable_access_debugfs(adev);
1186                         goto err;
1187                 }
1188
1189                 result += 4;
1190                 buf += 4;
1191                 size -= 4;
1192         }
1193
1194         kfree(data);
1195         amdgpu_virt_disable_access_debugfs(adev);
1196         return result;
1197
1198 err:
1199         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1200         kfree(data);
1201         return r;
1202 }
1203
1204 /**
1205  * amdgpu_debugfs_gfxoff_residency_read - Read GFXOFF residency
1206  *
1207  * @f: open file handle
1208  * @buf: User buffer to store read data in
1209  * @size: Number of bytes to read
1210  * @pos:  Offset to seek to
1211  *
1212  * Read the last residency value logged. It doesn't auto update, one needs to
1213  * stop logging before getting the current value.
1214  */
1215 static ssize_t amdgpu_debugfs_gfxoff_residency_read(struct file *f, char __user *buf,
1216                                                     size_t size, loff_t *pos)
1217 {
1218         struct amdgpu_device *adev = file_inode(f)->i_private;
1219         ssize_t result = 0;
1220         int r;
1221
1222         if (size & 0x3 || *pos & 0x3)
1223                 return -EINVAL;
1224
1225         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1226         if (r < 0) {
1227                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1228                 return r;
1229         }
1230
1231         while (size) {
1232                 uint32_t value;
1233
1234                 r = amdgpu_get_gfx_off_residency(adev, &value);
1235                 if (r)
1236                         goto out;
1237
1238                 r = put_user(value, (uint32_t *)buf);
1239                 if (r)
1240                         goto out;
1241
1242                 result += 4;
1243                 buf += 4;
1244                 *pos += 4;
1245                 size -= 4;
1246         }
1247
1248         r = result;
1249 out:
1250         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1251         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1252
1253         return r;
1254 }
1255
1256 /**
1257  * amdgpu_debugfs_gfxoff_residency_write - Log GFXOFF Residency
1258  *
1259  * @f: open file handle
1260  * @buf: User buffer to write data from
1261  * @size: Number of bytes to write
1262  * @pos:  Offset to seek to
1263  *
1264  * Write a 32-bit non-zero to start logging; write a 32-bit zero to stop
1265  */
1266 static ssize_t amdgpu_debugfs_gfxoff_residency_write(struct file *f, const char __user *buf,
1267                                                      size_t size, loff_t *pos)
1268 {
1269         struct amdgpu_device *adev = file_inode(f)->i_private;
1270         ssize_t result = 0;
1271         int r;
1272
1273         if (size & 0x3 || *pos & 0x3)
1274                 return -EINVAL;
1275
1276         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1277         if (r < 0) {
1278                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1279                 return r;
1280         }
1281
1282         while (size) {
1283                 u32 value;
1284
1285                 r = get_user(value, (uint32_t *)buf);
1286                 if (r)
1287                         goto out;
1288
1289                 amdgpu_set_gfx_off_residency(adev, value ? true : false);
1290
1291                 result += 4;
1292                 buf += 4;
1293                 *pos += 4;
1294                 size -= 4;
1295         }
1296
1297         r = result;
1298 out:
1299         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1300         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1301
1302         return r;
1303 }
1304
1305
1306 /**
1307  * amdgpu_debugfs_gfxoff_count_read - Read GFXOFF entry count
1308  *
1309  * @f: open file handle
1310  * @buf: User buffer to store read data in
1311  * @size: Number of bytes to read
1312  * @pos:  Offset to seek to
1313  */
1314 static ssize_t amdgpu_debugfs_gfxoff_count_read(struct file *f, char __user *buf,
1315                                                 size_t size, loff_t *pos)
1316 {
1317         struct amdgpu_device *adev = file_inode(f)->i_private;
1318         ssize_t result = 0;
1319         int r;
1320
1321         if (size & 0x3 || *pos & 0x3)
1322                 return -EINVAL;
1323
1324         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1325         if (r < 0) {
1326                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1327                 return r;
1328         }
1329
1330         while (size) {
1331                 u64 value = 0;
1332
1333                 r = amdgpu_get_gfx_off_entrycount(adev, &value);
1334                 if (r)
1335                         goto out;
1336
1337                 r = put_user(value, (u64 *)buf);
1338                 if (r)
1339                         goto out;
1340
1341                 result += 4;
1342                 buf += 4;
1343                 *pos += 4;
1344                 size -= 4;
1345         }
1346
1347         r = result;
1348 out:
1349         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1350         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1351
1352         return r;
1353 }
1354
1355 /**
1356  * amdgpu_debugfs_gfxoff_write - Enable/disable GFXOFF
1357  *
1358  * @f: open file handle
1359  * @buf: User buffer to write data from
1360  * @size: Number of bytes to write
1361  * @pos:  Offset to seek to
1362  *
1363  * Write a 32-bit zero to disable or a 32-bit non-zero to enable
1364  */
1365 static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *buf,
1366                                          size_t size, loff_t *pos)
1367 {
1368         struct amdgpu_device *adev = file_inode(f)->i_private;
1369         ssize_t result = 0;
1370         int r;
1371
1372         if (size & 0x3 || *pos & 0x3)
1373                 return -EINVAL;
1374
1375         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1376         if (r < 0) {
1377                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1378                 return r;
1379         }
1380
1381         while (size) {
1382                 uint32_t value;
1383
1384                 r = get_user(value, (uint32_t *)buf);
1385                 if (r)
1386                         goto out;
1387
1388                 amdgpu_gfx_off_ctrl(adev, value ? true : false);
1389
1390                 result += 4;
1391                 buf += 4;
1392                 *pos += 4;
1393                 size -= 4;
1394         }
1395
1396         r = result;
1397 out:
1398         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1399         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1400
1401         return r;
1402 }
1403
1404
1405 /**
1406  * amdgpu_debugfs_gfxoff_read - read gfxoff status
1407  *
1408  * @f: open file handle
1409  * @buf: User buffer to store read data in
1410  * @size: Number of bytes to read
1411  * @pos:  Offset to seek to
1412  */
1413 static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
1414                                          size_t size, loff_t *pos)
1415 {
1416         struct amdgpu_device *adev = file_inode(f)->i_private;
1417         ssize_t result = 0;
1418         int r;
1419
1420         if (size & 0x3 || *pos & 0x3)
1421                 return -EINVAL;
1422
1423         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1424         if (r < 0) {
1425                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1426                 return r;
1427         }
1428
1429         while (size) {
1430                 u32 value = adev->gfx.gfx_off_state;
1431
1432                 r = put_user(value, (u32 *)buf);
1433                 if (r)
1434                         goto out;
1435
1436                 result += 4;
1437                 buf += 4;
1438                 *pos += 4;
1439                 size -= 4;
1440         }
1441
1442         r = result;
1443 out:
1444         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1445         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1446
1447         return r;
1448 }
1449
1450 static ssize_t amdgpu_debugfs_gfxoff_status_read(struct file *f, char __user *buf,
1451                                                  size_t size, loff_t *pos)
1452 {
1453         struct amdgpu_device *adev = file_inode(f)->i_private;
1454         ssize_t result = 0;
1455         int r;
1456
1457         if (size & 0x3 || *pos & 0x3)
1458                 return -EINVAL;
1459
1460         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1461         if (r < 0) {
1462                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1463                 return r;
1464         }
1465
1466         while (size) {
1467                 u32 value;
1468
1469                 r = amdgpu_get_gfx_off_status(adev, &value);
1470                 if (r)
1471                         goto out;
1472
1473                 r = put_user(value, (u32 *)buf);
1474                 if (r)
1475                         goto out;
1476
1477                 result += 4;
1478                 buf += 4;
1479                 *pos += 4;
1480                 size -= 4;
1481         }
1482
1483         r = result;
1484 out:
1485         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1486         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1487
1488         return r;
1489 }
1490
1491 static const struct file_operations amdgpu_debugfs_regs2_fops = {
1492         .owner = THIS_MODULE,
1493         .unlocked_ioctl = amdgpu_debugfs_regs2_ioctl,
1494         .read = amdgpu_debugfs_regs2_read,
1495         .write = amdgpu_debugfs_regs2_write,
1496         .open = amdgpu_debugfs_regs2_open,
1497         .release = amdgpu_debugfs_regs2_release,
1498         .llseek = default_llseek
1499 };
1500
1501 static const struct file_operations amdgpu_debugfs_gprwave_fops = {
1502         .owner = THIS_MODULE,
1503         .unlocked_ioctl = amdgpu_debugfs_gprwave_ioctl,
1504         .read = amdgpu_debugfs_gprwave_read,
1505         .open = amdgpu_debugfs_gprwave_open,
1506         .release = amdgpu_debugfs_gprwave_release,
1507         .llseek = default_llseek
1508 };
1509
1510 static const struct file_operations amdgpu_debugfs_regs_fops = {
1511         .owner = THIS_MODULE,
1512         .read = amdgpu_debugfs_regs_read,
1513         .write = amdgpu_debugfs_regs_write,
1514         .llseek = default_llseek
1515 };
1516 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
1517         .owner = THIS_MODULE,
1518         .read = amdgpu_debugfs_regs_didt_read,
1519         .write = amdgpu_debugfs_regs_didt_write,
1520         .llseek = default_llseek
1521 };
1522 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
1523         .owner = THIS_MODULE,
1524         .read = amdgpu_debugfs_regs_pcie_read,
1525         .write = amdgpu_debugfs_regs_pcie_write,
1526         .llseek = default_llseek
1527 };
1528 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
1529         .owner = THIS_MODULE,
1530         .read = amdgpu_debugfs_regs_smc_read,
1531         .write = amdgpu_debugfs_regs_smc_write,
1532         .llseek = default_llseek
1533 };
1534
1535 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
1536         .owner = THIS_MODULE,
1537         .read = amdgpu_debugfs_gca_config_read,
1538         .llseek = default_llseek
1539 };
1540
1541 static const struct file_operations amdgpu_debugfs_sensors_fops = {
1542         .owner = THIS_MODULE,
1543         .read = amdgpu_debugfs_sensor_read,
1544         .llseek = default_llseek
1545 };
1546
1547 static const struct file_operations amdgpu_debugfs_wave_fops = {
1548         .owner = THIS_MODULE,
1549         .read = amdgpu_debugfs_wave_read,
1550         .llseek = default_llseek
1551 };
1552 static const struct file_operations amdgpu_debugfs_gpr_fops = {
1553         .owner = THIS_MODULE,
1554         .read = amdgpu_debugfs_gpr_read,
1555         .llseek = default_llseek
1556 };
1557
1558 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
1559         .owner = THIS_MODULE,
1560         .read = amdgpu_debugfs_gfxoff_read,
1561         .write = amdgpu_debugfs_gfxoff_write,
1562         .llseek = default_llseek
1563 };
1564
1565 static const struct file_operations amdgpu_debugfs_gfxoff_status_fops = {
1566         .owner = THIS_MODULE,
1567         .read = amdgpu_debugfs_gfxoff_status_read,
1568         .llseek = default_llseek
1569 };
1570
1571 static const struct file_operations amdgpu_debugfs_gfxoff_count_fops = {
1572         .owner = THIS_MODULE,
1573         .read = amdgpu_debugfs_gfxoff_count_read,
1574         .llseek = default_llseek
1575 };
1576
1577 static const struct file_operations amdgpu_debugfs_gfxoff_residency_fops = {
1578         .owner = THIS_MODULE,
1579         .read = amdgpu_debugfs_gfxoff_residency_read,
1580         .write = amdgpu_debugfs_gfxoff_residency_write,
1581         .llseek = default_llseek
1582 };
1583
1584 static const struct file_operations *debugfs_regs[] = {
1585         &amdgpu_debugfs_regs_fops,
1586         &amdgpu_debugfs_regs2_fops,
1587         &amdgpu_debugfs_gprwave_fops,
1588         &amdgpu_debugfs_regs_didt_fops,
1589         &amdgpu_debugfs_regs_pcie_fops,
1590         &amdgpu_debugfs_regs_smc_fops,
1591         &amdgpu_debugfs_gca_config_fops,
1592         &amdgpu_debugfs_sensors_fops,
1593         &amdgpu_debugfs_wave_fops,
1594         &amdgpu_debugfs_gpr_fops,
1595         &amdgpu_debugfs_gfxoff_fops,
1596         &amdgpu_debugfs_gfxoff_status_fops,
1597         &amdgpu_debugfs_gfxoff_count_fops,
1598         &amdgpu_debugfs_gfxoff_residency_fops,
1599 };
1600
1601 static const char * const debugfs_regs_names[] = {
1602         "amdgpu_regs",
1603         "amdgpu_regs2",
1604         "amdgpu_gprwave",
1605         "amdgpu_regs_didt",
1606         "amdgpu_regs_pcie",
1607         "amdgpu_regs_smc",
1608         "amdgpu_gca_config",
1609         "amdgpu_sensors",
1610         "amdgpu_wave",
1611         "amdgpu_gpr",
1612         "amdgpu_gfxoff",
1613         "amdgpu_gfxoff_status",
1614         "amdgpu_gfxoff_count",
1615         "amdgpu_gfxoff_residency",
1616 };
1617
1618 /**
1619  * amdgpu_debugfs_regs_init -   Initialize debugfs entries that provide
1620  *                              register access.
1621  *
1622  * @adev: The device to attach the debugfs entries to
1623  */
1624 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1625 {
1626         struct drm_minor *minor = adev_to_drm(adev)->primary;
1627         struct dentry *ent, *root = minor->debugfs_root;
1628         unsigned int i;
1629
1630         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
1631                 ent = debugfs_create_file(debugfs_regs_names[i],
1632                                           S_IFREG | 0444, root,
1633                                           adev, debugfs_regs[i]);
1634                 if (!i && !IS_ERR_OR_NULL(ent))
1635                         i_size_write(ent->d_inode, adev->rmmio_size);
1636         }
1637
1638         return 0;
1639 }
1640
1641 static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused)
1642 {
1643         struct amdgpu_device *adev = m->private;
1644         struct drm_device *dev = adev_to_drm(adev);
1645         int r = 0, i;
1646
1647         r = pm_runtime_get_sync(dev->dev);
1648         if (r < 0) {
1649                 pm_runtime_put_autosuspend(dev->dev);
1650                 return r;
1651         }
1652
1653         /* Avoid accidently unparking the sched thread during GPU reset */
1654         r = down_write_killable(&adev->reset_domain->sem);
1655         if (r)
1656                 return r;
1657
1658         /* hold on the scheduler */
1659         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1660                 struct amdgpu_ring *ring = adev->rings[i];
1661
1662                 if (!ring || !ring->sched.thread)
1663                         continue;
1664                 kthread_park(ring->sched.thread);
1665         }
1666
1667         seq_puts(m, "run ib test:\n");
1668         r = amdgpu_ib_ring_tests(adev);
1669         if (r)
1670                 seq_printf(m, "ib ring tests failed (%d).\n", r);
1671         else
1672                 seq_puts(m, "ib ring tests passed.\n");
1673
1674         /* go on the scheduler */
1675         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1676                 struct amdgpu_ring *ring = adev->rings[i];
1677
1678                 if (!ring || !ring->sched.thread)
1679                         continue;
1680                 kthread_unpark(ring->sched.thread);
1681         }
1682
1683         up_write(&adev->reset_domain->sem);
1684
1685         pm_runtime_mark_last_busy(dev->dev);
1686         pm_runtime_put_autosuspend(dev->dev);
1687
1688         return 0;
1689 }
1690
1691 static int amdgpu_debugfs_evict_vram(void *data, u64 *val)
1692 {
1693         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1694         struct drm_device *dev = adev_to_drm(adev);
1695         int r;
1696
1697         r = pm_runtime_get_sync(dev->dev);
1698         if (r < 0) {
1699                 pm_runtime_put_autosuspend(dev->dev);
1700                 return r;
1701         }
1702
1703         *val = amdgpu_ttm_evict_resources(adev, TTM_PL_VRAM);
1704
1705         pm_runtime_mark_last_busy(dev->dev);
1706         pm_runtime_put_autosuspend(dev->dev);
1707
1708         return 0;
1709 }
1710
1711
1712 static int amdgpu_debugfs_evict_gtt(void *data, u64 *val)
1713 {
1714         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1715         struct drm_device *dev = adev_to_drm(adev);
1716         int r;
1717
1718         r = pm_runtime_get_sync(dev->dev);
1719         if (r < 0) {
1720                 pm_runtime_put_autosuspend(dev->dev);
1721                 return r;
1722         }
1723
1724         *val = amdgpu_ttm_evict_resources(adev, TTM_PL_TT);
1725
1726         pm_runtime_mark_last_busy(dev->dev);
1727         pm_runtime_put_autosuspend(dev->dev);
1728
1729         return 0;
1730 }
1731
1732 static int amdgpu_debugfs_benchmark(void *data, u64 val)
1733 {
1734         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1735         struct drm_device *dev = adev_to_drm(adev);
1736         int r;
1737
1738         r = pm_runtime_get_sync(dev->dev);
1739         if (r < 0) {
1740                 pm_runtime_put_autosuspend(dev->dev);
1741                 return r;
1742         }
1743
1744         r = amdgpu_benchmark(adev, val);
1745
1746         pm_runtime_mark_last_busy(dev->dev);
1747         pm_runtime_put_autosuspend(dev->dev);
1748
1749         return r;
1750 }
1751
1752 static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused)
1753 {
1754         struct amdgpu_device *adev = m->private;
1755         struct drm_device *dev = adev_to_drm(adev);
1756         struct drm_file *file;
1757         int r;
1758
1759         r = mutex_lock_interruptible(&dev->filelist_mutex);
1760         if (r)
1761                 return r;
1762
1763         list_for_each_entry(file, &dev->filelist, lhead) {
1764                 struct amdgpu_fpriv *fpriv = file->driver_priv;
1765                 struct amdgpu_vm *vm = &fpriv->vm;
1766
1767                 seq_printf(m, "pid:%d\tProcess:%s ----------\n",
1768                                 vm->task_info.pid, vm->task_info.process_name);
1769                 r = amdgpu_bo_reserve(vm->root.bo, true);
1770                 if (r)
1771                         break;
1772                 amdgpu_debugfs_vm_bo_info(vm, m);
1773                 amdgpu_bo_unreserve(vm->root.bo);
1774         }
1775
1776         mutex_unlock(&dev->filelist_mutex);
1777
1778         return r;
1779 }
1780
1781 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib);
1782 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info);
1783 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram,
1784                          NULL, "%lld\n");
1785 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt,
1786                          NULL, "%lld\n");
1787 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark,
1788                          "%lld\n");
1789
1790 static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring,
1791                                           struct dma_fence **fences)
1792 {
1793         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1794         uint32_t sync_seq, last_seq;
1795
1796         last_seq = atomic_read(&ring->fence_drv.last_seq);
1797         sync_seq = ring->fence_drv.sync_seq;
1798
1799         last_seq &= drv->num_fences_mask;
1800         sync_seq &= drv->num_fences_mask;
1801
1802         do {
1803                 struct dma_fence *fence, **ptr;
1804
1805                 ++last_seq;
1806                 last_seq &= drv->num_fences_mask;
1807                 ptr = &drv->fences[last_seq];
1808
1809                 fence = rcu_dereference_protected(*ptr, 1);
1810                 RCU_INIT_POINTER(*ptr, NULL);
1811
1812                 if (!fence)
1813                         continue;
1814
1815                 fences[last_seq] = fence;
1816
1817         } while (last_seq != sync_seq);
1818 }
1819
1820 static void amdgpu_ib_preempt_signal_fences(struct dma_fence **fences,
1821                                             int length)
1822 {
1823         int i;
1824         struct dma_fence *fence;
1825
1826         for (i = 0; i < length; i++) {
1827                 fence = fences[i];
1828                 if (!fence)
1829                         continue;
1830                 dma_fence_signal(fence);
1831                 dma_fence_put(fence);
1832         }
1833 }
1834
1835 static void amdgpu_ib_preempt_job_recovery(struct drm_gpu_scheduler *sched)
1836 {
1837         struct drm_sched_job *s_job;
1838         struct dma_fence *fence;
1839
1840         spin_lock(&sched->job_list_lock);
1841         list_for_each_entry(s_job, &sched->pending_list, list) {
1842                 fence = sched->ops->run_job(s_job);
1843                 dma_fence_put(fence);
1844         }
1845         spin_unlock(&sched->job_list_lock);
1846 }
1847
1848 static void amdgpu_ib_preempt_mark_partial_job(struct amdgpu_ring *ring)
1849 {
1850         struct amdgpu_job *job;
1851         struct drm_sched_job *s_job, *tmp;
1852         uint32_t preempt_seq;
1853         struct dma_fence *fence, **ptr;
1854         struct amdgpu_fence_driver *drv = &ring->fence_drv;
1855         struct drm_gpu_scheduler *sched = &ring->sched;
1856         bool preempted = true;
1857
1858         if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
1859                 return;
1860
1861         preempt_seq = le32_to_cpu(*(drv->cpu_addr + 2));
1862         if (preempt_seq <= atomic_read(&drv->last_seq)) {
1863                 preempted = false;
1864                 goto no_preempt;
1865         }
1866
1867         preempt_seq &= drv->num_fences_mask;
1868         ptr = &drv->fences[preempt_seq];
1869         fence = rcu_dereference_protected(*ptr, 1);
1870
1871 no_preempt:
1872         spin_lock(&sched->job_list_lock);
1873         list_for_each_entry_safe(s_job, tmp, &sched->pending_list, list) {
1874                 if (dma_fence_is_signaled(&s_job->s_fence->finished)) {
1875                         /* remove job from ring_mirror_list */
1876                         list_del_init(&s_job->list);
1877                         sched->ops->free_job(s_job);
1878                         continue;
1879                 }
1880                 job = to_amdgpu_job(s_job);
1881                 if (preempted && (&job->hw_fence) == fence)
1882                         /* mark the job as preempted */
1883                         job->preemption_status |= AMDGPU_IB_PREEMPTED;
1884         }
1885         spin_unlock(&sched->job_list_lock);
1886 }
1887
1888 static int amdgpu_debugfs_ib_preempt(void *data, u64 val)
1889 {
1890         int r, length;
1891         struct amdgpu_ring *ring;
1892         struct dma_fence **fences = NULL;
1893         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1894
1895         if (val >= AMDGPU_MAX_RINGS)
1896                 return -EINVAL;
1897
1898         ring = adev->rings[val];
1899
1900         if (!ring || !ring->funcs->preempt_ib || !ring->sched.thread)
1901                 return -EINVAL;
1902
1903         /* the last preemption failed */
1904         if (ring->trail_seq != le32_to_cpu(*ring->trail_fence_cpu_addr))
1905                 return -EBUSY;
1906
1907         length = ring->fence_drv.num_fences_mask + 1;
1908         fences = kcalloc(length, sizeof(void *), GFP_KERNEL);
1909         if (!fences)
1910                 return -ENOMEM;
1911
1912         /* Avoid accidently unparking the sched thread during GPU reset */
1913         r = down_read_killable(&adev->reset_domain->sem);
1914         if (r)
1915                 goto pro_end;
1916
1917         /* stop the scheduler */
1918         kthread_park(ring->sched.thread);
1919
1920         /* preempt the IB */
1921         r = amdgpu_ring_preempt_ib(ring);
1922         if (r) {
1923                 DRM_WARN("failed to preempt ring %d\n", ring->idx);
1924                 goto failure;
1925         }
1926
1927         amdgpu_fence_process(ring);
1928
1929         if (atomic_read(&ring->fence_drv.last_seq) !=
1930             ring->fence_drv.sync_seq) {
1931                 DRM_INFO("ring %d was preempted\n", ring->idx);
1932
1933                 amdgpu_ib_preempt_mark_partial_job(ring);
1934
1935                 /* swap out the old fences */
1936                 amdgpu_ib_preempt_fences_swap(ring, fences);
1937
1938                 amdgpu_fence_driver_force_completion(ring);
1939
1940                 /* resubmit unfinished jobs */
1941                 amdgpu_ib_preempt_job_recovery(&ring->sched);
1942
1943                 /* wait for jobs finished */
1944                 amdgpu_fence_wait_empty(ring);
1945
1946                 /* signal the old fences */
1947                 amdgpu_ib_preempt_signal_fences(fences, length);
1948         }
1949
1950 failure:
1951         /* restart the scheduler */
1952         kthread_unpark(ring->sched.thread);
1953
1954         up_read(&adev->reset_domain->sem);
1955
1956 pro_end:
1957         kfree(fences);
1958
1959         return r;
1960 }
1961
1962 static int amdgpu_debugfs_sclk_set(void *data, u64 val)
1963 {
1964         int ret = 0;
1965         uint32_t max_freq, min_freq;
1966         struct amdgpu_device *adev = (struct amdgpu_device *)data;
1967
1968         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1969                 return -EINVAL;
1970
1971         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1972         if (ret < 0) {
1973                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1974                 return ret;
1975         }
1976
1977         ret = amdgpu_dpm_get_dpm_freq_range(adev, PP_SCLK, &min_freq, &max_freq);
1978         if (ret == -EOPNOTSUPP) {
1979                 ret = 0;
1980                 goto out;
1981         }
1982         if (ret || val > max_freq || val < min_freq) {
1983                 ret = -EINVAL;
1984                 goto out;
1985         }
1986
1987         ret = amdgpu_dpm_set_soft_freq_range(adev, PP_SCLK, (uint32_t)val, (uint32_t)val);
1988         if (ret)
1989                 ret = -EINVAL;
1990
1991 out:
1992         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1993         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1994
1995         return ret;
1996 }
1997
1998 DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL,
1999                         amdgpu_debugfs_ib_preempt, "%llu\n");
2000
2001 DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL,
2002                         amdgpu_debugfs_sclk_set, "%llu\n");
2003
2004 static ssize_t amdgpu_reset_dump_register_list_read(struct file *f,
2005                                 char __user *buf, size_t size, loff_t *pos)
2006 {
2007         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
2008         char reg_offset[12];
2009         int i, ret, len = 0;
2010
2011         if (*pos)
2012                 return 0;
2013
2014         memset(reg_offset, 0, 12);
2015         ret = down_read_killable(&adev->reset_domain->sem);
2016         if (ret)
2017                 return ret;
2018
2019         for (i = 0; i < adev->num_regs; i++) {
2020                 sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]);
2021                 up_read(&adev->reset_domain->sem);
2022                 if (copy_to_user(buf + len, reg_offset, strlen(reg_offset)))
2023                         return -EFAULT;
2024
2025                 len += strlen(reg_offset);
2026                 ret = down_read_killable(&adev->reset_domain->sem);
2027                 if (ret)
2028                         return ret;
2029         }
2030
2031         up_read(&adev->reset_domain->sem);
2032         *pos += len;
2033
2034         return len;
2035 }
2036
2037 static ssize_t amdgpu_reset_dump_register_list_write(struct file *f,
2038                         const char __user *buf, size_t size, loff_t *pos)
2039 {
2040         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
2041         char reg_offset[11];
2042         uint32_t *new = NULL, *tmp = NULL;
2043         int ret, i = 0, len = 0;
2044
2045         do {
2046                 memset(reg_offset, 0, 11);
2047                 if (copy_from_user(reg_offset, buf + len,
2048                                         min(10, ((int)size-len)))) {
2049                         ret = -EFAULT;
2050                         goto error_free;
2051                 }
2052
2053                 new = krealloc_array(tmp, i + 1, sizeof(uint32_t), GFP_KERNEL);
2054                 if (!new) {
2055                         ret = -ENOMEM;
2056                         goto error_free;
2057                 }
2058                 tmp = new;
2059                 if (sscanf(reg_offset, "%X %n", &tmp[i], &ret) != 1) {
2060                         ret = -EINVAL;
2061                         goto error_free;
2062                 }
2063
2064                 len += ret;
2065                 i++;
2066         } while (len < size);
2067
2068         new = kmalloc_array(i, sizeof(uint32_t), GFP_KERNEL);
2069         if (!new) {
2070                 ret = -ENOMEM;
2071                 goto error_free;
2072         }
2073         ret = down_write_killable(&adev->reset_domain->sem);
2074         if (ret)
2075                 goto error_free;
2076
2077         swap(adev->reset_dump_reg_list, tmp);
2078         swap(adev->reset_dump_reg_value, new);
2079         adev->num_regs = i;
2080         up_write(&adev->reset_domain->sem);
2081         ret = size;
2082
2083 error_free:
2084         if (tmp != new)
2085                 kfree(tmp);
2086         kfree(new);
2087         return ret;
2088 }
2089
2090 static const struct file_operations amdgpu_reset_dump_register_list = {
2091         .owner = THIS_MODULE,
2092         .read = amdgpu_reset_dump_register_list_read,
2093         .write = amdgpu_reset_dump_register_list_write,
2094         .llseek = default_llseek
2095 };
2096
2097 int amdgpu_debugfs_init(struct amdgpu_device *adev)
2098 {
2099         struct dentry *root = adev_to_drm(adev)->primary->debugfs_root;
2100         struct dentry *ent;
2101         int r, i;
2102
2103         if (!debugfs_initialized())
2104                 return 0;
2105
2106         debugfs_create_x32("amdgpu_smu_debug", 0600, root,
2107                            &adev->pm.smu_debug_mask);
2108
2109         ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev,
2110                                   &fops_ib_preempt);
2111         if (IS_ERR(ent)) {
2112                 DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n");
2113                 return PTR_ERR(ent);
2114         }
2115
2116         ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev,
2117                                   &fops_sclk_set);
2118         if (IS_ERR(ent)) {
2119                 DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n");
2120                 return PTR_ERR(ent);
2121         }
2122
2123         /* Register debugfs entries for amdgpu_ttm */
2124         amdgpu_ttm_debugfs_init(adev);
2125         amdgpu_debugfs_pm_init(adev);
2126         amdgpu_debugfs_sa_init(adev);
2127         amdgpu_debugfs_fence_init(adev);
2128         amdgpu_debugfs_gem_init(adev);
2129
2130         r = amdgpu_debugfs_regs_init(adev);
2131         if (r)
2132                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2133
2134         amdgpu_debugfs_firmware_init(adev);
2135         amdgpu_ta_if_debugfs_init(adev);
2136
2137 #if defined(CONFIG_DRM_AMD_DC)
2138         if (adev->dc_enabled)
2139                 dtn_debugfs_init(adev);
2140 #endif
2141
2142         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
2143                 struct amdgpu_ring *ring = adev->rings[i];
2144
2145                 if (!ring)
2146                         continue;
2147
2148                 amdgpu_debugfs_ring_init(adev, ring);
2149         }
2150
2151         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
2152                 if (!amdgpu_vcnfw_log)
2153                         break;
2154
2155                 if (adev->vcn.harvest_config & (1 << i))
2156                         continue;
2157
2158                 amdgpu_debugfs_vcn_fwlog_init(adev, i, &adev->vcn.inst[i]);
2159         }
2160
2161         amdgpu_ras_debugfs_create_all(adev);
2162         amdgpu_rap_debugfs_init(adev);
2163         amdgpu_securedisplay_debugfs_init(adev);
2164         amdgpu_fw_attestation_debugfs_init(adev);
2165
2166         debugfs_create_file("amdgpu_evict_vram", 0444, root, adev,
2167                             &amdgpu_evict_vram_fops);
2168         debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev,
2169                             &amdgpu_evict_gtt_fops);
2170         debugfs_create_file("amdgpu_test_ib", 0444, root, adev,
2171                             &amdgpu_debugfs_test_ib_fops);
2172         debugfs_create_file("amdgpu_vm_info", 0444, root, adev,
2173                             &amdgpu_debugfs_vm_info_fops);
2174         debugfs_create_file("amdgpu_benchmark", 0200, root, adev,
2175                             &amdgpu_benchmark_fops);
2176         debugfs_create_file("amdgpu_reset_dump_register_list", 0644, root, adev,
2177                             &amdgpu_reset_dump_register_list);
2178
2179         adev->debugfs_vbios_blob.data = adev->bios;
2180         adev->debugfs_vbios_blob.size = adev->bios_size;
2181         debugfs_create_blob("amdgpu_vbios", 0444, root,
2182                             &adev->debugfs_vbios_blob);
2183
2184         adev->debugfs_discovery_blob.data = adev->mman.discovery_bin;
2185         adev->debugfs_discovery_blob.size = adev->mman.discovery_tmr_size;
2186         debugfs_create_blob("amdgpu_discovery", 0444, root,
2187                             &adev->debugfs_discovery_blob);
2188
2189         return 0;
2190 }
2191
2192 #else
2193 int amdgpu_debugfs_init(struct amdgpu_device *adev)
2194 {
2195         return 0;
2196 }
2197 int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2198 {
2199         return 0;
2200 }
2201 #endif